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authorLarry Finger <Larry.Finger@lwfinger.net>2010-02-14 23:07:57 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2010-03-03 19:42:59 -0500
commitcd18964a1d67c4989474ffca0109ef1c0f8502a3 (patch)
tree4fed6694fe9312e2a55d0241f7c65eef67566c08 /drivers/staging
parent8daba6b94dce76254b10de0a9a777f792a120322 (diff)
Staging: r8187se: Remove dead code from r8185b_init.c
Remove dead code from r8185b_init.c. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging')
-rw-r--r--drivers/staging/rtl8187se/r8185b_init.c632
1 files changed, 2 insertions, 630 deletions
diff --git a/drivers/staging/rtl8187se/r8185b_init.c b/drivers/staging/rtl8187se/r8185b_init.c
index 19b5c9f90b5..a0ece1fd64a 100644
--- a/drivers/staging/rtl8187se/r8185b_init.c
+++ b/drivers/staging/rtl8187se/r8185b_init.c
@@ -243,82 +243,7 @@ void SetOutputEnableOfRfPins(struct net_device *dev)
243 write_nic_word(dev, RFPinsEnable, 0x1bff); 243 write_nic_word(dev, RFPinsEnable, 0x1bff);
244} 244}
245 245
246void 246static int
247ZEBRA_RFSerialWrite(
248 struct net_device *dev,
249 u32 data2Write,
250 u8 totalLength,
251 u8 low2high
252 )
253{
254 ThreeWireReg twreg;
255 int i;
256 u16 oval,oval2,oval3;
257 u32 mask;
258 u16 UshortBuffer;
259
260 u8 u1bTmp;
261 // RTL8187S HSSI Read/Write Function
262 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
263 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
264 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
265 UshortBuffer = read_nic_word(dev, RFPinsOutput);
266 oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
267
268 oval2 = read_nic_word(dev, RFPinsEnable);
269 oval3 = read_nic_word(dev, RFPinsSelect);
270
271 // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
272 oval3 &= 0xfff8;
273
274 write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
275 write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
276 udelay(10);
277
278 // Add this to avoid hardware and software 3-wire conflict.
279 // 2005.03.01, by rcnjko.
280 twreg.longData = 0;
281 twreg.struc.enableB = 1;
282 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
283 udelay(2);
284 twreg.struc.enableB = 0;
285 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
286 udelay(10);
287
288 mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
289
290 for(i=0; i<totalLength/2; i++)
291 {
292 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
293 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
294 twreg.struc.clk = 1;
295 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
296 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
297
298 mask = (low2high)?(mask<<1):(mask>>1);
299 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
300 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
301 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
302 twreg.struc.clk = 0;
303 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
304 mask = (low2high)?(mask<<1):(mask>>1);
305 }
306
307 twreg.struc.enableB = 1;
308 twreg.struc.clk = 0;
309 twreg.struc.data = 0;
310 write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
311 udelay(10);
312
313 write_nic_word(dev, RFPinsOutput, oval|0x0004);
314 write_nic_word(dev, RFPinsSelect, oval3|0x0000);
315
316 SetOutputEnableOfRfPins(dev);
317}
318//by amy
319
320
321int
322HwHSSIThreeWire( 247HwHSSIThreeWire(
323 struct net_device *dev, 248 struct net_device *dev,
324 u8 *pDataBuf, 249 u8 *pDataBuf,
@@ -456,138 +381,6 @@ HwHSSIThreeWire(
456 381
457 return bResult; 382 return bResult;
458} 383}
459//by amy
460
461int
462HwThreeWire(
463 struct net_device *dev,
464 u8 *pDataBuf,
465 u8 nDataBufBitCnt,
466 int bHold,
467 int bWrite
468 )
469{
470 int bResult = 1;
471 u8 TryCnt;
472 u8 u1bTmp;
473
474 do
475 {
476 // Check if WE and RE are cleared.
477 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
478 {
479 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
480 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
481 {
482 break;
483 }
484 udelay(10);
485 }
486 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
487 panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
488
489 // Fill up data buffer for write operation.
490 if(nDataBufBitCnt == 16)
491 {
492 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
493 }
494 else if(nDataBufBitCnt == 64)
495 {
496 write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
497 write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
498 }
499 else
500 {
501 int idx;
502 int ByteCnt = nDataBufBitCnt / 8;
503
504 if ((nDataBufBitCnt % 8) != 0)
505 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
506 nDataBufBitCnt);
507
508 if (nDataBufBitCnt > 64)
509 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
510 nDataBufBitCnt);
511
512 for(idx = 0; idx < ByteCnt; idx++)
513 {
514 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
515 }
516 }
517
518 // Fill up length field.
519 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
520 if(bHold)
521 u1bTmp |= SW_3W_CMD0_HOLD;
522 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
523
524 // Set up command: WE or RE.
525 if(bWrite)
526 {
527 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
528 }
529 else
530 {
531 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
532 }
533
534 // Check if WE and RE are cleared and DONE is set.
535 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
536 {
537 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
538 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
539 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
540 {
541 break;
542 }
543 udelay(10);
544 }
545 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
546 {
547 //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
548 // ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
549 // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
550 write_nic_byte(dev, SW_3W_CMD1, 0);
551 }
552
553 // Read back data for read operation.
554 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
555 if(bWrite == 0)
556 {
557 if(nDataBufBitCnt == 16)
558 {
559 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
560 }
561 else if(nDataBufBitCnt == 64)
562 {
563 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
564 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
565 }
566 else
567 {
568 int idx;
569 int ByteCnt = nDataBufBitCnt / 8;
570
571 if ((nDataBufBitCnt % 8) != 0)
572 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
573 nDataBufBitCnt);
574
575 if (nDataBufBitCnt > 64)
576 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
577 nDataBufBitCnt);
578
579 for(idx = 0; idx < ByteCnt; idx++)
580 {
581 *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
582 }
583 }
584 }
585
586 }while(0);
587
588 return bResult;
589}
590
591 384
592void 385void
593RF_WriteReg(struct net_device *dev, u8 offset, u32 data) 386RF_WriteReg(struct net_device *dev, u8 offset, u32 data)
@@ -602,125 +395,6 @@ RF_WriteReg(struct net_device *dev, u8 offset, u32 data)
602 HwHSSIThreeWire(dev, (u8 *)(&data2Write), len, 1, 1); 395 HwHSSIThreeWire(dev, (u8 *)(&data2Write), len, 1, 1);
603} 396}
604 397
605void
606ZEBRA_RFSerialRead(struct net_device *dev, u32 data2Write, u8 wLength,
607 u32 *data2Read, u8 rLength, u8 low2high)
608{
609 ThreeWireReg twreg;
610 int i;
611 u16 oval, oval2, oval3, tmp, wReg80;
612 u32 mask;
613 u8 u1bTmp;
614 ThreeWireReg tdata;
615 //PHAL_DATA_8187 pHalData = GetHalData8187(pAdapter);
616 { // RTL8187S HSSI Read/Write Function
617 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
618 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
619 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
620 }
621
622 wReg80 = oval = read_nic_word(dev, RFPinsOutput);
623 oval2 = read_nic_word(dev, RFPinsEnable);
624 oval3 = read_nic_word(dev, RFPinsSelect);
625
626 write_nic_word(dev, RFPinsEnable, oval2|0xf);
627 write_nic_word(dev, RFPinsSelect, oval3|0xf);
628
629 *data2Read = 0;
630
631 // We must clear BIT0-3 here, otherwise,
632 // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
633 // which will cause the value read become 0. 2005.04.11, by rcnjko.
634 oval &= ~0xf;
635
636 // Avoid collision with hardware three-wire.
637 twreg.longData = 0;
638 twreg.struc.enableB = 1;
639 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
640
641 twreg.longData = 0;
642 twreg.struc.enableB = 0;
643 twreg.struc.clk = 0;
644 twreg.struc.read_write = 0;
645 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
646
647 mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
648 for(i = 0; i < wLength/2; i++)
649 {
650 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
651 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
652 twreg.struc.clk = 1;
653 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
654 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
655
656 mask = (low2high) ? (mask<<1): (mask>>1);
657
658 if(i == 2)
659 {
660 // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
661 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe); // turn off data enable
662 //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
663
664 twreg.struc.read_write=1;
665 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
666 twreg.struc.clk = 0;
667 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
668 break;
669 }
670 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
671 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
672 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
673
674 twreg.struc.clk = 0;
675 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
676
677 mask = (low2high) ? (mask<<1) : (mask>>1);
678 }
679
680 twreg.struc.clk = 0;
681 twreg.struc.data = 0;
682 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
683 mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
684
685 //
686 // 061016, by rcnjko:
687 // We must set data pin to HW controled, otherwise RF can't driver it and
688 // value RF register won't be able to read back properly.
689 //
690 write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
691
692 for(i = 0; i < rLength; i++)
693 {
694 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
695 twreg.struc.clk = 1;
696 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
697 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
698 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
699 tmp = read_nic_word(dev, RFPinsInput);
700 tdata.longData = tmp;
701 *data2Read |= tdata.struc.clk ? mask : 0;
702
703 twreg.struc.clk = 0;
704 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
705
706 mask = (low2high) ? (mask<<1) : (mask>>1);
707 }
708 twreg.struc.enableB = 1;
709 twreg.struc.clk = 0;
710 twreg.struc.data = 0;
711 twreg.struc.read_write = 1;
712 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
713
714 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8); // Set To Output Enable
715 write_nic_word(dev, RFPinsEnable, oval2); // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
716 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
717 write_nic_word(dev, RFPinsSelect, oval3); // Set To SW Switch
718 //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
719 write_nic_word(dev, RFPinsOutput, 0x3a0);
720 //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
721}
722
723
724u32 RF_ReadReg(struct net_device *dev, u8 offset) 398u32 RF_ReadReg(struct net_device *dev, u8 offset)
725{ 399{
726 u32 data2Write; 400 u32 data2Write;
@@ -891,15 +565,12 @@ ZEBRA_Config_85BASIC_HardCode(
891 565
892 // Page0 : reg0-reg15 566 // Page0 : reg0-reg15
893 567
894// RF_WriteReg(dev, 0x00, 0x003f); mdelay(1);//1
895 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);// 1 568 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);// 1
896 569
897 RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1); 570 RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1);
898 571
899// RF_WriteReg(dev, 0x02, 0x004c); mdelay(1);//2
900 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);// 2 572 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);// 2
901 573
902// RF_WriteReg(dev, 0x03, 0x0000); mdelay(1);//3
903 RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);// 3 574 RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);// 3
904 575
905 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); 576 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1);
@@ -928,8 +599,6 @@ ZEBRA_Config_85BASIC_HardCode(
928 599
929 RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1); 600 RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1);
930// Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl. 601// Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
931// RF_WriteReg(dev, 0x08, 0x0597); mdelay(1);
932// RF_WriteReg(dev, 0x09, 0x050a); mdelay(1);
933 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1); 602 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
934 RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1); 603 RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1);
935 604
@@ -945,7 +614,6 @@ ZEBRA_Config_85BASIC_HardCode(
945 614
946 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); 615 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
947 616
948// RF_WriteReg(dev, 0x00, 0x017f); mdelay(1);//6
949 RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1);// 6 617 RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1);// 6
950 618
951 RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1); 619 RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1);
@@ -954,20 +622,14 @@ ZEBRA_Config_85BASIC_HardCode(
954 { 622 {
955 RF_WriteReg(dev, 0x01, i); mdelay(1); 623 RF_WriteReg(dev, 0x01, i); mdelay(1);
956 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1); 624 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
957 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
958 } 625 }
959 626
960 RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /// 203, 343 627 RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /// 203, 343
961 //RF_WriteReg(dev, 0x06, 0x0300); mdelay(1); // 400
962 RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); // 400 628 RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); // 400
963 629
964 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30, and HSSI disable 137 630 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30, and HSSI disable 137
965 mdelay(10); // Deay 10 ms. //0xfd 631 mdelay(10); // Deay 10 ms. //0xfd
966 632
967// RF_WriteReg(dev, 0x0c, 0x09be); mdelay(1); // 7
968 //RF_WriteReg(dev, 0x0c, 0x07be); mdelay(1);
969 //mdelay(10); // Deay 10 ms. //0xfd
970
971 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); // Z4 synthesizer loop filter setting, 392 633 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); // Z4 synthesizer loop filter setting, 392
972 mdelay(10); // Deay 10 ms. //0xfd 634 mdelay(10); // Deay 10 ms. //0xfd
973 635
@@ -1013,10 +675,8 @@ ZEBRA_Config_85BASIC_HardCode(
1013 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); 675 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
1014 } 676 }
1015//by amy 080312 677//by amy 080312
1016// RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); //-by amy 080312
1017 678
1018 RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1); // switch to reg0-reg15, and HSSI enable 679 RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1); // switch to reg0-reg15, and HSSI enable
1019// RF_WriteReg(dev, 0x0d, 0x009f); mdelay(1); // Rx BB start calibration, 00c//-edward
1020 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); // Rx BB start calibration, 00c//+edward 680 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); // Rx BB start calibration, 00c//+edward
1021 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1); // temperature meter off 681 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1); // temperature meter off
1022 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); // Rx mode 682 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); // Rx mode
@@ -1065,13 +725,10 @@ ZEBRA_Config_85BASIC_HardCode(
1065 // AGC.txt 725 // AGC.txt
1066 //============================================================================= 726 //=============================================================================
1067 727
1068// PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280); // Annie, 2006-05-05
1069 write_phy_ofdm(dev, 0x00, 0x12); 728 write_phy_ofdm(dev, 0x00, 0x12);
1070 //WriteBBPortUchar(dev, 0x00001280);
1071 729
1072 for (i=0; i<128; i++) 730 for (i=0; i<128; i++)
1073 { 731 {
1074 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1075 732
1076 data = ZEBRA_AGC[i+1]; 733 data = ZEBRA_AGC[i+1];
1077 data = data << 8; 734 data = data << 8;
@@ -1087,7 +744,6 @@ ZEBRA_Config_85BASIC_HardCode(
1087 } 744 }
1088 745
1089 PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080); // Annie, 2006-05-05 746 PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080); // Annie, 2006-05-05
1090 //WriteBBPortUchar(dev, 0x00001080);
1091 747
1092 //============================================================================= 748 //=============================================================================
1093 749
@@ -1100,8 +756,6 @@ ZEBRA_Config_85BASIC_HardCode(
1100 u4bRegOffset=i; 756 u4bRegOffset=i;
1101 u4bRegValue=OFDM_CONFIG[i]; 757 u4bRegValue=OFDM_CONFIG[i];
1102 758
1103 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1104
1105 WriteBBPortUchar(dev, 759 WriteBBPortUchar(dev,
1106 (0x00000080 | 760 (0x00000080 |
1107 (u4bRegOffset & 0x7f) | 761 (u4bRegOffset & 0x7f) |
@@ -1125,9 +779,6 @@ UpdateInitialGain(
1125 ) 779 )
1126{ 780{
1127 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 781 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1128 //unsigned char* IGTable;
1129 //u8 DIG_CurrentInitialGain = 4;
1130 //unsigned char u1Tmp;
1131 782
1132 //lzm add 080826 783 //lzm add 080826
1133 if(priv->eRFPowerState != eRfOn) 784 if(priv->eRFPowerState != eRfOn)
@@ -1205,13 +856,11 @@ InitTxPwrTracking87SE(
1205 struct net_device *dev 856 struct net_device *dev
1206) 857)
1207{ 858{
1208 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1209 u32 u4bRfReg; 859 u32 u4bRfReg;
1210 860
1211 u4bRfReg = RF_ReadReg(dev, 0x02); 861 u4bRfReg = RF_ReadReg(dev, 0x02);
1212 862
1213 // Enable Thermal meter indication. 863 // Enable Thermal meter indication.
1214 //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1215 RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1); 864 RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1);
1216} 865}
1217 866
@@ -1231,7 +880,6 @@ PhyConfig8185(
1231 { 880 {
1232 if(priv->InitialGain == 0) 881 if(priv->InitialGain == 0)
1233 priv->InitialGain = 4; 882 priv->InitialGain = 4;
1234 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1235 } 883 }
1236 884
1237 // 885 //
@@ -1249,34 +897,17 @@ PhyConfig8185(
1249 return; 897 return;
1250} 898}
1251 899
1252
1253
1254
1255void 900void
1256HwConfigureRTL8185( 901HwConfigureRTL8185(
1257 struct net_device *dev 902 struct net_device *dev
1258 ) 903 )
1259{ 904{
1260 //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control. 905 //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1261// u8 bUNIVERSAL_CONTROL_RL = 1;
1262 u8 bUNIVERSAL_CONTROL_RL = 0; 906 u8 bUNIVERSAL_CONTROL_RL = 0;
1263
1264 u8 bUNIVERSAL_CONTROL_AGC = 1; 907 u8 bUNIVERSAL_CONTROL_AGC = 1;
1265 u8 bUNIVERSAL_CONTROL_ANT = 1; 908 u8 bUNIVERSAL_CONTROL_ANT = 1;
1266 u8 bAUTO_RATE_FALLBACK_CTL = 1; 909 u8 bAUTO_RATE_FALLBACK_CTL = 1;
1267 u8 val8; 910 u8 val8;
1268 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1269 //struct ieee80211_device *ieee = priv->ieee80211;
1270 //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1271//{by amy 080312 if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1272// {
1273// write_nic_word(dev, BRSR, 0xffff);
1274// }
1275// else
1276// {
1277// write_nic_word(dev, BRSR, 0x000f);
1278// }
1279//by amy 080312}
1280 write_nic_word(dev, BRSR, 0x0fff); 911 write_nic_word(dev, BRSR, 0x0fff);
1281 // Retry limit 912 // Retry limit
1282 val8 = read_nic_byte(dev, CW_CONF); 913 val8 = read_nic_byte(dev, CW_CONF);
@@ -1327,20 +958,11 @@ HwConfigureRTL8185(
1327 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1; 958 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
1328 959
1329 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting. 960 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
1330 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
1331//by amy
1332 // Aadded by Roger, 2007.11.15.
1333 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps. 961 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
1334//by amy
1335 }
1336 else
1337 {
1338 } 962 }
1339 write_nic_byte(dev, RATE_FALLBACK, val8); 963 write_nic_byte(dev, RATE_FALLBACK, val8);
1340} 964}
1341 965
1342
1343
1344static void 966static void
1345MacConfig_85BASIC_HardCode( 967MacConfig_85BASIC_HardCode(
1346 struct net_device *dev) 968 struct net_device *dev)
@@ -1368,14 +990,11 @@ MacConfig_85BASIC_HardCode(
1368 { 990 {
1369 u4bRegOffset |= (u4bPageIndex << 8); 991 u4bRegOffset |= (u4bPageIndex << 8);
1370 } 992 }
1371 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1372 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue); 993 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
1373 } 994 }
1374 //============================================================================ 995 //============================================================================
1375} 996}
1376 997
1377
1378
1379static void 998static void
1380MacConfig_85BASIC( 999MacConfig_85BASIC(
1381 struct net_device *dev) 1000 struct net_device *dev)
@@ -1398,8 +1017,6 @@ MacConfig_85BASIC(
1398 PlatformIOWrite1Byte(dev, 0x1F8, 0x00); 1017 PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
1399 1018
1400 // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko. 1019 // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
1401 //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
1402//by amy
1403 // power save parameter based on "87SE power save parameters 20071127.doc", as follow. 1020 // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
1404 1021
1405 //Enable DA10 TX power saving 1022 //Enable DA10 TX power saving
@@ -1418,16 +1035,10 @@ MacConfig_85BASIC(
1418 write_nic_word(dev, 0x378, 0x0560); 1035 write_nic_word(dev, 0x378, 0x0560);
1419 write_nic_word(dev, 0x37A, 0x0560); 1036 write_nic_word(dev, 0x37A, 0x0560);
1420 write_nic_word(dev, 0x37C, 0x00EC); 1037 write_nic_word(dev, 0x37C, 0x00EC);
1421// write_nic_word(dev, 0x37E, 0x00FE);//-edward
1422 write_nic_word(dev, 0x37E, 0x00EC);//+edward 1038 write_nic_word(dev, 0x37E, 0x00EC);//+edward
1423 write_nic_byte(dev, 0x24E,0x01); 1039 write_nic_byte(dev, 0x24E,0x01);
1424//by amy
1425
1426} 1040}
1427 1041
1428
1429
1430
1431u8 1042u8
1432GetSupportedWirelessMode8185( 1043GetSupportedWirelessMode8185(
1433 struct net_device *dev 1044 struct net_device *dev
@@ -1450,7 +1061,6 @@ ActUpdateChannelAccessSetting(
1450 struct ieee80211_device *ieee = priv->ieee80211; 1061 struct ieee80211_device *ieee = priv->ieee80211;
1451 AC_CODING eACI; 1062 AC_CODING eACI;
1452 AC_PARAM AcParam; 1063 AC_PARAM AcParam;
1453 //PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos;
1454 u8 bFollowLegacySetting = 0; 1064 u8 bFollowLegacySetting = 0;
1455 u8 u1bAIFS; 1065 u8 u1bAIFS;
1456 1066
@@ -1472,40 +1082,14 @@ ActUpdateChannelAccessSetting(
1472 ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko. 1082 ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
1473 1083
1474 write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer); 1084 write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1475 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer ); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1476 write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29. 1085 write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1477 1086
1478 u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer ); 1087 u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
1479 1088
1480 //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
1481 //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
1482 //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
1483 //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
1484
1485 write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer); 1089 write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
1486 1090
1487 write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. 1091 write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1488 1092
1489#ifdef TODO
1490 // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
1491 if( pStaQos->CurrentQosMode > QOS_DISABLE )
1492 { // QoS mode.
1493 if(pStaQos->QBssWirelessMode == WirelessMode)
1494 {
1495 // Follow AC Parameters of the QBSS.
1496 for(eACI = 0; eACI < AC_MAX; eACI++)
1497 {
1498 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
1499 }
1500 }
1501 else
1502 {
1503 // Follow Default WMM AC Parameters.
1504 bFollowLegacySetting = 1;
1505 }
1506 }
1507 else
1508#endif
1509 { // Legacy 802.11. 1093 { // Legacy 802.11.
1510 bFollowLegacySetting = 1; 1094 bFollowLegacySetting = 1;
1511 1095
@@ -1528,14 +1112,12 @@ ActUpdateChannelAccessSetting(
1528 AcParam.f.TXOPLimit = 0; 1112 AcParam.f.TXOPLimit = 0;
1529 1113
1530 //lzm reserved 080826 1114 //lzm reserved 080826
1531#if 1
1532 // For turbo mode setting. port from 87B by Isaiah 2008-08-01 1115 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
1533 if( ieee->current_network.Turbo_Enable == 1 ) 1116 if( ieee->current_network.Turbo_Enable == 1 )
1534 AcParam.f.TXOPLimit = 0x01FF; 1117 AcParam.f.TXOPLimit = 0x01FF;
1535 // For 87SE with Intel 4965 Ad-Hoc mode have poor throughput (19MB) 1118 // For 87SE with Intel 4965 Ad-Hoc mode have poor throughput (19MB)
1536 if (ieee->iw_mode == IW_MODE_ADHOC) 1119 if (ieee->iw_mode == IW_MODE_ADHOC)
1537 AcParam.f.TXOPLimit = 0x0020; 1120 AcParam.f.TXOPLimit = 0x0020;
1538#endif
1539 1121
1540 for(eACI = 0; eACI < AC_MAX; eACI++) 1122 for(eACI = 0; eACI < AC_MAX; eACI++)
1541 { 1123 {
@@ -1579,18 +1161,13 @@ ActUpdateChannelAccessSetting(
1579 1161
1580 // Cehck ACM bit. 1162 // Cehck ACM bit.
1581 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. 1163 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
1582 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
1583 { 1164 {
1584 PACI_AIFSN pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn); 1165 PACI_AIFSN pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
1585 AC_CODING eACI = pAciAifsn->f.ACI; 1166 AC_CODING eACI = pAciAifsn->f.ACI;
1586 1167
1587 //modified Joseph 1168 //modified Joseph
1588 //for 8187B AsynIORead issue 1169 //for 8187B AsynIORead issue
1589#ifdef TODO
1590 u8 AcmCtrl = pHalData->AcmControl;
1591#else
1592 u8 AcmCtrl = 0; 1170 u8 AcmCtrl = 0;
1593#endif
1594 if( pAciAifsn->f.ACM ) 1171 if( pAciAifsn->f.ACM )
1595 { // ACM bit is 1. 1172 { // ACM bit is 1.
1596 switch(eACI) 1173 switch(eACI)
@@ -1632,19 +1209,10 @@ ActUpdateChannelAccessSetting(
1632 break; 1209 break;
1633 } 1210 }
1634 } 1211 }
1635
1636 //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1637
1638#ifdef TO_DO
1639 pHalData->AcmControl = AcmCtrl;
1640#endif
1641 //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
1642 write_nic_byte(dev, ACM_CONTROL, 0); 1212 write_nic_byte(dev, ACM_CONTROL, 0);
1643 } 1213 }
1644 } 1214 }
1645 } 1215 }
1646
1647
1648 } 1216 }
1649} 1217}
1650 1218
@@ -1656,7 +1224,6 @@ ActSetWirelessMode8185(
1656{ 1224{
1657 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1225 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1658 struct ieee80211_device *ieee = priv->ieee80211; 1226 struct ieee80211_device *ieee = priv->ieee80211;
1659 //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
1660 u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev); 1227 u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1661 1228
1662 if( (btWirelessMode & btSupportedWirelessMode) == 0 ) 1229 if( (btWirelessMode & btSupportedWirelessMode) == 0 )
@@ -1689,7 +1256,6 @@ ActSetWirelessMode8185(
1689 } 1256 }
1690 } 1257 }
1691 1258
1692
1693 /* 2. Swtich band: RF or BB specific actions, 1259 /* 2. Swtich band: RF or BB specific actions,
1694 * for example, refresh tables in omc8255, or change initial gain if necessary. 1260 * for example, refresh tables in omc8255, or change initial gain if necessary.
1695 * Nothing to do for Zebra to switch band. 1261 * Nothing to do for Zebra to switch band.
@@ -1706,7 +1272,6 @@ ActSetWirelessMode8185(
1706 else if( ieee->mode == WIRELESS_MODE_G ){ 1272 else if( ieee->mode == WIRELESS_MODE_G ){
1707 DMESG("WIRELESS_MODE_G\n"); 1273 DMESG("WIRELESS_MODE_G\n");
1708 } 1274 }
1709
1710 ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting); 1275 ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
1711} 1276}
1712 1277
@@ -1724,11 +1289,7 @@ DrvIFIndicateDisassociation(
1724 u16 reason 1289 u16 reason
1725 ) 1290 )
1726{ 1291{
1727 //printk("==> DrvIFIndicateDisassociation()\n");
1728
1729 // nothing is needed after disassociation request. 1292 // nothing is needed after disassociation request.
1730
1731 //printk("<== DrvIFIndicateDisassociation()\n");
1732} 1293}
1733void 1294void
1734MgntDisconnectIBSS( 1295MgntDisconnectIBSS(
@@ -1738,11 +1299,7 @@ MgntDisconnectIBSS(
1738 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1299 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1739 u8 i; 1300 u8 i;
1740 1301
1741 //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
1742
1743 DrvIFIndicateDisassociation(dev, unspec_reason); 1302 DrvIFIndicateDisassociation(dev, unspec_reason);
1744
1745// PlatformZeroMemory( pMgntInfo->Bssid, 6 );
1746 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x55; 1303 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x55;
1747 1304
1748 priv->ieee80211->state = IEEE80211_NOLINK; 1305 priv->ieee80211->state = IEEE80211_NOLINK;
@@ -1754,16 +1311,10 @@ MgntDisconnectIBSS(
1754 // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send. 1311 // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
1755 1312
1756 // Disable Beacon Queue Own bit, suggested by jong 1313 // Disable Beacon Queue Own bit, suggested by jong
1757// Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
1758 ieee80211_stop_send_beacons(priv->ieee80211); 1314 ieee80211_stop_send_beacons(priv->ieee80211);
1759 1315
1760 priv->ieee80211->link_change(dev); 1316 priv->ieee80211->link_change(dev);
1761 notify_wx_assoc_event(priv->ieee80211); 1317 notify_wx_assoc_event(priv->ieee80211);
1762
1763 // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
1764
1765// MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
1766
1767} 1318}
1768void 1319void
1769MlmeDisassociateRequest( 1320MlmeDisassociateRequest(
@@ -1783,14 +1334,8 @@ MlmeDisassociateRequest(
1783 DrvIFIndicateDisassociation(dev, unspec_reason); 1334 DrvIFIndicateDisassociation(dev, unspec_reason);
1784 1335
1785 1336
1786 // pMgntInfo->AsocTimestamp = 0;
1787 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22; 1337 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22;
1788// pMgntInfo->mBrates.Length = 0;
1789// Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
1790
1791 ieee80211_disassociate(priv->ieee80211); 1338 ieee80211_disassociate(priv->ieee80211);
1792
1793
1794 } 1339 }
1795 1340
1796} 1341}
@@ -1808,23 +1353,12 @@ MgntDisconnectAP(
1808// I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE(). 1353// I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
1809// 1354//
1810// //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success 1355// //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
1811// SecClearAllKeys(Adapter);
1812 1356
1813 // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking. 1357 // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
1814#ifdef TODO
1815 if( pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
1816 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) ) // In CCKM mode will Clear key
1817 {
1818 SecClearAllKeys(Adapter);
1819 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
1820 }
1821#endif
1822 // 2004.10.11, by rcnjko. 1358 // 2004.10.11, by rcnjko.
1823 //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
1824 MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn ); 1359 MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
1825 1360
1826 priv->ieee80211->state = IEEE80211_NOLINK; 1361 priv->ieee80211->state = IEEE80211_NOLINK;
1827// pMgntInfo->AsocTimestamp = 0;
1828} 1362}
1829bool 1363bool
1830MgntDisconnect( 1364MgntDisconnect(
@@ -1836,20 +1370,7 @@ MgntDisconnect(
1836 // 1370 //
1837 // Schedule an workitem to wake up for ps mode, 070109, by rcnjko. 1371 // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
1838 // 1372 //
1839#ifdef TODO
1840 if(pMgntInfo->mPss != eAwake)
1841 {
1842 //
1843 // Using AwkaeTimer to prevent mismatch ps state.
1844 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
1845 //
1846 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
1847 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
1848 }
1849#endif
1850 1373
1851 // Indication of disassociation event.
1852 //DrvIFIndicateDisassociation(Adapter, asRsn);
1853 if(IS_DOT11D_ENABLE(priv->ieee80211)) 1374 if(IS_DOT11D_ENABLE(priv->ieee80211))
1854 Dot11d_Reset(priv->ieee80211); 1375 Dot11d_Reset(priv->ieee80211);
1855 // In adhoc mode, update beacon frame. 1376 // In adhoc mode, update beacon frame.
@@ -1857,8 +1378,6 @@ MgntDisconnect(
1857 { 1378 {
1858 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC ) 1379 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
1859 { 1380 {
1860// RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
1861 //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
1862 MgntDisconnectIBSS(dev); 1381 MgntDisconnectIBSS(dev);
1863 } 1382 }
1864 if( priv->ieee80211->iw_mode == IW_MODE_INFRA ) 1383 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
@@ -1868,17 +1387,10 @@ MgntDisconnect(
1868 // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is 1387 // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
1869 // used to handle disassociation related things to AP, e.g. send Disassoc 1388 // used to handle disassociation related things to AP, e.g. send Disassoc
1870 // frame to AP. 2005.01.27, by rcnjko. 1389 // frame to AP. 2005.01.27, by rcnjko.
1871// SecClearAllKeys(Adapter);
1872
1873// RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
1874 //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
1875 MgntDisconnectAP(dev, asRsn); 1390 MgntDisconnectAP(dev, asRsn);
1876 } 1391 }
1877
1878 // Inidicate Disconnect, 2005.02.23, by rcnjko. 1392 // Inidicate Disconnect, 2005.02.23, by rcnjko.
1879// MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
1880 } 1393 }
1881
1882 return true; 1394 return true;
1883} 1395}
1884// 1396//
@@ -1898,10 +1410,8 @@ SetRFPowerState(
1898 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1410 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1899 bool bResult = false; 1411 bool bResult = false;
1900 1412
1901// printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
1902 if(eRFPowerState == priv->eRFPowerState) 1413 if(eRFPowerState == priv->eRFPowerState)
1903 { 1414 {
1904// printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
1905 return bResult; 1415 return bResult;
1906 } 1416 }
1907 1417
@@ -1935,33 +1445,25 @@ MgntActSet_RF_State(
1935 RT_RF_POWER_STATE rtState; 1445 RT_RF_POWER_STATE rtState;
1936 u16 RFWaitCounter = 0; 1446 u16 RFWaitCounter = 0;
1937 unsigned long flag; 1447 unsigned long flag;
1938// printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
1939 // 1448 //
1940 // Prevent the race condition of RF state change. By Bruce, 2007-11-28. 1449 // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
1941 // Only one thread can change the RF state at one time, and others should wait to be executed. 1450 // Only one thread can change the RF state at one time, and others should wait to be executed.
1942 // 1451 //
1943#if 1
1944 while(true) 1452 while(true)
1945 { 1453 {
1946// down(&priv->rf_state);
1947 spin_lock_irqsave(&priv->rf_ps_lock,flag); 1454 spin_lock_irqsave(&priv->rf_ps_lock,flag);
1948 if(priv->RFChangeInProgress) 1455 if(priv->RFChangeInProgress)
1949 { 1456 {
1950// printk("====================>haha111111111\n");
1951// up(&priv->rf_state);
1952// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
1953 spin_unlock_irqrestore(&priv->rf_ps_lock,flag); 1457 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
1954 // Set RF after the previous action is done. 1458 // Set RF after the previous action is done.
1955 while(priv->RFChangeInProgress) 1459 while(priv->RFChangeInProgress)
1956 { 1460 {
1957 RFWaitCounter ++; 1461 RFWaitCounter ++;
1958// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
1959 udelay(1000); // 1 ms 1462 udelay(1000); // 1 ms
1960 1463
1961 // Wait too long, return FALSE to avoid to be stuck here. 1464 // Wait too long, return FALSE to avoid to be stuck here.
1962 if(RFWaitCounter > 1000) // 1sec 1465 if(RFWaitCounter > 1000) // 1sec
1963 { 1466 {
1964// RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
1965 printk("MgntActSet_RF_State(): Wait too long to set RF\n"); 1467 printk("MgntActSet_RF_State(): Wait too long to set RF\n");
1966 // TODO: Reset RF state? 1468 // TODO: Reset RF state?
1967 return false; 1469 return false;
@@ -1970,17 +1472,13 @@ MgntActSet_RF_State(
1970 } 1472 }
1971 else 1473 else
1972 { 1474 {
1973// printk("========================>haha2\n");
1974 priv->RFChangeInProgress = true; 1475 priv->RFChangeInProgress = true;
1975// up(&priv->rf_state);
1976 spin_unlock_irqrestore(&priv->rf_ps_lock,flag); 1476 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
1977 break; 1477 break;
1978 } 1478 }
1979 } 1479 }
1980#endif
1981 rtState = priv->eRFPowerState; 1480 rtState = priv->eRFPowerState;
1982 1481
1983
1984 switch(StateToSet) 1482 switch(StateToSet)
1985 { 1483 {
1986 case eRfOn: 1484 case eRfOn:
@@ -2001,7 +1499,6 @@ MgntActSet_RF_State(
2001 } 1499 }
2002 } 1500 }
2003 else 1501 else
2004// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2005 ; 1502 ;
2006 break; 1503 break;
2007 1504
@@ -2018,38 +1515,26 @@ MgntActSet_RF_State(
2018 // 1515 //
2019 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(), 1516 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2020 // because we do NOT need to set ssid to dummy ones. 1517 // because we do NOT need to set ssid to dummy ones.
2021 // Revised by Roger, 2007.12.04.
2022 // 1518 //
2023 MgntDisconnect( dev, disas_lv_ss ); 1519 MgntDisconnect( dev, disas_lv_ss );
2024 1520
2025 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI. 1521 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2026 // 2007.05.28, by shien chang.
2027// PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2028// pMgntInfo->NumBssDesc = 0;
2029// PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2030// pMgntInfo->NumBssDesc4Query = 0;
2031 } 1522 }
2032 1523
2033
2034
2035 priv->RfOffReason |= ChangeSource; 1524 priv->RfOffReason |= ChangeSource;
2036 bActionAllowed = true; 1525 bActionAllowed = true;
2037 break; 1526 break;
2038
2039 case eRfSleep: 1527 case eRfSleep:
2040 priv->RfOffReason |= ChangeSource; 1528 priv->RfOffReason |= ChangeSource;
2041 bActionAllowed = true; 1529 bActionAllowed = true;
2042 break; 1530 break;
2043
2044 default: 1531 default:
2045 break; 1532 break;
2046 } 1533 }
2047 1534
2048 if(bActionAllowed) 1535 if(bActionAllowed)
2049 { 1536 {
2050// RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2051 // Config HW to the specified mode. 1537 // Config HW to the specified mode.
2052// printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2053 SetRFPowerState(dev, StateToSet); 1538 SetRFPowerState(dev, StateToSet);
2054 1539
2055 // Turn on RF. 1540 // Turn on RF.
@@ -2059,7 +1544,6 @@ MgntActSet_RF_State(
2059 if(bConnectBySSID) 1544 if(bConnectBySSID)
2060 { 1545 {
2061 // by amy not supported 1546 // by amy not supported
2062// MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2063 } 1547 }
2064 } 1548 }
2065 // Turn off RF. 1549 // Turn off RF.
@@ -2068,18 +1552,11 @@ MgntActSet_RF_State(
2068 HalDisableRx8185Dummy(dev); 1552 HalDisableRx8185Dummy(dev);
2069 } 1553 }
2070 } 1554 }
2071 else
2072 {
2073 // printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2074 }
2075 1555
2076 // Release RF spinlock 1556 // Release RF spinlock
2077// down(&priv->rf_state);
2078 spin_lock_irqsave(&priv->rf_ps_lock,flag); 1557 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2079 priv->RFChangeInProgress = false; 1558 priv->RFChangeInProgress = false;
2080// up(&priv->rf_state);
2081 spin_unlock_irqrestore(&priv->rf_ps_lock,flag); 1559 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2082// printk("<===MgntActSet_RF_State()\n");
2083 return bActionAllowed; 1560 return bActionAllowed;
2084} 1561}
2085void 1562void
@@ -2088,15 +1565,12 @@ InactivePowerSave(
2088 ) 1565 )
2089{ 1566{
2090 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1567 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2091 //u8 index = 0;
2092
2093 // 1568 //
2094 // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem 1569 // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2095 // is really scheduled. 1570 // is really scheduled.
2096 // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the 1571 // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2097 // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing 1572 // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2098 // blocks the IPS procedure of switching RF. 1573 // blocks the IPS procedure of switching RF.
2099 // By Bruce, 2007-12-25.
2100 // 1574 //
2101 priv->bSwRfProcessing = true; 1575 priv->bSwRfProcessing = true;
2102 1576
@@ -2112,7 +1586,6 @@ InactivePowerSave(
2112// 1586//
2113// Description: 1587// Description:
2114// Enter the inactive power save mode. RF will be off 1588// Enter the inactive power save mode. RF will be off
2115// 2007.08.17, by shien chang.
2116// 1589//
2117void 1590void
2118IPSEnter( 1591IPSEnter(
@@ -2121,13 +1594,11 @@ IPSEnter(
2121{ 1594{
2122 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1595 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2123 RT_RF_POWER_STATE rtState; 1596 RT_RF_POWER_STATE rtState;
2124 //printk("==============================>enter IPS\n");
2125 if (priv->bInactivePs) 1597 if (priv->bInactivePs)
2126 { 1598 {
2127 rtState = priv->eRFPowerState; 1599 rtState = priv->eRFPowerState;
2128 1600
2129 // 1601 //
2130 // Added by Bruce, 2007-12-25.
2131 // Do not enter IPS in the following conditions: 1602 // Do not enter IPS in the following conditions:
2132 // (1) RF is already OFF or Sleep 1603 // (1) RF is already OFF or Sleep
2133 // (2) bSwRfProcessing (indicates the IPS is still under going) 1604 // (2) bSwRfProcessing (indicates the IPS is still under going)
@@ -2138,12 +1609,10 @@ IPSEnter(
2138 if (rtState == eRfOn && !priv->bSwRfProcessing 1609 if (rtState == eRfOn && !priv->bSwRfProcessing
2139 && (priv->ieee80211->state != IEEE80211_LINKED )) 1610 && (priv->ieee80211->state != IEEE80211_LINKED ))
2140 { 1611 {
2141 // printk("IPSEnter(): Turn off RF.\n");
2142 priv->eInactivePowerState = eRfOff; 1612 priv->eInactivePowerState = eRfOff;
2143 InactivePowerSave(dev); 1613 InactivePowerSave(dev);
2144 } 1614 }
2145 } 1615 }
2146// printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2147} 1616}
2148void 1617void
2149IPSLeave( 1618IPSLeave(
@@ -2152,20 +1621,17 @@ IPSLeave(
2152{ 1621{
2153 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1622 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2154 RT_RF_POWER_STATE rtState; 1623 RT_RF_POWER_STATE rtState;
2155 //printk("===================================>leave IPS\n");
2156 if (priv->bInactivePs) 1624 if (priv->bInactivePs)
2157 { 1625 {
2158 rtState = priv->eRFPowerState; 1626 rtState = priv->eRFPowerState;
2159 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS) 1627 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2160 { 1628 {
2161// printk("IPSLeave(): Turn on RF.\n");
2162 priv->eInactivePowerState = eRfOn; 1629 priv->eInactivePowerState = eRfOn;
2163 InactivePowerSave(dev); 1630 InactivePowerSave(dev);
2164 } 1631 }
2165 } 1632 }
2166// printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2167} 1633}
2168//by amy for power save 1634
2169void rtl8185b_adapter_start(struct net_device *dev) 1635void rtl8185b_adapter_start(struct net_device *dev)
2170{ 1636{
2171 struct r8180_priv *priv = ieee80211_priv(dev); 1637 struct r8180_priv *priv = ieee80211_priv(dev);
@@ -2174,75 +1640,45 @@ void rtl8185b_adapter_start(struct net_device *dev)
2174 u8 SupportedWirelessMode; 1640 u8 SupportedWirelessMode;
2175 u8 InitWirelessMode; 1641 u8 InitWirelessMode;
2176 u8 bInvalidWirelessMode = 0; 1642 u8 bInvalidWirelessMode = 0;
2177 //int i;
2178 u8 tmpu8; 1643 u8 tmpu8;
2179 //u8 u1tmp,u2tmp;
2180 u8 btCR9346; 1644 u8 btCR9346;
2181 u8 TmpU1b; 1645 u8 TmpU1b;
2182 u8 btPSR; 1646 u8 btPSR;
2183 1647
2184 //rtl8180_rtx_disable(dev);
2185//{by amy 080312
2186 write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0)); 1648 write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2187//by amy 080312}
2188 rtl8180_reset(dev); 1649 rtl8180_reset(dev);
2189 1650
2190 priv->dma_poll_mask = 0; 1651 priv->dma_poll_mask = 0;
2191 priv->dma_poll_stop_mask = 0; 1652 priv->dma_poll_stop_mask = 0;
2192 1653
2193 //rtl8180_beacon_tx_disable(dev);
2194
2195 HwConfigureRTL8185(dev); 1654 HwConfigureRTL8185(dev);
2196
2197 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]); 1655 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2198 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff ); 1656 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2199
2200 write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); // default network type to 'No Link' 1657 write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); // default network type to 'No Link'
2201
2202 //write_nic_byte(dev, BRSR, 0x0); // Set BRSR= 1M
2203
2204 write_nic_word(dev, BcnItv, 100); 1658 write_nic_word(dev, BcnItv, 100);
2205 write_nic_word(dev, AtimWnd, 2); 1659 write_nic_word(dev, AtimWnd, 2);
2206
2207 //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2208 PlatformIOWrite2Byte(dev, FEMR, 0xFFFF); 1660 PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2209
2210 write_nic_byte(dev, WPA_CONFIG, 0); 1661 write_nic_byte(dev, WPA_CONFIG, 0);
2211
2212 MacConfig_85BASIC(dev); 1662 MacConfig_85BASIC(dev);
2213
2214 // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko. 1663 // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2215 // BT_DEMO_BOARD type 1664 // BT_DEMO_BOARD type
2216 PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a); 1665 PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2217//by amy
2218//#ifdef CONFIG_RTL818X_S
2219 // for jong required
2220// PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2221//#endif
2222//by amy
2223 //BT_QA_BOARD
2224 //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2225 1666
2226 //----------------------------------------------------------------------------- 1667 //-----------------------------------------------------------------------------
2227 // Set up PHY related. 1668 // Set up PHY related.
2228 //----------------------------------------------------------------------------- 1669 //-----------------------------------------------------------------------------
2229 // Enable Config3.PARAM_En to revise AnaaParm. 1670 // Enable Config3.PARAM_En to revise AnaaParm.
2230 write_nic_byte(dev, CR9346, 0xc0); // enable config register write 1671 write_nic_byte(dev, CR9346, 0xc0); // enable config register write
2231//by amy
2232 tmpu8 = read_nic_byte(dev, CONFIG3); 1672 tmpu8 = read_nic_byte(dev, CONFIG3);
2233 write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) ); 1673 write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2234//by amy
2235 // Turn on Analog power. 1674 // Turn on Analog power.
2236 // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko. 1675 // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2237 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON); 1676 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2238 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON); 1677 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2239//by amy
2240 write_nic_word(dev, ANAPARAM3, 0x0010); 1678 write_nic_word(dev, ANAPARAM3, 0x0010);
2241//by amy
2242 1679
2243 write_nic_byte(dev, CONFIG3, tmpu8); 1680 write_nic_byte(dev, CONFIG3, tmpu8);
2244 write_nic_byte(dev, CR9346, 0x00); 1681 write_nic_byte(dev, CR9346, 0x00);
2245//{by amy 080312 for led
2246 // enable EEM0 and EEM1 in 9346CR 1682 // enable EEM0 and EEM1 in 9346CR
2247 btCR9346 = read_nic_byte(dev, CR9346); 1683 btCR9346 = read_nic_byte(dev, CR9346);
2248 write_nic_byte(dev, CR9346, (btCR9346|0xC0) ); 1684 write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
@@ -2260,7 +1696,6 @@ void rtl8185b_adapter_start(struct net_device *dev)
2260 // B-cut RF Radio on/off 5e[3]=0 1696 // B-cut RF Radio on/off 5e[3]=0
2261 btPSR = read_nic_byte(dev, PSR); 1697 btPSR = read_nic_byte(dev, PSR);
2262 write_nic_byte(dev, PSR, (btPSR | BIT3)); 1698 write_nic_byte(dev, PSR, (btPSR | BIT3));
2263//by amy 080312 for led}
2264 // setup initial timing for RFE. 1699 // setup initial timing for RFE.
2265 write_nic_word(dev, RFPinsOutput, 0x0480); 1700 write_nic_word(dev, RFPinsOutput, 0x0480);
2266 SetOutputEnableOfRfPins(dev); 1701 SetOutputEnableOfRfPins(dev);
@@ -2323,55 +1758,19 @@ void rtl8185b_adapter_start(struct net_device *dev)
2323 InitWirelessMode = ieee->mode; 1758 InitWirelessMode = ieee->mode;
2324 } 1759 }
2325//by amy for power save 1760//by amy for power save
2326// printk("initialize ENABLE_IPS\n");
2327 priv->eRFPowerState = eRfOff; 1761 priv->eRFPowerState = eRfOff;
2328 priv->RfOffReason = 0; 1762 priv->RfOffReason = 0;
2329 { 1763 {
2330 // u32 tmp2;
2331 // u32 tmp = jiffies;
2332 MgntActSet_RF_State(dev, eRfOn, 0); 1764 MgntActSet_RF_State(dev, eRfOn, 0);
2333 // tmp2 = jiffies;
2334 // printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2335 } 1765 }
2336// DrvIFIndicateCurrentPhyStatus(priv);
2337 // 1766 //
2338 // If inactive power mode is enabled, disable rf while in disconnected state. 1767 // If inactive power mode is enabled, disable rf while in disconnected state.
2339 // 2007.07.16, by shien chang.
2340 // 1768 //
2341 if (priv->bInactivePs) 1769 if (priv->bInactivePs)
2342 { 1770 {
2343 // u32 tmp2;
2344 // u32 tmp = jiffies;
2345 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS); 1771 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
2346 // tmp2 = jiffies;
2347 // printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2348
2349 } 1772 }
2350// IPSEnter(dev);
2351//by amy for power save 1773//by amy for power save
2352#ifdef TODO
2353 // Turn off RF if necessary. 2005.08.23, by rcnjko.
2354 // We shall turn off RF after setting CMDR, otherwise,
2355 // RF will be turnned on after we enable MAC Tx/Rx.
2356 if(Adapter->MgntInfo.RegRfOff == TRUE)
2357 {
2358 SetRFPowerState8185(Adapter, RF_OFF);
2359 }
2360 else
2361 {
2362 SetRFPowerState8185(Adapter, RF_ON);
2363 }
2364#endif
2365
2366/* //these is equal with above TODO.
2367 write_nic_byte(dev, CR9346, 0xc0); // enable config register write
2368 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
2369 RF_WriteReg(dev, 0x4, 0x9FF);
2370 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2371 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2372 write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
2373 write_nic_byte(dev, CR9346, 0x00);
2374*/
2375 1774
2376 ActSetWirelessMode8185(dev, (u8)(InitWirelessMode)); 1775 ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
2377 1776
@@ -2380,14 +1779,11 @@ void rtl8185b_adapter_start(struct net_device *dev)
2380 rtl8185b_irq_enable(dev); 1779 rtl8185b_irq_enable(dev);
2381 1780
2382 netif_start_queue(dev); 1781 netif_start_queue(dev);
2383
2384 } 1782 }
2385 1783
2386
2387void rtl8185b_rx_enable(struct net_device *dev) 1784void rtl8185b_rx_enable(struct net_device *dev)
2388{ 1785{
2389 u8 cmd; 1786 u8 cmd;
2390 //u32 rxconf;
2391 /* for now we accept data, management & ctl frame*/ 1787 /* for now we accept data, management & ctl frame*/
2392 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1788 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2393 1789
@@ -2399,11 +1795,6 @@ void rtl8185b_rx_enable(struct net_device *dev)
2399 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP; 1795 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
2400 } 1796 }
2401 1797
2402 /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
2403 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2404 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2405 }*/
2406
2407 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){ 1798 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2408 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV; 1799 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
2409 } 1800 }
@@ -2415,9 +1806,6 @@ void rtl8185b_rx_enable(struct net_device *dev)
2415 1806
2416 fix_rx_fifo(dev); 1807 fix_rx_fifo(dev);
2417 1808
2418#ifdef DEBUG_RX
2419 DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
2420#endif
2421 cmd=read_nic_byte(dev,CMD); 1809 cmd=read_nic_byte(dev,CMD);
2422 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT)); 1810 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
2423 1811
@@ -2426,9 +1814,7 @@ void rtl8185b_rx_enable(struct net_device *dev)
2426void rtl8185b_tx_enable(struct net_device *dev) 1814void rtl8185b_tx_enable(struct net_device *dev)
2427{ 1815{
2428 u8 cmd; 1816 u8 cmd;
2429 //u8 tx_agc_ctl;
2430 u8 byte; 1817 u8 byte;
2431 //u32 txconf;
2432 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); 1818 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2433 1819
2434 write_nic_dword(dev, TCR, priv->TransmitConfig); 1820 write_nic_dword(dev, TCR, priv->TransmitConfig);
@@ -2438,21 +1824,7 @@ void rtl8185b_tx_enable(struct net_device *dev)
2438 1824
2439 fix_tx_fifo(dev); 1825 fix_tx_fifo(dev);
2440 1826
2441#ifdef DEBUG_TX
2442 DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
2443#endif
2444
2445 cmd=read_nic_byte(dev,CMD); 1827 cmd=read_nic_byte(dev,CMD);
2446 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT)); 1828 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
2447
2448 //write_nic_dword(dev,TX_CONF,txconf);
2449
2450
2451/*
2452 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2453 write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
2454 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
2455 */
2456} 1829}
2457 1830
2458