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authorAlan Cox <alan@linux.intel.com>2011-07-15 12:35:36 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-07-15 13:05:08 -0400
commit3caa89e933646263cb4efedd5660dba00a107b51 (patch)
tree79fc0790523e21665c231244ea1855b51c9d9f12 /drivers/staging
parentf75c7538c5ee3bfd0ac50d20457e773c43858a75 (diff)
gma500: resync with Medfield progress
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging')
-rw-r--r--drivers/staging/gma500/mdfld_dsi_dbi.c369
-rw-r--r--drivers/staging/gma500/mdfld_dsi_dbi.h21
-rw-r--r--drivers/staging/gma500/mdfld_dsi_dbi_dpu.h3
-rw-r--r--drivers/staging/gma500/mdfld_dsi_dpi.c319
-rw-r--r--drivers/staging/gma500/mdfld_dsi_dpi.h6
-rw-r--r--drivers/staging/gma500/mdfld_dsi_output.c250
-rw-r--r--drivers/staging/gma500/mdfld_dsi_output.h203
-rw-r--r--drivers/staging/gma500/mdfld_dsi_pkg_sender.c403
-rw-r--r--drivers/staging/gma500/mdfld_dsi_pkg_sender.h26
-rw-r--r--drivers/staging/gma500/mdfld_intel_display.c6
-rw-r--r--drivers/staging/gma500/mdfld_output.c8
-rw-r--r--drivers/staging/gma500/mdfld_output.h41
-rw-r--r--drivers/staging/gma500/mdfld_pyr_cmd.c18
-rw-r--r--drivers/staging/gma500/mdfld_tmd_vid.c62
-rw-r--r--drivers/staging/gma500/mdfld_tpo_cmd.c64
-rw-r--r--drivers/staging/gma500/mrst_lvds.c35
-rw-r--r--drivers/staging/gma500/psb_drv.h7
17 files changed, 917 insertions, 924 deletions
diff --git a/drivers/staging/gma500/mdfld_dsi_dbi.c b/drivers/staging/gma500/mdfld_dsi_dbi.c
index 1421f497d0a..06424f945bc 100644
--- a/drivers/staging/gma500/mdfld_dsi_dbi.c
+++ b/drivers/staging/gma500/mdfld_dsi_dbi.c
@@ -39,29 +39,10 @@ extern int gfxrtdelay;
39int enter_dsr; 39int enter_dsr;
40struct mdfld_dsi_dbi_output *gdbi_output; 40struct mdfld_dsi_dbi_output *gdbi_output;
41extern bool gbgfxsuspended; 41extern bool gbgfxsuspended;
42extern int enable_gfx_rtpm;
42extern int gfxrtdelay; 43extern int gfxrtdelay;
43 44
44#ifdef CONFIG_GFX_RTPM 45#define MDFLD_DSR_MAX_IDLE_COUNT 2
45static void psb_runtimepm_wq_handler(struct work_struct *work);
46DECLARE_DELAYED_WORK(rtpm_work, psb_runtimepm_wq_handler);
47
48void psb_runtimepm_wq_handler(struct work_struct *work)
49{
50 struct drm_psb_private *dev_priv = gpDrmDevice->dev_private;
51
52 if (drm_psb_ospm && !enable_gfx_rtpm) {
53 pr_info("Enable GFX runtime_pm\n");
54 dev_priv->rpm_enabled = 1;
55 enable_gfx_rtpm = 1;
56
57 pm_runtime_enable(&gpDrmDevice->pdev->dev);
58 pm_runtime_set_active(&gpDrmDevice->pdev->dev);
59
60 pm_runtime_allow(&gpDrmDevice->pdev->dev);
61 }
62}
63#endif
64
65 46
66/* 47/*
67 * set refreshing area 48 * set refreshing area
@@ -80,8 +61,8 @@ int mdfld_dsi_dbi_update_area(struct mdfld_dsi_dbi_output *dbi_output,
80 return -EINVAL; 61 return -EINVAL;
81 } 62 }
82 63
83 /*set column*/ 64 /* Set column */
84 cmd = set_column_address; 65 cmd = DCS_SET_COLUMN_ADDRESS;
85 param[0] = x1 >> 8; 66 param[0] = x1 >> 8;
86 param[1] = x1; 67 param[1] = x1;
87 param[2] = x2 >> 8; 68 param[2] = x2 >> 8;
@@ -98,8 +79,8 @@ int mdfld_dsi_dbi_update_area(struct mdfld_dsi_dbi_output *dbi_output,
98 goto err_out; 79 goto err_out;
99 } 80 }
100 81
101 /*set page*/ 82 /* Set page */
102 cmd = set_page_addr; 83 cmd = DCS_SET_PAGE_ADDRESS;
103 param[0] = y1 >> 8; 84 param[0] = y1 >> 8;
104 param[1] = y1; 85 param[1] = y1;
105 param[2] = y2 >> 8; 86 param[2] = y2 >> 8;
@@ -139,56 +120,46 @@ int mdfld_dsi_dbi_update_power(struct mdfld_dsi_dbi_output *dbi_output,
139 int mode) 120 int mode)
140{ 121{
141 struct drm_device *dev = dbi_output->dev; 122 struct drm_device *dev = dbi_output->dev;
142 struct drm_psb_private *dev_priv = dev->dev_private;
143 struct mdfld_dsi_pkg_sender *sender = 123 struct mdfld_dsi_pkg_sender *sender =
144 mdfld_dsi_encoder_get_pkg_sender(&dbi_output->base); 124 mdfld_dsi_encoder_get_pkg_sender(&dbi_output->base);
145 u8 param = 0; 125 u8 param = 0;
146 u32 err = 0; 126 u32 err = 0;
147 127
148 if (!dev_priv->dispstatus && mode != DRM_MODE_DPMS_ON) {
149 dev_err(dev->dev, "%s: already OFF ignoring\n", __func__);
150 return 0;
151 }
152 if (dev_priv->dispstatus && mode == DRM_MODE_DPMS_ON) {
153 dev_err(dev->dev, "%s: already ON ignoring\n", __func__);
154 return 0;
155 }
156
157 if (!sender) { 128 if (!sender) {
158 WARN_ON(1); 129 WARN_ON(1);
159 return -EINVAL; 130 return -EINVAL;
160 } 131 }
161 132
162 if (mode == DRM_MODE_DPMS_ON) { 133 if (mode == DRM_MODE_DPMS_ON) {
163 /*exit sleep mode*/ 134 /* Exit sleep mode */
164 err = mdfld_dsi_send_dcs(sender, 135 err = mdfld_dsi_send_dcs(sender,
165 exit_sleep_mode, 136 DCS_EXIT_SLEEP_MODE,
166 NULL, 137 NULL,
167 0, 138 0,
168 CMD_DATA_SRC_SYSTEM_MEM, 139 CMD_DATA_SRC_SYSTEM_MEM,
169 MDFLD_DSI_QUEUE_PACKAGE); 140 MDFLD_DSI_QUEUE_PACKAGE);
170 if (err) { 141 if (err) {
171 dev_err(dev->dev, "DCS 0x%x sent failed\n", 142 dev_err(dev->dev, "DCS 0x%x sent failed\n",
172 exit_sleep_mode); 143 DCS_EXIT_SLEEP_MODE);
173 goto power_err; 144 goto power_err;
174 } 145 }
175 146
176 /*set display on*/ 147 /* Set display on */
177 err = mdfld_dsi_send_dcs(sender, 148 err = mdfld_dsi_send_dcs(sender,
178 set_display_on, 149 DCS_SET_DISPLAY_ON,
179 NULL, 150 NULL,
180 0, 151 0,
181 CMD_DATA_SRC_SYSTEM_MEM, 152 CMD_DATA_SRC_SYSTEM_MEM,
182 MDFLD_DSI_QUEUE_PACKAGE); 153 MDFLD_DSI_QUEUE_PACKAGE);
183 if (err) { 154 if (err) {
184 dev_err(dev->dev, "DCS 0x%x sent failed\n", 155 dev_err(dev->dev, "DCS 0x%x sent failed\n",
185 set_display_on); 156 DCS_SET_DISPLAY_ON);
186 goto power_err; 157 goto power_err;
187 } 158 }
188 159
189 /* set tear effect on */ 160 /* set tear effect on */
190 err = mdfld_dsi_send_dcs(sender, 161 err = mdfld_dsi_send_dcs(sender,
191 set_tear_on, 162 DCS_SET_TEAR_ON,
192 &param, 163 &param,
193 1, 164 1,
194 CMD_DATA_SRC_SYSTEM_MEM, 165 CMD_DATA_SRC_SYSTEM_MEM,
@@ -203,53 +174,53 @@ int mdfld_dsi_dbi_update_power(struct mdfld_dsi_dbi_output *dbi_output,
203 * FIXME: remove this later 174 * FIXME: remove this later
204 */ 175 */
205 err = mdfld_dsi_send_dcs(sender, 176 err = mdfld_dsi_send_dcs(sender,
206 write_mem_start, 177 DCS_WRITE_MEM_START,
207 NULL, 178 NULL,
208 0, 179 0,
209 CMD_DATA_SRC_PIPE, 180 CMD_DATA_SRC_PIPE,
210 MDFLD_DSI_QUEUE_PACKAGE); 181 MDFLD_DSI_QUEUE_PACKAGE);
211 if (err) { 182 if (err) {
212 dev_err(dev->dev, "DCS 0x%x sent failed\n", 183 dev_err(dev->dev, "DCS 0x%x sent failed\n",
213 set_display_on); 184 DCS_WRITE_MEM_START);
214 goto power_err; 185 goto power_err;
215 } 186 }
216 } else { 187 } else {
217 /*set tear effect off */ 188 /* Set tear effect off */
218 err = mdfld_dsi_send_dcs(sender, 189 err = mdfld_dsi_send_dcs(sender,
219 set_tear_off, 190 DCS_SET_TEAR_OFF,
220 NULL, 191 NULL,
221 0, 192 0,
222 CMD_DATA_SRC_SYSTEM_MEM, 193 CMD_DATA_SRC_SYSTEM_MEM,
223 MDFLD_DSI_QUEUE_PACKAGE); 194 MDFLD_DSI_QUEUE_PACKAGE);
224 if (err) { 195 if (err) {
225 dev_err(dev->dev, "DCS 0x%x sent failed\n", 196 dev_err(dev->dev, "DCS 0x%x sent failed\n",
226 set_tear_off); 197 DCS_SET_TEAR_OFF);
227 goto power_err; 198 goto power_err;
228 } 199 }
229 200
230 /*set display off*/ 201 /* Turn display off */
231 err = mdfld_dsi_send_dcs(sender, 202 err = mdfld_dsi_send_dcs(sender,
232 set_display_off, 203 DCS_SET_DISPLAY_OFF,
233 NULL, 204 NULL,
234 0, 205 0,
235 CMD_DATA_SRC_SYSTEM_MEM, 206 CMD_DATA_SRC_SYSTEM_MEM,
236 MDFLD_DSI_QUEUE_PACKAGE); 207 MDFLD_DSI_QUEUE_PACKAGE);
237 if (err) { 208 if (err) {
238 dev_err(dev->dev, "DCS 0x%x sent failed\n", 209 dev_err(dev->dev, "DCS 0x%x sent failed\n",
239 set_display_off); 210 DCS_SET_DISPLAY_OFF);
240 goto power_err; 211 goto power_err;
241 } 212 }
242 213
243 /*enter sleep mode*/ 214 /* Now enter sleep mode */
244 err = mdfld_dsi_send_dcs(sender, 215 err = mdfld_dsi_send_dcs(sender,
245 enter_sleep_mode, 216 DCS_ENTER_SLEEP_MODE,
246 NULL, 217 NULL,
247 0, 218 0,
248 CMD_DATA_SRC_SYSTEM_MEM, 219 CMD_DATA_SRC_SYSTEM_MEM,
249 MDFLD_DSI_QUEUE_PACKAGE); 220 MDFLD_DSI_QUEUE_PACKAGE);
250 if (err) { 221 if (err) {
251 dev_err(dev->dev, "DCS 0x%x sent failed\n", 222 dev_err(dev->dev, "DCS 0x%x sent failed\n",
252 enter_sleep_mode); 223 DCS_ENTER_SLEEP_MODE);
253 goto power_err; 224 goto power_err;
254 } 225 }
255 } 226 }
@@ -283,7 +254,6 @@ int mdfld_dsi_dbi_send_dcs(struct mdfld_dsi_dbi_output *dbi_output,
283 return ret; 254 return ret;
284} 255}
285 256
286
287/* 257/*
288 * Enter DSR 258 * Enter DSR
289 */ 259 */
@@ -299,11 +269,12 @@ void mdfld_dsi_dbi_enter_dsr(struct mdfld_dsi_dbi_output *dbi_output, int pipe)
299 u32 pipeconf_reg = PIPEACONF; 269 u32 pipeconf_reg = PIPEACONF;
300 u32 dspcntr_reg = DSPACNTR; 270 u32 dspcntr_reg = DSPACNTR;
301 271
302 dev_priv->is_in_idle = true;
303
304 if (!dbi_output) 272 if (!dbi_output)
305 return; 273 return;
306 274
275 /* FIXME check if can go */
276 dev_priv->is_in_idle = true;
277
307 gdbi_output = dbi_output; 278 gdbi_output = dbi_output;
308 if ((dbi_output->mode_flags & MODE_SETTING_ON_GOING) || 279 if ((dbi_output->mode_flags & MODE_SETTING_ON_GOING) ||
309 (psb_crtc && psb_crtc->mode_flags & MODE_SETTING_ON_GOING)) 280 (psb_crtc && psb_crtc->mode_flags & MODE_SETTING_ON_GOING))
@@ -319,16 +290,17 @@ void mdfld_dsi_dbi_enter_dsr(struct mdfld_dsi_dbi_output *dbi_output, int pipe)
319 dev_err(dev->dev, "hw begin failed\n"); 290 dev_err(dev->dev, "hw begin failed\n");
320 return; 291 return;
321 } 292 }
322 /*disable te interrupts. */ 293 /* Disable te interrupts */
323 mdfld_disable_te(dev, pipe); 294 mdfld_disable_te(dev, pipe);
324 295
325 /*disable plane*/ 296 /* Disable plane */
326 reg_val = REG_READ(dspcntr_reg); 297 reg_val = REG_READ(dspcntr_reg);
327 if (!(reg_val & DISPLAY_PLANE_ENABLE)) { 298 if (!(reg_val & DISPLAY_PLANE_ENABLE)) {
328 REG_WRITE(dspcntr_reg, reg_val & ~DISPLAY_PLANE_ENABLE); 299 REG_WRITE(dspcntr_reg, reg_val & ~DISPLAY_PLANE_ENABLE);
329 REG_READ(dspcntr_reg); 300 REG_READ(dspcntr_reg);
330 } 301 }
331 /*disable pipe*/ 302
303 /* Disable pipe */
332 reg_val = REG_READ(pipeconf_reg); 304 reg_val = REG_READ(pipeconf_reg);
333 if (!(reg_val & DISPLAY_PLANE_ENABLE)) { 305 if (!(reg_val & DISPLAY_PLANE_ENABLE)) {
334 reg_val &= ~DISPLAY_PLANE_ENABLE; 306 reg_val &= ~DISPLAY_PLANE_ENABLE;
@@ -338,7 +310,7 @@ void mdfld_dsi_dbi_enter_dsr(struct mdfld_dsi_dbi_output *dbi_output, int pipe)
338 mdfldWaitForPipeDisable(dev, pipe); 310 mdfldWaitForPipeDisable(dev, pipe);
339 } 311 }
340 312
341 /*disable DPLL*/ 313 /* Disable DPLL */
342 reg_val = REG_READ(dpll_reg); 314 reg_val = REG_READ(dpll_reg);
343 if (!(reg_val & DPLL_VCO_ENABLE)) { 315 if (!(reg_val & DPLL_VCO_ENABLE)) {
344 reg_val &= ~DPLL_VCO_ENABLE; 316 reg_val &= ~DPLL_VCO_ENABLE;
@@ -357,10 +329,9 @@ void mdfld_dsi_dbi_enter_dsr(struct mdfld_dsi_dbi_output *dbi_output, int pipe)
357 329
358#ifndef CONFIG_MDFLD_DSI_DPU 330#ifndef CONFIG_MDFLD_DSI_DPU
359static void mdfld_dbi_output_exit_dsr(struct mdfld_dsi_dbi_output *dbi_output, 331static void mdfld_dbi_output_exit_dsr(struct mdfld_dsi_dbi_output *dbi_output,
360 int pipe, void *p_surfaceAddr, bool check_hw_on_only) 332 int pipe)
361{ 333{
362 struct drm_device *dev = dbi_output->dev; 334 struct drm_device *dev = dbi_output->dev;
363 struct drm_psb_private *dev_priv = dev->dev_private;
364 struct drm_crtc *crtc = dbi_output->base.base.crtc; 335 struct drm_crtc *crtc = dbi_output->base.base.crtc;
365 struct psb_intel_crtc *psb_crtc = (crtc) ? 336 struct psb_intel_crtc *psb_crtc = (crtc) ?
366 to_psb_intel_crtc(crtc) : NULL; 337 to_psb_intel_crtc(crtc) : NULL;
@@ -368,7 +339,6 @@ static void mdfld_dbi_output_exit_dsr(struct mdfld_dsi_dbi_output *dbi_output,
368 u32 dpll_reg = MRST_DPLL_A; 339 u32 dpll_reg = MRST_DPLL_A;
369 u32 pipeconf_reg = PIPEACONF; 340 u32 pipeconf_reg = PIPEACONF;
370 u32 dspcntr_reg = DSPACNTR; 341 u32 dspcntr_reg = DSPACNTR;
371 u32 dspsurf_reg = DSPASURF;
372 u32 reg_offset = 0; 342 u32 reg_offset = 0;
373 343
374 /*if mode setting on-going, back off*/ 344 /*if mode setting on-going, back off*/
@@ -380,24 +350,17 @@ static void mdfld_dbi_output_exit_dsr(struct mdfld_dsi_dbi_output *dbi_output,
380 dpll_reg = MRST_DPLL_A; 350 dpll_reg = MRST_DPLL_A;
381 pipeconf_reg = PIPECCONF; 351 pipeconf_reg = PIPECCONF;
382 dspcntr_reg = DSPCCNTR; 352 dspcntr_reg = DSPCCNTR;
383 dspsurf_reg = DSPCSURF;
384 reg_offset = MIPIC_REG_OFFSET; 353 reg_offset = MIPIC_REG_OFFSET;
385 } 354 }
386 355
387 if (check_hw_on_only) { 356 if (!gma_power_begin(dev, true)) {
388 if (0/* FIXME!ospm_power_is_hw_on(_DISPLAY_ISLAND)*/) {
389 dev_err(dev->dev, "hw begin failed\n");
390 return;
391 }
392 } else if (!gma_power_begin(dev, true)) {
393 dev_err(dev->dev, "hw begin failed\n"); 357 dev_err(dev->dev, "hw begin failed\n");
394 return; 358 return;
395 } 359 }
396 360
397 /*enable DPLL*/ 361 /* Enable DPLL */
398 reg_val = REG_READ(dpll_reg); 362 reg_val = REG_READ(dpll_reg);
399 if (!(reg_val & DPLL_VCO_ENABLE)) { 363 if (!(reg_val & DPLL_VCO_ENABLE)) {
400
401 if (reg_val & MDFLD_PWR_GATE_EN) { 364 if (reg_val & MDFLD_PWR_GATE_EN) {
402 reg_val &= ~MDFLD_PWR_GATE_EN; 365 reg_val &= ~MDFLD_PWR_GATE_EN;
403 REG_WRITE(dpll_reg, reg_val); 366 REG_WRITE(dpll_reg, reg_val);
@@ -415,7 +378,7 @@ static void mdfld_dbi_output_exit_dsr(struct mdfld_dsi_dbi_output *dbi_output,
415 cpu_relax(); 378 cpu_relax();
416 } 379 }
417 380
418 /*enable pipe*/ 381 /* Enable pipe */
419 reg_val = REG_READ(pipeconf_reg); 382 reg_val = REG_READ(pipeconf_reg);
420 if (!(reg_val & PIPEACONF_ENABLE)) { 383 if (!(reg_val & PIPEACONF_ENABLE)) {
421 reg_val |= PIPEACONF_ENABLE; 384 reg_val |= PIPEACONF_ENABLE;
@@ -425,7 +388,7 @@ static void mdfld_dbi_output_exit_dsr(struct mdfld_dsi_dbi_output *dbi_output,
425 mdfldWaitForPipeEnable(dev, pipe); 388 mdfldWaitForPipeEnable(dev, pipe);
426 } 389 }
427 390
428 /*enable plane*/ 391 /* Enable plane */
429 reg_val = REG_READ(dspcntr_reg); 392 reg_val = REG_READ(dspcntr_reg);
430 if (!(reg_val & DISPLAY_PLANE_ENABLE)) { 393 if (!(reg_val & DISPLAY_PLANE_ENABLE)) {
431 reg_val |= DISPLAY_PLANE_ENABLE; 394 reg_val |= DISPLAY_PLANE_ENABLE;
@@ -434,15 +397,9 @@ static void mdfld_dbi_output_exit_dsr(struct mdfld_dsi_dbi_output *dbi_output,
434 udelay(500); 397 udelay(500);
435 } 398 }
436 399
437 /* update the surface base address. */ 400 /* Enable TE interrupt on this pipe */
438 if (p_surfaceAddr)
439 REG_WRITE(dspsurf_reg, *((u32 *)p_surfaceAddr));
440
441 if (!check_hw_on_only)
442 gma_power_end(dev);
443
444 /*enable TE interrupt on this pipe*/
445 mdfld_enable_te(dev, pipe); 401 mdfld_enable_te(dev, pipe);
402 gma_power_end(dev);
446 403
447 /*clean IN_DSR flag*/ 404 /*clean IN_DSR flag*/
448 dbi_output->mode_flags &= ~MODE_SETTING_IN_DSR; 405 dbi_output->mode_flags &= ~MODE_SETTING_IN_DSR;
@@ -451,33 +408,33 @@ static void mdfld_dbi_output_exit_dsr(struct mdfld_dsi_dbi_output *dbi_output,
451/* 408/*
452 * Exit from DSR 409 * Exit from DSR
453 */ 410 */
454void mdfld_dsi_dbi_exit_dsr(struct drm_device *dev, u32 update_src, 411void mdfld_dsi_dbi_exit_dsr(struct drm_device *dev, u32 update_src)
455 void *p_surfaceAddr, bool check_hw_on_only)
456{ 412{
457 struct drm_psb_private *dev_priv = dev->dev_private; 413 struct drm_psb_private *dev_priv = dev->dev_private;
458 struct mdfld_dbi_dsr_info *dsr_info = dev_priv->dbi_dsr_info; 414 struct mdfld_dbi_dsr_info *dsr_info = dev_priv->dbi_dsr_info;
459 struct mdfld_dsi_dbi_output **dbi_output; 415 struct mdfld_dsi_dbi_output **dbi_output;
460 int i; 416 int i;
417 int pipe;
461 418
419 /* FIXME can go ? */
462 dev_priv->is_in_idle = false; 420 dev_priv->is_in_idle = false;
463 dbi_output = dsr_info->dbi_outputs; 421 dbi_output = dsr_info->dbi_outputs;
464 422
465#ifdef CONFIG_PM_RUNTIME 423#ifdef CONFIG_PM_RUNTIME
466 if (!enable_gfx_rtpm) { 424 if (!enable_gfx_rtpm) {
467/* pm_runtime_allow(&gpDrmDevice->pdev->dev); */ 425/* pm_runtime_allow(&gpDrmDevice->pdev->dev); */
468/* schedule_delayed_work(&rtpm_work, 120 * 1000); */ 426/* schedule_delayed_work(&rtpm_work, 30 * 1000);*/ /* FIXME: HZ ? */
469 } 427 }
470#endif 428#endif
471 429
472 /*for each output, exit dsr*/ 430 /* For each output, exit dsr */
473 for (i = 0; i < dsr_info->dbi_output_num; i++) { 431 for (i = 0; i < dsr_info->dbi_output_num; i++) {
474 /*if panel has been turned off, skip*/ 432 /* If panel has been turned off, skip */
475 if (!dbi_output[i]->dbi_panel_on) 433 if (!dbi_output[i] || !dbi_output[i]->dbi_panel_on)
476 continue; 434 continue;
477 if (dbi_output[i]->mode_flags & MODE_SETTING_IN_DSR) { 435 pipe = dbi_output[i]->channel_num ? 2 : 0;
478 enter_dsr = 0; 436 enter_dsr = 0;
479 mdfld_dbi_output_exit_dsr(dbi_output[i], dbi_output[i]->channel_num ? 2 : 0, p_surfaceAddr, check_hw_on_only); 437 mdfld_dbi_output_exit_dsr(dbi_output[i], pipe);
480 }
481 } 438 }
482 dev_priv->dsr_fb_update |= update_src; 439 dev_priv->dsr_fb_update |= update_src;
483} 440}
@@ -496,7 +453,7 @@ static bool mdfld_dbi_is_in_dsr(struct drm_device *dev)
496 return true; 453 return true;
497} 454}
498 455
499/* Perodically update dbi panel */ 456/* Periodically update dbi panel */
500void mdfld_dbi_update_panel(struct drm_device *dev, int pipe) 457void mdfld_dbi_update_panel(struct drm_device *dev, int pipe)
501{ 458{
502 struct drm_psb_private *dev_priv = dev->dev_private; 459 struct drm_psb_private *dev_priv = dev->dev_private;
@@ -504,8 +461,8 @@ void mdfld_dbi_update_panel(struct drm_device *dev, int pipe)
504 struct mdfld_dsi_dbi_output **dbi_outputs; 461 struct mdfld_dsi_dbi_output **dbi_outputs;
505 struct mdfld_dsi_dbi_output *dbi_output; 462 struct mdfld_dsi_dbi_output *dbi_output;
506 int i; 463 int i;
507 int enter_dsr = 0; 464 int can_enter_dsr = 0;
508 u32 damage_mask = 0; 465 u32 damage_mask;
509 466
510 dbi_outputs = dsr_info->dbi_outputs; 467 dbi_outputs = dsr_info->dbi_outputs;
511 dbi_output = pipe ? dbi_outputs[1] : dbi_outputs[0]; 468 dbi_output = pipe ? dbi_outputs[1] : dbi_outputs[0];
@@ -514,13 +471,13 @@ void mdfld_dbi_update_panel(struct drm_device *dev, int pipe)
514 return; 471 return;
515 472
516 if (pipe == 0) 473 if (pipe == 0)
517 damage_mask = dev_priv->dsr_fb_update & (MDFLD_DSR_DAMAGE_MASK_0); 474 damage_mask = dev_priv->dsr_fb_update & MDFLD_DSR_DAMAGE_MASK_0;
518 else if (pipe == 2) 475 else if (pipe == 2)
519 damage_mask = dev_priv->dsr_fb_update & (MDFLD_DSR_DAMAGE_MASK_2); 476 damage_mask = dev_priv->dsr_fb_update & MDFLD_DSR_DAMAGE_MASK_2;
520 else 477 else
521 return; 478 return;
522 479
523 /*if FB is damaged and panel is on update on-panel FB*/ 480 /* If FB is damaged and panel is on update on-panel FB */
524 if (damage_mask && dbi_output->dbi_panel_on) { 481 if (damage_mask && dbi_output->dbi_panel_on) {
525 dbi_output->dsr_fb_update_done = false; 482 dbi_output->dsr_fb_update_done = false;
526 483
@@ -538,11 +495,24 @@ void mdfld_dbi_update_panel(struct drm_device *dev, int pipe)
538 dbi_output->dsr_idle_count++; 495 dbi_output->dsr_idle_count++;
539 } 496 }
540 497
541 /*try to enter DSR*/ 498 switch (dsr_info->dbi_output_num) {
542 if (dbi_outputs[0]->dsr_idle_count > 1 499 case 1:
543 && dbi_outputs[1]->dsr_idle_count > 1) { 500 if (dbi_output->dsr_idle_count > MDFLD_DSR_MAX_IDLE_COUNT)
501 can_enter_dsr = 1;
502 break;
503 case 2:
504 if (dbi_outputs[0]->dsr_idle_count > MDFLD_DSR_MAX_IDLE_COUNT
505 && dbi_outputs[1]->dsr_idle_count > MDFLD_DSR_MAX_IDLE_COUNT)
506 can_enter_dsr = 1;
507 break;
508 default:
509 DRM_ERROR("Wrong DBI output number\n");
510 }
511
512 /* Try to enter DSR */
513 if (can_enter_dsr) {
544 for (i = 0; i < dsr_info->dbi_output_num; i++) { 514 for (i = 0; i < dsr_info->dbi_output_num; i++) {
545 if (!mdfld_dbi_is_in_dsr(dev) && 515 if (!mdfld_dbi_is_in_dsr(dev) && dbi_outputs[i] &&
546 !(dbi_outputs[i]->mode_flags & MODE_SETTING_ON_GOING)) { 516 !(dbi_outputs[i]->mode_flags & MODE_SETTING_ON_GOING)) {
547 mdfld_dsi_dbi_enter_dsr(dbi_outputs[i], 517 mdfld_dsi_dbi_enter_dsr(dbi_outputs[i],
548 dbi_outputs[i]->channel_num ? 2 : 0); 518 dbi_outputs[i]->channel_num ? 2 : 0);
@@ -565,61 +535,6 @@ void mdfld_dbi_update_panel(struct drm_device *dev, int pipe)
565 } 535 }
566} 536}
567 537
568/*timers for DSR*/
569static void mdfld_dsi_dbi_dsr_timer_func(unsigned long data)
570{
571 struct drm_device *dev = (struct drm_device *)data;
572 struct drm_psb_private *dev_priv = dev->dev_private;
573 struct mdfld_dbi_dsr_info *dsr_info = dev_priv->dbi_dsr_info;
574 struct timer_list *dsr_timer = &dsr_info->dsr_timer;
575 unsigned long flags;
576
577 mdfld_dbi_update_panel(dev, 0);
578
579 if (dsr_info->dsr_idle_count > 1)
580 return;
581
582 spin_lock_irqsave(&dsr_info->dsr_timer_lock, flags);
583 if (!timer_pending(dsr_timer)) {
584 dsr_timer->expires = jiffies + MDFLD_DSR_DELAY;
585 add_timer(dsr_timer);
586 }
587 spin_unlock_irqrestore(&dsr_info->dsr_timer_lock, flags);
588}
589
590static int mdfld_dsi_dbi_dsr_timer_init(struct drm_device *dev)
591{
592 struct drm_psb_private *dev_priv = dev->dev_private;
593 struct mdfld_dbi_dsr_info *dsr_info = dev_priv->dbi_dsr_info;
594 struct timer_list *dsr_timer = &dsr_info->dsr_timer;
595 unsigned long flags;
596
597 spin_lock_init(&dsr_info->dsr_timer_lock);
598 spin_lock_irqsave(&dsr_info->dsr_timer_lock, flags);
599
600 init_timer(dsr_timer);
601
602 dsr_timer->data = (unsigned long)dev;
603 dsr_timer->function = mdfld_dsi_dbi_dsr_timer_func;
604 dsr_timer->expires = jiffies + MDFLD_DSR_DELAY;
605
606 spin_unlock_irqrestore(&dsr_info->dsr_timer_lock, flags);
607 return 0;
608}
609
610void mdfld_dbi_dsr_timer_start(struct mdfld_dbi_dsr_info *dsr_info)
611{
612 struct timer_list *dsr_timer = &dsr_info->dsr_timer;
613 unsigned long flags;
614
615 spin_lock_irqsave(&dsr_info->dsr_timer_lock, flags);
616 if (!timer_pending(dsr_timer)) {
617 dsr_timer->expires = jiffies + MDFLD_DSR_DELAY;
618 add_timer(dsr_timer);
619 }
620 spin_unlock_irqrestore(&dsr_info->dsr_timer_lock, flags);
621}
622
623int mdfld_dbi_dsr_init(struct drm_device *dev) 538int mdfld_dbi_dsr_init(struct drm_device *dev)
624{ 539{
625 struct drm_psb_private *dev_priv = dev->dev_private; 540 struct drm_psb_private *dev_priv = dev->dev_private;
@@ -643,7 +558,6 @@ void mdfld_dbi_dsr_exit(struct drm_device *dev)
643 struct mdfld_dbi_dsr_info *dsr_info = dev_priv->dbi_dsr_info; 558 struct mdfld_dbi_dsr_info *dsr_info = dev_priv->dbi_dsr_info;
644 559
645 if (dsr_info) { 560 if (dsr_info) {
646 del_timer_sync(&dsr_info->dsr_timer);
647 kfree(dsr_info); 561 kfree(dsr_info);
648 dev_priv->dbi_dsr_info = NULL; 562 dev_priv->dbi_dsr_info = NULL;
649 } 563 }
@@ -660,13 +574,13 @@ void mdfld_dsi_controller_dbi_init(struct mdfld_dsi_config *dsi_config,
660 574
661 dev_dbg(dev->dev, "Init DBI interface on pipe %d...\n", pipe); 575 dev_dbg(dev->dev, "Init DBI interface on pipe %d...\n", pipe);
662 576
663 /*un-ready device*/ 577 /* Un-ready device */
664 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000000); 578 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000000);
665 579
666 /*init dsi adapter before kicking off*/ 580 /* Init dsi adapter before kicking off */
667 REG_WRITE((MIPIA_CONTROL_REG + reg_offset), 0x00000018); 581 REG_WRITE((MIPIA_CONTROL_REG + reg_offset), 0x00000018);
668 582
669 /*TODO: figure out how to setup these registers*/ 583 /* TODO: figure out how to setup these registers */
670 REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150c3408); 584 REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150c3408);
671 REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG + reg_offset), 585 REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG + reg_offset),
672 0x000a0014); 586 0x000a0014);
@@ -674,16 +588,16 @@ void mdfld_dsi_controller_dbi_init(struct mdfld_dsi_config *dsi_config,
674 REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000001); 588 REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000001);
675 REG_WRITE((MIPIA_HS_LS_DBI_ENABLE_REG + reg_offset), 0x00000000); 589 REG_WRITE((MIPIA_HS_LS_DBI_ENABLE_REG + reg_offset), 0x00000000);
676 590
677 /*enable all interrupts*/ 591 /* Enable all interrupts */
678 REG_WRITE((MIPIA_INTR_EN_REG + reg_offset), 0xffffffff); 592 REG_WRITE((MIPIA_INTR_EN_REG + reg_offset), 0xffffffff);
679 /*max value: 20 clock cycles of txclkesc*/ 593 /* Max value: 20 clock cycles of txclkesc */
680 REG_WRITE((MIPIA_TURN_AROUND_TIMEOUT_REG + reg_offset), 0x0000001f); 594 REG_WRITE((MIPIA_TURN_AROUND_TIMEOUT_REG + reg_offset), 0x0000001f);
681 /*min 21 txclkesc, max: ffffh*/ 595 /* Min 21 txclkesc, max: ffffh */
682 REG_WRITE((MIPIA_DEVICE_RESET_TIMER_REG + reg_offset), 0x0000ffff); 596 REG_WRITE((MIPIA_DEVICE_RESET_TIMER_REG + reg_offset), 0x0000ffff);
683 /*min: 7d0 max: 4e20*/ 597 /* Min: 7d0 max: 4e20 */
684 REG_WRITE((MIPIA_INIT_COUNT_REG + reg_offset), 0x00000fa0); 598 REG_WRITE((MIPIA_INIT_COUNT_REG + reg_offset), 0x00000fa0);
685 599
686 /*set up func_prg*/ 600 /* Set up func_prg */
687 val |= lane_count; 601 val |= lane_count;
688 val |= (dsi_config->channel_num << DSI_DBI_VIRT_CHANNEL_OFFSET); 602 val |= (dsi_config->channel_num << DSI_DBI_VIRT_CHANNEL_OFFSET);
689 val |= DSI_DBI_COLOR_FORMAT_OPTION2; 603 val |= DSI_DBI_COLOR_FORMAT_OPTION2;
@@ -692,7 +606,7 @@ void mdfld_dsi_controller_dbi_init(struct mdfld_dsi_config *dsi_config,
692 REG_WRITE((MIPIA_HS_TX_TIMEOUT_REG + reg_offset), 0x3fffff); 606 REG_WRITE((MIPIA_HS_TX_TIMEOUT_REG + reg_offset), 0x3fffff);
693 REG_WRITE((MIPIA_LP_RX_TIMEOUT_REG + reg_offset), 0xffff); 607 REG_WRITE((MIPIA_LP_RX_TIMEOUT_REG + reg_offset), 0xffff);
694 608
695 /*de-assert dbi_stall when half of DBI FIFO is empty*/ 609 /* De-assert dbi_stall when half of DBI FIFO is empty */
696 /* REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000000); */ 610 /* REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000000); */
697 611
698 REG_WRITE((MIPIA_HIGH_LOW_SWITCH_COUNT_REG + reg_offset), 0x46); 612 REG_WRITE((MIPIA_HIGH_LOW_SWITCH_COUNT_REG + reg_offset), 0x46);
@@ -718,42 +632,6 @@ static const struct drm_encoder_funcs mdfld_dsi_dbi_encoder_funcs = {
718 632
719#endif 633#endif
720 634
721static int mdfld_dbi_panel_reset(struct mdfld_dsi_dbi_output *output)
722{
723 unsigned gpio;
724 int ret;
725
726 switch (output->channel_num) {
727 case 0:
728 gpio = 128;
729 break;
730 case 1:
731 gpio = 34;
732 break;
733 default:
734 pr_err("Invalid output\n");
735 return -EINVAL;
736 }
737
738 ret = gpio_request(gpio, "gfx");
739 if (ret) {
740 pr_err("gpio_rqueset failed\n");
741 return ret;
742 }
743
744 ret = gpio_direction_output(gpio, 1);
745 if (ret) {
746 pr_err("gpio_direction_output failed\n");
747 goto gpio_error;
748 }
749 gpio_get_value(128);
750gpio_error:
751 if (gpio_is_valid(gpio))
752 gpio_free(gpio);
753
754 return ret;
755}
756
757/* 635/*
758 * Init DSI DBI encoder. 636 * Init DSI DBI encoder.
759 * Allocate an mdfld_dsi_encoder and attach it to given @dsi_connector 637 * Allocate an mdfld_dsi_encoder and attach it to given @dsi_connector
@@ -776,13 +654,44 @@ struct mdfld_dsi_encoder *mdfld_dsi_dbi_init(struct drm_device *dev,
776#else 654#else
777 struct mdfld_dbi_dsr_info *dsr_info = dev_priv ? (dev_priv->dbi_dsr_info) : NULL; 655 struct mdfld_dbi_dsr_info *dsr_info = dev_priv ? (dev_priv->dbi_dsr_info) : NULL;
778#endif 656#endif
657 u32 data = 0;
658 int pipe;
779 int ret; 659 int ret;
780 660
781 if (!pg || !dsi_connector) { 661 if (!pg || !dsi_connector || !p_funcs) {
782 WARN_ON(1); 662 WARN_ON(1);
783 return NULL; 663 return NULL;
784 } 664 }
785 665
666 dsi_config = mdfld_dsi_get_config(dsi_connector);
667 pipe = dsi_connector->pipe;
668
669 /*panel hard-reset*/
670 if (p_funcs->reset) {
671 ret = p_funcs->reset(pipe);
672 if (ret) {
673 DRM_ERROR("Panel %d hard-reset failed\n", pipe);
674 return NULL;
675 }
676 }
677 /* Panel drvIC init */
678 if (p_funcs->drv_ic_init)
679 p_funcs->drv_ic_init(dsi_config, pipe);
680
681 /* Panel power mode detect */
682 ret = mdfld_dsi_get_power_mode(dsi_config,
683 &data,
684 MDFLD_DSI_HS_TRANSMISSION);
685 if (ret) {
686 DRM_ERROR("Panel %d get power mode failed\n", pipe);
687 dsi_connector->status = connector_status_disconnected;
688 } else {
689 DRM_INFO("pipe %d power mode 0x%x\n", pipe, data);
690 dsi_connector->status = connector_status_connected;
691 }
692
693 /*TODO: get panel info from DDB*/
694
786 dbi_output = kzalloc(sizeof(struct mdfld_dsi_dbi_output), GFP_KERNEL); 695 dbi_output = kzalloc(sizeof(struct mdfld_dsi_dbi_output), GFP_KERNEL);
787 if (!dbi_output) { 696 if (!dbi_output) {
788 dev_err(dev->dev, "No memory\n"); 697 dev_err(dev->dev, "No memory\n");
@@ -802,23 +711,10 @@ struct mdfld_dsi_encoder *mdfld_dsi_dbi_init(struct drm_device *dev,
802 711
803 dbi_output->dev = dev; 712 dbi_output->dev = dev;
804 dbi_output->p_funcs = p_funcs; 713 dbi_output->p_funcs = p_funcs;
805
806 /*panel reset*/
807 ret = mdfld_dbi_panel_reset(dbi_output);
808 if (ret) {
809 dev_err(dev->dev, "reset panel error\n");
810 goto out_err1;
811 }
812
813 /*TODO: get panel info from DDB*/
814
815 /*get fixed mode*/
816 dsi_config = mdfld_dsi_get_config(dsi_connector);
817 fixed_mode = dsi_config->fixed_mode; 714 fixed_mode = dsi_config->fixed_mode;
818
819 dbi_output->panel_fixed_mode = fixed_mode; 715 dbi_output->panel_fixed_mode = fixed_mode;
820 716
821 /*create drm encoder object*/ 717 /* Create drm encoder object */
822 connector = &dsi_connector->base.base; 718 connector = &dsi_connector->base.base;
823 encoder = &dbi_output->base.base; 719 encoder = &dbi_output->base.base;
824 drm_encoder_init(dev, 720 drm_encoder_init(dev,
@@ -827,10 +723,10 @@ struct mdfld_dsi_encoder *mdfld_dsi_dbi_init(struct drm_device *dev,
827 DRM_MODE_ENCODER_MIPI); 723 DRM_MODE_ENCODER_MIPI);
828 drm_encoder_helper_add(encoder, p_funcs->encoder_helper_funcs); 724 drm_encoder_helper_add(encoder, p_funcs->encoder_helper_funcs);
829 725
830 /*attach to given connector*/ 726 /* Attach to given connector */
831 drm_mode_connector_attach_encoder(connector, encoder); 727 drm_mode_connector_attach_encoder(connector, encoder);
832 728
833 /*set possible crtcs and clones*/ 729 /* Set possible CRTCs and clones */
834 if (dsi_connector->pipe) { 730 if (dsi_connector->pipe) {
835 encoder->possible_crtcs = (1 << 2); 731 encoder->possible_crtcs = (1 << 2);
836 encoder->possible_clones = (1 << 1); 732 encoder->possible_clones = (1 << 1);
@@ -842,28 +738,31 @@ struct mdfld_dsi_encoder *mdfld_dsi_dbi_init(struct drm_device *dev,
842 dev_priv->dsr_fb_update = 0; 738 dev_priv->dsr_fb_update = 0;
843 dev_priv->dsr_enable = false; 739 dev_priv->dsr_enable = false;
844 dev_priv->exit_idle = mdfld_dsi_dbi_exit_dsr; 740 dev_priv->exit_idle = mdfld_dsi_dbi_exit_dsr;
845#if defined(CONFIG_MDFLD_DSI_DPU) || defined(CONFIG_MDFLD_DSI_DSR)
846 dev_priv->dsr_enable_config = false;
847#endif /*CONFIG_MDFLD_DSI_DSR*/
848 741
849 dbi_output->first_boot = true; 742 dbi_output->first_boot = true;
850 dbi_output->mode_flags = MODE_SETTING_IN_ENCODER; 743 dbi_output->mode_flags = MODE_SETTING_IN_ENCODER;
851 744
852#ifdef CONFIG_MDFLD_DSI_DPU 745#ifdef CONFIG_MDFLD_DSI_DPU
853 /*add this output to dpu_info*/ 746 /* Add this output to dpu_info */
854 if (dsi_connector->pipe == 0) 747 if (dsi_connector->status == connector_status_connected) {
855 dpu_info->dbi_outputs[0] = dbi_output; 748 if (dsi_connector->pipe == 0)
856 } else { 749 dpu_info->dbi_outputs[0] = dbi_output;
857 dpu_info->dbi_outputs[1] = dbi_output; 750 else
751 dpu_info->dbi_outputs[1] = dbi_output;
752
753 dpu_info->dbi_output_num++;
858 } 754 }
859 dpu_info->dbi_output_num++; 755
860#else /*CONFIG_MDFLD_DSI_DPU*/ 756#else /*CONFIG_MDFLD_DSI_DPU*/
861 /*add this output to dsr_info*/ 757 if (dsi_connector->status == connector_status_connected) {
862 if (dsi_connector->pipe == 0) 758 /* Add this output to dsr_info */
863 dsr_info->dbi_outputs[0] = dbi_output; 759 if (dsi_connector->pipe == 0)
864 else 760 dsr_info->dbi_outputs[0] = dbi_output;
865 dsr_info->dbi_outputs[1] = dbi_output; 761 else
866 dsr_info->dbi_output_num++; 762 dsr_info->dbi_outputs[1] = dbi_output;
763
764 dsr_info->dbi_output_num++;
765 }
867#endif 766#endif
868 return &dbi_output->base; 767 return &dbi_output->base;
869out_err1: 768out_err1:
diff --git a/drivers/staging/gma500/mdfld_dsi_dbi.h b/drivers/staging/gma500/mdfld_dsi_dbi.h
index a51e2f87518..a2ec6fd94ae 100644
--- a/drivers/staging/gma500/mdfld_dsi_dbi.h
+++ b/drivers/staging/gma500/mdfld_dsi_dbi.h
@@ -59,9 +59,6 @@ struct mdfld_dsi_dbi_output {
59 /* Backlight operations */ 59 /* Backlight operations */
60 60
61 /* DSR timer */ 61 /* DSR timer */
62 spinlock_t dsr_timer_lock;
63 struct timer_list dsr_timer;
64 void(*dsi_timer_func)(unsigned long data);
65 u32 dsr_idle_count; 62 u32 dsr_idle_count;
66 bool dsr_fb_update_done; 63 bool dsr_fb_update_done;
67 64
@@ -81,22 +78,11 @@ struct mdfld_dbi_dsr_info {
81 int dbi_output_num; 78 int dbi_output_num;
82 struct mdfld_dsi_dbi_output *dbi_outputs[2]; 79 struct mdfld_dsi_dbi_output *dbi_outputs[2];
83 80
84 spinlock_t dsr_timer_lock;
85 struct timer_list dsr_timer;
86 u32 dsr_idle_count; 81 u32 dsr_idle_count;
87}; 82};
88 83
89#define DBI_CB_TIMEOUT_COUNT 0xffff 84#define DBI_CB_TIMEOUT_COUNT 0xffff
90 85
91/* DCS commands */
92#define enter_sleep_mode 0x10
93#define exit_sleep_mode 0x11
94#define set_display_off 0x28
95#define set_dispaly_on 0x29
96#define set_column_address 0x2a
97#define set_page_addr 0x2b
98#define write_mem_start 0x2c
99
100/* Offsets */ 86/* Offsets */
101#define CMD_MEM_ADDR_OFFSET 0 87#define CMD_MEM_ADDR_OFFSET 0
102 88
@@ -132,7 +118,7 @@ static inline int mdfld_dsi_dbi_cmd_sent(struct mdfld_dsi_dbi_output *dbi_output
132 118
133 /* Query the command execution status */ 119 /* Query the command execution status */
134 while (retry--) 120 while (retry--)
135 if (!(REG_READ(MIPIA_CMD_ADD_REG + reg_offset) & (1 << 10))) 121 if (!(REG_READ(MIPIA_CMD_ADD_REG + reg_offset) & (1 << 0)))
136 break; 122 break;
137 123
138 if (!retry) { 124 if (!retry) {
@@ -164,13 +150,11 @@ static inline int mdfld_dsi_dbi_cb_ready(struct mdfld_dsi_dbi_output *dbi_output
164 150
165extern void mdfld_dsi_dbi_output_init(struct drm_device *dev, 151extern void mdfld_dsi_dbi_output_init(struct drm_device *dev,
166 struct psb_intel_mode_device *mode_dev, int pipe); 152 struct psb_intel_mode_device *mode_dev, int pipe);
167extern void mdfld_dsi_dbi_exit_dsr(struct drm_device *dev, u32 update_src, 153extern void mdfld_dsi_dbi_exit_dsr(struct drm_device *dev, u32 update_src);
168 void *p_surfaceAddr, bool check_hw_on_only);
169extern void mdfld_dsi_dbi_enter_dsr(struct mdfld_dsi_dbi_output *dbi_output, 154extern void mdfld_dsi_dbi_enter_dsr(struct mdfld_dsi_dbi_output *dbi_output,
170 int pipe); 155 int pipe);
171extern int mdfld_dbi_dsr_init(struct drm_device *dev); 156extern int mdfld_dbi_dsr_init(struct drm_device *dev);
172extern void mdfld_dbi_dsr_exit(struct drm_device *dev); 157extern void mdfld_dbi_dsr_exit(struct drm_device *dev);
173extern void mdfld_dbi_dsr_timer_start(struct mdfld_dbi_dsr_info *dsr_info);
174extern struct mdfld_dsi_encoder *mdfld_dsi_dbi_init(struct drm_device *dev, 158extern struct mdfld_dsi_encoder *mdfld_dsi_dbi_init(struct drm_device *dev,
175 struct mdfld_dsi_connector *dsi_connector, 159 struct mdfld_dsi_connector *dsi_connector,
176 struct panel_funcs *p_funcs); 160 struct panel_funcs *p_funcs);
@@ -178,7 +162,6 @@ extern int mdfld_dsi_dbi_send_dcs(struct mdfld_dsi_dbi_output *dbi_output,
178 u8 dcs, u8 *param, u32 num, u8 data_src); 162 u8 dcs, u8 *param, u32 num, u8 data_src);
179extern int mdfld_dsi_dbi_update_area(struct mdfld_dsi_dbi_output *dbi_output, 163extern int mdfld_dsi_dbi_update_area(struct mdfld_dsi_dbi_output *dbi_output,
180 u16 x1, u16 y1, u16 x2, u16 y2); 164 u16 x1, u16 y1, u16 x2, u16 y2);
181extern void mdfld_dbi_dsr_timer_start(struct mdfld_dbi_dsr_info *dsr_info);
182extern int mdfld_dsi_dbi_update_power(struct mdfld_dsi_dbi_output *dbi_output, 165extern int mdfld_dsi_dbi_update_power(struct mdfld_dsi_dbi_output *dbi_output,
183 int mode); 166 int mode);
184extern void mdfld_dsi_controller_dbi_init(struct mdfld_dsi_config *dsi_config, 167extern void mdfld_dsi_controller_dbi_init(struct mdfld_dsi_config *dsi_config,
diff --git a/drivers/staging/gma500/mdfld_dsi_dbi_dpu.h b/drivers/staging/gma500/mdfld_dsi_dbi_dpu.h
index 4ca9682c47c..42367ed48c0 100644
--- a/drivers/staging/gma500/mdfld_dsi_dbi_dpu.h
+++ b/drivers/staging/gma500/mdfld_dsi_dbi_dpu.h
@@ -90,9 +90,6 @@ static inline int mdfld_dpu_region_extent(struct psb_drm_dpu_rect *origin,
90{ 90{
91 int x1, y1, x2, y2; 91 int x1, y1, x2, y2;
92 92
93 /* PSB_DEBUG_ENTRY("rect (%d, %d, %d, %d)\n",
94 rect->x, rect->y, rect->width, rect->height); */
95
96 x1 = origin->x + origin->width; 93 x1 = origin->x + origin->width;
97 y1 = origin->y + origin->height; 94 y1 = origin->y + origin->height;
98 95
diff --git a/drivers/staging/gma500/mdfld_dsi_dpi.c b/drivers/staging/gma500/mdfld_dsi_dpi.c
index fce3c203134..6e03a91e947 100644
--- a/drivers/staging/gma500/mdfld_dsi_dpi.c
+++ b/drivers/staging/gma500/mdfld_dsi_dpi.c
@@ -69,26 +69,6 @@ static void mdfld_wait_for_HS_CTRL_FIFO(struct drm_device *dev, u32 pipe)
69 dev_warn(dev->dev, "MIPI: HS CMD FIFO was never cleared!\n"); 69 dev_warn(dev->dev, "MIPI: HS CMD FIFO was never cleared!\n");
70} 70}
71 71
72static void mdfld_wait_for_PIPEA_DISABLE(struct drm_device *dev, u32 pipe)
73{
74 u32 pipeconf_reg = PIPEACONF;
75 int timeout = 0;
76
77 if (pipe == 2)
78 pipeconf_reg = PIPECCONF;
79
80 udelay(500);
81
82 /* This will time out after approximately 2+ seconds */
83 while ((timeout < 20000) && (REG_READ(pipeconf_reg) & 0x40000000)) {
84 udelay(100);
85 timeout++;
86 }
87
88 if (timeout == 20000)
89 dev_warn(dev->dev, "MIPI: PIPE was not disabled!\n");
90}
91
92static void mdfld_wait_for_DPI_CTRL_FIFO(struct drm_device *dev, u32 pipe) 72static void mdfld_wait_for_DPI_CTRL_FIFO(struct drm_device *dev, u32 pipe)
93{ 73{
94 u32 gen_fifo_stat_reg = MIPIA_GEN_FIFO_STAT_REG; 74 u32 gen_fifo_stat_reg = MIPIA_GEN_FIFO_STAT_REG;
@@ -147,8 +127,6 @@ void mdfld_dsi_tpo_ic_init(struct mdfld_dsi_config *dsi_config, u32 pipe)
147 u32 gen_ctrl_reg = MIPIA_HS_GEN_CTRL_REG; 127 u32 gen_ctrl_reg = MIPIA_HS_GEN_CTRL_REG;
148 u32 gen_ctrl_val = GEN_LONG_WRITE; 128 u32 gen_ctrl_val = GEN_LONG_WRITE;
149 129
150 dev_warn(dev->dev, "Enter mrst init TPO MIPI display.\n");
151
152 if (pipe == 2) { 130 if (pipe == 2) {
153 gen_data_reg = HS_GEN_DATA_REG + MIPIC_REG_OFFSET; 131 gen_data_reg = HS_GEN_DATA_REG + MIPIC_REG_OFFSET;
154 gen_ctrl_reg = HS_GEN_CTRL_REG + MIPIC_REG_OFFSET; 132 gen_ctrl_reg = HS_GEN_CTRL_REG + MIPIC_REG_OFFSET;
@@ -331,51 +309,8 @@ void mdfld_dsi_tpo_ic_init(struct mdfld_dsi_config *dsi_config, u32 pipe)
331 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); 309 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS));
332} 310}
333 311
334/* ************************************************************************* *\ 312static u16 mdfld_dsi_dpi_to_byte_clock_count(int pixel_clock_count,
335 * FUNCTION: mdfld_init_TMD_MIPI 313 int num_lane, int bpp)
336 *
337 * DESCRIPTION: This function is called only by mrst_dsi_mode_set and
338 * restore_display_registers. since this function does not
339 * acquire the mutex, it is important that the calling function
340 * does!
341\* ************************************************************************* */
342
343static u32 tmd_cmd_mcap_off[] = {0x000000b2};
344static u32 tmd_cmd_enable_lane_switch[] = {0x000101ef};
345static u32 tmd_cmd_set_lane_num[] = {0x006360ef};
346static u32 tmd_cmd_set_mode[] = {0x000000b3};
347static u32 tmd_cmd_set_sync_pulse_mode[] = {0x000961ef};
348static u32 tmd_cmd_set_video_mode[] = {0x00000153};
349static u32 tmd_cmd_enable_backlight[] = {0x00005ab4};//no auto_bl,need add in furtrue
350static u32 tmd_cmd_set_backlight_dimming[] = {0x00000ebd};
351
352void mdfld_dsi_tmd_drv_ic_init(struct mdfld_dsi_config *dsi_config, u32 pipe)
353{
354 struct mdfld_dsi_pkg_sender *sender = mdfld_dsi_get_pkg_sender(dsi_config);
355
356 if(!sender) {
357 WARN_ON(1);
358 return;
359 }
360
361 if(dsi_config->dvr_ic_inited)
362 return;
363
364 msleep(3);
365
366 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_mcap_off, 1, 0);
367 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_enable_lane_switch, 1, 0);
368 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_set_lane_num, 1, 0);
369 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_set_mode, 1, 0);
370 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_set_sync_pulse_mode, 1, 0);
371 /*TODO: set page and column here*/
372 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_set_video_mode, 1, 0);
373 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_enable_backlight, 1, 0);
374 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_set_backlight_dimming,1,0);
375 dsi_config->dvr_ic_inited = 1;
376}
377
378static u16 mdfld_dsi_dpi_to_byte_clock_count(int pixel_clock_count, int num_lane, int bpp)
379{ 314{
380 return (u16)((pixel_clock_count * bpp) / (num_lane * 8)); 315 return (u16)((pixel_clock_count * bpp) / (num_lane * 8));
381} 316}
@@ -387,8 +322,8 @@ static u16 mdfld_dsi_dpi_to_byte_clock_count(int pixel_clock_count, int num_lane
387 * use crtc mode values later 322 * use crtc mode values later
388 */ 323 */
389int mdfld_dsi_dpi_timing_calculation(struct drm_display_mode *mode, 324int mdfld_dsi_dpi_timing_calculation(struct drm_display_mode *mode,
390 struct mdfld_dsi_dpi_timing *dpi_timing, 325 struct mdfld_dsi_dpi_timing *dpi_timing,
391 int num_lane, int bpp) 326 int num_lane, int bpp)
392{ 327{
393 int pclk_hsync, pclk_hfp, pclk_hbp, pclk_hactive; 328 int pclk_hsync, pclk_hfp, pclk_hbp, pclk_hactive;
394 int pclk_vsync, pclk_vfp, pclk_vbp, pclk_vactive; 329 int pclk_vsync, pclk_vfp, pclk_vbp, pclk_vactive;
@@ -408,16 +343,6 @@ int mdfld_dsi_dpi_timing_calculation(struct drm_display_mode *mode,
408 pclk_vsync = mode->vsync_end - mode->vsync_start; 343 pclk_vsync = mode->vsync_end - mode->vsync_start;
409 pclk_vbp = mode->vtotal - mode->vsync_end; 344 pclk_vbp = mode->vtotal - mode->vsync_end;
410 345
411#ifdef MIPI_DEBUG_LOG
412 printk(KERN_ALERT "[DISPLAY] %s: pclk_hactive = %d\n", __func__, pclk_hactive);
413 printk(KERN_ALERT "[DISPLAY] %s: pclk_hfp = %d\n", __func__, pclk_hfp);
414 printk(KERN_ALERT "[DISPLAY] %s: pclk_hsync = %d\n", __func__, pclk_hsync);
415 printk(KERN_ALERT "[DISPLAY] %s: pclk_hbp = %d\n", __func__, pclk_hbp);
416 printk(KERN_ALERT "[DISPLAY] %s: pclk_vactive = %d\n", __func__, pclk_vactive);
417 printk(KERN_ALERT "[DISPLAY] %s: pclk_vfp = %d\n", __func__, pclk_vfp);
418 printk(KERN_ALERT "[DISPLAY] %s: pclk_vsync = %d\n", __func__, pclk_vsync);
419 printk(KERN_ALERT "[DISPLAY] %s: pclk_vbp = %d\n", __func__, pclk_vbp);
420#endif
421 /* 346 /*
422 * byte clock counts were calculated by following formula 347 * byte clock counts were calculated by following formula
423 * bclock_count = pclk_count * bpp / num_lane / 8 348 * bclock_count = pclk_count * bpp / num_lane / 8
@@ -519,7 +444,6 @@ void mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config *dsi_config, int pipe
519void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output *output, int pipe) 444void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output *output, int pipe)
520{ 445{
521 struct drm_device *dev = output->dev; 446 struct drm_device *dev = output->dev;
522 /* struct drm_psb_private *dev_priv = dev->dev_private; */
523 u32 reg_offset = 0; 447 u32 reg_offset = 0;
524 448
525 if(output->panel_on) 449 if(output->panel_on)
@@ -555,7 +479,6 @@ void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output *output, int pipe)
555static void mdfld_dsi_dpi_shut_down(struct mdfld_dsi_dpi_output *output, int pipe) 479static void mdfld_dsi_dpi_shut_down(struct mdfld_dsi_dpi_output *output, int pipe)
556{ 480{
557 struct drm_device *dev = output->dev; 481 struct drm_device *dev = output->dev;
558 /* struct drm_psb_private *dev_priv = dev->dev_private; */
559 u32 reg_offset = 0; 482 u32 reg_offset = 0;
560 483
561 /*if output is on, or mode setting didn't happen, ignore this*/ 484 /*if output is on, or mode setting didn't happen, ignore this*/
@@ -576,6 +499,7 @@ static void mdfld_dsi_dpi_shut_down(struct mdfld_dsi_dpi_output *output, int pip
576 } 499 }
577 500
578 if(REG_READ(MIPIA_DPI_CONTROL_REG + reg_offset) == DSI_DPI_CTRL_HS_SHUTDOWN) { 501 if(REG_READ(MIPIA_DPI_CONTROL_REG + reg_offset) == DSI_DPI_CTRL_HS_SHUTDOWN) {
502 dev_warn(dev->dev, "try to send the same package again, abort!");
579 goto shutdown_out; 503 goto shutdown_out;
580 } 504 }
581 505
@@ -590,6 +514,14 @@ shutdown_out:
590 /* dev_priv->dpi_panel_on2 = false; */ 514 /* dev_priv->dpi_panel_on2 = false; */
591 /* else if (pipe == 0) */ 515 /* else if (pipe == 0) */
592 /* dev_priv->dpi_panel_on = false; */ 516 /* dev_priv->dpi_panel_on = false; */
517 /* #ifdef CONFIG_PM_RUNTIME*/
518 /* if (drm_psb_ospm && !enable_gfx_rtpm) { */
519 /* pm_runtime_allow(&gpDrmDevice->pdev->dev); */
520 /* schedule_delayed_work(&dev_priv->rtpm_work, 30 * 1000); */
521 /* } */
522 /*if (enable_gfx_rtpm) */
523 /* pm_schedule_suspend(&dev->pdev->dev, gfxrtdelay); */
524 /* #endif */
593} 525}
594 526
595void mdfld_dsi_dpi_set_power(struct drm_encoder *encoder, bool on) 527void mdfld_dsi_dpi_set_power(struct drm_encoder *encoder, bool on)
@@ -616,7 +548,7 @@ void mdfld_dsi_dpi_set_power(struct drm_encoder *encoder, bool on)
616 if (mdfld_get_panel_type(dev, pipe) == TMD_VID){ 548 if (mdfld_get_panel_type(dev, pipe) == TMD_VID){
617 mdfld_dsi_dpi_turn_on(dpi_output, pipe); 549 mdfld_dsi_dpi_turn_on(dpi_output, pipe);
618 } else { 550 } else {
619 /*enable mipi port*/ 551 /* Enable mipi port */
620 REG_WRITE(mipi_reg, (REG_READ(mipi_reg) | (1 << 31))); 552 REG_WRITE(mipi_reg, (REG_READ(mipi_reg) | (1 << 31)));
621 REG_READ(mipi_reg); 553 REG_READ(mipi_reg);
622 554
@@ -636,7 +568,7 @@ void mdfld_dsi_dpi_set_power(struct drm_encoder *encoder, bool on)
636 mdfld_dsi_dpi_shut_down(dpi_output, pipe); 568 mdfld_dsi_dpi_shut_down(dpi_output, pipe);
637 } else { 569 } else {
638 mdfld_dsi_dpi_shut_down(dpi_output, pipe); 570 mdfld_dsi_dpi_shut_down(dpi_output, pipe);
639 /*disable mipi port*/ 571 /* Disable mipi port */
640 REG_WRITE(mipi_reg, (REG_READ(mipi_reg) & ~(1<<31))); 572 REG_WRITE(mipi_reg, (REG_READ(mipi_reg) & ~(1<<31)));
641 REG_READ(mipi_reg); 573 REG_READ(mipi_reg);
642 } 574 }
@@ -656,8 +588,15 @@ void mdfld_dsi_dpi_dpms(struct drm_encoder *encoder, int mode)
656 588
657 if (mode == DRM_MODE_DPMS_ON) 589 if (mode == DRM_MODE_DPMS_ON)
658 mdfld_dsi_dpi_set_power(encoder, true); 590 mdfld_dsi_dpi_set_power(encoder, true);
659 else 591 else {
660 mdfld_dsi_dpi_set_power(encoder, false); 592 mdfld_dsi_dpi_set_power(encoder, false);
593#if 0 /* FIXME */
594#ifdef CONFIG_PM_RUNTIME
595 if (enable_gfx_rtpm)
596 pm_schedule_suspend(&gpDrmDevice->pdev->dev, gfxrtdelay);
597#endif
598#endif
599 }
661} 600}
662 601
663bool mdfld_dsi_dpi_mode_fixup(struct drm_encoder *encoder, 602bool mdfld_dsi_dpi_mode_fixup(struct drm_encoder *encoder,
@@ -694,77 +633,6 @@ void mdfld_dsi_dpi_commit(struct drm_encoder *encoder)
694 mdfld_dsi_dpi_set_power(encoder, true); 633 mdfld_dsi_dpi_set_power(encoder, true);
695} 634}
696 635
697void dsi_debug_MIPI_reg(struct drm_device *dev)
698{
699 u32 temp_val = 0;
700
701 temp_val = REG_READ(MIPI);
702 printk(KERN_ALERT "[DISPLAY] MIPI = %x\n", temp_val);
703
704 /* set the lane speed */
705 temp_val = REG_READ(MIPI_CONTROL_REG);
706 printk(KERN_ALERT "[DISPLAY] MIPI_CONTROL_REG = %x\n", temp_val);
707
708 /* Enable all the error interrupt */
709 temp_val = REG_READ(INTR_EN_REG);
710 printk(KERN_ALERT "[DISPLAY] INTR_EN_REG = %x\n", temp_val);
711 temp_val = REG_READ(TURN_AROUND_TIMEOUT_REG);
712 printk(KERN_ALERT "[DISPLAY] TURN_AROUND_TIMEOUT_REG = %x\n", temp_val);
713 temp_val = REG_READ(DEVICE_RESET_REG);
714 printk(KERN_ALERT "[DISPLAY] DEVICE_RESET_REG = %x\n", temp_val);
715 temp_val = REG_READ(INIT_COUNT_REG);
716 printk(KERN_ALERT "[DISPLAY] INIT_COUNT_REG = %x\n", temp_val);
717
718 temp_val = REG_READ(DSI_FUNC_PRG_REG);
719 printk(KERN_ALERT "[DISPLAY] DSI_FUNC_PRG_REG = %x\n", temp_val);
720
721 temp_val = REG_READ(DPI_RESOLUTION_REG);
722 printk(KERN_ALERT "[DISPLAY] DPI_RESOLUTION_REG = %x\n", temp_val);
723
724 temp_val = REG_READ(VERT_SYNC_PAD_COUNT_REG);
725 printk(KERN_ALERT "[DISPLAY] VERT_SYNC_PAD_COUNT_REG = %x\n", temp_val);
726 temp_val = REG_READ(VERT_BACK_PORCH_COUNT_REG);
727 printk(KERN_ALERT "[DISPLAY] VERT_BACK_PORCH_COUNT_REG = %x\n", temp_val);
728 temp_val = REG_READ(VERT_FRONT_PORCH_COUNT_REG);
729 printk(KERN_ALERT "[DISPLAY] VERT_FRONT_PORCH_COUNT_REG = %x\n", temp_val);
730
731 temp_val = REG_READ(HORIZ_SYNC_PAD_COUNT_REG);
732 printk(KERN_ALERT "[DISPLAY] HORIZ_SYNC_PAD_COUNT_REG = %x\n", temp_val);
733 temp_val = REG_READ(HORIZ_BACK_PORCH_COUNT_REG);
734 printk(KERN_ALERT "[DISPLAY] HORIZ_BACK_PORCH_COUNT_REG = %x\n", temp_val);
735 temp_val = REG_READ(HORIZ_FRONT_PORCH_COUNT_REG);
736 printk(KERN_ALERT "[DISPLAY] HORIZ_FRONT_PORCH_COUNT_REG = %x\n", temp_val);
737 temp_val = REG_READ(HORIZ_ACTIVE_AREA_COUNT_REG);
738 printk(KERN_ALERT "[DISPLAY] HORIZ_ACTIVE_AREA_COUNT_REG = %x\n", temp_val);
739
740 temp_val = REG_READ(VIDEO_FMT_REG);
741 printk(KERN_ALERT "[DISPLAY] VIDEO_FMT_REG = %x\n", temp_val);
742
743 temp_val = REG_READ(HS_TX_TIMEOUT_REG);
744 printk(KERN_ALERT "[DISPLAY] HS_TX_TIMEOUT_REG = %x\n", temp_val);
745 temp_val = REG_READ(LP_RX_TIMEOUT_REG);
746 printk(KERN_ALERT "[DISPLAY] LP_RX_TIMEOUT_REG = %x\n", temp_val);
747
748 temp_val = REG_READ(HIGH_LOW_SWITCH_COUNT_REG);
749 printk(KERN_ALERT "[DISPLAY] HIGH_LOW_SWITCH_COUNT_REG = %x\n", temp_val);
750
751 temp_val = REG_READ(EOT_DISABLE_REG);
752 printk(KERN_ALERT "[DISPLAY] EOT_DISABLE_REG = %x\n", temp_val);
753
754 temp_val = REG_READ(LP_BYTECLK_REG);
755 printk(KERN_ALERT "[DISPLAY] LP_BYTECLK_REG = %x\n", temp_val);
756 temp_val = REG_READ(MAX_RET_PAK_REG);
757 printk(KERN_ALERT "[DISPLAY] MAX_RET_PAK_REG = %x\n", temp_val);
758 temp_val = REG_READ(DPI_CONTROL_REG);
759 printk(KERN_ALERT "[DISPLAY] DPI_CONTROL_REG = %x\n", temp_val);
760 temp_val = REG_READ(DPHY_PARAM_REG);
761 printk(KERN_ALERT "[DISPLAY] DPHY_PARAM_REG = %x\n", temp_val);
762// temp_val = REG_READ(PIPEACONF);
763// printk(KERN_INFO "[DISPLAY] PIPEACONF = %x\n", temp_val);
764// temp_val = REG_READ(DSPACNTR);
765// printk(KERN_INFO "[DISPLAY] DSPACNTR = %x\n", temp_val);
766}
767
768void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, 636void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder,
769 struct drm_display_mode *mode, 637 struct drm_display_mode *mode,
770 struct drm_display_mode *adjusted_mode) 638 struct drm_display_mode *adjusted_mode)
@@ -804,14 +672,11 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder,
804 REG_WRITE(mipi_reg, mipi); 672 REG_WRITE(mipi_reg, mipi);
805 REG_READ(mipi_reg); 673 REG_READ(mipi_reg);
806 674
807 /* Set up DSI controller DPI interface*/ 675 /* Set up DSI controller DPI interface */
808 mdfld_dsi_dpi_controller_init(dsi_config, pipe); 676 mdfld_dsi_dpi_controller_init(dsi_config, pipe);
809 677
810 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { 678 if (mdfld_get_panel_type(dev, pipe) != TMD_VID) {
811 /* init driver ic */ 679 /* Turn on DPI interface */
812 mdfld_dsi_tmd_drv_ic_init(dsi_config, pipe);
813 } else {
814 /*turn on DPI interface*/
815 mdfld_dsi_dpi_turn_on(dpi_output, pipe); 680 mdfld_dsi_dpi_turn_on(dpi_output, pipe);
816 } 681 }
817 682
@@ -829,81 +694,15 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder,
829 REG_READ(MIPIA_INTR_STAT_REG + reg_offset), 694 REG_READ(MIPIA_INTR_STAT_REG + reg_offset),
830 dpi_output->panel_on); 695 dpi_output->panel_on);
831 696
832 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { 697 if (mdfld_get_panel_type(dev, pipe) != TMD_VID) {
833 //mdfld_dsi_dpi_turn_on(dpi_output, pipe); 698 /* Init driver ic */
834 } else {
835 /* init driver ic */
836 mdfld_dsi_tpo_ic_init(dsi_config, pipe); 699 mdfld_dsi_tpo_ic_init(dsi_config, pipe);
837 /*init backlight*/ 700 /* Init backlight */
838 mdfld_dsi_brightness_init(dsi_config, pipe); 701 mdfld_dsi_brightness_init(dsi_config, pipe);
839 } 702 }
840
841#ifdef MIPI_DEBUG_LOG
842 dsi_debug_MIPI_reg(dev);
843#endif
844 gma_power_end(dev); 703 gma_power_end(dev);
845} 704}
846 705
847static int mdfld_dpi_panel_reset(int pipe)
848{
849 unsigned gpio;
850 int ret = 0;
851
852 switch(pipe) {
853 case 0:
854 gpio = 128;
855 break;
856 case 2:
857 gpio = 34;
858 break;
859 default:
860 DRM_ERROR("Invalid output\n");
861 return -EINVAL;
862 }
863
864 ret = gpio_request(gpio, "gfx");
865 if(ret) {
866 DRM_ERROR("gpio_rqueset failed\n");
867 return ret;
868 }
869 ret = gpio_direction_output(gpio, 1);
870 if(ret) {
871 DRM_ERROR("gpio_direction_output failed\n");
872 goto gpio_error;
873 }
874
875 gpio_get_value(128);
876
877gpio_error:
878 if(gpio_is_valid(gpio))
879 gpio_free(gpio);
880 return ret;
881}
882
883/**
884 * Exit from DSR
885 */
886void mdfld_dsi_dpi_exit_idle (struct drm_device *dev, u32 update_src, void *p_surfaceAddr, bool check_hw_on_only)
887{
888 struct drm_psb_private *dev_priv = dev->dev_private;
889
890 if (!gma_power_begin(dev, true)) {
891 DRM_ERROR("hw begin failed\n");
892 return;
893 }
894
895 /* update the surface base address. */
896 if (p_surfaceAddr) {
897 REG_WRITE(DSPASURF, *((u32 *)p_surfaceAddr));
898#if defined(CONFIG_MDFD_DUAL_MIPI)
899 REG_WRITE(DSPCSURF, *((u32 *)p_surfaceAddr));
900#endif
901 }
902 mid_enable_pipe_event(dev_priv, 0);
903 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
904 dev_priv->is_in_idle = false;
905 dev_priv->dsr_idle_count = 0;
906}
907 706
908/* 707/*
909 * Init DSI DPI encoder. 708 * Init DSI DPI encoder.
@@ -912,40 +711,63 @@ void mdfld_dsi_dpi_exit_idle (struct drm_device *dev, u32 update_src, void *p_su
912 */ 711 */
913struct mdfld_dsi_encoder *mdfld_dsi_dpi_init(struct drm_device *dev, 712struct mdfld_dsi_encoder *mdfld_dsi_dpi_init(struct drm_device *dev,
914 struct mdfld_dsi_connector *dsi_connector, 713 struct mdfld_dsi_connector *dsi_connector,
915 struct panel_funcs*p_funcs) 714 struct panel_funcs *p_funcs)
916{ 715{
917 struct drm_psb_private *dev_priv = dev->dev_private;
918 struct mdfld_dsi_dpi_output *dpi_output = NULL; 716 struct mdfld_dsi_dpi_output *dpi_output = NULL;
919 struct mdfld_dsi_config *dsi_config; 717 struct mdfld_dsi_config *dsi_config;
920 struct drm_connector *connector = NULL; 718 struct drm_connector *connector = NULL;
921 struct drm_encoder *encoder = NULL; 719 struct drm_encoder *encoder = NULL;
922 struct drm_display_mode *fixed_mode = NULL; 720 struct drm_display_mode *fixed_mode = NULL;
721 int pipe;
722 u32 data;
923 int ret; 723 int ret;
924 724
925 if (!dsi_connector) { 725 if (!dsi_connector || !p_funcs) {
926 WARN_ON(1); 726 WARN_ON(1);
927 return NULL; 727 return NULL;
928 } 728 }
929 729
730 dsi_config = mdfld_dsi_get_config(dsi_connector);
731 pipe = dsi_connector->pipe;
732
733 /* Panel hard-reset */
734 if (p_funcs->reset) {
735 ret = p_funcs->reset(pipe);
736 if (ret) {
737 DRM_ERROR("Panel %d hard-reset failed\n", pipe);
738 return NULL;
739 }
740 }
741
742 /* Panel drvIC init */
743 if (p_funcs->drv_ic_init)
744 p_funcs->drv_ic_init(dsi_config, pipe);
745
746 /* Panel power mode detect */
747 ret = mdfld_dsi_get_power_mode(dsi_config,
748 &data,
749 MDFLD_DSI_LP_TRANSMISSION);
750 if (ret) {
751 DRM_ERROR("Panel %d get power mode failed\n", pipe);
752 dsi_connector->status = connector_status_disconnected;
753 } else {
754 DRM_INFO("pipe %d power mode 0x%x\n", pipe, data);
755 dsi_connector->status = connector_status_connected;
756 }
757
930 dpi_output = kzalloc(sizeof(struct mdfld_dsi_dpi_output), GFP_KERNEL); 758 dpi_output = kzalloc(sizeof(struct mdfld_dsi_dpi_output), GFP_KERNEL);
931 if(!dpi_output) { 759 if(!dpi_output) {
932 dev_err(dev->dev, "No memory for dsi_dpi_output\n"); 760 dev_err(dev->dev, "No memory for dsi_dpi_output\n");
933 return NULL; 761 return NULL;
934 } 762 }
935 /* Panel reset */ 763
936 ret = mdfld_dpi_panel_reset(dsi_connector->pipe);
937 if(ret) {
938 DRM_ERROR("reset panel error\n");
939 goto out_err1;
940 }
941
942 if(dsi_connector->pipe) 764 if(dsi_connector->pipe)
943 dpi_output->panel_on = 0; 765 dpi_output->panel_on = 0;
944 766 else
945 dpi_output->panel_on = 0; 767 dpi_output->panel_on = 0;
946 768
947
948 dpi_output->dev = dev; 769 dpi_output->dev = dev;
770 dpi_output->p_funcs = p_funcs;
949 dpi_output->first_boot = 1; 771 dpi_output->first_boot = 1;
950 772
951 /* Get fixed mode */ 773 /* Get fixed mode */
@@ -973,19 +795,6 @@ struct mdfld_dsi_encoder *mdfld_dsi_dpi_init(struct drm_device *dev,
973 encoder->possible_crtcs = (1 << 0); 795 encoder->possible_crtcs = (1 << 0);
974 encoder->possible_clones = (1 << 0); 796 encoder->possible_clones = (1 << 0);
975 } 797 }
976
977 dev_priv->dsr_fb_update = 0;
978 dev_priv->dsr_enable = false;
979 dev_priv->exit_idle = mdfld_dsi_dpi_exit_idle;
980#if defined(CONFIG_MDFLD_DSI_DPU) || defined(CONFIG_MDFLD_DSI_DSR)
981 dev_priv->dsr_enable_config = true;
982#endif /*CONFIG_MDFLD_DSI_DSR*/
983
984 return &dpi_output->base; 798 return &dpi_output->base;
985
986out_err1:
987 if(dpi_output)
988 kfree(dpi_output);
989 return NULL;
990} 799}
991 800
diff --git a/drivers/staging/gma500/mdfld_dsi_dpi.h b/drivers/staging/gma500/mdfld_dsi_dpi.h
index 68e65cce2a7..ed92d45ee74 100644
--- a/drivers/staging/gma500/mdfld_dsi_dpi.h
+++ b/drivers/staging/gma500/mdfld_dsi_dpi.h
@@ -47,6 +47,8 @@ struct mdfld_dsi_dpi_output {
47 47
48 int panel_on; 48 int panel_on;
49 int first_boot; 49 int first_boot;
50
51 struct panel_funcs *p_funcs;
50}; 52};
51 53
52#define MDFLD_DSI_DPI_OUTPUT(dsi_encoder) \ 54#define MDFLD_DSI_DPI_OUTPUT(dsi_encoder) \
@@ -73,8 +75,4 @@ extern void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output *output,
73 int pipe); 75 int pipe);
74extern void mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config *si_config, 76extern void mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config *si_config,
75 int pipe); 77 int pipe);
76extern void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe);
77extern void psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe,
78 u32 mask);
79
80#endif /*__MDFLD_DSI_DPI_H__*/ 78#endif /*__MDFLD_DSI_DPI_H__*/
diff --git a/drivers/staging/gma500/mdfld_dsi_output.c b/drivers/staging/gma500/mdfld_dsi_output.c
index ff75ece9dcf..3286c3da4d7 100644
--- a/drivers/staging/gma500/mdfld_dsi_output.c
+++ b/drivers/staging/gma500/mdfld_dsi_output.c
@@ -35,55 +35,18 @@
35 35
36#define MDFLD_DSI_BRIGHTNESS_MAX_LEVEL 100 36#define MDFLD_DSI_BRIGHTNESS_MAX_LEVEL 100
37 37
38/* get the CABC LABC from command line. */
39static int CABC_control = 1; 38static int CABC_control = 1;
40static int LABC_control = 1; 39static int LABC_control = 1;
41 40
42#ifdef MODULE
43module_param (CABC_control, int, 0644); 41module_param (CABC_control, int, 0644);
44module_param (LABC_control, int, 0644); 42module_param (LABC_control, int, 0644);
45#else
46static int __init parse_CABC_control(char *arg)
47{
48 /* CABC control can be passed in as a cmdline parameter */
49 /* to enable this feature add CABC=1 to cmdline */
50 /* to disable this feature add CABC=0 to cmdline */
51 if (!arg)
52 return -EINVAL;
53
54 if (!strcasecmp(arg, "0"))
55 CABC_control = 0;
56 else if (!strcasecmp (arg, "1"))
57 CABC_control = 1;
58
59 return 0;
60}
61early_param ("CABC", parse_CABC_control);
62
63static int __init parse_LABC_control(char *arg)
64{
65 /* LABC control can be passed in as a cmdline parameter */
66 /* to enable this feature add LABC=1 to cmdline */
67 /* to disable this feature add LABC=0 to cmdline */
68 if (!arg)
69 return -EINVAL;
70
71 if (!strcasecmp(arg, "0"))
72 LABC_control = 0;
73 else if (!strcasecmp (arg, "1"))
74 LABC_control = 1;
75
76 return 0;
77}
78early_param ("LABC", parse_LABC_control);
79#endif
80 43
81/** 44/**
82 * make these MCS command global 45 * make these MCS command global
83 * we don't need 'movl' everytime we send them. 46 * we don't need 'movl' everytime we send them.
84 * FIXME: these datas were provided by OEM, we should get them from GCT. 47 * FIXME: these datas were provided by OEM, we should get them from GCT.
85 **/ 48 **/
86static u32 mdfld_dbi_mcs_hysteresis[] = { 49static const u32 mdfld_dbi_mcs_hysteresis[] = {
87 0x42000f57, 0x8c006400, 0xff00bf00, 0xffffffff, 50 0x42000f57, 0x8c006400, 0xff00bf00, 0xffffffff,
88 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 51 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
89 0x38000aff, 0x82005000, 0xff00ab00, 0xffffffff, 52 0x38000aff, 0x82005000, 0xff00ab00, 0xffffffff,
@@ -91,25 +54,26 @@ static u32 mdfld_dbi_mcs_hysteresis[] = {
91 0x000000ff, 54 0x000000ff,
92}; 55};
93 56
94static u32 mdfld_dbi_mcs_display_profile[] = { 57static const u32 mdfld_dbi_mcs_display_profile[] = {
95 0x50281450, 0x0000c882, 0x00000000, 0x00000000, 58 0x50281450, 0x0000c882, 0x00000000, 0x00000000,
96 0x00000000, 59 0x00000000,
97}; 60};
98 61
99static u32 mdfld_dbi_mcs_kbbc_profile[] = { 62static const u32 mdfld_dbi_mcs_kbbc_profile[] = {
100 0x00ffcc60, 0x00000000, 0x00000000, 0x00000000, 63 0x00ffcc60, 0x00000000, 0x00000000, 0x00000000,
101}; 64};
102 65
103static u32 mdfld_dbi_mcs_gamma_profile[] = { 66static const u32 mdfld_dbi_mcs_gamma_profile[] = {
104 0x81111158, 0x88888888, 0x88888888, 67 0x81111158, 0x88888888, 0x88888888,
105}; 68};
106 69
107/* 70/*
108 * write hysteresis values. 71 * write hysteresis values.
109 */ 72 */
110static void mdfld_dsi_write_hysteresis (struct mdfld_dsi_config * dsi_config, int pipe) 73static void mdfld_dsi_write_hysteresis (struct mdfld_dsi_config *dsi_config,
74 int pipe)
111{ 75{
112 struct mdfld_dsi_pkg_sender * sender = mdfld_dsi_get_pkg_sender(dsi_config); 76 struct mdfld_dsi_pkg_sender *sender = mdfld_dsi_get_pkg_sender(dsi_config);
113 77
114 if(!sender) { 78 if(!sender) {
115 WARN_ON(1); 79 WARN_ON(1);
@@ -124,9 +88,9 @@ static void mdfld_dsi_write_hysteresis (struct mdfld_dsi_config * dsi_config, in
124/* 88/*
125 * write display profile values. 89 * write display profile values.
126 */ 90 */
127static void mdfld_dsi_write_display_profile (struct mdfld_dsi_config * dsi_config, int pipe) 91static void mdfld_dsi_write_display_profile(struct mdfld_dsi_config *dsi_config, int pipe)
128{ 92{
129 struct mdfld_dsi_pkg_sender * sender = mdfld_dsi_get_pkg_sender(dsi_config); 93 struct mdfld_dsi_pkg_sender *sender = mdfld_dsi_get_pkg_sender(dsi_config);
130 94
131 if(!sender) { 95 if(!sender) {
132 WARN_ON(1); 96 WARN_ON(1);
@@ -143,7 +107,7 @@ static void mdfld_dsi_write_display_profile (struct mdfld_dsi_config * dsi_confi
143 */ 107 */
144static void mdfld_dsi_write_kbbc_profile (struct mdfld_dsi_config * dsi_config, int pipe) 108static void mdfld_dsi_write_kbbc_profile (struct mdfld_dsi_config * dsi_config, int pipe)
145{ 109{
146 struct mdfld_dsi_pkg_sender * sender = mdfld_dsi_get_pkg_sender(dsi_config); 110 struct mdfld_dsi_pkg_sender *sender = mdfld_dsi_get_pkg_sender(dsi_config);
147 111
148 if(!sender) { 112 if(!sender) {
149 WARN_ON(1); 113 WARN_ON(1);
@@ -155,12 +119,12 @@ static void mdfld_dsi_write_kbbc_profile (struct mdfld_dsi_config * dsi_config,
155 MDFLD_DSI_SEND_PACKAGE); 119 MDFLD_DSI_SEND_PACKAGE);
156} 120}
157 121
158/** 122/*
159 * write gamma setting. 123 * write gamma setting.
160 */ 124 */
161static void mdfld_dsi_write_gamma_setting (struct mdfld_dsi_config * dsi_config, int pipe) 125static void mdfld_dsi_write_gamma_setting (struct mdfld_dsi_config *dsi_config, int pipe)
162{ 126{
163 struct mdfld_dsi_pkg_sender * sender = mdfld_dsi_get_pkg_sender(dsi_config); 127 struct mdfld_dsi_pkg_sender *sender = mdfld_dsi_get_pkg_sender(dsi_config);
164 128
165 if(!sender) { 129 if(!sender) {
166 WARN_ON(1); 130 WARN_ON(1);
@@ -172,7 +136,7 @@ static void mdfld_dsi_write_gamma_setting (struct mdfld_dsi_config * dsi_config,
172 MDFLD_DSI_SEND_PACKAGE); 136 MDFLD_DSI_SEND_PACKAGE);
173} 137}
174 138
175/** 139/*
176 * Check and see if the generic control or data buffer is empty and ready. 140 * Check and see if the generic control or data buffer is empty and ready.
177 */ 141 */
178void mdfld_dsi_gen_fifo_ready (struct drm_device *dev, u32 gen_fifo_stat_reg, u32 fifo_stat) 142void mdfld_dsi_gen_fifo_ready (struct drm_device *dev, u32 gen_fifo_stat_reg, u32 fifo_stat)
@@ -193,16 +157,16 @@ void mdfld_dsi_gen_fifo_ready (struct drm_device *dev, u32 gen_fifo_stat_reg, u3
193 gen_fifo_stat_reg); 157 gen_fifo_stat_reg);
194} 158}
195 159
196/** 160/*
197 * Manage the DSI MIPI keyboard and display brightness. 161 * Manage the DSI MIPI keyboard and display brightness.
198 * FIXME: this is exported to OSPM code. should work out an specific 162 * FIXME: this is exported to OSPM code. should work out an specific
199 * display interface to OSPM. 163 * display interface to OSPM.
200 */ 164 */
201void mdfld_dsi_brightness_init (struct mdfld_dsi_config * dsi_config, int pipe) 165void mdfld_dsi_brightness_init(struct mdfld_dsi_config *dsi_config, int pipe)
202{ 166{
203 struct mdfld_dsi_pkg_sender * sender = mdfld_dsi_get_pkg_sender(dsi_config); 167 struct mdfld_dsi_pkg_sender *sender = mdfld_dsi_get_pkg_sender(dsi_config);
204 struct drm_device * dev = sender->dev; 168 struct drm_device *dev = sender->dev;
205 struct drm_psb_private * dev_priv = dev->dev_private; 169 struct drm_psb_private *dev_priv = dev->dev_private;
206 u32 gen_ctrl_val; 170 u32 gen_ctrl_val;
207 171
208 if(!sender) { 172 if(!sender) {
@@ -223,7 +187,7 @@ void mdfld_dsi_brightness_init (struct mdfld_dsi_config * dsi_config, int pipe)
223 1, 187 1,
224 MDFLD_DSI_SEND_PACKAGE); 188 MDFLD_DSI_SEND_PACKAGE);
225 189
226 mdfld_dsi_write_hysteresis (dsi_config, pipe); 190 mdfld_dsi_write_hysteresis(dsi_config, pipe);
227 mdfld_dsi_write_display_profile (dsi_config, pipe); 191 mdfld_dsi_write_display_profile (dsi_config, pipe);
228 mdfld_dsi_write_kbbc_profile (dsi_config, pipe); 192 mdfld_dsi_write_kbbc_profile (dsi_config, pipe);
229 mdfld_dsi_write_gamma_setting (dsi_config, pipe); 193 mdfld_dsi_write_gamma_setting (dsi_config, pipe);
@@ -253,7 +217,7 @@ void mdfld_dsi_brightness_init (struct mdfld_dsi_config * dsi_config, int pipe)
253 MDFLD_DSI_SEND_PACKAGE); 217 MDFLD_DSI_SEND_PACKAGE);
254} 218}
255 219
256/** 220/*
257 * Manage the mipi display brightness. 221 * Manage the mipi display brightness.
258 * TODO: refine this interface later 222 * TODO: refine this interface later
259 */ 223 */
@@ -262,8 +226,8 @@ void mdfld_dsi_brightness_control(struct drm_device *dev, int pipe, int level)
262 struct mdfld_dsi_pkg_sender *sender; 226 struct mdfld_dsi_pkg_sender *sender;
263 struct drm_psb_private *dev_priv; 227 struct drm_psb_private *dev_priv;
264 struct mdfld_dsi_config *dsi_config; 228 struct mdfld_dsi_config *dsi_config;
265 u32 gen_ctrl_val = 0; 229 u32 gen_ctrl_val;
266 int p_type = TMD_VID; 230 int p_type;
267 231
268 if (!dev || (pipe != 0 && pipe != 2)) { 232 if (!dev || (pipe != 0 && pipe != 2)) {
269 dev_err(dev->dev, "Invalid parameter\n"); 233 dev_err(dev->dev, "Invalid parameter\n");
@@ -288,7 +252,8 @@ void mdfld_dsi_brightness_control(struct drm_device *dev, int pipe, int level)
288 252
289 gen_ctrl_val = ((level * 0xff) / MDFLD_DSI_BRIGHTNESS_MAX_LEVEL) & 0xff; 253 gen_ctrl_val = ((level * 0xff) / MDFLD_DSI_BRIGHTNESS_MAX_LEVEL) & 0xff;
290 254
291 dev_dbg(dev->dev, "pipe = %d, gen_ctrl_val = %d. \n", pipe, gen_ctrl_val); 255 dev_dbg(dev->dev,
256 "pipe = %d, gen_ctrl_val = %d. \n", pipe, gen_ctrl_val);
292 257
293 if(p_type == TMD_VID || p_type == TMD_CMD){ 258 if(p_type == TMD_VID || p_type == TMD_CMD){
294 /* Set display backlight value */ 259 /* Set display backlight value */
@@ -344,7 +309,7 @@ void mdfld_dsi_controller_shutdown(struct mdfld_dsi_config * dsi_config, int pip
344 if(!(REG_READ(MIPIA_DEVICE_READY_REG + reg_offset) & DSI_DEVICE_READY)) 309 if(!(REG_READ(MIPIA_DEVICE_READY_REG + reg_offset) & DSI_DEVICE_READY))
345 goto shutdown_out; 310 goto shutdown_out;
346 311
347 /*send shut down package, clean packet send bit first*/ 312 /* Send shut down package, clean packet send bit first */
348 if(REG_READ(MIPIA_INTR_STAT_REG + reg_offset) & DSI_INTR_STATE_SPL_PKG_SENT) { 313 if(REG_READ(MIPIA_INTR_STAT_REG + reg_offset) & DSI_INTR_STATE_SPL_PKG_SENT) {
349 REG_WRITE((MIPIA_INTR_STAT_REG + reg_offset), 314 REG_WRITE((MIPIA_INTR_STAT_REG + reg_offset),
350 (REG_READ(MIPIA_INTR_STAT_REG + reg_offset) | DSI_INTR_STATE_SPL_PKG_SENT)); 315 (REG_READ(MIPIA_INTR_STAT_REG + reg_offset) | DSI_INTR_STATE_SPL_PKG_SENT));
@@ -432,6 +397,53 @@ startup_out:
432 gma_power_end(dev); 397 gma_power_end(dev);
433} 398}
434 399
400
401static int mdfld_dsi_get_panel_status(struct mdfld_dsi_config *dsi_config,
402 u8 dcs,
403 u32 *data,
404 u8 transmission)
405{
406 struct mdfld_dsi_pkg_sender *sender
407 = mdfld_dsi_get_pkg_sender(dsi_config);
408
409 if (!sender || !data) {
410 DRM_ERROR("Invalid parameter\n");
411 return -EINVAL;
412 }
413
414 if (transmission == MDFLD_DSI_HS_TRANSMISSION)
415 return mdfld_dsi_read_mcs_hs(sender, dcs, data, 1);
416 else if (transmission == MDFLD_DSI_LP_TRANSMISSION)
417 return mdfld_dsi_read_mcs_lp(sender, dcs, data, 1);
418 else
419 return -EINVAL;
420}
421
422int mdfld_dsi_get_power_mode(struct mdfld_dsi_config *dsi_config,
423 u32 *mode,
424 u8 transmission)
425{
426 if (!dsi_config || !mode) {
427 DRM_ERROR("Invalid parameter\n");
428 return -EINVAL;
429 }
430
431 return mdfld_dsi_get_panel_status(dsi_config, 0x0a, mode, transmission);
432}
433
434int mdfld_dsi_get_diagnostic_result(struct mdfld_dsi_config *dsi_config,
435 u32 *result,
436 u8 transmission)
437{
438 if (!dsi_config || !result) {
439 DRM_ERROR("Invalid parameter\n");
440 return -EINVAL;
441 }
442
443 return mdfld_dsi_get_panel_status(dsi_config, 0x0f, result,
444 transmission);
445}
446
435/* 447/*
436 * NOTE: this function was used by OSPM. 448 * NOTE: this function was used by OSPM.
437 * TODO: will be removed later, should work out display interfaces for OSPM 449 * TODO: will be removed later, should work out display interfaces for OSPM
@@ -459,14 +471,18 @@ static void mdfld_dsi_connector_restore(struct drm_connector * connector)
459 471
460static enum drm_connector_status mdfld_dsi_connector_detect(struct drm_connector * connector, bool force) 472static enum drm_connector_status mdfld_dsi_connector_detect(struct drm_connector * connector, bool force)
461{ 473{
462 return connector_status_connected; 474 struct psb_intel_output *psb_output
475 = to_psb_intel_output(connector);
476 struct mdfld_dsi_connector *dsi_connector
477 = MDFLD_DSI_CONNECTOR(psb_output);
478 return dsi_connector->status;
463} 479}
464 480
465static int mdfld_dsi_connector_set_property(struct drm_connector * connector, 481static int mdfld_dsi_connector_set_property(struct drm_connector *connector,
466 struct drm_property * property, 482 struct drm_property *property,
467 uint64_t value) 483 uint64_t value)
468{ 484{
469 struct drm_encoder * encoder = connector->encoder; 485 struct drm_encoder *encoder = connector->encoder;
470 486
471 if (!strcmp(property->name, "scaling mode") && encoder) { 487 if (!strcmp(property->name, "scaling mode") && encoder) {
472 struct psb_intel_crtc * psb_crtc = to_psb_intel_crtc(encoder->crtc); 488 struct psb_intel_crtc * psb_crtc = to_psb_intel_crtc(encoder->crtc);
@@ -633,9 +649,12 @@ static void mdfld_dsi_connector_dpms(struct drm_connector *connector, int mode)
633 } 649 }
634 650
635 /* Then check all display panels + monitors status */ 651 /* Then check all display panels + monitors status */
652 /* Make sure that the Display (B) sub-system status isn't i3 when
653 * R/W the DC register, otherwise "Fabric error" issue would occur
654 * during S0i3 state. */
636 if(!panel_on && !panel_on2 && !(REG_READ(HDMIB_CONTROL) 655 if(!panel_on && !panel_on2 && !(REG_READ(HDMIB_CONTROL)
637 & HDMIB_PORT_EN)) { 656 & HDMIB_PORT_EN)) {
638 /*request rpm idle*/ 657 /* Request rpm idle */
639 if(dev_priv->rpm_enabled) 658 if(dev_priv->rpm_enabled)
640 pm_request_idle(&dev->pdev->dev); 659 pm_request_idle(&dev->pdev->dev);
641 } 660 }
@@ -652,8 +671,8 @@ static void mdfld_dsi_connector_dpms(struct drm_connector *connector, int mode)
652#endif 671#endif
653} 672}
654 673
655static struct drm_encoder * mdfld_dsi_connector_best_encoder( 674static struct drm_encoder *mdfld_dsi_connector_best_encoder(
656 struct drm_connector * connector) 675 struct drm_connector *connector)
657{ 676{
658 struct psb_intel_output * psb_output = to_psb_intel_output(connector); 677 struct psb_intel_output * psb_output = to_psb_intel_output(connector);
659 struct mdfld_dsi_connector * dsi_connector = MDFLD_DSI_CONNECTOR(psb_output); 678 struct mdfld_dsi_connector * dsi_connector = MDFLD_DSI_CONNECTOR(psb_output);
@@ -755,16 +774,6 @@ mdfld_dsi_get_configuration_mode(struct mdfld_dsi_config * dsi_config, int pipe)
755 mode->vtotal = mode->vdisplay + \ 774 mode->vtotal = mode->vdisplay + \
756 ((ti->vblank_hi << 8) | ti->vblank_lo); 775 ((ti->vblank_hi << 8) | ti->vblank_lo);
757 mode->clock = ti->pixel_clock * 10; 776 mode->clock = ti->pixel_clock * 10;
758
759 dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay);
760 dev_dbg(dev->dev, "vdisplay is %d\n", mode->vdisplay);
761 dev_dbg(dev->dev, "HSS is %d\n", mode->hsync_start);
762 dev_dbg(dev->dev, "HSE is %d\n", mode->hsync_end);
763 dev_dbg(dev->dev, "htotal is %d\n", mode->htotal);
764 dev_dbg(dev->dev, "VSS is %d\n", mode->vsync_start);
765 dev_dbg(dev->dev, "VSE is %d\n", mode->vsync_end);
766 dev_dbg(dev->dev, "vtotal is %d\n", mode->vtotal);
767 dev_dbg(dev->dev, "clock is %d\n", mode->clock);
768 } else { 777 } else {
769 if(dsi_config->type == MDFLD_DSI_ENCODER_DPI) { 778 if(dsi_config->type == MDFLD_DSI_ENCODER_DPI) {
770 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { 779 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) {
@@ -810,6 +819,44 @@ mdfld_dsi_get_configuration_mode(struct mdfld_dsi_config * dsi_config, int pipe)
810 return mode; 819 return mode;
811} 820}
812 821
822int mdfld_dsi_panel_reset(int pipe)
823{
824 unsigned gpio;
825 int ret = 0;
826
827 switch (pipe) {
828 case 0:
829 gpio = 128;
830 break;
831 case 2:
832 gpio = 34;
833 break;
834 default:
835 DRM_ERROR("Invalid output\n");
836 return -EINVAL;
837 }
838
839 ret = gpio_request(gpio, "gfx");
840 if (ret) {
841 DRM_ERROR("gpio_rqueset failed\n");
842 return ret;
843 }
844
845 ret = gpio_direction_output(gpio, 1);
846 if (ret) {
847 DRM_ERROR("gpio_direction_output failed\n");
848 goto gpio_error;
849 }
850
851 gpio_get_value(128);
852
853gpio_error:
854 if (gpio_is_valid(gpio))
855 gpio_free(gpio);
856
857 return ret;
858}
859
813/* 860/*
814 * MIPI output init 861 * MIPI output init
815 * @dev drm device 862 * @dev drm device
@@ -819,9 +866,9 @@ mdfld_dsi_get_configuration_mode(struct mdfld_dsi_config * dsi_config, int pipe)
819 * Do the initialization of a MIPI output, including create DRM mode objects 866 * Do the initialization of a MIPI output, including create DRM mode objects
820 * initialization of DSI output on @pipe 867 * initialization of DSI output on @pipe
821 */ 868 */
822void mdfld_dsi_output_init(struct drm_device * dev, 869void mdfld_dsi_output_init(struct drm_device *dev,
823 int pipe, 870 int pipe,
824 struct mdfld_dsi_config * config, 871 struct mdfld_dsi_config *config,
825 struct panel_funcs* p_cmd_funcs, 872 struct panel_funcs* p_cmd_funcs,
826 struct panel_funcs* p_vid_funcs) 873 struct panel_funcs* p_vid_funcs)
827{ 874{
@@ -869,7 +916,7 @@ void mdfld_dsi_output_init(struct drm_device * dev,
869 dsi_config->changed = 1; 916 dsi_config->changed = 1;
870 dsi_config->dev = dev; 917 dsi_config->dev = dev;
871 918
872 /*init fixed mode basing on DSI config type*/ 919 /* Init fixed mode basing on DSI config type */
873 if(dsi_config->type == MDFLD_DSI_ENCODER_DBI) { 920 if(dsi_config->type == MDFLD_DSI_ENCODER_DBI) {
874 dsi_config->fixed_mode = p_cmd_funcs->get_config_mode(dev); 921 dsi_config->fixed_mode = p_cmd_funcs->get_config_mode(dev);
875 if(p_cmd_funcs->get_panel_info(dev, pipe, &dsi_panel_info)) 922 if(p_cmd_funcs->get_panel_info(dev, pipe, &dsi_panel_info))
@@ -917,12 +964,18 @@ void mdfld_dsi_output_init(struct drm_device * dev,
917 connector->interlace_allowed = false; 964 connector->interlace_allowed = false;
918 connector->doublescan_allowed = false; 965 connector->doublescan_allowed = false;
919 966
920 /*attach properties*/ 967 /* Attach properties */
921 drm_connector_attach_property(connector, dev->mode_config.scaling_mode_property, DRM_MODE_SCALE_FULLSCREEN); 968 drm_connector_attach_property(connector, dev->mode_config.scaling_mode_property, DRM_MODE_SCALE_FULLSCREEN);
922 drm_connector_attach_property(connector, dev_priv->backlight_property, MDFLD_DSI_BRIGHTNESS_MAX_LEVEL); 969 drm_connector_attach_property(connector, dev_priv->backlight_property, MDFLD_DSI_BRIGHTNESS_MAX_LEVEL);
923 970
924 /*init DBI & DPI encoders*/ 971 /* Init DSI package sender on this output */
925 if(p_cmd_funcs) { 972 if (mdfld_dsi_pkg_sender_init(dsi_connector, pipe)) {
973 DRM_ERROR("Package Sender initialization failed on pipe %d\n", pipe);
974 goto dsi_init_err0;
975 }
976
977 /* Init DBI & DPI encoders */
978 if (p_cmd_funcs) {
926 encoder = mdfld_dsi_dbi_init(dev, dsi_connector, p_cmd_funcs); 979 encoder = mdfld_dsi_dbi_init(dev, dsi_connector, p_cmd_funcs);
927 if(!encoder) { 980 if(!encoder) {
928 dev_err(dev->dev, "Create DBI encoder failed\n"); 981 dev_err(dev->dev, "Create DBI encoder failed\n");
@@ -930,12 +983,6 @@ void mdfld_dsi_output_init(struct drm_device * dev,
930 } 983 }
931 encoder->private = dsi_config; 984 encoder->private = dsi_config;
932 dsi_config->encoders[MDFLD_DSI_ENCODER_DBI] = encoder; 985 dsi_config->encoders[MDFLD_DSI_ENCODER_DBI] = encoder;
933 if(pipe == 2)
934 dev_priv->encoder2 = encoder;
935
936 if(pipe == 0)
937 dev_priv->encoder0 = encoder;
938
939 } 986 }
940 987
941 if(p_vid_funcs) { 988 if(p_vid_funcs) {
@@ -946,31 +993,16 @@ void mdfld_dsi_output_init(struct drm_device * dev,
946 } 993 }
947 encoder->private = dsi_config; 994 encoder->private = dsi_config;
948 dsi_config->encoders[MDFLD_DSI_ENCODER_DPI] = encoder; 995 dsi_config->encoders[MDFLD_DSI_ENCODER_DPI] = encoder;
949
950 if(pipe == 2)
951 dev_priv->encoder2 = encoder;
952
953 if(pipe == 0)
954 dev_priv->encoder0 = encoder;
955 } 996 }
956 997
957 drm_sysfs_connector_add(connector); 998 drm_sysfs_connector_add(connector);
958
959 /*init DSI package sender on this output*/
960 if(mdfld_dsi_pkg_sender_init(dsi_connector, pipe)) {
961 dev_err(dev->dev,
962 "Package Sender initialization failed on pipe %d\n",
963 pipe);
964 goto dsi_init_err2;
965 }
966
967 dev_dbg(dev->dev, "successfully\n");
968 return; 999 return;
969 1000
970 /*TODO: add code to destroy outputs on error*/ 1001 /*TODO: add code to destroy outputs on error*/
971dsi_init_err2:
972 drm_sysfs_connector_remove(connector);
973dsi_init_err1: 1002dsi_init_err1:
1003 /*destroy sender*/
1004 mdfld_dsi_pkg_sender_destroy(dsi_connector->pkg_sender);
1005
974 drm_connector_cleanup(connector); 1006 drm_connector_cleanup(connector);
975 kfree(dsi_config->fixed_mode); 1007 kfree(dsi_config->fixed_mode);
976 kfree(dsi_config); 1008 kfree(dsi_config);
diff --git a/drivers/staging/gma500/mdfld_dsi_output.h b/drivers/staging/gma500/mdfld_dsi_output.h
index 4300f10fbc8..4699267efd6 100644
--- a/drivers/staging/gma500/mdfld_dsi_output.h
+++ b/drivers/staging/gma500/mdfld_dsi_output.h
@@ -42,202 +42,6 @@
42 42
43#include <asm/mrst.h> 43#include <asm/mrst.h>
44 44
45#define DRM_MODE_ENCODER_MIPI 5
46
47/* Medfield DSI controller registers */
48
49#define MIPIA_DEVICE_READY_REG 0xb000
50#define MIPIA_INTR_STAT_REG 0xb004
51#define MIPIA_INTR_EN_REG 0xb008
52#define MIPIA_DSI_FUNC_PRG_REG 0xb00c
53#define MIPIA_HS_TX_TIMEOUT_REG 0xb010
54#define MIPIA_LP_RX_TIMEOUT_REG 0xb014
55#define MIPIA_TURN_AROUND_TIMEOUT_REG 0xb018
56#define MIPIA_DEVICE_RESET_TIMER_REG 0xb01c
57#define MIPIA_DPI_RESOLUTION_REG 0xb020
58#define MIPIA_DBI_FIFO_THROTTLE_REG 0xb024
59#define MIPIA_HSYNC_COUNT_REG 0xb028
60#define MIPIA_HBP_COUNT_REG 0xb02c
61#define MIPIA_HFP_COUNT_REG 0xb030
62#define MIPIA_HACTIVE_COUNT_REG 0xb034
63#define MIPIA_VSYNC_COUNT_REG 0xb038
64#define MIPIA_VBP_COUNT_REG 0xb03c
65#define MIPIA_VFP_COUNT_REG 0xb040
66#define MIPIA_HIGH_LOW_SWITCH_COUNT_REG 0xb044
67#define MIPIA_DPI_CONTROL_REG 0xb048
68#define MIPIA_DPI_DATA_REG 0xb04c
69#define MIPIA_INIT_COUNT_REG 0xb050
70#define MIPIA_MAX_RETURN_PACK_SIZE_REG 0xb054
71#define MIPIA_VIDEO_MODE_FORMAT_REG 0xb058
72#define MIPIA_EOT_DISABLE_REG 0xb05c
73#define MIPIA_LP_BYTECLK_REG 0xb060
74#define MIPIA_LP_GEN_DATA_REG 0xb064
75#define MIPIA_HS_GEN_DATA_REG 0xb068
76#define MIPIA_LP_GEN_CTRL_REG 0xb06c
77#define MIPIA_HS_GEN_CTRL_REG 0xb070
78#define MIPIA_GEN_FIFO_STAT_REG 0xb074
79#define MIPIA_HS_LS_DBI_ENABLE_REG 0xb078
80#define MIPIA_DPHY_PARAM_REG 0xb080
81#define MIPIA_DBI_BW_CTRL_REG 0xb084
82#define MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG 0xb088
83
84#define DSI_DEVICE_READY (0x1)
85#define DSI_POWER_STATE_ULPS_ENTER (0x2 << 1)
86#define DSI_POWER_STATE_ULPS_EXIT (0x1 << 1)
87#define DSI_POWER_STATE_ULPS_OFFSET (0x1)
88
89
90#define DSI_ONE_DATA_LANE (0x1)
91#define DSI_TWO_DATA_LANE (0x2)
92#define DSI_THREE_DATA_LANE (0X3)
93#define DSI_FOUR_DATA_LANE (0x4)
94#define DSI_DPI_VIRT_CHANNEL_OFFSET (0x3)
95#define DSI_DBI_VIRT_CHANNEL_OFFSET (0x5)
96#define DSI_DPI_COLOR_FORMAT_RGB565 (0x01 << 7)
97#define DSI_DPI_COLOR_FORMAT_RGB666 (0x02 << 7)
98#define DSI_DPI_COLOR_FORMAT_RGB666_UNPACK (0x03 << 7)
99#define DSI_DPI_COLOR_FORMAT_RGB888 (0x04 << 7)
100#define DSI_DBI_COLOR_FORMAT_OPTION2 (0x05 << 13)
101
102#define DSI_INTR_STATE_RXSOTERROR 1
103
104#define DSI_INTR_STATE_SPL_PKG_SENT (1 << 30)
105#define DSI_INTR_STATE_TE (1 << 31)
106
107#define DSI_HS_TX_TIMEOUT_MASK (0xffffff)
108
109#define DSI_LP_RX_TIMEOUT_MASK (0xffffff)
110
111#define DSI_TURN_AROUND_TIMEOUT_MASK (0x3f)
112
113#define DSI_RESET_TIMER_MASK (0xffff)
114
115#define DSI_DBI_FIFO_WM_HALF (0x0)
116#define DSI_DBI_FIFO_WM_QUARTER (0x1)
117#define DSI_DBI_FIFO_WM_LOW (0x2)
118
119#define DSI_DPI_TIMING_MASK (0xffff)
120
121#define DSI_INIT_TIMER_MASK (0xffff)
122
123#define DSI_DBI_RETURN_PACK_SIZE_MASK (0x3ff)
124
125#define DSI_LP_BYTECLK_MASK (0x0ffff)
126
127#define DSI_HS_CTRL_GEN_SHORT_W0 (0x03)
128#define DSI_HS_CTRL_GEN_SHORT_W1 (0x13)
129#define DSI_HS_CTRL_GEN_SHORT_W2 (0x23)
130#define DSI_HS_CTRL_GEN_R0 (0x04)
131#define DSI_HS_CTRL_GEN_R1 (0x14)
132#define DSI_HS_CTRL_GEN_R2 (0x24)
133#define DSI_HS_CTRL_GEN_LONG_W (0x29)
134#define DSI_HS_CTRL_MCS_SHORT_W0 (0x05)
135#define DSI_HS_CTRL_MCS_SHORT_W1 (0x15)
136#define DSI_HS_CTRL_MCS_R0 (0x06)
137#define DSI_HS_CTRL_MCS_LONG_W (0x39)
138#define DSI_HS_CTRL_VC_OFFSET (0x06)
139#define DSI_HS_CTRL_WC_OFFSET (0x08)
140
141#define DSI_FIFO_GEN_HS_DATA_FULL (1 << 0)
142#define DSI_FIFO_GEN_HS_DATA_HALF_EMPTY (1 << 1)
143#define DSI_FIFO_GEN_HS_DATA_EMPTY (1 << 2)
144#define DSI_FIFO_GEN_LP_DATA_FULL (1 << 8)
145#define DSI_FIFO_GEN_LP_DATA_HALF_EMPTY (1 << 9)
146#define DSI_FIFO_GEN_LP_DATA_EMPTY (1 << 10)
147#define DSI_FIFO_GEN_HS_CTRL_FULL (1 << 16)
148#define DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY (1 << 17)
149#define DSI_FIFO_GEN_HS_CTRL_EMPTY (1 << 18)
150#define DSI_FIFO_GEN_LP_CTRL_FULL (1 << 24)
151#define DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY (1 << 25)
152#define DSI_FIFO_GEN_LP_CTRL_EMPTY (1 << 26)
153#define DSI_FIFO_DBI_EMPTY (1 << 27)
154#define DSI_FIFO_DPI_EMPTY (1 << 28)
155
156#define DSI_DBI_HS_LP_SWITCH_MASK (0x1)
157
158#define DSI_HS_LP_SWITCH_COUNTER_OFFSET (0x0)
159#define DSI_LP_HS_SWITCH_COUNTER_OFFSET (0x16)
160
161#define DSI_DPI_CTRL_HS_SHUTDOWN (0x00000001)
162#define DSI_DPI_CTRL_HS_TURN_ON (0x00000002)
163
164/* Medfield DSI adapter registers */
165#define MIPIA_CONTROL_REG 0xb104
166#define MIPIA_DATA_ADD_REG 0xb108
167#define MIPIA_DATA_LEN_REG 0xb10c
168#define MIPIA_CMD_ADD_REG 0xb110
169#define MIPIA_CMD_LEN_REG 0xb114
170
171enum {
172 MDFLD_DSI_ENCODER_DBI = 0,
173 MDFLD_DSI_ENCODER_DPI,
174};
175
176enum {
177 MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_PULSE = 1,
178 MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_EVENTS = 2,
179 MDFLD_DSI_VIDEO_BURST_MODE = 3,
180};
181
182#define DSI_DPI_COMPLETE_LAST_LINE (1 << 2)
183#define DSI_DPI_DISABLE_BTA (1 << 3)
184
185struct mdfld_dsi_connector_state {
186 u32 mipi_ctrl_reg;
187};
188
189struct mdfld_dsi_encoder_state {
190
191};
192
193struct mdfld_dsi_connector {
194 /*
195 * This is ugly, but I have to use connector in it! :-(
196 * FIXME: use drm_connector instead.
197 */
198 struct psb_intel_output base;
199
200 int pipe;
201 void *private;
202 void *pkg_sender;
203};
204
205struct mdfld_dsi_encoder {
206 struct drm_encoder base;
207 void *private;
208};
209
210/*
211 * DSI config, consists of one DSI connector, two DSI encoders.
212 * DRM will pick up on DSI encoder basing on differents configs.
213 */
214struct mdfld_dsi_config {
215 struct drm_device *dev;
216 struct drm_display_mode *fixed_mode;
217 struct drm_display_mode *mode;
218
219 struct mdfld_dsi_connector *connector;
220 struct mdfld_dsi_encoder *encoders[DRM_CONNECTOR_MAX_ENCODER];
221 struct mdfld_dsi_encoder *encoder;
222
223 int changed;
224
225 int bpp;
226 int type;
227 int lane_count;
228 /*Virtual channel number for this encoder*/
229 int channel_num;
230 /*video mode configure*/
231 int video_mode;
232
233 int dvr_ic_inited;
234};
235
236#define MDFLD_DSI_CONNECTOR(psb_output) \
237 (container_of(psb_output, struct mdfld_dsi_connector, base))
238
239#define MDFLD_DSI_ENCODER(encoder) \
240 (container_of(encoder, struct mdfld_dsi_encoder, base))
241 45
242static inline struct mdfld_dsi_config * 46static inline struct mdfld_dsi_config *
243 mdfld_dsi_get_config(struct mdfld_dsi_connector *connector) 47 mdfld_dsi_get_config(struct mdfld_dsi_connector *connector)
@@ -323,5 +127,12 @@ extern void mdfld_dsi_output_init(struct drm_device *dev, int pipe,
323 struct panel_funcs *p_vid_funcs); 127 struct panel_funcs *p_vid_funcs);
324extern void mdfld_dsi_controller_init(struct mdfld_dsi_config *dsi_config, 128extern void mdfld_dsi_controller_init(struct mdfld_dsi_config *dsi_config,
325 int pipe); 129 int pipe);
130extern int mdfld_dsi_get_power_mode(struct mdfld_dsi_config *dsi_config,
131 u32 *mode,
132 u8 transmission);
133extern int mdfld_dsi_get_diagnostic_result(struct mdfld_dsi_config *dsi_config,
134 u32 *result,
135 u8 transmission);
136extern int mdfld_dsi_panel_reset(int pipe);
326 137
327#endif /*__MDFLD_DSI_OUTPUT_H__*/ 138#endif /*__MDFLD_DSI_OUTPUT_H__*/
diff --git a/drivers/staging/gma500/mdfld_dsi_pkg_sender.c b/drivers/staging/gma500/mdfld_dsi_pkg_sender.c
index 745d4adc82b..9b96a5c9abc 100644
--- a/drivers/staging/gma500/mdfld_dsi_pkg_sender.c
+++ b/drivers/staging/gma500/mdfld_dsi_pkg_sender.c
@@ -29,8 +29,11 @@
29#include "mdfld_dsi_output.h" 29#include "mdfld_dsi_output.h"
30#include "mdfld_dsi_pkg_sender.h" 30#include "mdfld_dsi_pkg_sender.h"
31#include "mdfld_dsi_dbi.h" 31#include "mdfld_dsi_dbi.h"
32#include "mdfld_dsi_dpi.h"
32 33
33#define MDFLD_DSI_DBI_FIFO_TIMEOUT 100 34#define MDFLD_DSI_DBI_FIFO_TIMEOUT 100
35#define MDFLD_DSI_MAX_RETURN_PACKET_SIZE 512
36#define MDFLD_DSI_READ_MAX_COUNT 5000
34 37
35static const char * const dsi_errors[] = { 38static const char * const dsi_errors[] = {
36 "RX SOT Error", 39 "RX SOT Error",
@@ -404,8 +407,10 @@ static int send_pkg_prepare(struct mdfld_dsi_pkg_sender *sender,
404 } 407 }
405 408
406 /* Wait for 120 milliseconds in case exit_sleep_mode just be sent */ 409 /* Wait for 120 milliseconds in case exit_sleep_mode just be sent */
407 if (cmd == enter_sleep_mode) 410 if (cmd == DCS_ENTER_SLEEP_MODE) {
411 /*TODO: replace it with msleep later*/
408 mdelay(120); 412 mdelay(120);
413 }
409 return 0; 414 return 0;
410} 415}
411 416
@@ -432,16 +437,18 @@ static int send_pkg_done(struct mdfld_dsi_pkg_sender *sender,
432 } 437 }
433 438
434 /* Update panel status */ 439 /* Update panel status */
435 if (cmd == enter_sleep_mode) { 440 if (cmd == DCS_ENTER_SLEEP_MODE) {
436 sender->panel_mode |= MDFLD_DSI_PANEL_MODE_SLEEP; 441 sender->panel_mode |= MDFLD_DSI_PANEL_MODE_SLEEP;
437 /*TODO: replace it with msleep later*/ 442 /*TODO: replace it with msleep later*/
438 mdelay(120); 443 mdelay(120);
439 } else if (cmd == exit_sleep_mode) { 444 } else if (cmd == DCS_EXIT_SLEEP_MODE) {
440 sender->panel_mode &= ~MDFLD_DSI_PANEL_MODE_SLEEP; 445 sender->panel_mode &= ~MDFLD_DSI_PANEL_MODE_SLEEP;
441 /*TODO: replace it with msleep later*/ 446 /*TODO: replace it with msleep later*/
442 mdelay(120); 447 mdelay(120);
443 } 448 } else if (unlikely(cmd == DCS_SOFT_RESET)) {
444 449 /*TODO: replace it with msleep later*/
450 mdelay(5);
451 }
445 sender->status = MDFLD_DSI_PKG_SENDER_FREE; 452 sender->status = MDFLD_DSI_PKG_SENDER_FREE;
446 return 0; 453 return 0;
447 454
@@ -470,6 +477,9 @@ static int do_send_pkg(struct mdfld_dsi_pkg_sender *sender,
470 case MDFLD_DSI_PKG_GEN_SHORT_WRITE_0: 477 case MDFLD_DSI_PKG_GEN_SHORT_WRITE_0:
471 case MDFLD_DSI_PKG_GEN_SHORT_WRITE_1: 478 case MDFLD_DSI_PKG_GEN_SHORT_WRITE_1:
472 case MDFLD_DSI_PKG_GEN_SHORT_WRITE_2: 479 case MDFLD_DSI_PKG_GEN_SHORT_WRITE_2:
480 case MDFLD_DSI_PKG_GEN_READ_0:
481 case MDFLD_DSI_PKG_GEN_READ_1:
482 case MDFLD_DSI_PKG_GEN_READ_2:
473 ret = send_gen_short_pkg(sender, pkg); 483 ret = send_gen_short_pkg(sender, pkg);
474 break; 484 break;
475 case MDFLD_DSI_PKG_GEN_LONG_WRITE: 485 case MDFLD_DSI_PKG_GEN_LONG_WRITE:
@@ -477,6 +487,7 @@ static int do_send_pkg(struct mdfld_dsi_pkg_sender *sender,
477 break; 487 break;
478 case MDFLD_DSI_PKG_MCS_SHORT_WRITE_0: 488 case MDFLD_DSI_PKG_MCS_SHORT_WRITE_0:
479 case MDFLD_DSI_PKG_MCS_SHORT_WRITE_1: 489 case MDFLD_DSI_PKG_MCS_SHORT_WRITE_1:
490 case MDFLD_DSI_PKG_MCS_READ:
480 ret = send_mcs_short_pkg(sender, pkg); 491 ret = send_mcs_short_pkg(sender, pkg);
481 break; 492 break;
482 case MDFLD_DSI_PKG_MCS_LONG_WRITE: 493 case MDFLD_DSI_PKG_MCS_LONG_WRITE:
@@ -548,6 +559,7 @@ static int mdfld_dbi_cb_init(struct mdfld_dsi_pkg_sender *sender,
548 559
549 switch (pipe) { 560 switch (pipe) {
550 case 0: 561 case 0:
562 /* FIXME: Doesn't this collide with stolen space ? */
551 phys = pg->gtt_phys_start - 0x1000; 563 phys = pg->gtt_phys_start - 0x1000;
552 break; 564 break;
553 case 2: 565 case 2:
@@ -735,6 +747,292 @@ static int mdfld_dsi_send_gen_long(struct mdfld_dsi_pkg_sender *sender,
735 return 0; 747 return 0;
736} 748}
737 749
750static int __read_panel_data(struct mdfld_dsi_pkg_sender *sender,
751 struct mdfld_dsi_pkg *pkg,
752 u32 *data,
753 u16 len)
754{
755 unsigned long flags;
756 struct drm_device *dev = sender->dev;
757 int i;
758 u32 gen_data_reg;
759 int retry = MDFLD_DSI_READ_MAX_COUNT;
760 u8 transmission = pkg->transmission_type;
761
762 /*
763 * do reading.
764 * 0) send out generic read request
765 * 1) polling read data avail interrupt
766 * 2) read data
767 */
768 spin_lock_irqsave(&sender->lock, flags);
769
770 REG_WRITE(sender->mipi_intr_stat_reg, 1 << 29);
771
772 if ((REG_READ(sender->mipi_intr_stat_reg) & (1 << 29)))
773 DRM_ERROR("Can NOT clean read data valid interrupt\n");
774
775 /*send out read request*/
776 send_pkg(sender, pkg);
777
778 pkg_sender_put_pkg_locked(sender, pkg);
779
780 /*polling read data avail interrupt*/
781 while (retry && !(REG_READ(sender->mipi_intr_stat_reg) & (1 << 29))) {
782 udelay(100);
783 retry--;
784 }
785
786 if (!retry) {
787 spin_unlock_irqrestore(&sender->lock, flags);
788 return -ETIMEDOUT;
789 }
790
791 REG_WRITE(sender->mipi_intr_stat_reg, (1 << 29));
792
793 /*read data*/
794 if (transmission == MDFLD_DSI_HS_TRANSMISSION)
795 gen_data_reg = sender->mipi_hs_gen_data_reg;
796 else if (transmission == MDFLD_DSI_LP_TRANSMISSION)
797 gen_data_reg = sender->mipi_lp_gen_data_reg;
798 else {
799 DRM_ERROR("Unknown transmission");
800 spin_unlock_irqrestore(&sender->lock, flags);
801 return -EINVAL;
802 }
803
804 for (i=0; i<len; i++)
805 *(data + i) = REG_READ(gen_data_reg);
806
807 spin_unlock_irqrestore(&sender->lock, flags);
808
809 return 0;
810}
811
812static int mdfld_dsi_read_gen(struct mdfld_dsi_pkg_sender *sender,
813 u8 param0,
814 u8 param1,
815 u8 param_num,
816 u32 *data,
817 u16 len,
818 u8 transmission)
819{
820 struct mdfld_dsi_pkg *pkg;
821 unsigned long flags;
822
823 spin_lock_irqsave(&sender->lock, flags);
824
825 pkg = pkg_sender_get_pkg_locked(sender);
826
827 spin_unlock_irqrestore(&sender->lock,flags);
828
829 if (!pkg) {
830 dev_err(sender->dev->dev, "No pkg memory\n");
831 return -ENOMEM;
832 }
833
834 switch (param_num) {
835 case 0:
836 pkg->pkg_type = MDFLD_DSI_PKG_GEN_READ_0;
837 pkg->pkg.short_pkg.cmd = 0;
838 pkg->pkg.short_pkg.param = 0;
839 break;
840 case 1:
841 pkg->pkg_type = MDFLD_DSI_PKG_GEN_READ_1;
842 pkg->pkg.short_pkg.cmd = param0;
843 pkg->pkg.short_pkg.param = 0;
844 break;
845 case 2:
846 pkg->pkg_type = MDFLD_DSI_PKG_GEN_READ_2;
847 pkg->pkg.short_pkg.cmd = param0;
848 pkg->pkg.short_pkg.param = param1;
849 break;
850 }
851
852 pkg->transmission_type = transmission;
853
854 INIT_LIST_HEAD(&pkg->entry);
855
856 return __read_panel_data(sender, pkg, data, len);
857}
858
859static int mdfld_dsi_read_mcs(struct mdfld_dsi_pkg_sender *sender,
860 u8 cmd,
861 u32 *data,
862 u16 len,
863 u8 transmission)
864{
865 struct mdfld_dsi_pkg *pkg;
866 unsigned long flags;
867
868 spin_lock_irqsave(&sender->lock, flags);
869
870 pkg = pkg_sender_get_pkg_locked(sender);
871
872 spin_unlock_irqrestore(&sender->lock, flags);
873
874 if (!pkg) {
875 dev_err(sender->dev->dev, "No pkg memory\n");
876 return -ENOMEM;
877 }
878
879 pkg->pkg_type = MDFLD_DSI_PKG_MCS_READ;
880 pkg->pkg.short_pkg.cmd = cmd;
881 pkg->pkg.short_pkg.param = 0;
882
883 pkg->transmission_type = transmission;
884
885 INIT_LIST_HEAD(&pkg->entry);
886
887 return __read_panel_data(sender, pkg, data, len);
888}
889
890void dsi_controller_dbi_init(struct mdfld_dsi_config * dsi_config, int pipe)
891{
892 struct drm_device * dev = dsi_config->dev;
893 u32 reg_offset = pipe ? MIPIC_REG_OFFSET : 0;
894 int lane_count = dsi_config->lane_count;
895 u32 val = 0;
896
897 /*un-ready device*/
898 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000000);
899
900 /*init dsi adapter before kicking off*/
901 REG_WRITE((MIPIA_CONTROL_REG + reg_offset), 0x00000018);
902
903 /*TODO: figure out how to setup these registers*/
904 REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150c3408);
905 REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG + reg_offset), 0x000a0014);
906 REG_WRITE((MIPIA_DBI_BW_CTRL_REG + reg_offset), 0x00000400);
907 REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000001);
908 REG_WRITE((MIPIA_HS_LS_DBI_ENABLE_REG + reg_offset), 0x00000000);
909
910 /*enable all interrupts*/
911 REG_WRITE((MIPIA_INTR_EN_REG + reg_offset), 0xffffffff);
912 /*max value: 20 clock cycles of txclkesc*/
913 REG_WRITE((MIPIA_TURN_AROUND_TIMEOUT_REG + reg_offset), 0x0000001f);
914 /*min 21 txclkesc, max: ffffh*/
915 REG_WRITE((MIPIA_DEVICE_RESET_TIMER_REG + reg_offset), 0x0000ffff);
916 /*min: 7d0 max: 4e20*/
917 REG_WRITE((MIPIA_INIT_COUNT_REG + reg_offset), 0x00000fa0);
918
919 /*set up max return packet size*/
920 REG_WRITE((MIPIA_MAX_RETURN_PACK_SIZE_REG + reg_offset),
921 MDFLD_DSI_MAX_RETURN_PACKET_SIZE);
922
923 /*set up func_prg*/
924 val |= lane_count;
925 val |= (dsi_config->channel_num << DSI_DBI_VIRT_CHANNEL_OFFSET);
926 val |= DSI_DBI_COLOR_FORMAT_OPTION2;
927 REG_WRITE((MIPIA_DSI_FUNC_PRG_REG + reg_offset), val);
928
929 REG_WRITE((MIPIA_HS_TX_TIMEOUT_REG + reg_offset), 0x3fffff);
930 REG_WRITE((MIPIA_LP_RX_TIMEOUT_REG + reg_offset), 0xffff);
931
932 REG_WRITE((MIPIA_HIGH_LOW_SWITCH_COUNT_REG + reg_offset), 0x46);
933 REG_WRITE((MIPIA_EOT_DISABLE_REG + reg_offset), 0x00000000);
934 REG_WRITE((MIPIA_LP_BYTECLK_REG + reg_offset), 0x00000004);
935 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000001);
936}
937
938void dsi_controller_dpi_init(struct mdfld_dsi_config * dsi_config, int pipe)
939{
940 struct drm_device * dev = dsi_config->dev;
941 u32 reg_offset = pipe ? MIPIC_REG_OFFSET : 0;
942 int lane_count = dsi_config->lane_count;
943 struct mdfld_dsi_dpi_timing dpi_timing;
944 struct drm_display_mode * mode = dsi_config->mode;
945 u32 val = 0;
946
947 /*un-ready device*/
948 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000000);
949
950 /*init dsi adapter before kicking off*/
951 REG_WRITE((MIPIA_CONTROL_REG + reg_offset), 0x00000018);
952
953 /*enable all interrupts*/
954 REG_WRITE((MIPIA_INTR_EN_REG + reg_offset), 0xffffffff);
955
956 /*set up func_prg*/
957 val |= lane_count;
958 val |= dsi_config->channel_num << DSI_DPI_VIRT_CHANNEL_OFFSET;
959
960 switch(dsi_config->bpp) {
961 case 16:
962 val |= DSI_DPI_COLOR_FORMAT_RGB565;
963 break;
964 case 18:
965 val |= DSI_DPI_COLOR_FORMAT_RGB666;
966 break;
967 case 24:
968 val |= DSI_DPI_COLOR_FORMAT_RGB888;
969 break;
970 default:
971 DRM_ERROR("unsupported color format, bpp = %d\n", dsi_config->bpp);
972 }
973
974 REG_WRITE((MIPIA_DSI_FUNC_PRG_REG + reg_offset), val);
975
976 REG_WRITE((MIPIA_HS_TX_TIMEOUT_REG + reg_offset),
977 (mode->vtotal * mode->htotal * dsi_config->bpp / (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK);
978 REG_WRITE((MIPIA_LP_RX_TIMEOUT_REG + reg_offset), 0xffff & DSI_LP_RX_TIMEOUT_MASK);
979
980 /*max value: 20 clock cycles of txclkesc*/
981 REG_WRITE((MIPIA_TURN_AROUND_TIMEOUT_REG + reg_offset), 0x14 & DSI_TURN_AROUND_TIMEOUT_MASK);
982
983 /*min 21 txclkesc, max: ffffh*/
984 REG_WRITE((MIPIA_DEVICE_RESET_TIMER_REG + reg_offset), 0xffff & DSI_RESET_TIMER_MASK);
985
986 REG_WRITE((MIPIA_DPI_RESOLUTION_REG + reg_offset), mode->vdisplay << 16 | mode->hdisplay);
987
988 /*set DPI timing registers*/
989 mdfld_dsi_dpi_timing_calculation(mode, &dpi_timing, dsi_config->lane_count, dsi_config->bpp);
990
991 REG_WRITE((MIPIA_HSYNC_COUNT_REG + reg_offset), dpi_timing.hsync_count & DSI_DPI_TIMING_MASK);
992 REG_WRITE((MIPIA_HBP_COUNT_REG + reg_offset), dpi_timing.hbp_count & DSI_DPI_TIMING_MASK);
993 REG_WRITE((MIPIA_HFP_COUNT_REG + reg_offset), dpi_timing.hfp_count & DSI_DPI_TIMING_MASK);
994 REG_WRITE((MIPIA_HACTIVE_COUNT_REG + reg_offset), dpi_timing.hactive_count & DSI_DPI_TIMING_MASK);
995 REG_WRITE((MIPIA_VSYNC_COUNT_REG + reg_offset), dpi_timing.vsync_count & DSI_DPI_TIMING_MASK);
996 REG_WRITE((MIPIA_VBP_COUNT_REG + reg_offset), dpi_timing.vbp_count & DSI_DPI_TIMING_MASK);
997 REG_WRITE((MIPIA_VFP_COUNT_REG + reg_offset), dpi_timing.vfp_count & DSI_DPI_TIMING_MASK);
998
999 REG_WRITE((MIPIA_HIGH_LOW_SWITCH_COUNT_REG + reg_offset), 0x46);
1000
1001 /*min: 7d0 max: 4e20*/
1002 REG_WRITE((MIPIA_INIT_COUNT_REG + reg_offset), 0x000007d0);
1003
1004 /*set up video mode*/
1005 val = dsi_config->video_mode | DSI_DPI_COMPLETE_LAST_LINE;
1006 REG_WRITE((MIPIA_VIDEO_MODE_FORMAT_REG + reg_offset), val);
1007
1008 REG_WRITE((MIPIA_EOT_DISABLE_REG + reg_offset), 0x00000000);
1009
1010 REG_WRITE((MIPIA_LP_BYTECLK_REG + reg_offset), 0x00000004);
1011
1012 /*TODO: figure out how to setup these registers*/
1013 REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150c3408);
1014
1015 REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG + reg_offset), (0xa << 16) | 0x14);
1016
1017 /*set device ready*/
1018 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000001);
1019}
1020
1021static void dsi_controller_init(struct mdfld_dsi_config * dsi_config, int pipe)
1022{
1023 if (!dsi_config || ((pipe != 0) && (pipe != 2))) {
1024 DRM_ERROR("Invalid parameters\n");
1025 return;
1026 }
1027
1028 if (dsi_config->type == MDFLD_DSI_ENCODER_DPI)
1029 dsi_controller_dpi_init(dsi_config, pipe);
1030 else if (dsi_config->type == MDFLD_DSI_ENCODER_DBI)
1031 dsi_controller_dbi_init(dsi_config, pipe);
1032 else
1033 DRM_ERROR("Bad DSI encoder type\n");
1034}
1035
738void mdfld_dsi_cmds_kick_out(struct mdfld_dsi_pkg_sender *sender) 1036void mdfld_dsi_cmds_kick_out(struct mdfld_dsi_pkg_sender *sender)
739{ 1037{
740 process_pkg_list(sender); 1038 process_pkg_list(sender);
@@ -774,7 +1072,7 @@ int mdfld_dsi_send_dcs(struct mdfld_dsi_pkg_sender *sender,
774 * If dcs is write_mem_start, send it directly using DSI adapter 1072 * If dcs is write_mem_start, send it directly using DSI adapter
775 * interface 1073 * interface
776 */ 1074 */
777 if (dcs == write_mem_start) { 1075 if (dcs == DCS_WRITE_MEM_START) {
778 if (!spin_trylock(&sender->lock)) 1076 if (!spin_trylock(&sender->lock))
779 return -EAGAIN; 1077 return -EAGAIN;
780 1078
@@ -944,6 +1242,69 @@ int mdfld_dsi_send_gen_long_lp(struct mdfld_dsi_pkg_sender *sender,
944 MDFLD_DSI_LP_TRANSMISSION, delay); 1242 MDFLD_DSI_LP_TRANSMISSION, delay);
945} 1243}
946 1244
1245int mdfld_dsi_read_gen_hs(struct mdfld_dsi_pkg_sender *sender,
1246 u8 param0,
1247 u8 param1,
1248 u8 param_num,
1249 u32 *data,
1250 u16 len)
1251{
1252 if (!sender || !data || param_num < 0 || param_num > 2
1253 || !data || !len) {
1254 DRM_ERROR("Invalid parameters\n");
1255 return -EINVAL;
1256 }
1257
1258 return mdfld_dsi_read_gen(sender, param0, param1, param_num,
1259 data, len, MDFLD_DSI_HS_TRANSMISSION);
1260
1261}
1262
1263int mdfld_dsi_read_gen_lp(struct mdfld_dsi_pkg_sender *sender,
1264 u8 param0,
1265 u8 param1,
1266 u8 param_num,
1267 u32 *data,
1268 u16 len)
1269{
1270 if (!sender || !data || param_num < 0 || param_num > 2
1271 || !data || !len) {
1272 DRM_ERROR("Invalid parameters\n");
1273 return -EINVAL;
1274 }
1275
1276 return mdfld_dsi_read_gen(sender, param0, param1, param_num,
1277 data, len, MDFLD_DSI_LP_TRANSMISSION);
1278}
1279
1280int mdfld_dsi_read_mcs_hs(struct mdfld_dsi_pkg_sender *sender,
1281 u8 cmd,
1282 u32 *data,
1283 u16 len)
1284{
1285 if (!sender || !data || !len) {
1286 DRM_ERROR("Invalid parameters\n");
1287 return -EINVAL;
1288 }
1289
1290 return mdfld_dsi_read_mcs(sender, cmd, data, len,
1291 MDFLD_DSI_HS_TRANSMISSION);
1292}
1293
1294int mdfld_dsi_read_mcs_lp(struct mdfld_dsi_pkg_sender *sender,
1295 u8 cmd,
1296 u32 *data,
1297 u16 len)
1298{
1299 if (!sender || !data || !len) {
1300 WARN_ON(1);
1301 return -EINVAL;
1302 }
1303
1304 return mdfld_dsi_read_mcs(sender, cmd, data, len,
1305 MDFLD_DSI_LP_TRANSMISSION);
1306}
1307
947int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector, 1308int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
948 int pipe) 1309 int pipe)
949{ 1310{
@@ -956,6 +1317,7 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
956 struct psb_gtt *pg = &dev_priv->gtt; 1317 struct psb_gtt *pg = &dev_priv->gtt;
957 int i; 1318 int i;
958 struct mdfld_dsi_pkg *pkg, *tmp; 1319 struct mdfld_dsi_pkg *pkg, *tmp;
1320 u32 mipi_val = 0;
959 1321
960 if (!dsi_connector) { 1322 if (!dsi_connector) {
961 WARN_ON(1); 1323 WARN_ON(1);
@@ -1018,7 +1380,7 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
1018 pkg_sender->pipeconf_reg = PIPECCONF; 1380 pkg_sender->pipeconf_reg = PIPECCONF;
1019 pkg_sender->dsplinoff_reg = DSPCLINOFF; 1381 pkg_sender->dsplinoff_reg = DSPCLINOFF;
1020 pkg_sender->dspsurf_reg = DSPCSURF; 1382 pkg_sender->dspsurf_reg = DSPCSURF;
1021 pkg_sender->pipestat_reg = 72024; 1383 pkg_sender->pipestat_reg = PIPECSTAT;
1022 1384
1023 pkg_sender->mipi_intr_stat_reg = 1385 pkg_sender->mipi_intr_stat_reg =
1024 MIPIA_INTR_STAT_REG + MIPIC_REG_OFFSET; 1386 MIPIA_INTR_STAT_REG + MIPIC_REG_OFFSET;
@@ -1059,6 +1421,31 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
1059 INIT_LIST_HEAD(&pkg->entry); 1421 INIT_LIST_HEAD(&pkg->entry);
1060 list_add_tail(&pkg->entry, &pkg_sender->free_list); 1422 list_add_tail(&pkg->entry, &pkg_sender->free_list);
1061 } 1423 }
1424
1425 /*
1426 * For video mode, don't enable DPI timing output here,
1427 * will init the DPI timing output during mode setting.
1428 */
1429 if (dsi_config->type == MDFLD_DSI_ENCODER_DPI)
1430 mipi_val = PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX;
1431 else if (dsi_config->type == MDFLD_DSI_ENCODER_DBI)
1432 mipi_val = PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX
1433 | TE_TRIGGER_GPIO_PIN;
1434 else
1435 DRM_ERROR("Bad DSI encoder type\n");
1436
1437 if (pipe == 0) {
1438 mipi_val |= 0x2;
1439 REG_WRITE(MIPI, mipi_val);
1440 REG_READ(MIPI);
1441 } else if (pipe == 2) {
1442 REG_WRITE(MIPI_C, mipi_val);
1443 REG_READ(MIPI_C);
1444 }
1445
1446 /*do dsi controller init*/
1447 dsi_controller_init(dsi_config, pipe);
1448
1062 return 0; 1449 return 0;
1063 1450
1064pkg_alloc_err: 1451pkg_alloc_err:
diff --git a/drivers/staging/gma500/mdfld_dsi_pkg_sender.h b/drivers/staging/gma500/mdfld_dsi_pkg_sender.h
index 296b1eac140..f24abc70068 100644
--- a/drivers/staging/gma500/mdfld_dsi_pkg_sender.h
+++ b/drivers/staging/gma500/mdfld_dsi_pkg_sender.h
@@ -36,9 +36,13 @@ enum {
36 MDFLD_DSI_PKG_GEN_SHORT_WRITE_0 = 0x03, 36 MDFLD_DSI_PKG_GEN_SHORT_WRITE_0 = 0x03,
37 MDFLD_DSI_PKG_GEN_SHORT_WRITE_1 = 0x13, 37 MDFLD_DSI_PKG_GEN_SHORT_WRITE_1 = 0x13,
38 MDFLD_DSI_PKG_GEN_SHORT_WRITE_2 = 0x23, 38 MDFLD_DSI_PKG_GEN_SHORT_WRITE_2 = 0x23,
39 MDFLD_DSI_PKG_GEN_READ_0 = 0x04,
40 MDFLD_DSI_PKG_GEN_READ_1 = 0x14,
41 MDFLD_DSI_PKG_GEN_READ_2 = 0x24,
39 MDFLD_DSI_PKG_GEN_LONG_WRITE = 0x29, 42 MDFLD_DSI_PKG_GEN_LONG_WRITE = 0x29,
40 MDFLD_DSI_PKG_MCS_SHORT_WRITE_0 = 0x05, 43 MDFLD_DSI_PKG_MCS_SHORT_WRITE_0 = 0x05,
41 MDFLD_DSI_PKG_MCS_SHORT_WRITE_1 = 0x15, 44 MDFLD_DSI_PKG_MCS_SHORT_WRITE_1 = 0x15,
45 MDFLD_DSI_PKG_MCS_READ = 0x06,
42 MDFLD_DSI_PKG_MCS_LONG_WRITE = 0x39, 46 MDFLD_DSI_PKG_MCS_LONG_WRITE = 0x39,
43}; 47};
44 48
@@ -132,6 +136,18 @@ struct mdfld_dsi_pkg_sender {
132 u32 mipi_cmd_len_reg; 136 u32 mipi_cmd_len_reg;
133}; 137};
134 138
139/* DCS definitions */
140#define DCS_SOFT_RESET 0x01
141#define DCS_ENTER_SLEEP_MODE 0x10
142#define DCS_EXIT_SLEEP_MODE 0x11
143#define DCS_SET_DISPLAY_OFF 0x28
144#define DCS_SET_DISPLAY_ON 0x29
145#define DCS_SET_COLUMN_ADDRESS 0x2a
146#define DCS_SET_PAGE_ADDRESS 0x2b
147#define DCS_WRITE_MEM_START 0x2c
148#define DCS_SET_TEAR_OFF 0x34
149#define DCS_SET_TEAR_ON 0x35
150
135extern int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector, 151extern int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
136 int pipe); 152 int pipe);
137extern void mdfld_dsi_pkg_sender_destroy(struct mdfld_dsi_pkg_sender *sender); 153extern void mdfld_dsi_pkg_sender_destroy(struct mdfld_dsi_pkg_sender *sender);
@@ -153,6 +169,16 @@ extern int mdfld_dsi_send_gen_long_hs(struct mdfld_dsi_pkg_sender *sender,
153 u32 *data, u32 len, int delay); 169 u32 *data, u32 len, int delay);
154extern int mdfld_dsi_send_gen_long_lp(struct mdfld_dsi_pkg_sender *sender, 170extern int mdfld_dsi_send_gen_long_lp(struct mdfld_dsi_pkg_sender *sender,
155 u32 *data, u32 len, int delay); 171 u32 *data, u32 len, int delay);
172
173extern int mdfld_dsi_read_gen_hs(struct mdfld_dsi_pkg_sender *sender,
174 u8 param0, u8 param1, u8 param_num, u32 *data, u16 len);
175extern int mdfld_dsi_read_gen_lp(struct mdfld_dsi_pkg_sender *sender,
176 u8 param0, u8 param1, u8 param_num, u32 *data, u16 len);
177extern int mdfld_dsi_read_mcs_hs(struct mdfld_dsi_pkg_sender *sender,
178 u8 cmd, u32 *data, u16 len);
179extern int mdfld_dsi_read_mcs_lp(struct mdfld_dsi_pkg_sender *sender,
180 u8 cmd, u32 *data, u16 len);
181
156extern void mdfld_dsi_cmds_kick_out(struct mdfld_dsi_pkg_sender *sender); 182extern void mdfld_dsi_cmds_kick_out(struct mdfld_dsi_pkg_sender *sender);
157 183
158#endif /* __MDFLD_DSI_PKG_SENDER_H__ */ 184#endif /* __MDFLD_DSI_PKG_SENDER_H__ */
diff --git a/drivers/staging/gma500/mdfld_intel_display.c b/drivers/staging/gma500/mdfld_intel_display.c
index fa849908281..ac74a8d00b5 100644
--- a/drivers/staging/gma500/mdfld_intel_display.c
+++ b/drivers/staging/gma500/mdfld_intel_display.c
@@ -140,7 +140,6 @@ static int mdfld_intel_crtc_cursor_set(struct drm_crtc *crtc,
140 uint32_t width, uint32_t height) 140 uint32_t width, uint32_t height)
141{ 141{
142 struct drm_device *dev = crtc->dev; 142 struct drm_device *dev = crtc->dev;
143 struct drm_psb_private * dev_priv = (struct drm_psb_private *)dev->dev_private;
144 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 143 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
145 int pipe = psb_intel_crtc->pipe; 144 int pipe = psb_intel_crtc->pipe;
146 uint32_t control = CURACNTR; 145 uint32_t control = CURACNTR;
@@ -263,7 +262,7 @@ static int mdfld_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
263 case 0: 262 case 0:
264#ifndef CONFIG_MDFLD_DSI_DPU 263#ifndef CONFIG_MDFLD_DSI_DPU
265 if (!(dev_priv->dsr_fb_update & MDFLD_DSR_CURSOR_0)) 264 if (!(dev_priv->dsr_fb_update & MDFLD_DSR_CURSOR_0))
266 mdfld_dsi_dbi_exit_dsr (dev, MDFLD_DSR_CURSOR_0, 0, 0); 265 mdfld_dsi_dbi_exit_dsr (dev, MDFLD_DSR_CURSOR_0);
267#else /*CONFIG_MDFLD_DSI_DPU*/ 266#else /*CONFIG_MDFLD_DSI_DPU*/
268 rect.x = x; 267 rect.x = x;
269 rect.y = y; 268 rect.y = y;
@@ -279,7 +278,7 @@ static int mdfld_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
279 case 2: 278 case 2:
280#ifndef CONFIG_MDFLD_DSI_DPU 279#ifndef CONFIG_MDFLD_DSI_DPU
281 if (!(dev_priv->dsr_fb_update & MDFLD_DSR_CURSOR_2)) 280 if (!(dev_priv->dsr_fb_update & MDFLD_DSR_CURSOR_2))
282 mdfld_dsi_dbi_exit_dsr (dev, MDFLD_DSR_CURSOR_2, 0, 0); 281 mdfld_dsi_dbi_exit_dsr (dev, MDFLD_DSR_CURSOR_2);
283#else /*CONFIG_MDFLD_DSI_DPU*/ 282#else /*CONFIG_MDFLD_DSI_DPU*/
284 mdfld_dbi_dpu_report_damage(dev, MDFLD_CURSORC, &rect); 283 mdfld_dbi_dpu_report_damage(dev, MDFLD_CURSORC, &rect);
285 mdfld_dpu_exit_dsr(dev); 284 mdfld_dpu_exit_dsr(dev);
@@ -354,7 +353,6 @@ int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, struct drm_f
354 /* struct drm_i915_master_private *master_priv; */ 353 /* struct drm_i915_master_private *master_priv; */
355 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 354 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
356 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); 355 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
357 struct psb_intel_mode_device *mode_dev = psb_intel_crtc->mode_dev;
358 int pipe = psb_intel_crtc->pipe; 356 int pipe = psb_intel_crtc->pipe;
359 unsigned long start, offset; 357 unsigned long start, offset;
360 int dsplinoff = DSPALINOFF; 358 int dsplinoff = DSPALINOFF;
diff --git a/drivers/staging/gma500/mdfld_output.c b/drivers/staging/gma500/mdfld_output.c
index 7e11401d67b..ffa2c1f0c19 100644
--- a/drivers/staging/gma500/mdfld_output.c
+++ b/drivers/staging/gma500/mdfld_output.c
@@ -100,7 +100,6 @@ static int init_panel(struct drm_device *dev, int mipi_pipe, int p_type)
100 mdfld_dsi_output_init(dev, mipi_pipe, NULL, p_cmd_funcs, NULL); 100 mdfld_dsi_output_init(dev, mipi_pipe, NULL, p_cmd_funcs, NULL);
101 break; 101 break;
102 case PYR_VID: 102 case PYR_VID:
103 /*pyr_vid_init(dev, p_vid_funcs); */
104 mdfld_dsi_output_init(dev, mipi_pipe, NULL, NULL, p_vid_funcs); 103 mdfld_dsi_output_init(dev, mipi_pipe, NULL, NULL, p_vid_funcs);
105 break; 104 break;
106 case TPO: /* TPO panel supports both cmd & vid interfaces */ 105 case TPO: /* TPO panel supports both cmd & vid interfaces */
@@ -135,10 +134,15 @@ int mdfld_output_init(struct drm_device *dev)
135 dev_info(dev->dev, "panel 1: type is %d\n", type); 134 dev_info(dev->dev, "panel 1: type is %d\n", type);
136 init_panel(dev, 0, type); 135 init_panel(dev, 0, type);
137 136
137#ifdef CONFIG_MDFD_DUAL_MIPI
138 /* MIPI panel 2 */ 138 /* MIPI panel 2 */
139 type = mdfld_get_panel_type(dev, 2); 139 type = mdfld_get_panel_type(dev, 2);
140 dev_info(dev->dev, "panel 2: type is %d\n", type); 140 dev_info(dev->dev, "panel 2: type is %d\n", type);
141 init_panel(dev, 2, type); 141 init_panel(dev, 2, type);
142 142#endif
143#ifdef CONFIG_MDFD_HDMI
144 /* HDMI panel */
145 init_panel(dev, 0, HDMI);
146#endif
143 return 0; 147 return 0;
144} 148}
diff --git a/drivers/staging/gma500/mdfld_output.h b/drivers/staging/gma500/mdfld_output.h
index 70f2302ad25..e747fdb8913 100644
--- a/drivers/staging/gma500/mdfld_output.h
+++ b/drivers/staging/gma500/mdfld_output.h
@@ -28,47 +28,6 @@
28#ifndef MDFLD_OUTPUT_H 28#ifndef MDFLD_OUTPUT_H
29#define MDFLD_OUTPUT_H 29#define MDFLD_OUTPUT_H
30 30
31#include "psb_drv.h"
32
33/* Panel types */
34enum {
35 TPO_CMD,
36 TPO_VID,
37 TMD_CMD,
38 TMD_VID,
39 PYR_CMD,
40 PYR_VID,
41 TPO,
42 TMD,
43 PYR,
44 HDMI,
45 GCT_DETECT
46};
47
48/* Junk that belongs elsewhere */
49#define TPO_PANEL_WIDTH 84
50#define TPO_PANEL_HEIGHT 46
51#define TMD_PANEL_WIDTH 39
52#define TMD_PANEL_HEIGHT 71
53#define PYR_PANEL_WIDTH 53
54#define PYR_PANEL_HEIGHT 95
55
56/* Panel interface */
57struct panel_info {
58 u32 width_mm;
59 u32 height_mm;
60};
61
62struct mdfld_dsi_dbi_output;
63
64struct panel_funcs {
65 const struct drm_encoder_funcs *encoder_funcs;
66 const struct drm_encoder_helper_funcs *encoder_helper_funcs;
67 struct drm_display_mode *(*get_config_mode) (struct drm_device *);
68 void (*update_fb) (struct mdfld_dsi_dbi_output *, int);
69 int (*get_panel_info) (struct drm_device *, int, struct panel_info *);
70};
71
72int mdfld_output_init(struct drm_device *dev); 31int mdfld_output_init(struct drm_device *dev);
73int mdfld_panel_dpi(struct drm_device *dev); 32int mdfld_panel_dpi(struct drm_device *dev);
74int mdfld_get_panel_type(struct drm_device *dev, int pipe); 33int mdfld_get_panel_type(struct drm_device *dev, int pipe);
diff --git a/drivers/staging/gma500/mdfld_pyr_cmd.c b/drivers/staging/gma500/mdfld_pyr_cmd.c
index 0d89384fe37..5f38e8df375 100644
--- a/drivers/staging/gma500/mdfld_pyr_cmd.c
+++ b/drivers/staging/gma500/mdfld_pyr_cmd.c
@@ -188,7 +188,7 @@ static void pyr_dsi_controller_dbi_init(struct mdfld_dsi_config *dsi_config,
188 188
189 dev_dbg(dev->dev, "Init DBI interface on pipe %d...\n", pipe); 189 dev_dbg(dev->dev, "Init DBI interface on pipe %d...\n", pipe);
190 190
191 /* In-ready device */ 191 /* Un-ready device */
192 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000000); 192 REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000000);
193 193
194 /* Init dsi adapter before kicking off */ 194 /* Init dsi adapter before kicking off */
@@ -394,25 +394,13 @@ static void pyr_dsi_dbi_dpms(struct drm_encoder *encoder, int mode)
394 struct mdfld_dsi_dbi_output *dbi_output = 394 struct mdfld_dsi_dbi_output *dbi_output =
395 MDFLD_DSI_DBI_OUTPUT(dsi_encoder); 395 MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
396 struct drm_device *dev = dbi_output->dev; 396 struct drm_device *dev = dbi_output->dev;
397 struct drm_psb_private *dev_priv = dev->dev_private;
398 static bool bdispoff;
399 397
400 dev_dbg(dev->dev, "%s\n", (mode == DRM_MODE_DPMS_ON ? "on" : "off")); 398 dev_dbg(dev->dev, "%s\n", (mode == DRM_MODE_DPMS_ON ? "on" : "off"));
401 399
402 if (mode == DRM_MODE_DPMS_ON) { 400 if (mode == DRM_MODE_DPMS_ON)
403 if (/*gbgfxsuspended && */bdispoff) {
404 bdispoff = false;
405 dev_priv->dispstatus = true;
406 /*gbgfxsuspended = false;
407 */
408 mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_2D_3D, 0, 0);
409 }
410 pyr_dsi_dbi_set_power(encoder, true); 401 pyr_dsi_dbi_set_power(encoder, true);
411 } else { 402 else
412 bdispoff = true;
413 dev_priv->dispstatus = false;
414 pyr_dsi_dbi_set_power(encoder, false); 403 pyr_dsi_dbi_set_power(encoder, false);
415 }
416} 404}
417 405
418/* 406/*
diff --git a/drivers/staging/gma500/mdfld_tmd_vid.c b/drivers/staging/gma500/mdfld_tmd_vid.c
index b29c905f077..affdc09c676 100644
--- a/drivers/staging/gma500/mdfld_tmd_vid.c
+++ b/drivers/staging/gma500/mdfld_tmd_vid.c
@@ -114,6 +114,66 @@ static int tmd_vid_get_panel_info(struct drm_device *dev,
114 return 0; 114 return 0;
115} 115}
116 116
117/*
118 * mdfld_init_TMD_MIPI - initialise a TMD interface
119 * @dsi_config: configuration
120 * @pipe: pipe to configure
121 *
122 * This function is called only by mrst_dsi_mode_set and
123 * restore_display_registers. since this function does not
124 * acquire the mutex, it is important that the calling function
125 * does!
126 */
127
128
129static void mdfld_dsi_tmd_drv_ic_init(struct mdfld_dsi_config *dsi_config,
130 int pipe)
131{
132 static u32 tmd_cmd_mcap_off[] = {0x000000b2};
133 static u32 tmd_cmd_enable_lane_switch[] = {0x000101ef};
134 static u32 tmd_cmd_set_lane_num[] = {0x006360ef};
135 static u32 tmd_cmd_pushing_clock0[] = {0x00cc2fef};
136 static u32 tmd_cmd_pushing_clock1[] = {0x00dd6eef};
137 static u32 tmd_cmd_set_mode[] = {0x000000b3};
138 static u32 tmd_cmd_set_sync_pulse_mode[] = {0x000961ef};
139 static u32 tmd_cmd_set_column[] = {0x0100002a, 0x000000df};
140 static u32 tmd_cmd_set_page[] = {0x0300002b, 0x00000055};
141 static u32 tmd_cmd_set_video_mode[] = {0x00000153};
142 /*no auto_bl,need add in furture*/
143 static u32 tmd_cmd_enable_backlight[] = {0x00005ab4};
144 static u32 tmd_cmd_set_backlight_dimming[] = {0x00000ebd};
145
146 struct mdfld_dsi_pkg_sender *sender
147 = mdfld_dsi_get_pkg_sender(dsi_config);
148
149 DRM_INFO("Enter mdfld init TMD MIPI display.\n");
150
151 if (!sender) {
152 DRM_ERROR("Cannot get sender\n");
153 return;
154 }
155
156 if (dsi_config->dvr_ic_inited)
157 return;
158
159 msleep(3);
160
161 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_mcap_off, 1, 0);
162 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_enable_lane_switch, 1, 0);
163 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_set_lane_num, 1, 0);
164 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_pushing_clock0, 1, 0);
165 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_pushing_clock1, 1, 0);
166 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_set_mode, 1, 0);
167 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_set_sync_pulse_mode, 1, 0);
168 mdfld_dsi_send_mcs_long_lp(sender, tmd_cmd_set_column, 2, 0);
169 mdfld_dsi_send_mcs_long_lp(sender, tmd_cmd_set_page, 2, 0);
170 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_set_video_mode, 1, 0);
171 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_enable_backlight, 1, 0);
172 mdfld_dsi_send_gen_long_lp(sender, tmd_cmd_set_backlight_dimming, 1, 0);
173
174 dsi_config->dvr_ic_inited = 1;
175}
176
117/* TMD DPI encoder helper funcs */ 177/* TMD DPI encoder helper funcs */
118static const struct drm_encoder_helper_funcs 178static const struct drm_encoder_helper_funcs
119 mdfld_tpo_dpi_encoder_helper_funcs = { 179 mdfld_tpo_dpi_encoder_helper_funcs = {
@@ -141,4 +201,6 @@ void tmd_vid_init(struct drm_device *dev, struct panel_funcs *p_funcs)
141 p_funcs->get_config_mode = &tmd_vid_get_config_mode; 201 p_funcs->get_config_mode = &tmd_vid_get_config_mode;
142 p_funcs->update_fb = NULL; 202 p_funcs->update_fb = NULL;
143 p_funcs->get_panel_info = tmd_vid_get_panel_info; 203 p_funcs->get_panel_info = tmd_vid_get_panel_info;
204 p_funcs->reset = mdfld_dsi_panel_reset;
205 p_funcs->drv_ic_init = mdfld_dsi_tmd_drv_ic_init;
144} 206}
diff --git a/drivers/staging/gma500/mdfld_tpo_cmd.c b/drivers/staging/gma500/mdfld_tpo_cmd.c
index d2e1818bb41..4cf7647257f 100644
--- a/drivers/staging/gma500/mdfld_tpo_cmd.c
+++ b/drivers/staging/gma500/mdfld_tpo_cmd.c
@@ -126,11 +126,15 @@ static void mdfld_dsi_dbi_set_power(struct drm_encoder *encoder, bool on)
126 struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder); 126 struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
127 struct mdfld_dsi_dbi_output *dbi_output = 127 struct mdfld_dsi_dbi_output *dbi_output =
128 MDFLD_DSI_DBI_OUTPUT(dsi_encoder); 128 MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
129 /*struct drm_device *dev = dbi_output->dev;*/ 129 struct mdfld_dsi_config *dsi_config =
130 mdfld_dsi_encoder_get_config(dsi_encoder);
131 struct mdfld_dsi_pkg_sender *sender =
132 mdfld_dsi_encoder_get_pkg_sender(dsi_encoder);
130 struct drm_device *dev = encoder->dev; 133 struct drm_device *dev = encoder->dev;
131 struct drm_psb_private *dev_priv = dev->dev_private; 134 struct drm_psb_private *dev_priv = dev->dev_private;
132 u32 reg_offset = 0; 135 u32 reg_offset = 0;
133 int pipe = (dbi_output->channel_num == 0) ? 0 : 2; 136 int pipe = (dbi_output->channel_num == 0) ? 0 : 2;
137 u32 data = 0;
134 138
135 dev_dbg(dev->dev, "pipe %d : %s, panel on: %s\n", 139 dev_dbg(dev->dev, "pipe %d : %s, panel on: %s\n",
136 pipe, on ? "On" : "Off", 140 pipe, on ? "On" : "Off",
@@ -190,9 +194,33 @@ static void mdfld_dsi_dbi_set_power(struct drm_encoder *encoder, bool on)
190 } 194 }
191 } 195 }
192 196
197 /*
198 * FIXME: this is a WA for TPO panel crash on DPMS on & off around
199 * 83 times. the root cause of this issue is that Booster in
200 * drvIC crashed. Add this WA so that we can resume the driver IC
201 * once we found that booster has a fault
202 */
203 mdfld_dsi_get_power_mode(dsi_config,
204 &data,
205 MDFLD_DSI_HS_TRANSMISSION);
206
207 if (on && data && !(data & (1 << 7))) {
208 /* Soft reset */
209 mdfld_dsi_send_dcs(sender,
210 DCS_SOFT_RESET,
211 NULL,
212 0,
213 CMD_DATA_SRC_PIPE,
214 MDFLD_DSI_SEND_PACKAGE);
215
216 /* Init drvIC */
217 if (dbi_output->p_funcs->drv_ic_init)
218 dbi_output->p_funcs->drv_ic_init(dsi_config,
219 pipe);
220 }
221
193out_err: 222out_err:
194 gma_power_end(dev); 223 gma_power_end(dev);
195
196 if (ret) 224 if (ret)
197 dev_err(dev->dev, "failed\n"); 225 dev_err(dev->dev, "failed\n");
198} 226}
@@ -253,14 +281,6 @@ static void mdfld_dsi_dbi_mode_set(struct drm_encoder *encoder,
253 return; 281 return;
254 } 282 }
255 283
256 /* Set up pipe related registers */
257 REG_WRITE(mipi_reg, mipi_val);
258 REG_READ(mipi_reg);
259
260 mdfld_dsi_controller_dbi_init(dsi_config, pipe);
261
262 msleep(20);
263
264 REG_WRITE(dspcntr_reg, dspcntr_val); 284 REG_WRITE(dspcntr_reg, dspcntr_val);
265 REG_READ(dspcntr_reg); 285 REG_READ(dspcntr_reg);
266 286
@@ -268,7 +288,7 @@ static void mdfld_dsi_dbi_mode_set(struct drm_encoder *encoder,
268 msleep(20); 288 msleep(20);
269 289
270 /* Send exit_sleep_mode DCS */ 290 /* Send exit_sleep_mode DCS */
271 ret = mdfld_dsi_dbi_send_dcs(dsi_output, exit_sleep_mode, 291 ret = mdfld_dsi_dbi_send_dcs(dsi_output, DCS_EXIT_SLEEP_MODE,
272 NULL, 0, CMD_DATA_SRC_SYSTEM_MEM); 292 NULL, 0, CMD_DATA_SRC_SYSTEM_MEM);
273 if (ret) { 293 if (ret) {
274 dev_err(dev->dev, "sent exit_sleep_mode faild\n"); 294 dev_err(dev->dev, "sent exit_sleep_mode faild\n");
@@ -276,7 +296,7 @@ static void mdfld_dsi_dbi_mode_set(struct drm_encoder *encoder,
276 } 296 }
277 297
278 /* Send set_tear_on DCS */ 298 /* Send set_tear_on DCS */
279 ret = mdfld_dsi_dbi_send_dcs(dsi_output, set_tear_on, 299 ret = mdfld_dsi_dbi_send_dcs(dsi_output, DCS_SET_TEAR_ON,
280 &param, 1, CMD_DATA_SRC_SYSTEM_MEM); 300 &param, 1, CMD_DATA_SRC_SYSTEM_MEM);
281 if (ret) { 301 if (ret) {
282 dev_err(dev->dev, "%s - sent set_tear_on faild\n", __func__); 302 dev_err(dev->dev, "%s - sent set_tear_on faild\n", __func__);
@@ -284,11 +304,6 @@ static void mdfld_dsi_dbi_mode_set(struct drm_encoder *encoder,
284 } 304 }
285 305
286 /* Do some init stuff */ 306 /* Do some init stuff */
287 mdfld_dsi_brightness_init(dsi_config, pipe);
288
289 mdfld_dsi_gen_fifo_ready(dev, (MIPIA_GEN_FIFO_STAT_REG + reg_offset),
290 HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
291
292 REG_WRITE(pipeconf_reg, pipeconf_val | PIPEACONF_DSR); 307 REG_WRITE(pipeconf_reg, pipeconf_val | PIPEACONF_DSR);
293 REG_READ(pipeconf_reg); 308 REG_READ(pipeconf_reg);
294 309
@@ -375,23 +390,24 @@ static void mdfld_dsi_dbi_dpms(struct drm_encoder *encoder, int mode)
375 * if everything goes right, hw_begin will resume them all 390 * if everything goes right, hw_begin will resume them all
376 * during set_power. 391 * during set_power.
377 */ 392 */
378 if (bdispoff) 393 if (bdispoff /* FIXME && gbgfxsuspended */) {
379 mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_2D_3D, 0, 0); 394 mdfld_dsi_dbi_exit_dsr(dev, MDFLD_DSR_2D_3D);
395 bdispoff = false;
396 dev_priv->dispstatus = true;
397 }
380 398
381 mdfld_dsi_dbi_set_power(encoder, true); 399 mdfld_dsi_dbi_set_power(encoder, true);
382 /* FIXME if (gbgfxsuspended) 400 /* FIXME if (gbgfxsuspended)
383 gbgfxsuspended = false; */ 401 gbgfxsuspended = false; */
384 bdispoff = false;
385 dev_priv->dispstatus = true;
386 } else { 402 } else {
387 /* 403 /*
388 * I am not sure whether this is the perfect place to 404 * I am not sure whether this is the perfect place to
389 * turn rpm on since we still have a lot of CRTC turnning 405 * turn rpm on since we still have a lot of CRTC turnning
390 * on work to do. 406 * on work to do.
391 */ 407 */
392 mdfld_dsi_dbi_set_power(encoder, false);
393 bdispoff = true; 408 bdispoff = true;
394 dev_priv->dispstatus = false; 409 dev_priv->dispstatus = false;
410 mdfld_dsi_dbi_set_power(encoder, false);
395 } 411 }
396} 412}
397 413
@@ -446,7 +462,7 @@ static void mdfld_dsi_dbi_update_fb(struct mdfld_dsi_dbi_output *dbi_output,
446 REG_READ(dspsurf_reg); 462 REG_READ(dspsurf_reg);
447 463
448 mdfld_dsi_send_dcs(sender, 464 mdfld_dsi_send_dcs(sender,
449 write_mem_start, 465 DCS_WRITE_MEM_START,
450 NULL, 466 NULL,
451 0, 467 0,
452 CMD_DATA_SRC_PIPE, 468 CMD_DATA_SRC_PIPE,
@@ -492,4 +508,6 @@ void tpo_cmd_init(struct drm_device *dev, struct panel_funcs *p_funcs)
492 p_funcs->get_config_mode = &tpo_cmd_get_config_mode; 508 p_funcs->get_config_mode = &tpo_cmd_get_config_mode;
493 p_funcs->update_fb = mdfld_dsi_dbi_update_fb; 509 p_funcs->update_fb = mdfld_dsi_dbi_update_fb;
494 p_funcs->get_panel_info = tpo_cmd_get_panel_info; 510 p_funcs->get_panel_info = tpo_cmd_get_panel_info;
511 p_funcs->reset = mdfld_dsi_panel_reset;
512 p_funcs->drv_ic_init = mdfld_dsi_brightness_init;
495} 513}
diff --git a/drivers/staging/gma500/mrst_lvds.c b/drivers/staging/gma500/mrst_lvds.c
index 25fde4cc910..ac791c48eed 100644
--- a/drivers/staging/gma500/mrst_lvds.c
+++ b/drivers/staging/gma500/mrst_lvds.c
@@ -58,11 +58,11 @@ static void mrst_lvds_set_power(struct drm_device *dev,
58 pp_status = REG_READ(PP_STATUS); 58 pp_status = REG_READ(PP_STATUS);
59 } while ((pp_status & (PP_ON | PP_READY)) == PP_READY); 59 } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
60 dev_priv->is_lvds_on = true; 60 dev_priv->is_lvds_on = true;
61 if (dev_priv->ops->lvds_bl_power) 61 if (dev_priv->ops->lvds_bl_power)
62 dev_priv->ops->lvds_bl_power(dev, true); 62 dev_priv->ops->lvds_bl_power(dev, true);
63 } else { 63 } else {
64 if (dev_priv->ops->lvds_bl_power) 64 if (dev_priv->ops->lvds_bl_power)
65 dev_priv->ops->lvds_bl_power(dev, false); 65 dev_priv->ops->lvds_bl_power(dev, false);
66 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & 66 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
67 ~POWER_TARGET_ON); 67 ~POWER_TARGET_ON);
68 do { 68 do {
@@ -151,6 +151,7 @@ static void mrst_lvds_prepare(struct drm_encoder *encoder)
151{ 151{
152 struct drm_device *dev = encoder->dev; 152 struct drm_device *dev = encoder->dev;
153 struct psb_intel_output *output = enc_to_psb_intel_output(encoder); 153 struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
154 struct psb_intel_mode_device *mode_dev = output->mode_dev;
154 155
155 if (!gma_power_begin(dev, true)) 156 if (!gma_power_begin(dev, true))
156 return; 157 return;
@@ -162,23 +163,43 @@ static void mrst_lvds_prepare(struct drm_encoder *encoder)
162 gma_power_end(dev); 163 gma_power_end(dev);
163} 164}
164 165
166static u32 mrst_lvds_get_max_backlight(struct drm_device *dev)
167{
168 struct drm_psb_private *dev_priv = dev->dev_private;
169 u32 ret;
170
171 if (gma_power_begin(dev, false)) {
172 ret = ((REG_READ(BLC_PWM_CTL) &
173 BACKLIGHT_MODULATION_FREQ_MASK) >>
174 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
175
176 gma_power_end(dev);
177 } else
178 ret = ((dev_priv->saveBLC_PWM_CTL &
179 BACKLIGHT_MODULATION_FREQ_MASK) >>
180 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
181
182 return ret;
183}
184
165static void mrst_lvds_commit(struct drm_encoder *encoder) 185static void mrst_lvds_commit(struct drm_encoder *encoder)
166{ 186{
167 struct drm_device *dev = encoder->dev; 187 struct drm_device *dev = encoder->dev;
168 struct psb_intel_output *output = enc_to_psb_intel_output(encoder); 188 struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
189 struct psb_intel_mode_device *mode_dev = output->mode_dev;
169 190
170 if (mode_dev->backlight_duty_cycle == 0) 191 if (mode_dev->backlight_duty_cycle == 0)
171 mode_dev->backlight_duty_cycle = 192 mode_dev->backlight_duty_cycle =
172 psb_intel_lvds_get_max_backlight(dev); 193 mrst_lvds_get_max_backlight(dev);
173 mrst_lvds_set_power(dev, output, true); 194 mrst_lvds_set_power(dev, output, true);
174} 195}
175 196
176static const struct drm_encoder_helper_funcs mrst_lvds_helper_funcs = { 197static const struct drm_encoder_helper_funcs mrst_lvds_helper_funcs = {
177 .dpms = mrst_lvds_dpms, 198 .dpms = mrst_lvds_dpms,
178 .mode_fixup = psb_intel_lvds_mode_fixup, 199 .mode_fixup = psb_intel_lvds_mode_fixup,
179 .prepare = mrst_intel_lvds_prepare, 200 .prepare = mrst_lvds_prepare,
180 .mode_set = mrst_lvds_mode_set, 201 .mode_set = mrst_lvds_mode_set,
181 .commit = mrst_intel_lvds_commit, 202 .commit = mrst_lvds_commit,
182}; 203};
183 204
184static struct drm_display_mode lvds_configuration_modes[] = { 205static struct drm_display_mode lvds_configuration_modes[] = {
diff --git a/drivers/staging/gma500/psb_drv.h b/drivers/staging/gma500/psb_drv.h
index 194c64fb6c6..72f487a2a1b 100644
--- a/drivers/staging/gma500/psb_drv.h
+++ b/drivers/staging/gma500/psb_drv.h
@@ -31,6 +31,7 @@
31#include "gtt.h" 31#include "gtt.h"
32#include "power.h" 32#include "power.h"
33#include "mrst.h" 33#include "mrst.h"
34#include "medfield.h"
34 35
35/* Append new drm mode definition here, align with libdrm definition */ 36/* Append new drm mode definition here, align with libdrm definition */
36#define DRM_MODE_SCALE_NO_SCALE 2 37#define DRM_MODE_SCALE_NO_SCALE 2
@@ -216,8 +217,8 @@ enum {
216#define MDFLD_DSR_OVERLAY_0 (1 << 4) 217#define MDFLD_DSR_OVERLAY_0 (1 << 4)
217#define MDFLD_DSR_OVERLAY_2 (1 << 5) 218#define MDFLD_DSR_OVERLAY_2 (1 << 5)
218#define MDFLD_DSR_MIPI_CONTROL (1 << 6) 219#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
219#define MDFLD_DSR_DAMAGE_MASK_0 (1 << 0) | (1 << 2) | (1 << 4) 220#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
220#define MDFLD_DSR_DAMAGE_MASK_2 (1 << 1) | (1 << 3) | (1 << 5) 221#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
221#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2) 222#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
222 223
223#define MDFLD_DSR_RR 45 224#define MDFLD_DSR_RR 45
@@ -605,7 +606,7 @@ struct drm_psb_private {
605 uint32_t dsr_idle_count; 606 uint32_t dsr_idle_count;
606 bool is_in_idle; 607 bool is_in_idle;
607 bool dsr_enable; 608 bool dsr_enable;
608 void (*exit_idle)(struct drm_device *dev, u32 update_src, void *p_surfaceAddr, bool check_hw_on_only); 609 void (*exit_idle)(struct drm_device *dev, u32 update_src);
609 610
610 /* 2D acceleration */ 611 /* 2D acceleration */
611 struct mutex mutex_2d; 612 struct mutex mutex_2d;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 18:39:34 -0400