diff options
author | Arend van Spriel <arend@broadcom.com> | 2011-02-25 10:39:24 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-02-28 21:20:35 -0500 |
commit | 06d278c51a072a655d7da23e3acc53f676967375 (patch) | |
tree | 58a06f243cabb7d50f6f399ee7a27da8fec3d6b6 /drivers/staging | |
parent | 7c0e45d7fb4ca3f9505b316598f4c2d748f3e8d0 (diff) |
staging: brcm80211: remove usage of struct osl_info to access device
For accessing the PCI or SDIO device in the driver the device is stored
in a separate structure osl_info. To get rid of the osl concept the use
of this device pointer attribute is removed from the drivers.
Reviewed-by: Roland Vossen <rvossen@broadcom.com>
Reviewed-by: Brett Rudley <brudley@broadcom.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging')
-rw-r--r-- | drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c | 2 | ||||
-rw-r--r-- | drivers/staging/brcm80211/include/nicpci.h | 4 | ||||
-rw-r--r-- | drivers/staging/brcm80211/include/osl.h | 21 | ||||
-rw-r--r-- | drivers/staging/brcm80211/include/siutils.h | 4 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/aiutils.c | 6 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/hnddma.c | 34 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/nicpci.c | 59 | ||||
-rw-r--r-- | drivers/staging/brcm80211/util/siutils.c | 53 |
8 files changed, 93 insertions, 90 deletions
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c index 151c9b26276..faca5e5449f 100644 --- a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c +++ b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c | |||
@@ -442,7 +442,7 @@ void write_phy_reg(phy_info_t *pi, u16 addr, u16 val) | |||
442 | if (addr == 0x72) | 442 | if (addr == 0x72) |
443 | (void)R_REG(osh, ®s->phyregdata); | 443 | (void)R_REG(osh, ®s->phyregdata); |
444 | #else | 444 | #else |
445 | W_REG(osh, (volatile u32 *)(®s->phyregaddr), | 445 | W_REG(osh, (u32 *)(®s->phyregaddr), |
446 | addr | (val << 16)); | 446 | addr | (val << 16)); |
447 | if (pi->sh->bustype == PCI_BUS) { | 447 | if (pi->sh->bustype == PCI_BUS) { |
448 | if (++pi->phy_wreg >= pi->phy_wreg_limit) { | 448 | if (++pi->phy_wreg >= pi->phy_wreg_limit) { |
diff --git a/drivers/staging/brcm80211/include/nicpci.h b/drivers/staging/brcm80211/include/nicpci.h index 928818daedd..eb842c838df 100644 --- a/drivers/staging/brcm80211/include/nicpci.h +++ b/drivers/staging/brcm80211/include/nicpci.h | |||
@@ -45,7 +45,7 @@ | |||
45 | #else | 45 | #else |
46 | struct sbpcieregs; | 46 | struct sbpcieregs; |
47 | 47 | ||
48 | extern u8 pcicore_find_pci_capability(struct osl_info *osh, u8 req_cap_id, | 48 | extern u8 pcicore_find_pci_capability(void *dev, u8 req_cap_id, |
49 | unsigned char *buf, u32 *buflen); | 49 | unsigned char *buf, u32 *buflen); |
50 | extern uint pcie_readreg(struct osl_info *osh, struct sbpcieregs *pcieregs, | 50 | extern uint pcie_readreg(struct osl_info *osh, struct sbpcieregs *pcieregs, |
51 | uint addrtype, uint offset); | 51 | uint addrtype, uint offset); |
@@ -70,7 +70,7 @@ extern u32 pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset, | |||
70 | extern u32 pcicore_pciereg(void *pch, u32 offset, u32 mask, | 70 | extern u32 pcicore_pciereg(void *pch, u32 offset, u32 mask, |
71 | u32 val, uint type); | 71 | u32 val, uint type); |
72 | 72 | ||
73 | extern bool pcicore_pmecap_fast(struct osl_info *osh); | 73 | extern bool pcicore_pmecap_fast(void *pch); |
74 | extern void pcicore_pmeen(void *pch); | 74 | extern void pcicore_pmeen(void *pch); |
75 | extern void pcicore_pmeclr(void *pch); | 75 | extern void pcicore_pmeclr(void *pch); |
76 | extern bool pcicore_pmestat(void *pch); | 76 | extern bool pcicore_pmestat(void *pch); |
diff --git a/drivers/staging/brcm80211/include/osl.h b/drivers/staging/brcm80211/include/osl.h index f118b30552e..0aac64af8de 100644 --- a/drivers/staging/brcm80211/include/osl.h +++ b/drivers/staging/brcm80211/include/osl.h | |||
@@ -66,14 +66,11 @@ extern uint osl_pci_slot(struct osl_info *osh); | |||
66 | #endif | 66 | #endif |
67 | 67 | ||
68 | #if defined(BCMSDIO) | 68 | #if defined(BCMSDIO) |
69 | #define SELECT_BUS_WRITE(osh, mmap_op, bus_op) \ | 69 | #define SELECT_BUS_WRITE(mmap_op, bus_op) bus_op |
70 | if ((osh)->mmbus) \ | 70 | #define SELECT_BUS_READ(mmap_op, bus_op) bus_op |
71 | mmap_op else bus_op | ||
72 | #define SELECT_BUS_READ(osh, mmap_op, bus_op) \ | ||
73 | ((osh)->mmbus) ? mmap_op : bus_op | ||
74 | #else | 71 | #else |
75 | #define SELECT_BUS_WRITE(osh, mmap_op, bus_op) mmap_op | 72 | #define SELECT_BUS_WRITE(mmap_op, bus_op) mmap_op |
76 | #define SELECT_BUS_READ(osh, mmap_op, bus_op) mmap_op | 73 | #define SELECT_BUS_READ(mmap_op, bus_op) mmap_op |
77 | #endif | 74 | #endif |
78 | 75 | ||
79 | /* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */ | 76 | /* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */ |
@@ -89,14 +86,14 @@ extern uint osl_pci_slot(struct osl_info *osh); | |||
89 | #ifndef IL_BIGENDIAN | 86 | #ifndef IL_BIGENDIAN |
90 | #ifndef __mips__ | 87 | #ifndef __mips__ |
91 | #define R_REG(osh, r) (\ | 88 | #define R_REG(osh, r) (\ |
92 | SELECT_BUS_READ(osh, sizeof(*(r)) == sizeof(u8) ? \ | 89 | SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \ |
93 | readb((volatile u8*)(r)) : \ | 90 | readb((volatile u8*)(r)) : \ |
94 | sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \ | 91 | sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \ |
95 | readl((volatile u32*)(r)), OSL_READ_REG(osh, r)) \ | 92 | readl((volatile u32*)(r)), OSL_READ_REG(osh, r)) \ |
96 | ) | 93 | ) |
97 | #else /* __mips__ */ | 94 | #else /* __mips__ */ |
98 | #define R_REG(osh, r) (\ | 95 | #define R_REG(osh, r) (\ |
99 | SELECT_BUS_READ(osh, \ | 96 | SELECT_BUS_READ( \ |
100 | ({ \ | 97 | ({ \ |
101 | __typeof(*(r)) __osl_v; \ | 98 | __typeof(*(r)) __osl_v; \ |
102 | __asm__ __volatile__("sync"); \ | 99 | __asm__ __volatile__("sync"); \ |
@@ -126,7 +123,7 @@ extern uint osl_pci_slot(struct osl_info *osh); | |||
126 | #endif /* __mips__ */ | 123 | #endif /* __mips__ */ |
127 | 124 | ||
128 | #define W_REG(osh, r, v) do { \ | 125 | #define W_REG(osh, r, v) do { \ |
129 | SELECT_BUS_WRITE(osh, \ | 126 | SELECT_BUS_WRITE( \ |
130 | switch (sizeof(*(r))) { \ | 127 | switch (sizeof(*(r))) { \ |
131 | case sizeof(u8): \ | 128 | case sizeof(u8): \ |
132 | writeb((u8)(v), (volatile u8*)(r)); break; \ | 129 | writeb((u8)(v), (volatile u8*)(r)); break; \ |
@@ -139,7 +136,7 @@ extern uint osl_pci_slot(struct osl_info *osh); | |||
139 | } while (0) | 136 | } while (0) |
140 | #else /* IL_BIGENDIAN */ | 137 | #else /* IL_BIGENDIAN */ |
141 | #define R_REG(osh, r) (\ | 138 | #define R_REG(osh, r) (\ |
142 | SELECT_BUS_READ(osh, \ | 139 | SELECT_BUS_READ( \ |
143 | ({ \ | 140 | ({ \ |
144 | __typeof(*(r)) __osl_v; \ | 141 | __typeof(*(r)) __osl_v; \ |
145 | switch (sizeof(*(r))) { \ | 142 | switch (sizeof(*(r))) { \ |
@@ -160,7 +157,7 @@ extern uint osl_pci_slot(struct osl_info *osh); | |||
160 | OSL_READ_REG(osh, r)) \ | 157 | OSL_READ_REG(osh, r)) \ |
161 | ) | 158 | ) |
162 | #define W_REG(osh, r, v) do { \ | 159 | #define W_REG(osh, r, v) do { \ |
163 | SELECT_BUS_WRITE(osh, \ | 160 | SELECT_BUS_WRITE( \ |
164 | switch (sizeof(*(r))) { \ | 161 | switch (sizeof(*(r))) { \ |
165 | case sizeof(u8): \ | 162 | case sizeof(u8): \ |
166 | writeb((u8)(v), \ | 163 | writeb((u8)(v), \ |
diff --git a/drivers/staging/brcm80211/include/siutils.h b/drivers/staging/brcm80211/include/siutils.h index 2932bf58278..3301cf07cd2 100644 --- a/drivers/staging/brcm80211/include/siutils.h +++ b/drivers/staging/brcm80211/include/siutils.h | |||
@@ -212,9 +212,9 @@ typedef struct gpioh_item { | |||
212 | 212 | ||
213 | /* misc si info needed by some of the routines */ | 213 | /* misc si info needed by some of the routines */ |
214 | typedef struct si_info { | 214 | typedef struct si_info { |
215 | struct si_pub pub; /* back plane public state (must be first field) */ | 215 | struct si_pub pub; /* back plane public state (must be first) */ |
216 | struct osl_info *osh; /* osl os handle */ | 216 | struct osl_info *osh; /* osl os handle */ |
217 | void *sdh; /* bcmsdh handle */ | 217 | void *pbus; /* handle to bus (pci/sdio/..) */ |
218 | uint dev_coreid; /* the core provides driver functions */ | 218 | uint dev_coreid; /* the core provides driver functions */ |
219 | void *intr_arg; /* interrupt callback function arg */ | 219 | void *intr_arg; /* interrupt callback function arg */ |
220 | si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */ | 220 | si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */ |
diff --git a/drivers/staging/brcm80211/util/aiutils.c b/drivers/staging/brcm80211/util/aiutils.c index e4842c12ccf..67d3706e055 100644 --- a/drivers/staging/brcm80211/util/aiutils.c +++ b/drivers/staging/brcm80211/util/aiutils.c | |||
@@ -127,7 +127,7 @@ void ai_scan(si_t *sih, void *regs, uint devid) | |||
127 | sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE); | 127 | sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE); |
128 | 128 | ||
129 | /* Now point the window at the erom */ | 129 | /* Now point the window at the erom */ |
130 | pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN, erombase); | 130 | pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, erombase); |
131 | eromptr = regs; | 131 | eromptr = regs; |
132 | break; | 132 | break; |
133 | 133 | ||
@@ -347,10 +347,10 @@ void *ai_setcoreidx(si_t *sih, uint coreidx) | |||
347 | 347 | ||
348 | case PCI_BUS: | 348 | case PCI_BUS: |
349 | /* point bar0 window */ | 349 | /* point bar0 window */ |
350 | pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN, addr); | 350 | pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, addr); |
351 | regs = sii->curmap; | 351 | regs = sii->curmap; |
352 | /* point bar0 2nd 4KB window */ | 352 | /* point bar0 2nd 4KB window */ |
353 | pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN2, wrap); | 353 | pci_write_config_dword(sii->pbus, PCI_BAR0_WIN2, wrap); |
354 | break; | 354 | break; |
355 | 355 | ||
356 | case SPI_BUS: | 356 | case SPI_BUS: |
diff --git a/drivers/staging/brcm80211/util/hnddma.c b/drivers/staging/brcm80211/util/hnddma.c index 3c913a65da0..3c71f7549d1 100644 --- a/drivers/staging/brcm80211/util/hnddma.c +++ b/drivers/staging/brcm80211/util/hnddma.c | |||
@@ -81,6 +81,7 @@ typedef struct dma_info { | |||
81 | char name[MAXNAMEL]; /* callers name for diag msgs */ | 81 | char name[MAXNAMEL]; /* callers name for diag msgs */ |
82 | 82 | ||
83 | struct osl_info *osh; /* os handle */ | 83 | struct osl_info *osh; /* os handle */ |
84 | void *pbus; /* bus handle */ | ||
84 | si_t *sih; /* sb handle */ | 85 | si_t *sih; /* sb handle */ |
85 | 86 | ||
86 | bool dma64; /* this dma engine is operating in 64-bit mode */ | 87 | bool dma64; /* this dma engine is operating in 64-bit mode */ |
@@ -201,7 +202,7 @@ static void _dma_counterreset(dma_info_t *di); | |||
201 | static void _dma_fifoloopbackenable(dma_info_t *di); | 202 | static void _dma_fifoloopbackenable(dma_info_t *di); |
202 | static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags); | 203 | static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags); |
203 | static u8 dma_align_sizetobits(uint size); | 204 | static u8 dma_align_sizetobits(uint size); |
204 | static void *dma_ringalloc(struct osl_info *osh, u32 boundary, uint size, | 205 | static void *dma_ringalloc(dma_info_t *di, u32 boundary, uint size, |
205 | u16 *alignbits, uint *alloced, | 206 | u16 *alignbits, uint *alloced, |
206 | dmaaddr_t *descpa, osldma_t **dmah); | 207 | dmaaddr_t *descpa, osldma_t **dmah); |
207 | 208 | ||
@@ -338,6 +339,7 @@ struct hnddma_pub *dma_attach(struct osl_info *osh, char *name, si_t *sih, | |||
338 | 339 | ||
339 | di->osh = osh; | 340 | di->osh = osh; |
340 | di->sih = sih; | 341 | di->sih = sih; |
342 | di->pbus = osh->pdev; | ||
341 | 343 | ||
342 | /* save tunables */ | 344 | /* save tunables */ |
343 | di->ntxd = (u16) ntxd; | 345 | di->ntxd = (u16) ntxd; |
@@ -531,7 +533,7 @@ static bool _dma_alloc(dma_info_t *di, uint direction) | |||
531 | return dma64_alloc(di, direction); | 533 | return dma64_alloc(di, direction); |
532 | } | 534 | } |
533 | 535 | ||
534 | void *dma_alloc_consistent(struct osl_info *osh, uint size, u16 align_bits, | 536 | void *dma_alloc_consistent(struct pci_dev *pdev, uint size, u16 align_bits, |
535 | uint *alloced, unsigned long *pap) | 537 | uint *alloced, unsigned long *pap) |
536 | { | 538 | { |
537 | if (align_bits) { | 539 | if (align_bits) { |
@@ -540,7 +542,7 @@ void *dma_alloc_consistent(struct osl_info *osh, uint size, u16 align_bits, | |||
540 | size += align; | 542 | size += align; |
541 | *alloced = size; | 543 | *alloced = size; |
542 | } | 544 | } |
543 | return pci_alloc_consistent(osh->pdev, size, (dma_addr_t *) pap); | 545 | return pci_alloc_consistent(pdev, size, (dma_addr_t *) pap); |
544 | } | 546 | } |
545 | 547 | ||
546 | /* !! may be called with core in reset */ | 548 | /* !! may be called with core in reset */ |
@@ -555,11 +557,11 @@ static void _dma_detach(dma_info_t *di) | |||
555 | 557 | ||
556 | /* free dma descriptor rings */ | 558 | /* free dma descriptor rings */ |
557 | if (di->txd64) | 559 | if (di->txd64) |
558 | pci_free_consistent(di->osh->pdev, di->txdalloc, | 560 | pci_free_consistent(di->pbus, di->txdalloc, |
559 | ((s8 *)di->txd64 - di->txdalign), | 561 | ((s8 *)di->txd64 - di->txdalign), |
560 | (di->txdpaorig)); | 562 | (di->txdpaorig)); |
561 | if (di->rxd64) | 563 | if (di->rxd64) |
562 | pci_free_consistent(di->osh->pdev, di->rxdalloc, | 564 | pci_free_consistent(di->pbus, di->rxdalloc, |
563 | ((s8 *)di->rxd64 - di->rxdalign), | 565 | ((s8 *)di->rxd64 - di->rxdalign), |
564 | (di->rxdpaorig)); | 566 | (di->rxdpaorig)); |
565 | 567 | ||
@@ -880,7 +882,7 @@ static bool BCMFASTPATH _dma_rxfill(dma_info_t *di) | |||
880 | memset(&di->rxp_dmah[rxout], 0, | 882 | memset(&di->rxp_dmah[rxout], 0, |
881 | sizeof(hnddma_seg_map_t)); | 883 | sizeof(hnddma_seg_map_t)); |
882 | 884 | ||
883 | pa = pci_map_single(di->osh->pdev, p->data, | 885 | pa = pci_map_single(di->pbus, p->data, |
884 | di->rxbufsize, PCI_DMA_FROMDEVICE); | 886 | di->rxbufsize, PCI_DMA_FROMDEVICE); |
885 | 887 | ||
886 | ASSERT(IS_ALIGNED(PHYSADDRLO(pa), 4)); | 888 | ASSERT(IS_ALIGNED(PHYSADDRLO(pa), 4)); |
@@ -1086,7 +1088,7 @@ u8 dma_align_sizetobits(uint size) | |||
1086 | * descriptor ring size aligned location. This will ensure that the ring will | 1088 | * descriptor ring size aligned location. This will ensure that the ring will |
1087 | * not cross page boundary | 1089 | * not cross page boundary |
1088 | */ | 1090 | */ |
1089 | static void *dma_ringalloc(struct osl_info *osh, u32 boundary, uint size, | 1091 | static void *dma_ringalloc(dma_info_t *di, u32 boundary, uint size, |
1090 | u16 *alignbits, uint *alloced, | 1092 | u16 *alignbits, uint *alloced, |
1091 | dmaaddr_t *descpa, osldma_t **dmah) | 1093 | dmaaddr_t *descpa, osldma_t **dmah) |
1092 | { | 1094 | { |
@@ -1094,7 +1096,7 @@ static void *dma_ringalloc(struct osl_info *osh, u32 boundary, uint size, | |||
1094 | u32 desc_strtaddr; | 1096 | u32 desc_strtaddr; |
1095 | u32 alignbytes = 1 << *alignbits; | 1097 | u32 alignbytes = 1 << *alignbits; |
1096 | 1098 | ||
1097 | va = dma_alloc_consistent(osh, size, *alignbits, alloced, descpa); | 1099 | va = dma_alloc_consistent(di->pbus, size, *alignbits, alloced, descpa); |
1098 | 1100 | ||
1099 | if (NULL == va) | 1101 | if (NULL == va) |
1100 | return NULL; | 1102 | return NULL; |
@@ -1103,8 +1105,8 @@ static void *dma_ringalloc(struct osl_info *osh, u32 boundary, uint size, | |||
1103 | if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr | 1105 | if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr |
1104 | & boundary)) { | 1106 | & boundary)) { |
1105 | *alignbits = dma_align_sizetobits(size); | 1107 | *alignbits = dma_align_sizetobits(size); |
1106 | pci_free_consistent(osh->pdev, size, va, *descpa); | 1108 | pci_free_consistent(di->pbus, size, va, *descpa); |
1107 | va = dma_alloc_consistent(osh, size, *alignbits, | 1109 | va = dma_alloc_consistent(di->pbus, size, *alignbits, |
1108 | alloced, descpa); | 1110 | alloced, descpa); |
1109 | } | 1111 | } |
1110 | return va; | 1112 | return va; |
@@ -1228,7 +1230,7 @@ static bool dma64_alloc(dma_info_t *di, uint direction) | |||
1228 | align = (1 << align_bits); | 1230 | align = (1 << align_bits); |
1229 | 1231 | ||
1230 | if (direction == DMA_TX) { | 1232 | if (direction == DMA_TX) { |
1231 | va = dma_ringalloc(di->osh, D64RINGALIGN, size, &align_bits, | 1233 | va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits, |
1232 | &alloced, &di->txdpaorig, &di->tx_dmah); | 1234 | &alloced, &di->txdpaorig, &di->tx_dmah); |
1233 | if (va == NULL) { | 1235 | if (va == NULL) { |
1234 | DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name)); | 1236 | DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name)); |
@@ -1246,7 +1248,7 @@ static bool dma64_alloc(dma_info_t *di, uint direction) | |||
1246 | di->txdalloc = alloced; | 1248 | di->txdalloc = alloced; |
1247 | ASSERT(IS_ALIGNED((unsigned long)di->txd64, align)); | 1249 | ASSERT(IS_ALIGNED((unsigned long)di->txd64, align)); |
1248 | } else { | 1250 | } else { |
1249 | va = dma_ringalloc(di->osh, D64RINGALIGN, size, &align_bits, | 1251 | va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits, |
1250 | &alloced, &di->rxdpaorig, &di->rx_dmah); | 1252 | &alloced, &di->rxdpaorig, &di->rx_dmah); |
1251 | if (va == NULL) { | 1253 | if (va == NULL) { |
1252 | DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name)); | 1254 | DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name)); |
@@ -1397,7 +1399,7 @@ static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit) | |||
1397 | if (len == 0) | 1399 | if (len == 0) |
1398 | return 0; | 1400 | return 0; |
1399 | 1401 | ||
1400 | pa = pci_map_single(di->osh->pdev, buf, len, PCI_DMA_TODEVICE); | 1402 | pa = pci_map_single(di->pbus, buf, len, PCI_DMA_TODEVICE); |
1401 | 1403 | ||
1402 | flags = (D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF); | 1404 | flags = (D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF); |
1403 | 1405 | ||
@@ -1477,7 +1479,7 @@ static int BCMFASTPATH dma64_txfast(dma_info_t *di, struct sk_buff *p0, | |||
1477 | memset(&di->txp_dmah[txout], 0, | 1479 | memset(&di->txp_dmah[txout], 0, |
1478 | sizeof(hnddma_seg_map_t)); | 1480 | sizeof(hnddma_seg_map_t)); |
1479 | 1481 | ||
1480 | pa = pci_map_single(di->osh->pdev, data, len, PCI_DMA_TODEVICE); | 1482 | pa = pci_map_single(di->pbus, data, len, PCI_DMA_TODEVICE); |
1481 | 1483 | ||
1482 | if (DMASGLIST_ENAB) { | 1484 | if (DMASGLIST_ENAB) { |
1483 | map = &di->txp_dmah[txout]; | 1485 | map = &di->txp_dmah[txout]; |
@@ -1639,7 +1641,7 @@ static void *BCMFASTPATH dma64_getnexttxp(dma_info_t *di, txd_range_t range) | |||
1639 | i = NEXTTXD(i); | 1641 | i = NEXTTXD(i); |
1640 | } | 1642 | } |
1641 | 1643 | ||
1642 | pci_unmap_single(di->osh->pdev, pa, size, PCI_DMA_TODEVICE); | 1644 | pci_unmap_single(di->pbus, pa, size, PCI_DMA_TODEVICE); |
1643 | } | 1645 | } |
1644 | 1646 | ||
1645 | di->txin = i; | 1647 | di->txin = i; |
@@ -1690,7 +1692,7 @@ static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall) | |||
1690 | di->dataoffsethigh)); | 1692 | di->dataoffsethigh)); |
1691 | 1693 | ||
1692 | /* clear this packet from the descriptor ring */ | 1694 | /* clear this packet from the descriptor ring */ |
1693 | pci_unmap_single(di->osh->pdev, pa, di->rxbufsize, PCI_DMA_FROMDEVICE); | 1695 | pci_unmap_single(di->pbus, pa, di->rxbufsize, PCI_DMA_FROMDEVICE); |
1694 | 1696 | ||
1695 | W_SM(&di->rxd64[i].addrlow, 0xdeadbeef); | 1697 | W_SM(&di->rxd64[i].addrlow, 0xdeadbeef); |
1696 | W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef); | 1698 | W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef); |
diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c index 56e658c429a..7f587f30844 100644 --- a/drivers/staging/brcm80211/util/nicpci.c +++ b/drivers/staging/brcm80211/util/nicpci.c | |||
@@ -36,6 +36,7 @@ typedef struct { | |||
36 | } regs; /* Memory mapped register to the core */ | 36 | } regs; /* Memory mapped register to the core */ |
37 | 37 | ||
38 | si_t *sih; /* System interconnect handle */ | 38 | si_t *sih; /* System interconnect handle */ |
39 | struct pci_dev *dev; | ||
39 | struct osl_info *osh; /* OSL handle */ | 40 | struct osl_info *osh; /* OSL handle */ |
40 | u8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */ | 41 | u8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */ |
41 | bool pcie_pr42767; | 42 | bool pcie_pr42767; |
@@ -95,12 +96,13 @@ void *pcicore_init(si_t *sih, struct osl_info *osh, void *regs) | |||
95 | 96 | ||
96 | pi->sih = sih; | 97 | pi->sih = sih; |
97 | pi->osh = osh; | 98 | pi->osh = osh; |
99 | pi->dev = osh->pdev; | ||
98 | 100 | ||
99 | if (sih->buscoretype == PCIE_CORE_ID) { | 101 | if (sih->buscoretype == PCIE_CORE_ID) { |
100 | u8 cap_ptr; | 102 | u8 cap_ptr; |
101 | pi->regs.pcieregs = (sbpcieregs_t *) regs; | 103 | pi->regs.pcieregs = (sbpcieregs_t *) regs; |
102 | cap_ptr = | 104 | cap_ptr = |
103 | pcicore_find_pci_capability(pi->osh, PCI_CAP_PCIECAP_ID, | 105 | pcicore_find_pci_capability(pi->dev, PCI_CAP_PCIECAP_ID, |
104 | NULL, NULL); | 106 | NULL, NULL); |
105 | ASSERT(cap_ptr); | 107 | ASSERT(cap_ptr); |
106 | pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET; | 108 | pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET; |
@@ -122,7 +124,7 @@ void pcicore_deinit(void *pch) | |||
122 | /* return cap_offset if requested capability exists in the PCI config space */ | 124 | /* return cap_offset if requested capability exists in the PCI config space */ |
123 | /* Note that it's caller's responsibility to make sure it's a pci bus */ | 125 | /* Note that it's caller's responsibility to make sure it's a pci bus */ |
124 | u8 | 126 | u8 |
125 | pcicore_find_pci_capability(struct osl_info *osh, u8 req_cap_id, | 127 | pcicore_find_pci_capability(void *dev, u8 req_cap_id, |
126 | unsigned char *buf, u32 *buflen) | 128 | unsigned char *buf, u32 *buflen) |
127 | { | 129 | { |
128 | u8 cap_id; | 130 | u8 cap_id; |
@@ -131,29 +133,29 @@ pcicore_find_pci_capability(struct osl_info *osh, u8 req_cap_id, | |||
131 | u8 byte_val; | 133 | u8 byte_val; |
132 | 134 | ||
133 | /* check for Header type 0 */ | 135 | /* check for Header type 0 */ |
134 | pci_read_config_byte(osh->pdev, PCI_CFG_HDR, &byte_val); | 136 | pci_read_config_byte(dev, PCI_CFG_HDR, &byte_val); |
135 | if ((byte_val & 0x7f) != PCI_HEADER_NORMAL) | 137 | if ((byte_val & 0x7f) != PCI_HEADER_NORMAL) |
136 | goto end; | 138 | goto end; |
137 | 139 | ||
138 | /* check if the capability pointer field exists */ | 140 | /* check if the capability pointer field exists */ |
139 | pci_read_config_byte(osh->pdev, PCI_CFG_STAT, &byte_val); | 141 | pci_read_config_byte(dev, PCI_CFG_STAT, &byte_val); |
140 | if (!(byte_val & PCI_CAPPTR_PRESENT)) | 142 | if (!(byte_val & PCI_CAPPTR_PRESENT)) |
141 | goto end; | 143 | goto end; |
142 | 144 | ||
143 | pci_read_config_byte(osh->pdev, PCI_CFG_CAPPTR, &cap_ptr); | 145 | pci_read_config_byte(dev, PCI_CFG_CAPPTR, &cap_ptr); |
144 | /* check if the capability pointer is 0x00 */ | 146 | /* check if the capability pointer is 0x00 */ |
145 | if (cap_ptr == 0x00) | 147 | if (cap_ptr == 0x00) |
146 | goto end; | 148 | goto end; |
147 | 149 | ||
148 | /* loop thr'u the capability list and see if the pcie capabilty exists */ | 150 | /* loop thr'u the capability list and see if the pcie capabilty exists */ |
149 | 151 | ||
150 | pci_read_config_byte(osh->pdev, cap_ptr, &cap_id); | 152 | pci_read_config_byte(dev, cap_ptr, &cap_id); |
151 | 153 | ||
152 | while (cap_id != req_cap_id) { | 154 | while (cap_id != req_cap_id) { |
153 | pci_read_config_byte(osh->pdev, cap_ptr + 1, &cap_ptr); | 155 | pci_read_config_byte(dev, cap_ptr + 1, &cap_ptr); |
154 | if (cap_ptr == 0x00) | 156 | if (cap_ptr == 0x00) |
155 | break; | 157 | break; |
156 | pci_read_config_byte(osh->pdev, cap_ptr, &cap_id); | 158 | pci_read_config_byte(dev, cap_ptr, &cap_id); |
157 | } | 159 | } |
158 | if (cap_id != req_cap_id) { | 160 | if (cap_id != req_cap_id) { |
159 | goto end; | 161 | goto end; |
@@ -172,7 +174,7 @@ pcicore_find_pci_capability(struct osl_info *osh, u8 req_cap_id, | |||
172 | bufsize = SZPCR - cap_data; | 174 | bufsize = SZPCR - cap_data; |
173 | *buflen = bufsize; | 175 | *buflen = bufsize; |
174 | while (bufsize--) { | 176 | while (bufsize--) { |
175 | pci_read_config_byte(osh->pdev, cap_data, buf); | 177 | pci_read_config_byte(dev, cap_data, buf); |
176 | cap_data++; | 178 | cap_data++; |
177 | buf++; | 179 | buf++; |
178 | } | 180 | } |
@@ -347,15 +349,15 @@ u8 pcie_clkreq(void *pch, u32 mask, u32 val) | |||
347 | if (!offset) | 349 | if (!offset) |
348 | return 0; | 350 | return 0; |
349 | 351 | ||
350 | pci_read_config_dword(pi->osh->pdev, offset, ®_val); | 352 | pci_read_config_dword(pi->dev, offset, ®_val); |
351 | /* set operation */ | 353 | /* set operation */ |
352 | if (mask) { | 354 | if (mask) { |
353 | if (val) | 355 | if (val) |
354 | reg_val |= PCIE_CLKREQ_ENAB; | 356 | reg_val |= PCIE_CLKREQ_ENAB; |
355 | else | 357 | else |
356 | reg_val &= ~PCIE_CLKREQ_ENAB; | 358 | reg_val &= ~PCIE_CLKREQ_ENAB; |
357 | pci_write_config_dword(pi->osh->pdev, offset, reg_val); | 359 | pci_write_config_dword(pi->dev, offset, reg_val); |
358 | pci_read_config_dword(pi->osh->pdev, offset, ®_val); | 360 | pci_read_config_dword(pi->dev, offset, ®_val); |
359 | } | 361 | } |
360 | if (reg_val & PCIE_CLKREQ_ENAB) | 362 | if (reg_val & PCIE_CLKREQ_ENAB) |
361 | return 1; | 363 | return 1; |
@@ -476,11 +478,11 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi) | |||
476 | 478 | ||
477 | W_REG(pi->osh, reg16, val16); | 479 | W_REG(pi->osh, reg16, val16); |
478 | 480 | ||
479 | pci_read_config_dword(pi->osh->pdev, pi->pciecap_lcreg_offset, | 481 | pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, |
480 | &w); | 482 | &w); |
481 | w &= ~PCIE_ASPM_ENAB; | 483 | w &= ~PCIE_ASPM_ENAB; |
482 | w |= pi->pcie_war_aspm_ovr; | 484 | w |= pi->pcie_war_aspm_ovr; |
483 | pci_write_config_dword(pi->osh->pdev, | 485 | pci_write_config_dword(pi->dev, |
484 | pi->pciecap_lcreg_offset, w); | 486 | pi->pciecap_lcreg_offset, w); |
485 | } | 487 | } |
486 | 488 | ||
@@ -668,9 +670,9 @@ void pcicore_sleep(void *pch) | |||
668 | if (!pi || !PCIE_ASPM(pi->sih)) | 670 | if (!pi || !PCIE_ASPM(pi->sih)) |
669 | return; | 671 | return; |
670 | 672 | ||
671 | pci_read_config_dword(pi->osh->pdev, pi->pciecap_lcreg_offset, &w); | 673 | pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w); |
672 | w &= ~PCIE_CAP_LCREG_ASPML1; | 674 | w &= ~PCIE_CAP_LCREG_ASPML1; |
673 | pci_write_config_dword(pi->osh->pdev, pi->pciecap_lcreg_offset, w); | 675 | pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w); |
674 | 676 | ||
675 | pi->pcie_pr42767 = false; | 677 | pi->pcie_pr42767 = false; |
676 | } | 678 | } |
@@ -690,19 +692,20 @@ void pcicore_down(void *pch, int state) | |||
690 | 692 | ||
691 | /* ***** Wake-on-wireless-LAN (WOWL) support functions ***** */ | 693 | /* ***** Wake-on-wireless-LAN (WOWL) support functions ***** */ |
692 | /* Just uses PCI config accesses to find out, when needed before sb_attach is done */ | 694 | /* Just uses PCI config accesses to find out, when needed before sb_attach is done */ |
693 | bool pcicore_pmecap_fast(struct osl_info *osh) | 695 | bool pcicore_pmecap_fast(void *pch) |
694 | { | 696 | { |
697 | pcicore_info_t *pi = (pcicore_info_t *) pch; | ||
695 | u8 cap_ptr; | 698 | u8 cap_ptr; |
696 | u32 pmecap; | 699 | u32 pmecap; |
697 | 700 | ||
698 | cap_ptr = | 701 | cap_ptr = |
699 | pcicore_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID, NULL, | 702 | pcicore_find_pci_capability(pi->dev, PCI_CAP_POWERMGMTCAP_ID, NULL, |
700 | NULL); | 703 | NULL); |
701 | 704 | ||
702 | if (!cap_ptr) | 705 | if (!cap_ptr) |
703 | return false; | 706 | return false; |
704 | 707 | ||
705 | pci_read_config_dword(osh->pdev, cap_ptr, &pmecap); | 708 | pci_read_config_dword(pi->dev, cap_ptr, &pmecap); |
706 | 709 | ||
707 | return (pmecap & PME_CAP_PM_STATES) != 0; | 710 | return (pmecap & PME_CAP_PM_STATES) != 0; |
708 | } | 711 | } |
@@ -717,7 +720,7 @@ static bool pcicore_pmecap(pcicore_info_t *pi) | |||
717 | 720 | ||
718 | if (!pi->pmecap_offset) { | 721 | if (!pi->pmecap_offset) { |
719 | cap_ptr = | 722 | cap_ptr = |
720 | pcicore_find_pci_capability(pi->osh, | 723 | pcicore_find_pci_capability(pi->dev, |
721 | PCI_CAP_POWERMGMTCAP_ID, NULL, | 724 | PCI_CAP_POWERMGMTCAP_ID, NULL, |
722 | NULL); | 725 | NULL); |
723 | if (!cap_ptr) | 726 | if (!cap_ptr) |
@@ -725,7 +728,7 @@ static bool pcicore_pmecap(pcicore_info_t *pi) | |||
725 | 728 | ||
726 | pi->pmecap_offset = cap_ptr; | 729 | pi->pmecap_offset = cap_ptr; |
727 | 730 | ||
728 | pci_read_config_dword(pi->osh->pdev, pi->pmecap_offset, | 731 | pci_read_config_dword(pi->dev, pi->pmecap_offset, |
729 | &pmecap); | 732 | &pmecap); |
730 | 733 | ||
731 | /* At least one state can generate PME */ | 734 | /* At least one state can generate PME */ |
@@ -745,10 +748,10 @@ void pcicore_pmeen(void *pch) | |||
745 | if (!pcicore_pmecap(pi)) | 748 | if (!pcicore_pmecap(pi)) |
746 | return; | 749 | return; |
747 | 750 | ||
748 | pci_read_config_dword(pi->osh->pdev, pi->pmecap_offset + PME_CSR_OFFSET, | 751 | pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET, |
749 | &w); | 752 | &w); |
750 | w |= (PME_CSR_PME_EN); | 753 | w |= (PME_CSR_PME_EN); |
751 | pci_write_config_dword(pi->osh->pdev, | 754 | pci_write_config_dword(pi->dev, |
752 | pi->pmecap_offset + PME_CSR_OFFSET, w); | 755 | pi->pmecap_offset + PME_CSR_OFFSET, w); |
753 | } | 756 | } |
754 | 757 | ||
@@ -763,7 +766,7 @@ bool pcicore_pmestat(void *pch) | |||
763 | if (!pcicore_pmecap(pi)) | 766 | if (!pcicore_pmecap(pi)) |
764 | return false; | 767 | return false; |
765 | 768 | ||
766 | pci_read_config_dword(pi->osh->pdev, pi->pmecap_offset + PME_CSR_OFFSET, | 769 | pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET, |
767 | &w); | 770 | &w); |
768 | 771 | ||
769 | return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT; | 772 | return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT; |
@@ -779,7 +782,7 @@ void pcicore_pmeclr(void *pch) | |||
779 | if (!pcicore_pmecap(pi)) | 782 | if (!pcicore_pmecap(pi)) |
780 | return; | 783 | return; |
781 | 784 | ||
782 | pci_read_config_dword(pi->osh->pdev, pi->pmecap_offset + PME_CSR_OFFSET, | 785 | pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET, |
783 | &w); | 786 | &w); |
784 | 787 | ||
785 | PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w)); | 788 | PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w)); |
@@ -787,7 +790,7 @@ void pcicore_pmeclr(void *pch) | |||
787 | /* PMESTAT is cleared by writing 1 to it */ | 790 | /* PMESTAT is cleared by writing 1 to it */ |
788 | w &= ~(PME_CSR_PME_EN); | 791 | w &= ~(PME_CSR_PME_EN); |
789 | 792 | ||
790 | pci_write_config_dword(pi->osh->pdev, | 793 | pci_write_config_dword(pi->dev, |
791 | pi->pmecap_offset + PME_CSR_OFFSET, w); | 794 | pi->pmecap_offset + PME_CSR_OFFSET, w); |
792 | } | 795 | } |
793 | 796 | ||
@@ -803,9 +806,9 @@ u32 pcie_lcreg(void *pch, u32 mask, u32 val) | |||
803 | 806 | ||
804 | /* set operation */ | 807 | /* set operation */ |
805 | if (mask) | 808 | if (mask) |
806 | pci_write_config_dword(pi->osh->pdev, offset, val); | 809 | pci_write_config_dword(pi->dev, offset, val); |
807 | 810 | ||
808 | pci_read_config_dword(pi->osh->pdev, offset, &tmpval); | 811 | pci_read_config_dword(pi->dev, offset, &tmpval); |
809 | return tmpval; | 812 | return tmpval; |
810 | } | 813 | } |
811 | 814 | ||
diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c index 5631d5b55c2..9a2e2c0f77b 100644 --- a/drivers/staging/brcm80211/util/siutils.c +++ b/drivers/staging/brcm80211/util/siutils.c | |||
@@ -313,7 +313,7 @@ static __used void si_nvram_process(si_info_t *sii, char *pvars) | |||
313 | switch (sii->pub.bustype) { | 313 | switch (sii->pub.bustype) { |
314 | case PCI_BUS: | 314 | case PCI_BUS: |
315 | /* do a pci config read to get subsystem id and subvendor id */ | 315 | /* do a pci config read to get subsystem id and subvendor id */ |
316 | pci_read_config_dword(sii->osh->pdev, PCI_CFG_SVID, &w); | 316 | pci_read_config_dword(sii->pbus, PCI_CFG_SVID, &w); |
317 | /* Let nvram variables override subsystem Vend/ID */ | 317 | /* Let nvram variables override subsystem Vend/ID */ |
318 | sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub, | 318 | sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub, |
319 | "boardvendor"); | 319 | "boardvendor"); |
@@ -367,7 +367,7 @@ static __used void si_nvram_process(si_info_t *sii, char *pvars) | |||
367 | /* this has been customized for the bcm 4329 ONLY */ | 367 | /* this has been customized for the bcm 4329 ONLY */ |
368 | #ifdef BCMSDIO | 368 | #ifdef BCMSDIO |
369 | static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, | 369 | static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, |
370 | void *regs, uint bustype, void *sdh, | 370 | void *regs, uint bustype, void *pbus, |
371 | char **vars, uint *varsz) | 371 | char **vars, uint *varsz) |
372 | { | 372 | { |
373 | struct si_pub *sih = &sii->pub; | 373 | struct si_pub *sih = &sii->pub; |
@@ -385,7 +385,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, | |||
385 | sih->buscoreidx = BADIDX; | 385 | sih->buscoreidx = BADIDX; |
386 | 386 | ||
387 | sii->curmap = regs; | 387 | sii->curmap = regs; |
388 | sii->sdh = sdh; | 388 | sii->pbus = pbus; |
389 | sii->osh = osh; | 389 | sii->osh = osh; |
390 | 390 | ||
391 | /* find Chipcommon address */ | 391 | /* find Chipcommon address */ |
@@ -393,7 +393,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, | |||
393 | sih->bustype = bustype; | 393 | sih->bustype = bustype; |
394 | 394 | ||
395 | /* bus/core/clk setup for register access */ | 395 | /* bus/core/clk setup for register access */ |
396 | if (!si_buscore_prep(sii, bustype, devid, sdh)) { | 396 | if (!si_buscore_prep(sii, bustype, devid, pbus)) { |
397 | SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", | 397 | SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", |
398 | bustype)); | 398 | bustype)); |
399 | return NULL; | 399 | return NULL; |
@@ -497,7 +497,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, | |||
497 | 497 | ||
498 | #else /* BCMSDIO */ | 498 | #else /* BCMSDIO */ |
499 | static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, | 499 | static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, |
500 | void *regs, uint bustype, void *sdh, | 500 | void *regs, uint bustype, void *pbus, |
501 | char **vars, uint *varsz) | 501 | char **vars, uint *varsz) |
502 | { | 502 | { |
503 | struct si_pub *sih = &sii->pub; | 503 | struct si_pub *sih = &sii->pub; |
@@ -515,12 +515,12 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, | |||
515 | sih->buscoreidx = BADIDX; | 515 | sih->buscoreidx = BADIDX; |
516 | 516 | ||
517 | sii->curmap = regs; | 517 | sii->curmap = regs; |
518 | sii->sdh = sdh; | 518 | sii->pbus = pbus; |
519 | sii->osh = osh; | 519 | sii->osh = osh; |
520 | 520 | ||
521 | /* check to see if we are a si core mimic'ing a pci core */ | 521 | /* check to see if we are a si core mimic'ing a pci core */ |
522 | if (bustype == PCI_BUS) { | 522 | if (bustype == PCI_BUS) { |
523 | pci_read_config_dword(sii->osh->pdev, PCI_SPROM_CONTROL, &w); | 523 | pci_read_config_dword(sii->pbus, PCI_SPROM_CONTROL, &w); |
524 | if (w == 0xffffffff) { | 524 | if (w == 0xffffffff) { |
525 | SI_ERROR(("%s: incoming bus is PCI but it's a lie, " | 525 | SI_ERROR(("%s: incoming bus is PCI but it's a lie, " |
526 | " switching to SI devid:0x%x\n", | 526 | " switching to SI devid:0x%x\n", |
@@ -531,10 +531,10 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, | |||
531 | 531 | ||
532 | /* find Chipcommon address */ | 532 | /* find Chipcommon address */ |
533 | if (bustype == PCI_BUS) { | 533 | if (bustype == PCI_BUS) { |
534 | pci_read_config_dword(sii->osh->pdev, PCI_BAR0_WIN, &savewin); | 534 | pci_read_config_dword(sii->pbus, PCI_BAR0_WIN, &savewin); |
535 | if (!GOODCOREADDR(savewin, SI_ENUM_BASE)) | 535 | if (!GOODCOREADDR(savewin, SI_ENUM_BASE)) |
536 | savewin = SI_ENUM_BASE; | 536 | savewin = SI_ENUM_BASE; |
537 | pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN, | 537 | pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, |
538 | SI_ENUM_BASE); | 538 | SI_ENUM_BASE); |
539 | cc = (chipcregs_t *) regs; | 539 | cc = (chipcregs_t *) regs; |
540 | } else { | 540 | } else { |
@@ -544,7 +544,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh, | |||
544 | sih->bustype = bustype; | 544 | sih->bustype = bustype; |
545 | 545 | ||
546 | /* bus/core/clk setup for register access */ | 546 | /* bus/core/clk setup for register access */ |
547 | if (!si_buscore_prep(sii, bustype, devid, sdh)) { | 547 | if (!si_buscore_prep(sii, bustype, devid, pbus)) { |
548 | SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", | 548 | SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n", |
549 | bustype)); | 549 | bustype)); |
550 | return NULL; | 550 | return NULL; |
@@ -1087,7 +1087,7 @@ static uint si_slowclk_src(si_info_t *sii) | |||
1087 | 1087 | ||
1088 | if (sii->pub.ccrev < 6) { | 1088 | if (sii->pub.ccrev < 6) { |
1089 | if (sii->pub.bustype == PCI_BUS) { | 1089 | if (sii->pub.bustype == PCI_BUS) { |
1090 | pci_read_config_dword(sii->osh->pdev, PCI_GPIO_OUT, | 1090 | pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, |
1091 | &val); | 1091 | &val); |
1092 | if (val & PCI_CFG_GPIO_SCS) | 1092 | if (val & PCI_CFG_GPIO_SCS) |
1093 | return SCC_SS_PCI; | 1093 | return SCC_SS_PCI; |
@@ -1274,9 +1274,9 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on) | |||
1274 | if (PCIE(sii)) | 1274 | if (PCIE(sii)) |
1275 | return -1; | 1275 | return -1; |
1276 | 1276 | ||
1277 | pci_read_config_dword(sii->osh->pdev, PCI_GPIO_IN, &in); | 1277 | pci_read_config_dword(sii->pbus, PCI_GPIO_IN, &in); |
1278 | pci_read_config_dword(sii->osh->pdev, PCI_GPIO_OUT, &out); | 1278 | pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, &out); |
1279 | pci_read_config_dword(sii->osh->pdev, PCI_GPIO_OUTEN, &outen); | 1279 | pci_read_config_dword(sii->pbus, PCI_GPIO_OUTEN, &outen); |
1280 | 1280 | ||
1281 | /* | 1281 | /* |
1282 | * Avoid glitching the clock if GPRS is already using it. | 1282 | * Avoid glitching the clock if GPRS is already using it. |
@@ -1297,9 +1297,9 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on) | |||
1297 | out |= PCI_CFG_GPIO_XTAL; | 1297 | out |= PCI_CFG_GPIO_XTAL; |
1298 | if (what & PLL) | 1298 | if (what & PLL) |
1299 | out |= PCI_CFG_GPIO_PLL; | 1299 | out |= PCI_CFG_GPIO_PLL; |
1300 | pci_write_config_dword(sii->osh->pdev, | 1300 | pci_write_config_dword(sii->pbus, |
1301 | PCI_GPIO_OUT, out); | 1301 | PCI_GPIO_OUT, out); |
1302 | pci_write_config_dword(sii->osh->pdev, | 1302 | pci_write_config_dword(sii->pbus, |
1303 | PCI_GPIO_OUTEN, outen); | 1303 | PCI_GPIO_OUTEN, outen); |
1304 | udelay(XTAL_ON_DELAY); | 1304 | udelay(XTAL_ON_DELAY); |
1305 | } | 1305 | } |
@@ -1307,7 +1307,7 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on) | |||
1307 | /* turn pll on */ | 1307 | /* turn pll on */ |
1308 | if (what & PLL) { | 1308 | if (what & PLL) { |
1309 | out &= ~PCI_CFG_GPIO_PLL; | 1309 | out &= ~PCI_CFG_GPIO_PLL; |
1310 | pci_write_config_dword(sii->osh->pdev, | 1310 | pci_write_config_dword(sii->pbus, |
1311 | PCI_GPIO_OUT, out); | 1311 | PCI_GPIO_OUT, out); |
1312 | mdelay(2); | 1312 | mdelay(2); |
1313 | } | 1313 | } |
@@ -1316,9 +1316,9 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on) | |||
1316 | out &= ~PCI_CFG_GPIO_XTAL; | 1316 | out &= ~PCI_CFG_GPIO_XTAL; |
1317 | if (what & PLL) | 1317 | if (what & PLL) |
1318 | out |= PCI_CFG_GPIO_PLL; | 1318 | out |= PCI_CFG_GPIO_PLL; |
1319 | pci_write_config_dword(sii->osh->pdev, | 1319 | pci_write_config_dword(sii->pbus, |
1320 | PCI_GPIO_OUT, out); | 1320 | PCI_GPIO_OUT, out); |
1321 | pci_write_config_dword(sii->osh->pdev, | 1321 | pci_write_config_dword(sii->pbus, |
1322 | PCI_GPIO_OUTEN, outen); | 1322 | PCI_GPIO_OUTEN, outen); |
1323 | } | 1323 | } |
1324 | 1324 | ||
@@ -1463,8 +1463,9 @@ int si_devpath(si_t *sih, char *path, int size) | |||
1463 | case PCI_BUS: | 1463 | case PCI_BUS: |
1464 | ASSERT((SI_INFO(sih))->osh != NULL); | 1464 | ASSERT((SI_INFO(sih))->osh != NULL); |
1465 | slen = snprintf(path, (size_t) size, "pci/%u/%u/", | 1465 | slen = snprintf(path, (size_t) size, "pci/%u/%u/", |
1466 | OSL_PCI_BUS((SI_INFO(sih))->osh), | 1466 | ((struct pci_dev *)((SI_INFO(sih))->pbus))->bus->number, |
1467 | OSL_PCI_SLOT((SI_INFO(sih))->osh)); | 1467 | PCI_SLOT( |
1468 | ((struct pci_dev *)((SI_INFO(sih))->pbus))->devfn)); | ||
1468 | break; | 1469 | break; |
1469 | 1470 | ||
1470 | #ifdef BCMSDIO | 1471 | #ifdef BCMSDIO |
@@ -1549,7 +1550,7 @@ static __used bool si_ispcie(si_info_t *sii) | |||
1549 | return false; | 1550 | return false; |
1550 | 1551 | ||
1551 | cap_ptr = | 1552 | cap_ptr = |
1552 | pcicore_find_pci_capability(sii->osh, PCI_CAP_PCIECAP_ID, NULL, | 1553 | pcicore_find_pci_capability(sii->pbus, PCI_CAP_PCIECAP_ID, NULL, |
1553 | NULL); | 1554 | NULL); |
1554 | if (!cap_ptr) | 1555 | if (!cap_ptr) |
1555 | return false; | 1556 | return false; |
@@ -1591,7 +1592,7 @@ void si_sdio_init(si_t *sih) | |||
1591 | } | 1592 | } |
1592 | 1593 | ||
1593 | /* enable interrupts */ | 1594 | /* enable interrupts */ |
1594 | bcmsdh_intr_enable(sii->sdh); | 1595 | bcmsdh_intr_enable(sii->pbus); |
1595 | 1596 | ||
1596 | } | 1597 | } |
1597 | #endif /* BCMSDIO */ | 1598 | #endif /* BCMSDIO */ |
@@ -1687,9 +1688,9 @@ void si_pci_setup(si_t *sih, uint coremask) | |||
1687 | */ | 1688 | */ |
1688 | if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) { | 1689 | if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) { |
1689 | /* pci config write to set this core bit in PCIIntMask */ | 1690 | /* pci config write to set this core bit in PCIIntMask */ |
1690 | pci_read_config_dword(sii->osh->pdev, PCI_INT_MASK, &w); | 1691 | pci_read_config_dword(sii->pbus, PCI_INT_MASK, &w); |
1691 | w |= (coremask << PCI_SBIM_SHIFT); | 1692 | w |= (coremask << PCI_SBIM_SHIFT); |
1692 | pci_write_config_dword(sii->osh->pdev, PCI_INT_MASK, w); | 1693 | pci_write_config_dword(sii->pbus, PCI_INT_MASK, w); |
1693 | } else { | 1694 | } else { |
1694 | /* set sbintvec bit for our flag number */ | 1695 | /* set sbintvec bit for our flag number */ |
1695 | si_setint(sih, siflag); | 1696 | si_setint(sih, siflag); |
@@ -1927,7 +1928,7 @@ bool si_deviceremoved(si_t *sih) | |||
1927 | switch (sih->bustype) { | 1928 | switch (sih->bustype) { |
1928 | case PCI_BUS: | 1929 | case PCI_BUS: |
1929 | ASSERT(sii->osh != NULL); | 1930 | ASSERT(sii->osh != NULL); |
1930 | pci_read_config_dword(sii->osh->pdev, PCI_CFG_VID, &w); | 1931 | pci_read_config_dword(sii->pbus, PCI_CFG_VID, &w); |
1931 | if ((w & 0xFFFF) != VENDOR_BROADCOM) | 1932 | if ((w & 0xFFFF) != VENDOR_BROADCOM) |
1932 | return true; | 1933 | return true; |
1933 | break; | 1934 | break; |