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authorKenji Toyama <kenji.toyama@gmail.com>2011-04-23 00:11:16 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-04-25 20:29:27 -0400
commitbf32fcb9fe0aec95c2fac78edee3e39d7e98a1b1 (patch)
tree5dfcdb3b854e2f36164b17bcc17a14bf17714006 /drivers/staging/xgifb/vb_init.c
parent6622995b3212e3c5b39b2ef0dd4d2b02ed183aa5 (diff)
Staging: xgifb: Fixed lots of coding style issues.
There were hundreds of warnings, but now there's only four. These are related to the 'volatile' keyword and printk(), which I think should be left to the maintainers to modify if deemed necessary. Signed-off-by: Daniel Kenji Toyama <kenji.toyama@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/xgifb/vb_init.c')
-rw-r--r--drivers/staging/xgifb/vb_init.c527
1 files changed, 366 insertions, 161 deletions
diff --git a/drivers/staging/xgifb/vb_init.c b/drivers/staging/xgifb/vb_init.c
index 61d137098aa..33c6876d2a8 100644
--- a/drivers/staging/xgifb/vb_init.c
+++ b/drivers/staging/xgifb/vb_init.c
@@ -13,7 +13,7 @@
13#include "vb_ext.h" 13#include "vb_ext.h"
14 14
15 15
16#include <asm/io.h> 16#include <linux/io.h>
17 17
18static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth; 18static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
19 19
@@ -39,8 +39,9 @@ static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
39 39
40static int XGINew_RAMType; 40static int XGINew_RAMType;
41 41
42static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension, 42static unsigned char
43 struct vb_device_info *pVBInfo) 43XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
44 struct vb_device_info *pVBInfo)
44{ 45{
45 unsigned char data, temp; 46 unsigned char data, temp;
46 47
@@ -50,10 +51,9 @@ static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceE
50 return data; 51 return data;
51 } else { 52 } else {
52 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02; 53 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
53
54 if (data == 0) 54 if (data == 0)
55 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) & 0x02) >> 1; 55 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
56 56 0x02) >> 1;
57 return data; 57 return data;
58 } 58 }
59 } else if (HwDeviceExtension->jChipType == XG27) { 59 } else if (HwDeviceExtension->jChipType == XG27) {
@@ -62,19 +62,22 @@ static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceE
62 return data; 62 return data;
63 } 63 }
64 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B); 64 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
65 65 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
66 if ((temp & 0x88) == 0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */ 66 if ((temp & 0x88) == 0x80)
67 data = 0; /* DDR */ 67 data = 0; /* DDR */
68 else 68 else
69 data = 1; /* DDRII */ 69 data = 1; /* DDRII */
70 return data; 70 return data;
71 } else if (HwDeviceExtension->jChipType == XG21) { 71 } else if (HwDeviceExtension->jChipType == XG21) {
72 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02); /* Independent GPIO control */ 72 /* Independent GPIO control */
73 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
73 udelay(800); 74 udelay(800);
74 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */ 75 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
75 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48); /* GPIOF 0:DVI 1:DVO */ 76 /* GPIOF 0:DVI 1:DVO */
77 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
76 /* HOTPLUG_SUPPORT */ 78 /* HOTPLUG_SUPPORT */
77 /* for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily */ 79 /* for current XG20 & XG21, GPIOH is floating, driver will
80 * fix DDR temporarily */
78 if (temp & 0x01) /* DVI read GPIOH */ 81 if (temp & 0x01) /* DVI read GPIOH */
79 data = 1; /* DDRII */ 82 data = 1; /* DDRII */
80 else 83 else
@@ -92,7 +95,8 @@ static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceE
92 } 95 }
93} 96}
94 97
95static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo) 98static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
99 struct vb_device_info *pVBInfo)
96{ 100{
97 xgifb_reg_set(P3c4, 0x18, 0x01); 101 xgifb_reg_set(P3c4, 0x18, 0x01);
98 xgifb_reg_set(P3c4, 0x19, 0x20); 102 xgifb_reg_set(P3c4, 0x19, 0x20);
@@ -126,24 +130,42 @@ static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
126 struct vb_device_info *pVBInfo) 130 struct vb_device_info *pVBInfo)
127{ 131{
128 132
129 xgifb_reg_set(pVBInfo->P3c4, 0x28, pVBInfo->MCLKData[XGINew_RAMType].SR28); 133 xgifb_reg_set(pVBInfo->P3c4,
130 xgifb_reg_set(pVBInfo->P3c4, 0x29, pVBInfo->MCLKData[XGINew_RAMType].SR29); 134 0x28,
131 xgifb_reg_set(pVBInfo->P3c4, 0x2A, pVBInfo->MCLKData[XGINew_RAMType].SR2A); 135 pVBInfo->MCLKData[XGINew_RAMType].SR28);
132 136 xgifb_reg_set(pVBInfo->P3c4,
133 xgifb_reg_set(pVBInfo->P3c4, 0x2E, pVBInfo->ECLKData[XGINew_RAMType].SR2E); 137 0x29,
134 xgifb_reg_set(pVBInfo->P3c4, 0x2F, pVBInfo->ECLKData[XGINew_RAMType].SR2F); 138 pVBInfo->MCLKData[XGINew_RAMType].SR29);
135 xgifb_reg_set(pVBInfo->P3c4, 0x30, pVBInfo->ECLKData[XGINew_RAMType].SR30); 139 xgifb_reg_set(pVBInfo->P3c4,
136 140 0x2A,
137 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */ 141 pVBInfo->MCLKData[XGINew_RAMType].SR2A);
138 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */ 142
143 xgifb_reg_set(pVBInfo->P3c4,
144 0x2E,
145 pVBInfo->ECLKData[XGINew_RAMType].SR2E);
146 xgifb_reg_set(pVBInfo->P3c4,
147 0x2F,
148 pVBInfo->ECLKData[XGINew_RAMType].SR2F);
149 xgifb_reg_set(pVBInfo->P3c4,
150 0x30,
151 pVBInfo->ECLKData[XGINew_RAMType].SR30);
152
153 /* [Vicent] 2004/07/07,
154 * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
155 /* [Hsuan] 2004/08/20,
156 * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
157 * Set SR32 D[1:0] = 10b */
139 if (HwDeviceExtension->jChipType == XG42) { 158 if (HwDeviceExtension->jChipType == XG42) {
140 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C) 159 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C) &&
141 && (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01) 160 (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01) &&
142 && (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C) 161 (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C) &&
143 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)) 162 (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)) ||
144 || ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22) 163 ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22) &&
145 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)))) 164 (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
146 xgifb_reg_set(pVBInfo->P3c4, 0x32, ((unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02); 165 xgifb_reg_set(pVBInfo->P3c4,
166 0x32,
167 ((unsigned char) xgifb_reg_get(
168 pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
147 } 169 }
148} 170}
149 171
@@ -152,7 +174,8 @@ static void XGINew_DDRII_Bootup_XG27(
152 unsigned long P3c4, struct vb_device_info *pVBInfo) 174 unsigned long P3c4, struct vb_device_info *pVBInfo)
153{ 175{
154 unsigned long P3d4 = P3c4 + 0x10; 176 unsigned long P3d4 = P3c4 + 0x10;
155 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo); 177 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
178 pVBInfo);
156 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo); 179 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
157 180
158 /* Set Double Frequency */ 181 /* Set Double Frequency */
@@ -216,7 +239,8 @@ static void XGINew_DDRII_Bootup_XG27(
216 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */ 239 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
217 udelay(15); 240 udelay(15);
218 241
219 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B refresh control 000:close; 010:open */ 242 /* Set SR1B refresh control 000:close; 010:open */
243 xgifb_reg_set(P3c4, 0x1B, 0x04);
220 udelay(200); 244 udelay(200);
221 245
222} 246}
@@ -226,7 +250,8 @@ static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
226{ 250{
227 unsigned long P3d4 = P3c4 + 0x10; 251 unsigned long P3d4 = P3c4 + 0x10;
228 252
229 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo); 253 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
254 pVBInfo);
230 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo); 255 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
231 256
232 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */ 257 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
@@ -268,9 +293,9 @@ static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
268 udelay(200); 293 udelay(200);
269} 294}
270 295
271static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo) 296static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
297 struct vb_device_info *pVBInfo)
272{ 298{
273
274 xgifb_reg_set(P3c4, 0x18, 0x01); 299 xgifb_reg_set(P3c4, 0x18, 0x01);
275 xgifb_reg_set(P3c4, 0x19, 0x40); 300 xgifb_reg_set(P3c4, 0x19, 0x40);
276 xgifb_reg_set(P3c4, 0x16, 0x00); 301 xgifb_reg_set(P3c4, 0x16, 0x00);
@@ -306,9 +331,15 @@ static void XGINew_DDR1x_DefaultRegister(
306 331
307 if (HwDeviceExtension->jChipType >= XG20) { 332 if (HwDeviceExtension->jChipType >= XG20) {
308 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo); 333 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
309 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */ 334 xgifb_reg_set(P3d4,
310 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */ 335 0x82,
311 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */ 336 pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
337 xgifb_reg_set(P3d4,
338 0x85,
339 pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
340 xgifb_reg_set(P3d4,
341 0x86,
342 pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
312 343
313 xgifb_reg_set(P3d4, 0x98, 0x01); 344 xgifb_reg_set(P3d4, 0x98, 0x01);
314 xgifb_reg_set(P3d4, 0x9A, 0x02); 345 xgifb_reg_set(P3d4, 0x9A, 0x02);
@@ -320,24 +351,46 @@ static void XGINew_DDR1x_DefaultRegister(
320 switch (HwDeviceExtension->jChipType) { 351 switch (HwDeviceExtension->jChipType) {
321 case XG41: 352 case XG41:
322 case XG42: 353 case XG42:
323 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */ 354 /* CR82 */
324 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */ 355 xgifb_reg_set(P3d4,
325 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */ 356 0x82,
357 pVBInfo->CR40[11][XGINew_RAMType]);
358 /* CR85 */
359 xgifb_reg_set(P3d4,
360 0x85,
361 pVBInfo->CR40[12][XGINew_RAMType]);
362 /* CR86 */
363 xgifb_reg_set(P3d4,
364 0x86,
365 pVBInfo->CR40[13][XGINew_RAMType]);
326 break; 366 break;
327 default: 367 default:
328 xgifb_reg_set(P3d4, 0x82, 0x88); 368 xgifb_reg_set(P3d4, 0x82, 0x88);
329 xgifb_reg_set(P3d4, 0x86, 0x00); 369 xgifb_reg_set(P3d4, 0x86, 0x00);
330 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */ 370 /* Insert read command for delay */
371 xgifb_reg_get(P3d4, 0x86);
331 xgifb_reg_set(P3d4, 0x86, 0x88); 372 xgifb_reg_set(P3d4, 0x86, 0x88);
332 xgifb_reg_get(P3d4, 0x86); 373 xgifb_reg_get(P3d4, 0x86);
333 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); 374 xgifb_reg_set(P3d4,
375 0x86,
376 pVBInfo->CR40[13][XGINew_RAMType]);
334 xgifb_reg_set(P3d4, 0x82, 0x77); 377 xgifb_reg_set(P3d4, 0x82, 0x77);
335 xgifb_reg_set(P3d4, 0x85, 0x00); 378 xgifb_reg_set(P3d4, 0x85, 0x00);
336 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */ 379
380 /* Insert read command for delay */
381 xgifb_reg_get(P3d4, 0x85);
337 xgifb_reg_set(P3d4, 0x85, 0x88); 382 xgifb_reg_set(P3d4, 0x85, 0x88);
338 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */ 383
339 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */ 384 /* Insert read command for delay */
340 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */ 385 xgifb_reg_get(P3d4, 0x85);
386 /* CR85 */
387 xgifb_reg_set(P3d4,
388 0x85,
389 pVBInfo->CR40[12][XGINew_RAMType]);
390 /* CR82 */
391 xgifb_reg_set(P3d4,
392 0x82,
393 pVBInfo->CR40[11][XGINew_RAMType]);
341 break; 394 break;
342 } 395 }
343 396
@@ -354,13 +407,15 @@ static void XGINew_DDR2_DefaultRegister(
354{ 407{
355 unsigned long P3d4 = Port, P3c4 = Port - 0x10; 408 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
356 409
357 /* keep following setting sequence, each setting in the same reg insert idle */ 410 /* keep following setting sequence, each setting in
411 * the same reg insert idle */
358 xgifb_reg_set(P3d4, 0x82, 0x77); 412 xgifb_reg_set(P3d4, 0x82, 0x77);
359 xgifb_reg_set(P3d4, 0x86, 0x00); 413 xgifb_reg_set(P3d4, 0x86, 0x00);
360 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */ 414 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
361 xgifb_reg_set(P3d4, 0x86, 0x88); 415 xgifb_reg_set(P3d4, 0x86, 0x88);
362 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */ 416 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
363 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */ 417 /* CR86 */
418 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
364 xgifb_reg_set(P3d4, 0x82, 0x77); 419 xgifb_reg_set(P3d4, 0x82, 0x77);
365 xgifb_reg_set(P3d4, 0x85, 0x00); 420 xgifb_reg_set(P3d4, 0x85, 0x00);
366 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */ 421 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
@@ -368,7 +423,8 @@ static void XGINew_DDR2_DefaultRegister(
368 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */ 423 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
369 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */ 424 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
370 if (HwDeviceExtension->jChipType == XG27) 425 if (HwDeviceExtension->jChipType == XG27)
371 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */ 426 /* CR82 */
427 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]);
372 else 428 else
373 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */ 429 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
374 430
@@ -395,12 +451,14 @@ static void XGINew_SetDRAMDefaultRegister340(
395 451
396 temp2 = 0; 452 temp2 = 0;
397 for (i = 0; i < 4; i++) { 453 for (i = 0; i < 4; i++) {
398 temp = pVBInfo->CR6B[XGINew_RAMType][i]; /* CR6B DQS fine tune delay */ 454 /* CR6B DQS fine tune delay */
455 temp = pVBInfo->CR6B[XGINew_RAMType][i];
399 for (j = 0; j < 4; j++) { 456 for (j = 0; j < 4; j++) {
400 temp1 = ((temp >> (2 * j)) & 0x03) << 2; 457 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
401 temp2 |= temp1; 458 temp2 |= temp1;
402 xgifb_reg_set(P3d4, 0x6B, temp2); 459 xgifb_reg_set(P3d4, 0x6B, temp2);
403 xgifb_reg_get(P3d4, 0x6B); /* Insert read command for delay */ 460 /* Insert read command for delay */
461 xgifb_reg_get(P3d4, 0x6B);
404 temp2 &= 0xF0; 462 temp2 &= 0xF0;
405 temp2 += 0x10; 463 temp2 += 0x10;
406 } 464 }
@@ -408,12 +466,14 @@ static void XGINew_SetDRAMDefaultRegister340(
408 466
409 temp2 = 0; 467 temp2 = 0;
410 for (i = 0; i < 4; i++) { 468 for (i = 0; i < 4; i++) {
411 temp = pVBInfo->CR6E[XGINew_RAMType][i]; /* CR6E DQM fine tune delay */ 469 /* CR6E DQM fine tune delay */
470 temp = pVBInfo->CR6E[XGINew_RAMType][i];
412 for (j = 0; j < 4; j++) { 471 for (j = 0; j < 4; j++) {
413 temp1 = ((temp >> (2 * j)) & 0x03) << 2; 472 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
414 temp2 |= temp1; 473 temp2 |= temp1;
415 xgifb_reg_set(P3d4, 0x6E, temp2); 474 xgifb_reg_set(P3d4, 0x6E, temp2);
416 xgifb_reg_get(P3d4, 0x6E); /* Insert read command for delay */ 475 /* Insert read command for delay */
476 xgifb_reg_get(P3d4, 0x6E);
417 temp2 &= 0xF0; 477 temp2 &= 0xF0;
418 temp2 += 0x10; 478 temp2 += 0x10;
419 } 479 }
@@ -421,15 +481,18 @@ static void XGINew_SetDRAMDefaultRegister340(
421 481
422 temp3 = 0; 482 temp3 = 0;
423 for (k = 0; k < 4; k++) { 483 for (k = 0; k < 4; k++) {
424 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3); /* CR6E_D[1:0] select channel */ 484 /* CR6E_D[1:0] select channel */
485 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
425 temp2 = 0; 486 temp2 = 0;
426 for (i = 0; i < 8; i++) { 487 for (i = 0; i < 8; i++) {
427 temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i]; /* CR6F DQ fine tune delay */ 488 /* CR6F DQ fine tune delay */
489 temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i];
428 for (j = 0; j < 4; j++) { 490 for (j = 0; j < 4; j++) {
429 temp1 = (temp >> (2 * j)) & 0x03; 491 temp1 = (temp >> (2 * j)) & 0x03;
430 temp2 |= temp1; 492 temp2 |= temp1;
431 xgifb_reg_set(P3d4, 0x6F, temp2); 493 xgifb_reg_set(P3d4, 0x6F, temp2);
432 xgifb_reg_get(P3d4, 0x6F); /* Insert read command for delay */ 494 /* Insert read command for delay */
495 xgifb_reg_get(P3d4, 0x6F);
433 temp2 &= 0xF8; 496 temp2 &= 0xF8;
434 temp2 += 0x08; 497 temp2 += 0x08;
435 } 498 }
@@ -441,7 +504,8 @@ static void XGINew_SetDRAMDefaultRegister340(
441 xgifb_reg_set(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */ 504 xgifb_reg_set(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
442 505
443 temp2 = 0x80; 506 temp2 = 0x80;
444 temp = pVBInfo->CR89[XGINew_RAMType][0]; /* CR89 terminator type select */ 507 /* CR89 terminator type select */
508 temp = pVBInfo->CR89[XGINew_RAMType][0];
445 for (j = 0; j < 4; j++) { 509 for (j = 0; j < 4; j++) {
446 temp1 = (temp >> (2 * j)) & 0x03; 510 temp1 = (temp >> (2 * j)) & 0x03;
447 temp2 |= temp1; 511 temp2 |= temp1;
@@ -468,19 +532,20 @@ static void XGINew_SetDRAMDefaultRegister340(
468 if (HwDeviceExtension->jChipType == XG27) 532 if (HwDeviceExtension->jChipType == XG27)
469 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */ 533 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
470 534
471 for (j = 0; j <= 6; j++) 535 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
472 xgifb_reg_set(P3d4, (0x90 + j), 536 xgifb_reg_set(P3d4, (0x90 + j),
473 pVBInfo->CR40[14 + j][XGINew_RAMType]); /* CR90 - CR96 */ 537 pVBInfo->CR40[14 + j][XGINew_RAMType]);
474 538
475 for (j = 0; j <= 2; j++) 539 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
476 xgifb_reg_set(P3d4, (0xC3 + j), 540 xgifb_reg_set(P3d4, (0xC3 + j),
477 pVBInfo->CR40[21 + j][XGINew_RAMType]); /* CRC3 - CRC5 */ 541 pVBInfo->CR40[21 + j][XGINew_RAMType]);
478 542
479 for (j = 0; j < 2; j++) 543 for (j = 0; j < 2; j++) /* CR8A - CR8B */
480 xgifb_reg_set(P3d4, (0x8A + j), 544 xgifb_reg_set(P3d4, (0x8A + j),
481 pVBInfo->CR40[1 + j][XGINew_RAMType]); /* CR8A - CR8B */ 545 pVBInfo->CR40[1 + j][XGINew_RAMType]);
482 546
483 if ((HwDeviceExtension->jChipType == XG41) || (HwDeviceExtension->jChipType == XG42)) 547 if ((HwDeviceExtension->jChipType == XG41) ||
548 (HwDeviceExtension->jChipType == XG42))
484 xgifb_reg_set(P3d4, 0x8C, 0x87); 549 xgifb_reg_set(P3d4, 0x8C, 0x87);
485 550
486 xgifb_reg_set(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */ 551 xgifb_reg_set(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
@@ -550,7 +615,10 @@ static unsigned short XGINew_SetDRAMSizeReg(int index,
550 memsize = data >> 4; 615 memsize = data >> 4;
551 616
552 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */ 617 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
553 xgifb_reg_set(pVBInfo->P3c4, 0x14, (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0)); 618 xgifb_reg_set(pVBInfo->P3c4,
619 0x14,
620 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
621 (data & 0xF0));
554 622
555 /* data |= XGINew_ChannelAB << 2; */ 623 /* data |= XGINew_ChannelAB << 2; */
556 /* data |= (XGINew_DataBusWidth / 64) << 1; */ 624 /* data |= (XGINew_DataBusWidth / 64) << 1; */
@@ -591,7 +659,10 @@ static unsigned short XGINew_SetDRAMSize20Reg(int index,
591 memsize = data >> 4; 659 memsize = data >> 4;
592 660
593 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */ 661 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
594 xgifb_reg_set(pVBInfo->P3c4, 0x14, (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0)); 662 xgifb_reg_set(pVBInfo->P3c4,
663 0x14,
664 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
665 (data & 0xF0));
595 udelay(15); 666 udelay(15);
596 667
597 /* data |= XGINew_ChannelAB << 2; */ 668 /* data |= XGINew_ChannelAB << 2; */
@@ -617,7 +688,8 @@ static int XGINew_ReadWriteRest(unsigned short StopAddr,
617 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position; 688 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
618 } 689 }
619 690
620 udelay(500); /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */ 691 udelay(500); /* [Vicent] 2004/04/16.
692 Fix #1759 Memory Size error in Multi-Adapter. */
621 693
622 Position = 0; 694 Position = 0;
623 695
@@ -626,7 +698,8 @@ static int XGINew_ReadWriteRest(unsigned short StopAddr,
626 698
627 for (i = StartAddr; i <= StopAddr; i++) { 699 for (i = StartAddr; i <= StopAddr; i++) {
628 Position = 1 << i; 700 Position = 1 << i;
629 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position) 701 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) !=
702 Position)
630 return 0; 703 return 0;
631 } 704 }
632 return 1; 705 return 1;
@@ -665,67 +738,96 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
665 > 0x1000000) { 738 > 0x1000000) {
666 739
667 XGINew_DataBusWidth = 32; /* 32 bits */ 740 XGINew_DataBusWidth = 32; /* 32 bits */
668 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 32bit */ 741 /* 22bit + 2 rank + 32bit */
742 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
669 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52); 743 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
670 udelay(15); 744 udelay(15);
671 745
672 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) 746 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
673 return; 747 return;
674 748
675 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) { 749 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
676 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31); /* 22bit + 1 rank + 32bit */ 750 0x800000) {
677 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42); 751 /* 22bit + 1 rank + 32bit */
752 xgifb_reg_set(pVBInfo->P3c4,
753 0x13,
754 0x31);
755 xgifb_reg_set(pVBInfo->P3c4,
756 0x14,
757 0x42);
678 udelay(15); 758 udelay(15);
679 759
680 if (XGINew_ReadWriteRest(23, 23, pVBInfo) == 1) 760 if (XGINew_ReadWriteRest(23,
761 23,
762 pVBInfo) == 1)
681 return; 763 return;
682 } 764 }
683 } 765 }
684 766
685 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) { 767 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
768 0x800000) {
686 XGINew_DataBusWidth = 16; /* 16 bits */ 769 XGINew_DataBusWidth = 16; /* 16 bits */
687 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 16bit */ 770 /* 22bit + 2 rank + 16bit */
771 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
688 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41); 772 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
689 udelay(15); 773 udelay(15);
690 774
691 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1) 775 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
692 return; 776 return;
693 else 777 else
694 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31); 778 xgifb_reg_set(pVBInfo->P3c4,
779 0x13,
780 0x31);
695 udelay(15); 781 udelay(15);
696 } 782 }
697 783
698 } else { /* Dual_16_8 */ 784 } else { /* Dual_16_8 */
699 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) { 785 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
700 786 0x800000) {
701 XGINew_DataBusWidth = 16; /* 16 bits */ 787 XGINew_DataBusWidth = 16; /* 16 bits */
702 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */ 788 /* (0x31:12x8x2) 22bit + 2 rank */
703 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41); /* 0x41:16Mx16 bit*/ 789 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
790 /* 0x41:16Mx16 bit*/
791 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
704 udelay(15); 792 udelay(15);
705 793
706 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1) 794 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
707 return; 795 return;
708 796
709 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) { 797 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
710 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */ 798 0x400000) {
711 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31); /* 0x31:8Mx16 bit*/ 799 /* (0x31:12x8x2) 22bit + 1 rank */
800 xgifb_reg_set(pVBInfo->P3c4,
801 0x13,
802 0x31);
803 /* 0x31:8Mx16 bit*/
804 xgifb_reg_set(pVBInfo->P3c4,
805 0x14,
806 0x31);
712 udelay(15); 807 udelay(15);
713 808
714 if (XGINew_ReadWriteRest(22, 22, pVBInfo) == 1) 809 if (XGINew_ReadWriteRest(22,
810 22,
811 pVBInfo) == 1)
715 return; 812 return;
716 } 813 }
717 } 814 }
718 815
719 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) { 816 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
817 0x400000) {
720 XGINew_DataBusWidth = 8; /* 8 bits */ 818 XGINew_DataBusWidth = 8; /* 8 bits */
721 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */ 819 /* (0x31:12x8x2) 22bit + 2 rank */
722 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30); /* 0x30:8Mx8 bit*/ 820 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
821 /* 0x30:8Mx8 bit*/
822 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
723 udelay(15); 823 udelay(15);
724 824
725 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1) 825 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
726 return; 826 return;
727 else 827 else /* (0x31:12x8x2) 22bit + 1 rank */
728 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */ 828 xgifb_reg_set(pVBInfo->P3c4,
829 0x13,
830 0x31);
729 udelay(15); 831 udelay(15);
730 } 832 }
731 } 833 }
@@ -911,13 +1013,18 @@ static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
911 1013
912 if (HwDeviceExtension->jChipType >= XG20) { 1014 if (HwDeviceExtension->jChipType >= XG20) {
913 for (i = 0; i < 12; i++) { 1015 for (i = 0; i < 12; i++) {
914 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE20, pVBInfo); 1016 XGINew_SetDRAMSizingType(i,
915 memsize = XGINew_SetDRAMSize20Reg(i, XGINew_DDRDRAM_TYPE20, pVBInfo); 1017 XGINew_DDRDRAM_TYPE20,
1018 pVBInfo);
1019 memsize = XGINew_SetDRAMSize20Reg(i,
1020 XGINew_DDRDRAM_TYPE20,
1021 pVBInfo);
916 if (memsize == 0) 1022 if (memsize == 0)
917 continue; 1023 continue;
918 1024
919 addr = memsize + (XGINew_ChannelAB - 2) + 20; 1025 addr = memsize + (XGINew_ChannelAB - 2) + 20;
920 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr)) 1026 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1027 (unsigned long) (1 << addr))
921 continue; 1028 continue;
922 1029
923 if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1) 1030 if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
@@ -925,14 +1032,19 @@ static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
925 } 1032 }
926 } else { 1033 } else {
927 for (i = 0; i < 4; i++) { 1034 for (i = 0; i < 4; i++) {
928 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE340, pVBInfo); 1035 XGINew_SetDRAMSizingType(i,
929 memsize = XGINew_SetDRAMSizeReg(i, XGINew_DDRDRAM_TYPE340, pVBInfo); 1036 XGINew_DDRDRAM_TYPE340,
1037 pVBInfo);
1038 memsize = XGINew_SetDRAMSizeReg(i,
1039 XGINew_DDRDRAM_TYPE340,
1040 pVBInfo);
930 1041
931 if (memsize == 0) 1042 if (memsize == 0)
932 continue; 1043 continue;
933 1044
934 addr = memsize + (XGINew_ChannelAB - 2) + 20; 1045 addr = memsize + (XGINew_ChannelAB - 2) + 20;
935 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr)) 1046 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1047 (unsigned long) (1 << addr))
936 continue; 1048 continue;
937 1049
938 if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1) 1050 if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
@@ -953,7 +1065,8 @@ static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
953 XGISetModeNew(HwDeviceExtension, 0x2e); 1065 XGISetModeNew(HwDeviceExtension, 0x2e);
954 1066
955 data = xgifb_reg_get(pVBInfo->P3c4, 0x21); 1067 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
956 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */ 1068 /* disable read cache */
1069 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
957 XGI_DisplayOff(HwDeviceExtension, pVBInfo); 1070 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
958 1071
959 /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */ 1072 /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
@@ -961,12 +1074,15 @@ static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
961 /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */ 1074 /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
962 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo); 1075 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
963 data = xgifb_reg_get(pVBInfo->P3c4, 0x21); 1076 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
964 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */ 1077 /* enable read cache */
1078 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
965} 1079}
966 1080
967static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo) 1081static void ReadVBIOSTablData(unsigned char ChipType,
1082 struct vb_device_info *pVBInfo)
968{ 1083{
969 volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr; 1084 volatile unsigned char *pVideoMemory =
1085 (unsigned char *) pVBInfo->ROMAddr;
970 unsigned long i; 1086 unsigned long i;
971 unsigned char j, k; 1087 unsigned char j, k;
972 /* Volari customize data area end */ 1088 /* Volari customize data area end */
@@ -980,24 +1096,34 @@ static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVB
980 if (j != 0xff) { 1096 if (j != 0xff) {
981 k = 0; 1097 k = 0;
982 do { 1098 do {
983 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability 1099 pVBInfo->XG21_LVDSCapList[k].
984 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8); 1100 LVDS_Capability
1101 = pVideoMemory[i] |
1102 (pVideoMemory[i + 1] << 8);
985 pVBInfo->XG21_LVDSCapList[k].LVDSHT 1103 pVBInfo->XG21_LVDSCapList[k].LVDSHT
986 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8); 1104 = pVideoMemory[i + 2] |
1105 (pVideoMemory[i + 3] << 8);
987 pVBInfo->XG21_LVDSCapList[k].LVDSVT 1106 pVBInfo->XG21_LVDSCapList[k].LVDSVT
988 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8); 1107 = pVideoMemory[i + 4] |
1108 (pVideoMemory[i + 5] << 8);
989 pVBInfo->XG21_LVDSCapList[k].LVDSHDE 1109 pVBInfo->XG21_LVDSCapList[k].LVDSHDE
990 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8); 1110 = pVideoMemory[i + 6] |
1111 (pVideoMemory[i + 7] << 8);
991 pVBInfo->XG21_LVDSCapList[k].LVDSVDE 1112 pVBInfo->XG21_LVDSCapList[k].LVDSVDE
992 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8); 1113 = pVideoMemory[i + 8] |
1114 (pVideoMemory[i + 9] << 8);
993 pVBInfo->XG21_LVDSCapList[k].LVDSHFP 1115 pVBInfo->XG21_LVDSCapList[k].LVDSHFP
994 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8); 1116 = pVideoMemory[i + 10] |
1117 (pVideoMemory[i + 11] << 8);
995 pVBInfo->XG21_LVDSCapList[k].LVDSVFP 1118 pVBInfo->XG21_LVDSCapList[k].LVDSVFP
996 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8); 1119 = pVideoMemory[i + 12] |
1120 (pVideoMemory[i + 13] << 8);
997 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC 1121 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
998 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8); 1122 = pVideoMemory[i + 14] |
1123 (pVideoMemory[i + 15] << 8);
999 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC 1124 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1000 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8); 1125 = pVideoMemory[i + 16] |
1126 (pVideoMemory[i + 17] << 8);
1001 pVBInfo->XG21_LVDSCapList[k].VCLKData1 1127 pVBInfo->XG21_LVDSCapList[k].VCLKData1
1002 = pVideoMemory[i + 18]; 1128 = pVideoMemory[i + 18];
1003 pVBInfo->XG21_LVDSCapList[k].VCLKData2 1129 pVBInfo->XG21_LVDSCapList[k].VCLKData2
@@ -1015,26 +1141,38 @@ static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVB
1015 i += 25; 1141 i += 25;
1016 j--; 1142 j--;
1017 k++; 1143 k++;
1018 } while ((j > 0) && (k < (sizeof(XGI21_LCDCapList) / sizeof(struct XGI21_LVDSCapStruct)))); 1144 } while ((j > 0) &&
1145 (k < (sizeof(XGI21_LCDCapList) /
1146 sizeof(struct
1147 XGI21_LVDSCapStruct))));
1019 } else { 1148 } else {
1020 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability 1149 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1021 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8); 1150 = pVideoMemory[i] |
1151 (pVideoMemory[i + 1] << 8);
1022 pVBInfo->XG21_LVDSCapList[0].LVDSHT 1152 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1023 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8); 1153 = pVideoMemory[i + 2] |
1154 (pVideoMemory[i + 3] << 8);
1024 pVBInfo->XG21_LVDSCapList[0].LVDSVT 1155 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1025 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8); 1156 = pVideoMemory[i + 4] |
1157 (pVideoMemory[i + 5] << 8);
1026 pVBInfo->XG21_LVDSCapList[0].LVDSHDE 1158 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1027 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8); 1159 = pVideoMemory[i + 6] |
1160 (pVideoMemory[i + 7] << 8);
1028 pVBInfo->XG21_LVDSCapList[0].LVDSVDE 1161 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1029 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8); 1162 = pVideoMemory[i + 8] |
1163 (pVideoMemory[i + 9] << 8);
1030 pVBInfo->XG21_LVDSCapList[0].LVDSHFP 1164 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1031 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8); 1165 = pVideoMemory[i + 10] |
1166 (pVideoMemory[i + 11] << 8);
1032 pVBInfo->XG21_LVDSCapList[0].LVDSVFP 1167 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1033 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8); 1168 = pVideoMemory[i + 12] |
1169 (pVideoMemory[i + 13] << 8);
1034 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC 1170 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1035 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8); 1171 = pVideoMemory[i + 14] |
1172 (pVideoMemory[i + 15] << 8);
1036 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC 1173 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1037 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8); 1174 = pVideoMemory[i + 16] |
1175 (pVideoMemory[i + 17] << 8);
1038 pVBInfo->XG21_LVDSCapList[0].VCLKData1 1176 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1039 = pVideoMemory[i + 18]; 1177 = pVideoMemory[i + 18];
1040 pVBInfo->XG21_LVDSCapList[0].VCLKData2 1178 pVBInfo->XG21_LVDSCapList[0].VCLKData2
@@ -1197,21 +1335,31 @@ static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1197 if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */ 1335 if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1198 pVBInfo->IF_DEF_LVDS = 1; 1336 pVBInfo->IF_DEF_LVDS = 1;
1199 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense); 1337 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1200 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS on chip */ 1338 /* LVDS on chip */
1339 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1201 } else { 1340 } else {
1202#endif 1341#endif
1203 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* Enable GPIOA/B read */ 1342 /* Enable GPIOA/B read */
1343 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1204 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0; 1344 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1205 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */ 1345 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1206 XGINew_SenseLCD(HwDeviceExtension, pVBInfo); 1346 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1207 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense); 1347 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1208 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20); /* Enable read GPIOF */ 1348 /* Enable read GPIOF */
1349 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1209 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04; 1350 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1210 if (!Temp) 1351 if (!Temp)
1211 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0x80); /* TMDS on chip */ 1352 xgifb_reg_and_or(pVBInfo->P3d4,
1353 0x38,
1354 ~0xE0,
1355 0x80); /* TMDS on chip */
1212 else 1356 else
1213 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* Only DVO on chip */ 1357 xgifb_reg_and_or(pVBInfo->P3d4,
1214 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20); /* Disable read GPIOF */ 1358 0x38,
1359 ~0xE0,
1360 0xA0); /* Only DVO on chip */
1361 /* Disable read GPIOF */
1362 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1215 } 1363 }
1216#if 1 1364#if 1
1217 } 1365 }
@@ -1225,16 +1373,19 @@ static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1225 1373
1226 pVBInfo->IF_DEF_LVDS = 0; 1374 pVBInfo->IF_DEF_LVDS = 0;
1227 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A); 1375 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1228 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07); /* Enable GPIOA/B/C read */ 1376 /* Enable GPIOA/B/C read */
1377 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1229 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07; 1378 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1230 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A); 1379 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1231 1380
1232 if (Temp <= 0x02) { 1381 if (Temp <= 0x02) {
1233 pVBInfo->IF_DEF_LVDS = 1; 1382 pVBInfo->IF_DEF_LVDS = 1;
1234 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS setting */ 1383 /* LVDS setting */
1384 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1235 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21); 1385 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1236 } else { 1386 } else {
1237 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* TMDS/DVO setting */ 1387 /* TMDS/DVO setting */
1388 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1238 } 1389 }
1239 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense); 1390 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1240 1391
@@ -1245,7 +1396,8 @@ static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1245 unsigned char CR38, CR4A, temp; 1396 unsigned char CR38, CR4A, temp;
1246 1397
1247 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A); 1398 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1248 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10); /* enable GPIOE read */ 1399 /* enable GPIOE read */
1400 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1249 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38); 1401 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1250 temp = 0; 1402 temp = 0;
1251 if ((CR38 & 0xE0) > 0x80) { 1403 if ((CR38 & 0xE0) > 0x80) {
@@ -1264,7 +1416,8 @@ static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1264 unsigned char CR4A, temp; 1416 unsigned char CR4A, temp;
1265 1417
1266 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A); 1418 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1267 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* enable GPIOA/B/C read */ 1419 /* enable GPIOA/B/C read */
1420 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1268 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48); 1421 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1269 if (temp <= 2) 1422 if (temp <= 2)
1270 temp &= 0x03; 1423 temp &= 0x03;
@@ -1344,7 +1497,8 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1344 printk("5"); 1497 printk("5");
1345 1498
1346 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */ 1499 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1347 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */ 1500 /* Run XGI_GetVBType before InitTo330Pointer */
1501 XGI_GetVBType(pVBInfo);
1348 1502
1349 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo); 1503 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1350 1504
@@ -1381,7 +1535,8 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1381 xgifb_reg_set(pVBInfo->P3c4, i, 0); 1535 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1382 printk("9"); 1536 printk("9");
1383 1537
1384 if (HwDeviceExtension->jChipType == XG42) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */ 1538 /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1539 if (HwDeviceExtension->jChipType == XG42)
1385 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0); 1540 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1386 1541
1387 /* for (i = 0x30; i <= 0x3F; i++) */ 1542 /* for (i = 0x30; i <= 0x3F; i++) */
@@ -1397,7 +1552,8 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1397 1552
1398 /* 3.SetMemoryClock 1553 /* 3.SetMemoryClock
1399 1554
1400 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo); 1555 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension,
1556 pVBInfo);
1401 */ 1557 */
1402 1558
1403 printk("11"); 1559 printk("11");
@@ -1411,8 +1567,10 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1411 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F); 1567 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1412 xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F); 1568 xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1413 /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */ 1569 /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1414 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */ 1570 /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1415 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70); /* Hsuan, 2006/01/01 H/W request for slow corner chip */ 1571 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1572 /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1573 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1416 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */ 1574 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1417 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36); 1575 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1418 1576
@@ -1441,14 +1599,24 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1441 1599
1442 ChipsetID &= 0x0000FFFF; 1600 ChipsetID &= 0x0000FFFF;
1443 1601
1444 if ((ChipsetID == 0x700E) || (ChipsetID == 0x1022) || (ChipsetID == 0x1106) || (ChipsetID == 0x10DE)) { 1602 if ((ChipsetID == 0x700E) ||
1603 (ChipsetID == 0x1022) ||
1604 (ChipsetID == 0x1106) ||
1605 (ChipsetID == 0x10DE)) {
1445 if (ChipsetID == 0x1106) { 1606 if (ChipsetID == 0x1106) {
1446 if ((VendorID == 0x1019) && (GraphicVendorID == 0x1019)) 1607 if ((VendorID == 0x1019) &&
1447 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x0D); 1608 (GraphicVendorID == 0x1019))
1609 xgifb_reg_set(pVBInfo->P3d4,
1610 0x5F,
1611 0x0D);
1448 else 1612 else
1449 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x0B); 1613 xgifb_reg_set(pVBInfo->P3d4,
1614 0x5F,
1615 0x0B);
1450 } else { 1616 } else {
1451 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x0B); 1617 xgifb_reg_set(pVBInfo->P3d4,
1618 0x5F,
1619 0x0B);
1452 } 1620 }
1453 } 1621 }
1454 } 1622 }
@@ -1458,13 +1626,19 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1458 1626
1459 /* Set AGP customize registers (in SetDefAGPRegs) Start */ 1627 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1460 for (i = 0x47; i <= 0x4C; i++) 1628 for (i = 0x47; i <= 0x4C; i++)
1461 xgifb_reg_set(pVBInfo->P3d4, i, pVBInfo->AGPReg[i - 0x47]); 1629 xgifb_reg_set(pVBInfo->P3d4,
1630 i,
1631 pVBInfo->AGPReg[i - 0x47]);
1462 1632
1463 for (i = 0x70; i <= 0x71; i++) 1633 for (i = 0x70; i <= 0x71; i++)
1464 xgifb_reg_set(pVBInfo->P3d4, i, pVBInfo->AGPReg[6 + i - 0x70]); 1634 xgifb_reg_set(pVBInfo->P3d4,
1635 i,
1636 pVBInfo->AGPReg[6 + i - 0x70]);
1465 1637
1466 for (i = 0x74; i <= 0x77; i++) 1638 for (i = 0x74; i <= 0x77; i++)
1467 xgifb_reg_set(pVBInfo->P3d4, i, pVBInfo->AGPReg[8 + i - 0x74]); 1639 xgifb_reg_set(pVBInfo->P3d4,
1640 i,
1641 pVBInfo->AGPReg[8 + i - 0x74]);
1468 /* Set AGP customize registers (in SetDefAGPRegs) End */ 1642 /* Set AGP customize registers (in SetDefAGPRegs) End */
1469 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */ 1643 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1470 /* outl(0x80000000, 0xcf8); */ 1644 /* outl(0x80000000, 0xcf8); */
@@ -1472,7 +1646,10 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1472 /* if (ChipsetID == 0x25308086) */ 1646 /* if (ChipsetID == 0x25308086) */
1473 /* xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */ 1647 /* xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1474 1648
1475 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x50, 0, &Temp); /* Get */ 1649 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension,
1650 0x50,
1651 0,
1652 &Temp); /* Get */
1476 Temp >>= 20; 1653 Temp >>= 20;
1477 Temp &= 0xF; 1654 Temp &= 0xF;
1478 1655
@@ -1490,12 +1667,16 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1490 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */ 1667 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1491 /* Set VB */ 1668 /* Set VB */
1492 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo); 1669 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1493 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); /* alan, disable VideoCapture */ 1670 /* alan, disable VideoCapture */
1671 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1494 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00); 1672 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1495 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */ 1673 /* chk if BCLK>=100MHz */
1674 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1496 temp = (unsigned char) ((temp1 >> 4) & 0x0F); 1675 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1497 1676
1498 xgifb_reg_set(pVBInfo->Part1Port, 0x02, (*pVBInfo->pCRT2Data_1_2)); 1677 xgifb_reg_set(pVBInfo->Part1Port,
1678 0x02,
1679 (*pVBInfo->pCRT2Data_1_2));
1499 1680
1500 printk("16"); 1681 printk("16");
1501 1682
@@ -1504,10 +1685,15 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1504 1685
1505 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F); 1686 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1506 1687
1507 if ((HwDeviceExtension->jChipType == XG42) 1688 if ((HwDeviceExtension->jChipType == XG42) &&
1508 && XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) { /* Not DDR */ 1689 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1509 xgifb_reg_set(pVBInfo->P3c4, 0x31, (*pVBInfo->pSR31 & 0x3F) | 0x40); 1690 /* Not DDR */
1510 xgifb_reg_set(pVBInfo->P3c4, 0x32, (*pVBInfo->pSR32 & 0xFC) | 0x01); 1691 xgifb_reg_set(pVBInfo->P3c4,
1692 0x31,
1693 (*pVBInfo->pSR31 & 0x3F) | 0x40);
1694 xgifb_reg_set(pVBInfo->P3c4,
1695 0x32,
1696 (*pVBInfo->pSR32 & 0xFC) | 0x01);
1511 } else { 1697 } else {
1512 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31); 1698 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1513 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32); 1699 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
@@ -1522,9 +1708,15 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1522 if (XGI_BridgeIsOn(pVBInfo) == 1) { 1708 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1523 if (pVBInfo->IF_DEF_LVDS == 0) { 1709 if (pVBInfo->IF_DEF_LVDS == 0) {
1524 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C); 1710 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1525 xgifb_reg_set(pVBInfo->Part4Port, 0x0D, *pVBInfo->pCRT2Data_4_D); 1711 xgifb_reg_set(pVBInfo->Part4Port,
1526 xgifb_reg_set(pVBInfo->Part4Port, 0x0E, *pVBInfo->pCRT2Data_4_E); 1712 0x0D,
1527 xgifb_reg_set(pVBInfo->Part4Port, 0x10, *pVBInfo->pCRT2Data_4_10); 1713 *pVBInfo->pCRT2Data_4_D);
1714 xgifb_reg_set(pVBInfo->Part4Port,
1715 0x0E,
1716 *pVBInfo->pCRT2Data_4_E);
1717 xgifb_reg_set(pVBInfo->Part4Port,
1718 0x10,
1719 *pVBInfo->pCRT2Data_4_10);
1528 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F); 1720 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1529 } 1721 }
1530 1722
@@ -1542,31 +1734,42 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1542 printk("183"); 1734 printk("183");
1543 /* XGINew_DetectMonitor(HwDeviceExtension); */ 1735 /* XGINew_DetectMonitor(HwDeviceExtension); */
1544 pVBInfo->IF_DEF_CH7007 = 0; 1736 pVBInfo->IF_DEF_CH7007 = 0;
1545 if ((HwDeviceExtension->jChipType == XG21) && (pVBInfo->IF_DEF_CH7007)) { 1737 if ((HwDeviceExtension->jChipType == XG21) &&
1738 (pVBInfo->IF_DEF_CH7007)) {
1546 printk("184"); 1739 printk("184");
1547 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo); /* sense CRT2 */ 1740 /* sense CRT2 */
1741 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo);
1548 printk("185"); 1742 printk("185");
1549 1743
1550 } 1744 }
1551 if (HwDeviceExtension->jChipType == XG21) { 1745 if (HwDeviceExtension->jChipType == XG21) {
1552 printk("186"); 1746 printk("186");
1553 1747
1554 xgifb_reg_and_or(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */ 1748 xgifb_reg_and_or(pVBInfo->P3d4,
1749 0x32,
1750 ~Monitor1Sense,
1751 Monitor1Sense); /* Z9 default has CRT */
1555 temp = GetXG21FPBits(pVBInfo); 1752 temp = GetXG21FPBits(pVBInfo);
1556 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp); 1753 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1557 printk("187"); 1754 printk("187");
1558 1755
1559 } 1756 }
1560 if (HwDeviceExtension->jChipType == XG27) { 1757 if (HwDeviceExtension->jChipType == XG27) {
1561 xgifb_reg_and_or(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */ 1758 xgifb_reg_and_or(pVBInfo->P3d4,
1759 0x32,
1760 ~Monitor1Sense,
1761 Monitor1Sense); /* Z9 default has CRT */
1562 temp = GetXG27FPBits(pVBInfo); 1762 temp = GetXG27FPBits(pVBInfo);
1563 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp); 1763 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1564 } 1764 }
1565 printk("19"); 1765 printk("19");
1566 1766
1567 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo); 1767 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
1768 pVBInfo);
1568 1769
1569 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension, pVBInfo->P3d4, pVBInfo); 1770 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1771 pVBInfo->P3d4,
1772 pVBInfo);
1570 1773
1571 printk("20"); 1774 printk("20");
1572 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo); 1775 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
@@ -1594,7 +1797,9 @@ unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1594 /* OutPortLong(0xcf8, base); */ 1797 /* OutPortLong(0xcf8, base); */
1595 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */ 1798 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1596 /* if (Temp == 0x1039) { */ 1799 /* if (Temp == 0x1039) { */
1597 xgifb_reg_set(pVBInfo->P3c4, 0x22, (unsigned char) ((*pVBInfo->pSR22) & 0xFE)); 1800 xgifb_reg_set(pVBInfo->P3c4,
1801 0x22,
1802 (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1598 /* } else { */ 1803 /* } else { */
1599 /* xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */ 1804 /* xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1600 /* } */ 1805 /* } */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 01:40:44 -0400