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authorTimofey Trofimov <tumoxep@gmail.com>2010-05-25 10:19:54 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-06-18 13:01:31 -0400
commit3a4d1b9096cce99f3dd8870cc87980dcabf6787e (patch)
tree832be09b6e0e48135692e228015d6283c5133f1a /drivers/staging/winbond
parent07bbf350483e75823ff9c21d213d63a8bbf751ca (diff)
Staging: winbond: fix some checkpatch.pl issues in phy_calibration.c
This is a patch to the phy_calibration.c that fixes up almost all warnings and errors (except 80 characters limit and lack of tabs errors) found by the checkpatch.pl tool Signed-off-by: Timofey Trofimov <tumoxep@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/winbond')
-rw-r--r--drivers/staging/winbond/phy_calibration.c835
1 files changed, 345 insertions, 490 deletions
diff --git a/drivers/staging/winbond/phy_calibration.c b/drivers/staging/winbond/phy_calibration.c
index 78935865df1..5eefea31948 100644
--- a/drivers/staging/winbond/phy_calibration.c
+++ b/drivers/staging/winbond/phy_calibration.c
@@ -19,23 +19,25 @@
19 19
20/****************** LOCAL CONSTANT AND MACRO SECTION ************************/ 20/****************** LOCAL CONSTANT AND MACRO SECTION ************************/
21#define LOOP_TIMES 20 21#define LOOP_TIMES 20
22#define US 1000//MICROSECOND 22#define US 1000/* MICROSECOND*/
23 23
24#define AG_CONST 0.6072529350 24#define AG_CONST 0.6072529350
25#define FIXED(X) ((s32)((X) * 32768.0)) 25#define FIXED(X) ((s32)((X) * 32768.0))
26#define DEG2RAD(X) 0.017453 * (X) 26#define DEG2RAD(X) 0.017453 * (X)
27 27
28static const s32 Angles[] = 28static const s32 Angles[] = {
29{ 29 FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)),
30 FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)), 30 FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)),
31 FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)), 31 FIXED(DEG2RAD(0.895174)), FIXED(DEG2RAD(0.447614)), FIXED(DEG2RAD(0.223811)),
32 FIXED(DEG2RAD(0.895174)),FIXED(DEG2RAD(0.447614)),FIXED(DEG2RAD(0.223811)), 32 FIXED(DEG2RAD(0.111906)), FIXED(DEG2RAD(0.055953)), FIXED(DEG2RAD(0.027977))
33 FIXED(DEG2RAD(0.111906)),FIXED(DEG2RAD(0.055953)),FIXED(DEG2RAD(0.027977))
34}; 33};
35 34
36/****************** LOCAL FUNCTION DECLARATION SECTION **********************/ 35/****************** LOCAL FUNCTION DECLARATION SECTION **********************
37//void _phy_rf_write_delay(struct hw_data *phw_data); 36
38//void phy_init_rf(struct hw_data *phw_data); 37/*
38 * void _phy_rf_write_delay(struct hw_data *phw_data);
39 * void phy_init_rf(struct hw_data *phw_data);
40 */
39 41
40/****************** FUNCTION DEFINITION SECTION *****************************/ 42/****************** FUNCTION DEFINITION SECTION *****************************/
41 43
@@ -46,9 +48,7 @@ s32 _s13_to_s32(u32 data)
46 val = (data & 0x0FFF); 48 val = (data & 0x0FFF);
47 49
48 if ((data & BIT(12)) != 0) 50 if ((data & BIT(12)) != 0)
49 {
50 val |= 0xFFFFF000; 51 val |= 0xFFFFF000;
51 }
52 52
53 return ((s32) val); 53 return ((s32) val);
54} 54}
@@ -58,13 +58,9 @@ u32 _s32_to_s13(s32 data)
58 u32 val; 58 u32 val;
59 59
60 if (data > 4095) 60 if (data > 4095)
61 {
62 data = 4095; 61 data = 4095;
63 }
64 else if (data < -4096) 62 else if (data < -4096)
65 {
66 data = -4096; 63 data = -4096;
67 }
68 64
69 val = data & 0x1FFF; 65 val = data & 0x1FFF;
70 66
@@ -79,9 +75,7 @@ s32 _s4_to_s32(u32 data)
79 val = (data & 0x0007); 75 val = (data & 0x0007);
80 76
81 if ((data & BIT(3)) != 0) 77 if ((data & BIT(3)) != 0)
82 {
83 val |= 0xFFFFFFF8; 78 val |= 0xFFFFFFF8;
84 }
85 79
86 return val; 80 return val;
87} 81}
@@ -91,13 +85,9 @@ u32 _s32_to_s4(s32 data)
91 u32 val; 85 u32 val;
92 86
93 if (data > 7) 87 if (data > 7)
94 {
95 data = 7; 88 data = 7;
96 }
97 else if (data < -8) 89 else if (data < -8)
98 {
99 data = -8; 90 data = -8;
100 }
101 91
102 val = data & 0x000F; 92 val = data & 0x000F;
103 93
@@ -112,9 +102,7 @@ s32 _s5_to_s32(u32 data)
112 val = (data & 0x000F); 102 val = (data & 0x000F);
113 103
114 if ((data & BIT(4)) != 0) 104 if ((data & BIT(4)) != 0)
115 {
116 val |= 0xFFFFFFF0; 105 val |= 0xFFFFFFF0;
117 }
118 106
119 return val; 107 return val;
120} 108}
@@ -124,13 +112,9 @@ u32 _s32_to_s5(s32 data)
124 u32 val; 112 u32 val;
125 113
126 if (data > 15) 114 if (data > 15)
127 {
128 data = 15; 115 data = 15;
129 }
130 else if (data < -16) 116 else if (data < -16)
131 {
132 data = -16; 117 data = -16;
133 }
134 118
135 val = data & 0x001F; 119 val = data & 0x001F;
136 120
@@ -145,9 +129,7 @@ s32 _s6_to_s32(u32 data)
145 val = (data & 0x001F); 129 val = (data & 0x001F);
146 130
147 if ((data & BIT(5)) != 0) 131 if ((data & BIT(5)) != 0)
148 {
149 val |= 0xFFFFFFE0; 132 val |= 0xFFFFFFE0;
150 }
151 133
152 return val; 134 return val;
153} 135}
@@ -157,11 +139,8 @@ u32 _s32_to_s6(s32 data)
157 u32 val; 139 u32 val;
158 140
159 if (data > 31) 141 if (data > 31)
160 {
161 data = 31; 142 data = 31;
162 }
163 else if (data < -32) 143 else if (data < -32)
164 {
165 data = -32; 144 data = -32;
166 } 145 }
167 146
@@ -178,9 +157,7 @@ s32 _s9_to_s32(u32 data)
178 val = data & 0x00FF; 157 val = data & 0x00FF;
179 158
180 if ((data & BIT(8)) != 0) 159 if ((data & BIT(8)) != 0)
181 {
182 val |= 0xFFFFFF00; 160 val |= 0xFFFFFF00;
183 }
184 161
185 return val; 162 return val;
186} 163}
@@ -190,13 +167,9 @@ u32 _s32_to_s9(s32 data)
190 u32 val; 167 u32 val;
191 168
192 if (data > 255) 169 if (data > 255)
193 {
194 data = 255; 170 data = 255;
195 }
196 else if (data < -256) 171 else if (data < -256)
197 {
198 data = -256; 172 data = -256;
199 }
200 173
201 val = data & 0x01FF; 174 val = data & 0x01FF;
202 175
@@ -207,21 +180,19 @@ u32 _s32_to_s9(s32 data)
207s32 _floor(s32 n) 180s32 _floor(s32 n)
208{ 181{
209 if (n > 0) 182 if (n > 0)
210 { 183 n += 5;
211 n += 5;
212 }
213 else 184 else
214 {
215 n -= 5; 185 n -= 5;
216 }
217 186
218 return (n/10); 187 return (n/10);
219} 188}
220 189
221/****************************************************************************/ 190/****************************************************************************/
222// The following code is sqare-root function. 191/*
223// sqsum is the input and the output is sq_rt; 192 * The following code is sqare-root function.
224// The maximum of sqsum = 2^27 -1; 193 * sqsum is the input and the output is sq_rt;
194 * The maximum of sqsum = 2^27 -1;
195 */
225u32 _sqrt(u32 sqsum) 196u32 _sqrt(u32 sqsum)
226{ 197{
227 u32 sq_rt; 198 u32 sq_rt;
@@ -232,18 +203,17 @@ u32 _sqrt(u32 sqsum)
232 int step; 203 int step;
233 204
234 g4 = sqsum / 100000000; 205 g4 = sqsum / 100000000;
235 g3 = (sqsum - g4*100000000) /1000000; 206 g3 = (sqsum - g4*100000000) / 1000000;
236 g2 = (sqsum - g4*100000000 - g3*1000000) /10000; 207 g2 = (sqsum - g4*100000000 - g3*1000000) / 10000;
237 g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) /100; 208 g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) / 100;
238 g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100); 209 g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100);
239 210
240 next = g4; 211 next = g4;
241 step = 0; 212 step = 0;
242 seed = 0; 213 seed = 0;
243 while (((seed+1)*(step+1)) <= next) 214 while (((seed+1)*(step+1)) <= next) {
244 { 215 step++;
245 step++; 216 seed++;
246 seed++;
247 } 217 }
248 218
249 sq_rt = seed * 10000; 219 sq_rt = seed * 10000;
@@ -251,20 +221,18 @@ u32 _sqrt(u32 sqsum)
251 221
252 step = 0; 222 step = 0;
253 seed = 2 * seed * 10; 223 seed = 2 * seed * 10;
254 while (((seed+1)*(step+1)) <= next) 224 while (((seed+1)*(step+1)) <= next) {
255 {
256 step++; 225 step++;
257 seed++; 226 seed++;
258 } 227 }
259 228
260 sq_rt = sq_rt + step * 1000; 229 sq_rt = sq_rt + step * 1000;
261 next = (next - seed * step) * 100 + g2; 230 next = (next - seed * step) * 100 + g2;
262 seed = (seed + step) * 10; 231 seed = (seed + step) * 10;
263 step = 0; 232 step = 0;
264 while (((seed+1)*(step+1)) <= next) 233 while (((seed+1)*(step+1)) <= next) {
265 {
266 step++; 234 step++;
267 seed++; 235 seed++;
268 } 236 }
269 237
270 sq_rt = sq_rt + step * 100; 238 sq_rt = sq_rt + step * 100;
@@ -272,21 +240,19 @@ u32 _sqrt(u32 sqsum)
272 seed = (seed + step) * 10; 240 seed = (seed + step) * 10;
273 step = 0; 241 step = 0;
274 242
275 while (((seed+1)*(step+1)) <= next) 243 while (((seed+1)*(step+1)) <= next) {
276 {
277 step++; 244 step++;
278 seed++; 245 seed++;
279 } 246 }
280 247
281 sq_rt = sq_rt + step * 10; 248 sq_rt = sq_rt + step * 10;
282 next = (next - seed* step) * 100 + g0; 249 next = (next - seed * step) * 100 + g0;
283 seed = (seed + step) * 10; 250 seed = (seed + step) * 10;
284 step = 0; 251 step = 0;
285 252
286 while (((seed+1)*(step+1)) <= next) 253 while (((seed+1)*(step+1)) <= next) {
287 {
288 step++; 254 step++;
289 seed++; 255 seed++;
290 } 256 }
291 257
292 sq_rt = sq_rt + step; 258 sq_rt = sq_rt + step;
@@ -300,38 +266,31 @@ void _sin_cos(s32 angle, s32 *sin, s32 *cos)
300 s32 X, Y, TargetAngle, CurrAngle; 266 s32 X, Y, TargetAngle, CurrAngle;
301 unsigned Step; 267 unsigned Step;
302 268
303 X=FIXED(AG_CONST); // AG_CONST * cos(0) 269 X = FIXED(AG_CONST); /* AG_CONST * cos(0) */
304 Y=0; // AG_CONST * sin(0) 270 Y = 0; /* AG_CONST * sin(0) */
305 TargetAngle=abs(angle); 271 TargetAngle = abs(angle);
306 CurrAngle=0; 272 CurrAngle = 0;
307 273
308 for (Step=0; Step < 12; Step++) 274 for (Step = 0; Step < 12; Step++) {
309 {
310 s32 NewX; 275 s32 NewX;
311 276
312 if(TargetAngle > CurrAngle) 277 if (TargetAngle > CurrAngle) {
313 { 278 NewX = X - (Y >> Step);
314 NewX=X - (Y >> Step); 279 Y = (X >> Step) + Y;
315 Y=(X >> Step) + Y; 280 X = NewX;
316 X=NewX;
317 CurrAngle += Angles[Step]; 281 CurrAngle += Angles[Step];
318 } 282 } else {
319 else 283 NewX = X + (Y >> Step);
320 { 284 Y = -(X >> Step) + Y;
321 NewX=X + (Y >> Step); 285 X = NewX;
322 Y=-(X >> Step) + Y;
323 X=NewX;
324 CurrAngle -= Angles[Step]; 286 CurrAngle -= Angles[Step];
325 } 287 }
326 } 288 }
327 289
328 if (angle > 0) 290 if (angle > 0) {
329 {
330 *cos = X; 291 *cos = X;
331 *sin = Y; 292 *sin = Y;
332 } 293 } else {
333 else
334 {
335 *cos = X; 294 *cos = X;
336 *sin = -Y; 295 *sin = -Y;
337 } 296 }
@@ -343,7 +302,7 @@ static unsigned char hal_get_dxx_reg(struct hw_data *pHwData, u16 number, u32 *
343 number += 0x1000; 302 number += 0x1000;
344 return Wb35Reg_ReadSync(pHwData, number, pValue); 303 return Wb35Reg_ReadSync(pHwData, number, pValue);
345} 304}
346#define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (u32 *)_C ) 305#define hw_get_dxx_reg(_A, _B, _C) hal_get_dxx_reg(_A, _B, (u32 *)_C)
347 306
348static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, u32 value) 307static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, u32 value)
349{ 308{
@@ -354,7 +313,7 @@ static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, u32 va
354 ret = Wb35Reg_WriteSync(pHwData, number, value); 313 ret = Wb35Reg_WriteSync(pHwData, number, value);
355 return ret; 314 return ret;
356} 315}
357#define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C ) 316#define hw_set_dxx_reg(_A, _B, _C) hal_set_dxx_reg(_A, _B, (u32)_C)
358 317
359 318
360void _reset_rx_cal(struct hw_data *phw_data) 319void _reset_rx_cal(struct hw_data *phw_data)
@@ -363,25 +322,20 @@ void _reset_rx_cal(struct hw_data *phw_data)
363 322
364 hw_get_dxx_reg(phw_data, 0x54, &val); 323 hw_get_dxx_reg(phw_data, 0x54, &val);
365 324
366 if (phw_data->revision == 0x2002) // 1st-cut 325 if (phw_data->revision == 0x2002) /* 1st-cut */
367 {
368 val &= 0xFFFF0000; 326 val &= 0xFFFF0000;
369 } 327 else /* 2nd-cut */
370 else // 2nd-cut
371 {
372 val &= 0x000003FF; 328 val &= 0x000003FF;
373 }
374 329
375 hw_set_dxx_reg(phw_data, 0x54, val); 330 hw_set_dxx_reg(phw_data, 0x54, val);
376} 331}
377 332
378 333
379// ************for winbond calibration********* 334/**************for winbond calibration*********/
380// 335
336
381 337
382// 338/**********************************************/
383//
384// *********************************************
385void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency) 339void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency)
386{ 340{
387 u32 reg_agc_ctrl3; 341 u32 reg_agc_ctrl3;
@@ -392,35 +346,31 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
392 PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n")); 346 PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n"));
393 phy_init_rf(phw_data); 347 phy_init_rf(phw_data);
394 348
395 // set calibration channel 349 /* set calibration channel */
396 if( (RF_WB_242 == phw_data->phy_type) || 350 if ((RF_WB_242 == phw_data->phy_type) ||
397 (RF_WB_242_1 == phw_data->phy_type) ) // 20060619.5 Add 351 (RF_WB_242_1 == phw_data->phy_type)) /* 20060619.5 Add */{
398 { 352 if ((frequency >= 2412) && (frequency <= 2484)) {
399 if ((frequency >= 2412) && (frequency <= 2484)) 353 /* w89rf242 change frequency to 2390Mhz */
400 {
401 // w89rf242 change frequency to 2390Mhz
402 PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n")); 354 PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n"));
403 phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); 355 phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
404 356
405 } 357 }
406 } 358 } else {
407 else
408 {
409 359
410 } 360 }
411 361
412 // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel 362 /* reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel */
413 hw_get_dxx_reg(phw_data, 0x5C, &val); 363 hw_get_dxx_reg(phw_data, 0x5C, &val);
414 val &= ~(0x03FF); 364 val &= ~(0x03FF);
415 hw_set_dxx_reg(phw_data, 0x5C, val); 365 hw_set_dxx_reg(phw_data, 0x5C, val);
416 366
417 // reset the TX and RX IQ calibration data 367 /* reset the TX and RX IQ calibration data */
418 hw_set_dxx_reg(phw_data, 0x3C, 0); 368 hw_set_dxx_reg(phw_data, 0x3C, 0);
419 hw_set_dxx_reg(phw_data, 0x54, 0); 369 hw_set_dxx_reg(phw_data, 0x54, 0);
420 370
421 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed 371 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
422 372
423 // a. Disable AGC 373 /* a. Disable AGC */
424 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 374 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
425 reg_agc_ctrl3 &= ~BIT(2); 375 reg_agc_ctrl3 &= ~BIT(2);
426 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 376 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
@@ -430,7 +380,7 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
430 val |= MASK_AGC_FIX_GAIN; 380 val |= MASK_AGC_FIX_GAIN;
431 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 381 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
432 382
433 // b. Turn off BB RX 383 /* b. Turn off BB RX */
434 hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl); 384 hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl);
435 reg_a_acq_ctrl |= MASK_AMER_OFF_REG; 385 reg_a_acq_ctrl |= MASK_AMER_OFF_REG;
436 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl); 386 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
@@ -439,9 +389,9 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
439 reg_b_acq_ctrl |= MASK_BMER_OFF_REG; 389 reg_b_acq_ctrl |= MASK_BMER_OFF_REG;
440 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl); 390 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
441 391
442 // c. Make sure MAC is in receiving mode 392 /* c. Make sure MAC is in receiving mode
443 // d. Turn ON ADC calibration 393 * d. Turn ON ADC calibration
444 // - ADC calibrator is triggered by this signal rising from 0 to 1 394 * - ADC calibrator is triggered by this signal rising from 0 to 1 */
445 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); 395 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
446 val &= ~MASK_ADC_DC_CAL_STR; 396 val &= ~MASK_ADC_DC_CAL_STR;
447 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); 397 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
@@ -449,7 +399,7 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
449 val |= MASK_ADC_DC_CAL_STR; 399 val |= MASK_ADC_DC_CAL_STR;
450 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); 400 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
451 401
452 // e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]" 402 /* e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]" */
453#ifdef _DEBUG 403#ifdef _DEBUG
454 hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val); 404 hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val);
455 PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val)); 405 PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val));
@@ -464,23 +414,23 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
464 val &= ~MASK_ADC_DC_CAL_STR; 414 val &= ~MASK_ADC_DC_CAL_STR;
465 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); 415 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
466 416
467 // f. Turn on BB RX 417 /* f. Turn on BB RX */
468 //hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl); 418 /* hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl); */
469 reg_a_acq_ctrl &= ~MASK_AMER_OFF_REG; 419 reg_a_acq_ctrl &= ~MASK_AMER_OFF_REG;
470 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl); 420 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
471 421
472 //hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl); 422 /* hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl); */
473 reg_b_acq_ctrl &= ~MASK_BMER_OFF_REG; 423 reg_b_acq_ctrl &= ~MASK_BMER_OFF_REG;
474 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl); 424 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
475 425
476 // g. Enable AGC 426 /* g. Enable AGC */
477 //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); 427 /* hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); */
478 reg_agc_ctrl3 |= BIT(2); 428 reg_agc_ctrl3 |= BIT(2);
479 reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 429 reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
480 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 430 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
481} 431}
482 432
483//////////////////////////////////////////////////////// 433/****************************************************************/
484void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data) 434void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
485{ 435{
486 u32 reg_agc_ctrl3; 436 u32 reg_agc_ctrl3;
@@ -497,22 +447,22 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
497 447
498 PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n")); 448 PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n"));
499 449
500 // a. Set to "TX calibration mode" 450 /* a. Set to "TX calibration mode" */
501 451
502 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits 452 /* 0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */
503 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); 453 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
504 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit 454 /* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */
505 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6); 455 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
506 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized 456 /* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
507 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A); 457 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
508 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized 458 /* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
509 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C); 459 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
510 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode 460 /* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
511 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); 461 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
512 462
513 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed 463 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
514 464
515 // a. Disable AGC 465 /* a. Disable AGC */
516 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 466 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
517 reg_agc_ctrl3 &= ~BIT(2); 467 reg_agc_ctrl3 &= ~BIT(2);
518 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 468 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
@@ -522,19 +472,19 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
522 val |= MASK_AGC_FIX_GAIN; 472 val |= MASK_AGC_FIX_GAIN;
523 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 473 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
524 474
525 // b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0 475 /* b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0 */
526 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 476 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
527 477
528 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 478 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
529 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 479 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
530 480
531 // mode=2, tone=0 481 /* mode=2, tone=0 */
532 //reg_mode_ctrl |= (MASK_CALIB_START|2); 482 /* reg_mode_ctrl |= (MASK_CALIB_START|2); */
533 483
534 // mode=2, tone=1 484 /* mode=2, tone=1 */
535 //reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2)); 485 /* reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2)); */
536 486
537 // mode=2, tone=2 487 /* mode=2, tone=2 */
538 reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2)); 488 reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2));
539 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 489 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
540 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 490 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
@@ -542,12 +492,10 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
542 hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel); 492 hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel);
543 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel)); 493 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
544 494
545 for (loop = 0; loop < LOOP_TIMES; loop++) 495 for (loop = 0; loop < LOOP_TIMES; loop++) {
546 {
547 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop)); 496 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
548 497
549 // c. 498 /* c. reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel */
550 // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
551 reg_dc_cancel &= ~(0x03FF); 499 reg_dc_cancel &= ~(0x03FF);
552 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 500 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
553 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 501 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
@@ -562,7 +510,7 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
562 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 510 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
563 mag_0, iqcal_image_i, iqcal_image_q)); 511 mag_0, iqcal_image_i, iqcal_image_q));
564 512
565 // d. 513 /* d. */
566 reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT); 514 reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT);
567 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 515 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
568 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 516 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
@@ -577,18 +525,12 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
577 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 525 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
578 mag_1, iqcal_image_i, iqcal_image_q)); 526 mag_1, iqcal_image_i, iqcal_image_q));
579 527
580 // e. Calculate the correct DC offset cancellation value for I 528 /* e. Calculate the correct DC offset cancellation value for I */
581 if (mag_0 != mag_1) 529 if (mag_0 != mag_1)
582 {
583 fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000); 530 fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
584 } 531 else {
585 else
586 {
587 if (mag_0 == mag_1) 532 if (mag_0 == mag_1)
588 {
589 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n")); 533 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
590 }
591
592 fix_cancel_dc_i = 0; 534 fix_cancel_dc_i = 0;
593 } 535 }
594 536
@@ -596,12 +538,10 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
596 fix_cancel_dc_i, _s32_to_s5(fix_cancel_dc_i))); 538 fix_cancel_dc_i, _s32_to_s5(fix_cancel_dc_i)));
597 539
598 if ((abs(mag_1-mag_0)*6) > mag_0) 540 if ((abs(mag_1-mag_0)*6) > mag_0)
599 {
600 break; 541 break;
601 }
602 } 542 }
603 543
604 if ( loop >= 19 ) 544 if (loop >= 19)
605 fix_cancel_dc_i = 0; 545 fix_cancel_dc_i = 0;
606 546
607 reg_dc_cancel &= ~(0x03FF); 547 reg_dc_cancel &= ~(0x03FF);
@@ -609,13 +549,13 @@ void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
609 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 549 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
610 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 550 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
611 551
612 // g. 552 /* g. */
613 reg_mode_ctrl &= ~MASK_CALIB_START; 553 reg_mode_ctrl &= ~MASK_CALIB_START;
614 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 554 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
615 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 555 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
616} 556}
617 557
618/////////////////////////////////////////////////////// 558/*****************************************************/
619void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data) 559void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
620{ 560{
621 u32 reg_agc_ctrl3; 561 u32 reg_agc_ctrl3;
@@ -631,20 +571,20 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
631 int loop; 571 int loop;
632 572
633 PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n")); 573 PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n"));
634 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits 574 /*0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */
635 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); 575 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
636 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit 576 /* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */
637 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6); 577 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
638 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized 578 /* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
639 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A); 579 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
640 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized 580 /* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
641 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C); 581 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
642 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode 582 /* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
643 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); 583 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
644 584
645 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed 585 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
646 586
647 // a. Disable AGC 587 /* a. Disable AGC */
648 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 588 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
649 reg_agc_ctrl3 &= ~BIT(2); 589 reg_agc_ctrl3 &= ~BIT(2);
650 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 590 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
@@ -654,11 +594,11 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
654 val |= MASK_AGC_FIX_GAIN; 594 val |= MASK_AGC_FIX_GAIN;
655 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 595 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
656 596
657 // a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0 597 /* a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0 */
658 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 598 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
659 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 599 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
660 600
661 //reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 601 /* reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); */
662 reg_mode_ctrl &= ~(MASK_IQCAL_MODE); 602 reg_mode_ctrl &= ~(MASK_IQCAL_MODE);
663 reg_mode_ctrl |= (MASK_CALIB_START|3); 603 reg_mode_ctrl |= (MASK_CALIB_START|3);
664 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 604 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
@@ -667,12 +607,10 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
667 hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel); 607 hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel);
668 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel)); 608 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
669 609
670 for (loop = 0; loop < LOOP_TIMES; loop++) 610 for (loop = 0; loop < LOOP_TIMES; loop++) {
671 {
672 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop)); 611 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
673 612
674 // b. 613 /* b. reset cancel_dc_q[4:0] in register DC_Cancel */
675 // reset cancel_dc_q[4:0] in register DC_Cancel
676 reg_dc_cancel &= ~(0x001F); 614 reg_dc_cancel &= ~(0x001F);
677 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 615 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
678 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 616 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
@@ -687,7 +625,7 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
687 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 625 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
688 mag_0, iqcal_image_i, iqcal_image_q)); 626 mag_0, iqcal_image_i, iqcal_image_q));
689 627
690 // c. 628 /* c. */
691 reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT); 629 reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT);
692 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 630 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
693 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 631 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
@@ -702,18 +640,12 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
702 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 640 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
703 mag_1, iqcal_image_i, iqcal_image_q)); 641 mag_1, iqcal_image_i, iqcal_image_q));
704 642
705 // d. Calculate the correct DC offset cancellation value for I 643 /* d. Calculate the correct DC offset cancellation value for I */
706 if (mag_0 != mag_1) 644 if (mag_0 != mag_1)
707 {
708 fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000); 645 fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
709 } 646 else {
710 else
711 {
712 if (mag_0 == mag_1) 647 if (mag_0 == mag_1)
713 {
714 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n")); 648 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
715 }
716
717 fix_cancel_dc_q = 0; 649 fix_cancel_dc_q = 0;
718 } 650 }
719 651
@@ -721,12 +653,10 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
721 fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q))); 653 fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q)));
722 654
723 if ((abs(mag_1-mag_0)*6) > mag_0) 655 if ((abs(mag_1-mag_0)*6) > mag_0)
724 {
725 break; 656 break;
726 }
727 } 657 }
728 658
729 if ( loop >= 19 ) 659 if (loop >= 19)
730 fix_cancel_dc_q = 0; 660 fix_cancel_dc_q = 0;
731 661
732 reg_dc_cancel &= ~(0x001F); 662 reg_dc_cancel &= ~(0x001F);
@@ -735,13 +665,13 @@ void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
735 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 665 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
736 666
737 667
738 // f. 668 /* f. */
739 reg_mode_ctrl &= ~MASK_CALIB_START; 669 reg_mode_ctrl &= ~MASK_CALIB_START;
740 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 670 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
741 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 671 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
742} 672}
743 673
744//20060612.1.a 20060718.1 Modify 674/* 20060612.1.a 20060718.1 Modify */
745u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data, 675u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
746 s32 a_2_threshold, 676 s32 a_2_threshold,
747 s32 b_2_threshold) 677 s32 b_2_threshold)
@@ -765,7 +695,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
765 s32 temp1, temp2; 695 s32 temp1, temp2;
766 u32 val; 696 u32 val;
767 u16 loop; 697 u16 loop;
768 s32 iqcal_tone_i_avg,iqcal_tone_q_avg; 698 s32 iqcal_tone_i_avg, iqcal_tone_q_avg;
769 u8 verify_count; 699 u8 verify_count;
770 int capture_time; 700 int capture_time;
771 701
@@ -780,18 +710,18 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
780 710
781 loop = LOOP_TIMES; 711 loop = LOOP_TIMES;
782 712
783 while (loop > 0) 713 while (loop > 0) {
784 {
785 PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1))); 714 PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
786 715
787 iqcal_tone_i_avg=0; 716 iqcal_tone_i_avg = 0;
788 iqcal_tone_q_avg=0; 717 iqcal_tone_q_avg = 0;
789 if( !hw_set_dxx_reg(phw_data, 0x3C, 0x00) ) // 20060718.1 modify 718 if (!hw_set_dxx_reg(phw_data, 0x3C, 0x00)) /* 20060718.1 modify */
790 return 0; 719 return 0;
791 for(capture_time=0;capture_time<10;capture_time++) 720 for (capture_time = 0; capture_time < 10; capture_time++) {
792 { 721 /*
793 // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to 722 * a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
794 // enable "IQ alibration Mode II" 723 * enable "IQ alibration Mode II"
724 */
795 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 725 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
796 reg_mode_ctrl &= ~MASK_IQCAL_MODE; 726 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
797 reg_mode_ctrl |= (MASK_CALIB_START|0x02); 727 reg_mode_ctrl |= (MASK_CALIB_START|0x02);
@@ -799,7 +729,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
799 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 729 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
800 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 730 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
801 731
802 // b. 732 /* b. */
803 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 733 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
804 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 734 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
805 735
@@ -813,21 +743,23 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
813 iq_mag_0_tx = (s32) _sqrt(sqsum); 743 iq_mag_0_tx = (s32) _sqrt(sqsum);
814 PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx)); 744 PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx));
815 745
816 // c. Set "calib_start" to 0x0 746 /* c. Set "calib_start" to 0x0 */
817 reg_mode_ctrl &= ~MASK_CALIB_START; 747 reg_mode_ctrl &= ~MASK_CALIB_START;
818 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 748 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
819 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 749 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
820 750
821 // d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to 751 /*
822 // enable "IQ alibration Mode II" 752 * d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to
823 //hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); 753 * enable "IQ alibration Mode II"
754 */
755 /* hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); */
824 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 756 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
825 reg_mode_ctrl &= ~MASK_IQCAL_MODE; 757 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
826 reg_mode_ctrl |= (MASK_CALIB_START|0x03); 758 reg_mode_ctrl |= (MASK_CALIB_START|0x03);
827 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 759 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
828 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 760 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
829 761
830 // e. 762 /* e. */
831 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 763 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
832 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 764 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
833 765
@@ -835,14 +767,11 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
835 iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13); 767 iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
836 PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n", 768 PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
837 iqcal_tone_i, iqcal_tone_q)); 769 iqcal_tone_i, iqcal_tone_q));
838 if( capture_time == 0) 770 if (capture_time == 0)
839 {
840 continue; 771 continue;
841 } 772 else {
842 else 773 iqcal_tone_i_avg = (iqcal_tone_i_avg*(capture_time-1) + iqcal_tone_i)/capture_time;
843 { 774 iqcal_tone_q_avg = (iqcal_tone_q_avg*(capture_time-1) + iqcal_tone_q)/capture_time;
844 iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time;
845 iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time;
846 } 775 }
847 } 776 }
848 777
@@ -857,11 +786,10 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
857 PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n", 786 PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n",
858 rot_i_b, rot_q_b)); 787 rot_i_b, rot_q_b));
859 788
860 // f. 789 /* f. */
861 divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2; 790 divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2;
862 791
863 if (divisor == 0) 792 if (divisor == 0) {
864 {
865 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n")); 793 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
866 PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n")); 794 PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n"));
867 PHY_DEBUG(("[CAL] ******************************************\n")); 795 PHY_DEBUG(("[CAL] ******************************************\n"));
@@ -876,18 +804,16 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
876 phw_data->iq_rsdl_gain_tx_d2 = a_2; 804 phw_data->iq_rsdl_gain_tx_d2 = a_2;
877 phw_data->iq_rsdl_phase_tx_d2 = b_2; 805 phw_data->iq_rsdl_phase_tx_d2 = b_2;
878 806
879 //if ((abs(a_2) < 150) && (abs(b_2) < 100)) 807 /* if ((abs(a_2) < 150) && (abs(b_2) < 100)) */
880 //if ((abs(a_2) < 200) && (abs(b_2) < 200)) 808 /* if ((abs(a_2) < 200) && (abs(b_2) < 200)) */
881 if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold)) 809 if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold)) {
882 {
883 verify_count++; 810 verify_count++;
884 811
885 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); 812 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
886 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count)); 813 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count));
887 PHY_DEBUG(("[CAL] ******************************************\n")); 814 PHY_DEBUG(("[CAL] ******************************************\n"));
888 815
889 if (verify_count > 2) 816 if (verify_count > 2) {
890 {
891 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); 817 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
892 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n")); 818 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n"));
893 PHY_DEBUG(("[CAL] **************************************\n")); 819 PHY_DEBUG(("[CAL] **************************************\n"));
@@ -895,37 +821,29 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
895 } 821 }
896 822
897 continue; 823 continue;
898 } 824 } else
899 else
900 {
901 verify_count = 0; 825 verify_count = 0;
902 }
903 826
904 _sin_cos(b_2, &sin_b, &cos_b); 827 _sin_cos(b_2, &sin_b, &cos_b);
905 _sin_cos(b_2*2, &sin_2b, &cos_2b); 828 _sin_cos(b_2*2, &sin_2b, &cos_2b);
906 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b)); 829 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b));
907 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b)); 830 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b));
908 831
909 if (cos_2b == 0) 832 if (cos_2b == 0) {
910 {
911 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n")); 833 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
912 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n")); 834 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
913 PHY_DEBUG(("[CAL] ******************************************\n")); 835 PHY_DEBUG(("[CAL] ******************************************\n"));
914 break; 836 break;
915 } 837 }
916 838
917 // 1280 * 32768 = 41943040 839 /* 1280 * 32768 = 41943040 */
918 temp1 = (41943040/cos_2b)*cos_b; 840 temp1 = (41943040/cos_2b)*cos_b;
919 841
920 //temp2 = (41943040/cos_2b)*sin_b*(-1); 842 /* temp2 = (41943040/cos_2b)*sin_b*(-1); */
921 if (phw_data->revision == 0x2002) // 1st-cut 843 if (phw_data->revision == 0x2002) /* 1st-cut */
922 {
923 temp2 = (41943040/cos_2b)*sin_b*(-1); 844 temp2 = (41943040/cos_2b)*sin_b*(-1);
924 } 845 else /* 2nd-cut */
925 else // 2nd-cut
926 {
927 temp2 = (41943040*4/cos_2b)*sin_b*(-1); 846 temp2 = (41943040*4/cos_2b)*sin_b*(-1);
928 }
929 847
930 tx_cal_flt_b[0] = _floor(temp1/(32768+a_2)); 848 tx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
931 tx_cal_flt_b[1] = _floor(temp2/(32768+a_2)); 849 tx_cal_flt_b[1] = _floor(temp2/(32768+a_2));
@@ -937,37 +855,34 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
937 PHY_DEBUG(("[CAL] tx_cal_flt_b[3] = %d\n", tx_cal_flt_b[3])); 855 PHY_DEBUG(("[CAL] tx_cal_flt_b[3] = %d\n", tx_cal_flt_b[3]));
938 856
939 tx_cal[2] = tx_cal_flt_b[2]; 857 tx_cal[2] = tx_cal_flt_b[2];
940 tx_cal[2] = tx_cal[2] +3; 858 tx_cal[2] = tx_cal[2] + 3;
941 tx_cal[1] = tx_cal[2]; 859 tx_cal[1] = tx_cal[2];
942 tx_cal[3] = tx_cal_flt_b[3] - 128; 860 tx_cal[3] = tx_cal_flt_b[3] - 128;
943 tx_cal[0] = -tx_cal[3]+1; 861 tx_cal[0] = -tx_cal[3] + 1;
944 862
945 PHY_DEBUG(("[CAL] tx_cal[0] = %d\n", tx_cal[0])); 863 PHY_DEBUG(("[CAL] tx_cal[0] = %d\n", tx_cal[0]));
946 PHY_DEBUG(("[CAL] tx_cal[1] = %d\n", tx_cal[1])); 864 PHY_DEBUG(("[CAL] tx_cal[1] = %d\n", tx_cal[1]));
947 PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal[2])); 865 PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal[2]));
948 PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal[3])); 866 PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal[3]));
949 867
950 //if ((tx_cal[0] == 0) && (tx_cal[1] == 0) && 868 /* if ((tx_cal[0] == 0) && (tx_cal[1] == 0) &&
951 // (tx_cal[2] == 0) && (tx_cal[3] == 0)) 869 (tx_cal[2] == 0) && (tx_cal[3] == 0))
952 //{ 870 { */
953 // PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); 871 /* PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
954 // PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n")); 872 * PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n"));
955 // PHY_DEBUG(("[CAL] ******************************************\n")); 873 * PHY_DEBUG(("[CAL] ******************************************\n"));
956 // return 0; 874 * return 0;
957 //} 875 } */
958 876
959 // g. 877 /* g. */
960 if (phw_data->revision == 0x2002) // 1st-cut 878 if (phw_data->revision == 0x2002) /* 1st-cut */{
961 {
962 hw_get_dxx_reg(phw_data, 0x54, &val); 879 hw_get_dxx_reg(phw_data, 0x54, &val);
963 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 880 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
964 tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28); 881 tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
965 tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24); 882 tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
966 tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20); 883 tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
967 tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16); 884 tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
968 } 885 } else /* 2nd-cut */{
969 else // 2nd-cut
970 {
971 hw_get_dxx_reg(phw_data, 0x3C, &val); 886 hw_get_dxx_reg(phw_data, 0x3C, &val);
972 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val)); 887 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
973 tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 888 tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
@@ -982,22 +897,17 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
982 PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2])); 897 PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2]));
983 PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3])); 898 PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3]));
984 899
985 if (phw_data->revision == 0x2002) // 1st-cut 900 if (phw_data->revision == 0x2002) /* 1st-cut */{
986 { 901 if (((tx_cal_reg[0] == 7) || (tx_cal_reg[0] == (-8))) &&
987 if (((tx_cal_reg[0]==7) || (tx_cal_reg[0]==(-8))) && 902 ((tx_cal_reg[3] == 7) || (tx_cal_reg[3] == (-8)))) {
988 ((tx_cal_reg[3]==7) || (tx_cal_reg[3]==(-8))))
989 {
990 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); 903 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
991 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n")); 904 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
992 PHY_DEBUG(("[CAL] **************************************\n")); 905 PHY_DEBUG(("[CAL] **************************************\n"));
993 break; 906 break;
994 } 907 }
995 } 908 } else /* 2nd-cut */{
996 else // 2nd-cut 909 if (((tx_cal_reg[0] == 31) || (tx_cal_reg[0] == (-32))) &&
997 { 910 ((tx_cal_reg[3] == 31) || (tx_cal_reg[3] == (-32)))) {
998 if (((tx_cal_reg[0]==31) || (tx_cal_reg[0]==(-32))) &&
999 ((tx_cal_reg[3]==31) || (tx_cal_reg[3]==(-32))))
1000 {
1001 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); 911 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
1002 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n")); 912 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
1003 PHY_DEBUG(("[CAL] **************************************\n")); 913 PHY_DEBUG(("[CAL] **************************************\n"));
@@ -1014,8 +924,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
1014 PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2])); 924 PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2]));
1015 PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3])); 925 PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3]));
1016 926
1017 if (phw_data->revision == 0x2002) // 1st-cut 927 if (phw_data->revision == 0x2002) /* 1st-cut */{
1018 {
1019 val &= 0x0000FFFF; 928 val &= 0x0000FFFF;
1020 val |= ((_s32_to_s4(tx_cal[0]) << 28)| 929 val |= ((_s32_to_s4(tx_cal[0]) << 28)|
1021 (_s32_to_s4(tx_cal[1]) << 24)| 930 (_s32_to_s4(tx_cal[1]) << 24)|
@@ -1024,9 +933,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
1024 hw_set_dxx_reg(phw_data, 0x54, val); 933 hw_set_dxx_reg(phw_data, 0x54, val);
1025 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val)); 934 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
1026 return 0; 935 return 0;
1027 } 936 } else /* 2nd-cut */{
1028 else // 2nd-cut
1029 {
1030 val &= 0x000003FF; 937 val &= 0x000003FF;
1031 val |= ((_s32_to_s5(tx_cal[0]) << 27)| 938 val |= ((_s32_to_s5(tx_cal[0]) << 27)|
1032 (_s32_to_s6(tx_cal[1]) << 21)| 939 (_s32_to_s6(tx_cal[1]) << 21)|
@@ -1037,7 +944,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
1037 return 0; 944 return 0;
1038 } 945 }
1039 946
1040 // i. Set "calib_start" to 0x0 947 /* i. Set "calib_start" to 0x0 */
1041 reg_mode_ctrl &= ~MASK_CALIB_START; 948 reg_mode_ctrl &= ~MASK_CALIB_START;
1042 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 949 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1043 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 950 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
@@ -1061,26 +968,26 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
1061 968
1062 PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n")); 969 PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n"));
1063 970
1064 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits 971 /* 0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */
1065 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); 972 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
1066 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit 973 /* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */
1067 phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); // 20060612.1.a 0x1905D6); 974 phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); /* 20060612.1.a 0x1905D6); */
1068 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized 975 /* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
1069 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); //0x24C60A (high temperature) 976 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); /* 0x24C60A (high temperature) */
1070 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized 977 /* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
1071 phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); // 20060612.1.a 0x06890C); 978 phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); /* 20060612.1.a 0x06890C); */
1072 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode 979 /* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
1073 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); 980 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
1074 //; [BB-chip]: Calibration (6f).Send test pattern 981 /* ; [BB-chip]: Calibration (6f).Send test pattern */
1075 //; [BB-chip]: Calibration (6g). Search RXGCL optimal value 982 /* ; [BB-chip]: Calibration (6g). Search RXGCL optimal value */
1076 //; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table 983 /* ; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table */
1077 //phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); 984 /* phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); */
1078 985
1079 msleep(30); // 20060612.1.a 30ms delay. Add the follow 2 lines 986 msleep(30); /* 20060612.1.a 30ms delay. Add the follow 2 lines */
1080 //To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750 987 /* To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750 */
1081 adjust_TXVGA_for_iq_mag( phw_data ); 988 adjust_TXVGA_for_iq_mag(phw_data);
1082 989
1083 // a. Disable AGC 990 /* a. Disable AGC */
1084 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 991 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
1085 reg_agc_ctrl3 &= ~BIT(2); 992 reg_agc_ctrl3 &= ~BIT(2);
1086 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 993 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
@@ -1092,16 +999,12 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
1092 999
1093 result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100); 1000 result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100);
1094 1001
1095 if (result > 0) 1002 if (result > 0) {
1096 { 1003 if (phw_data->revision == 0x2002) /* 1st-cut */{
1097 if (phw_data->revision == 0x2002) // 1st-cut
1098 {
1099 hw_get_dxx_reg(phw_data, 0x54, &val); 1004 hw_get_dxx_reg(phw_data, 0x54, &val);
1100 val &= 0x0000FFFF; 1005 val &= 0x0000FFFF;
1101 hw_set_dxx_reg(phw_data, 0x54, val); 1006 hw_set_dxx_reg(phw_data, 0x54, val);
1102 } 1007 } else /* 2nd-cut*/{
1103 else // 2nd-cut
1104 {
1105 hw_get_dxx_reg(phw_data, 0x3C, &val); 1008 hw_get_dxx_reg(phw_data, 0x3C, &val);
1106 val &= 0x000003FF; 1009 val &= 0x000003FF;
1107 hw_set_dxx_reg(phw_data, 0x3C, val); 1010 hw_set_dxx_reg(phw_data, 0x3C, val);
@@ -1109,32 +1012,24 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
1109 1012
1110 result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200); 1013 result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200);
1111 1014
1112 if (result > 0) 1015 if (result > 0) {
1113 { 1016 if (phw_data->revision == 0x2002) /* 1st-cut */{
1114 if (phw_data->revision == 0x2002) // 1st-cut
1115 {
1116 hw_get_dxx_reg(phw_data, 0x54, &val); 1017 hw_get_dxx_reg(phw_data, 0x54, &val);
1117 val &= 0x0000FFFF; 1018 val &= 0x0000FFFF;
1118 hw_set_dxx_reg(phw_data, 0x54, val); 1019 hw_set_dxx_reg(phw_data, 0x54, val);
1119 } 1020 } else /* 2nd-cut*/{
1120 else // 2nd-cut
1121 {
1122 hw_get_dxx_reg(phw_data, 0x3C, &val); 1021 hw_get_dxx_reg(phw_data, 0x3C, &val);
1123 val &= 0x000003FF; 1022 val &= 0x000003FF;
1124 hw_set_dxx_reg(phw_data, 0x3C, val); 1023 hw_set_dxx_reg(phw_data, 0x3C, val);
1125 } 1024 }
1126 1025
1127 result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400); 1026 result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400);
1128 if (result > 0) 1027 if (result > 0) {
1129 { 1028 if (phw_data->revision == 0x2002) /* 1st-cut */{
1130 if (phw_data->revision == 0x2002) // 1st-cut
1131 {
1132 hw_get_dxx_reg(phw_data, 0x54, &val); 1029 hw_get_dxx_reg(phw_data, 0x54, &val);
1133 val &= 0x0000FFFF; 1030 val &= 0x0000FFFF;
1134 hw_set_dxx_reg(phw_data, 0x54, val); 1031 hw_set_dxx_reg(phw_data, 0x54, val);
1135 } 1032 } else /* 2nd-cut */{
1136 else // 2nd-cut
1137 {
1138 hw_get_dxx_reg(phw_data, 0x3C, &val); 1033 hw_get_dxx_reg(phw_data, 0x3C, &val);
1139 val &= 0x000003FF; 1034 val &= 0x000003FF;
1140 hw_set_dxx_reg(phw_data, 0x3C, val); 1035 hw_set_dxx_reg(phw_data, 0x3C, val);
@@ -1143,20 +1038,16 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
1143 1038
1144 result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500); 1039 result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500);
1145 1040
1146 if (result > 0) 1041 if (result > 0) {
1147 {
1148 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n")); 1042 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n"));
1149 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n")); 1043 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n"));
1150 PHY_DEBUG(("[CAL] **************************************\n")); 1044 PHY_DEBUG(("[CAL] **************************************\n"));
1151 1045
1152 if (phw_data->revision == 0x2002) // 1st-cut 1046 if (phw_data->revision == 0x2002) /* 1st-cut */{
1153 {
1154 hw_get_dxx_reg(phw_data, 0x54, &val); 1047 hw_get_dxx_reg(phw_data, 0x54, &val);
1155 val &= 0x0000FFFF; 1048 val &= 0x0000FFFF;
1156 hw_set_dxx_reg(phw_data, 0x54, val); 1049 hw_set_dxx_reg(phw_data, 0x54, val);
1157 } 1050 } else /* 2nd-cut */{
1158 else // 2nd-cut
1159 {
1160 hw_get_dxx_reg(phw_data, 0x3C, &val); 1051 hw_get_dxx_reg(phw_data, 0x3C, &val);
1161 val &= 0x000003FF; 1052 val &= 0x000003FF;
1162 hw_set_dxx_reg(phw_data, 0x3C, val); 1053 hw_set_dxx_reg(phw_data, 0x3C, val);
@@ -1166,30 +1057,27 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
1166 } 1057 }
1167 } 1058 }
1168 1059
1169 // i. Set "calib_start" to 0x0 1060 /* i. Set "calib_start" to 0x0 */
1170 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 1061 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
1171 reg_mode_ctrl &= ~MASK_CALIB_START; 1062 reg_mode_ctrl &= ~MASK_CALIB_START;
1172 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1063 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1173 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1064 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1174 1065
1175 // g. Enable AGC 1066 /* g. Enable AGC */
1176 //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); 1067 /* hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); */
1177 reg_agc_ctrl3 |= BIT(2); 1068 reg_agc_ctrl3 |= BIT(2);
1178 reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 1069 reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
1179 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 1070 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
1180 1071
1181#ifdef _DEBUG 1072#ifdef _DEBUG
1182 if (phw_data->revision == 0x2002) // 1st-cut 1073 if (phw_data->revision == 0x2002) /* 1st-cut */{
1183 {
1184 hw_get_dxx_reg(phw_data, 0x54, &val); 1074 hw_get_dxx_reg(phw_data, 0x54, &val);
1185 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 1075 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
1186 tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28); 1076 tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
1187 tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24); 1077 tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
1188 tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20); 1078 tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
1189 tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16); 1079 tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
1190 } 1080 } else /* 2nd-cut */ {
1191 else // 2nd-cut
1192 {
1193 hw_get_dxx_reg(phw_data, 0x3C, &val); 1081 hw_get_dxx_reg(phw_data, 0x3C, &val);
1194 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val)); 1082 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
1195 tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 1083 tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
@@ -1206,11 +1094,13 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
1206#endif 1094#endif
1207 1095
1208 1096
1209 // for test - BEN 1097 /*
1210 // RF Control Override 1098 * for test - BEN
1099 * RF Control Override
1100 */
1211} 1101}
1212 1102
1213///////////////////////////////////////////////////////////////////////////////////////// 1103/*****************************************************/
1214u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency) 1104u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency)
1215{ 1105{
1216 u32 reg_mode_ctrl; 1106 u32 reg_mode_ctrl;
@@ -1236,51 +1126,49 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1236 u32 pwr_image; 1126 u32 pwr_image;
1237 u8 verify_count; 1127 u8 verify_count;
1238 1128
1239 s32 iqcal_tone_i_avg,iqcal_tone_q_avg; 1129 s32 iqcal_tone_i_avg, iqcal_tone_q_avg;
1240 s32 iqcal_image_i_avg,iqcal_image_q_avg; 1130 s32 iqcal_image_i_avg, iqcal_image_q_avg;
1241 u16 capture_time; 1131 u16 capture_time;
1242 1132
1243 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n")); 1133 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n"));
1244 PHY_DEBUG(("[CAL] ** factor = %d\n", factor)); 1134 PHY_DEBUG(("[CAL] ** factor = %d\n", factor));
1245 1135
1246 1136
1247// RF Control Override 1137/* RF Control Override */
1248 hw_get_cxx_reg(phw_data, 0x80, &val); 1138 hw_get_cxx_reg(phw_data, 0x80, &val);
1249 val |= BIT(19); 1139 val |= BIT(19);
1250 hw_set_cxx_reg(phw_data, 0x80, val); 1140 hw_set_cxx_reg(phw_data, 0x80, val);
1251 1141
1252// RF_Ctrl 1142/* RF_Ctrl */
1253 hw_get_cxx_reg(phw_data, 0xE4, &val); 1143 hw_get_cxx_reg(phw_data, 0xE4, &val);
1254 val |= BIT(0); 1144 val |= BIT(0);
1255 hw_set_cxx_reg(phw_data, 0xE4, val); 1145 hw_set_cxx_reg(phw_data, 0xE4, val);
1256 PHY_DEBUG(("[CAL] ** RF_CTRL(0xE4) = 0x%08X", val)); 1146 PHY_DEBUG(("[CAL] ** RF_CTRL(0xE4) = 0x%08X", val));
1257 1147
1258 hw_set_dxx_reg(phw_data, 0x58, 0x44444444); // IQ_Alpha 1148 hw_set_dxx_reg(phw_data, 0x58, 0x44444444); /* IQ_Alpha */
1259 1149
1260 // b. 1150 /* b. */
1261 1151
1262 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 1152 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
1263 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 1153 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
1264 1154
1265 verify_count = 0; 1155 verify_count = 0;
1266 1156
1267 //for (loop = 0; loop < 1; loop++) 1157 /* for (loop = 0; loop < 1; loop++) */
1268 //for (loop = 0; loop < LOOP_TIMES; loop++) 1158 /* for (loop = 0; loop < LOOP_TIMES; loop++) */
1269 loop = LOOP_TIMES; 1159 loop = LOOP_TIMES;
1270 while (loop > 0) 1160 while (loop > 0) {
1271 {
1272 PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1))); 1161 PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
1273 iqcal_tone_i_avg=0; 1162 iqcal_tone_i_avg = 0;
1274 iqcal_tone_q_avg=0; 1163 iqcal_tone_q_avg = 0;
1275 iqcal_image_i_avg=0; 1164 iqcal_image_i_avg = 0;
1276 iqcal_image_q_avg=0; 1165 iqcal_image_q_avg = 0;
1277 capture_time=0; 1166 capture_time = 0;
1278 1167
1279 for(capture_time=0; capture_time<10; capture_time++) 1168 for (capture_time = 0; capture_time < 10; capture_time++) {
1280 { 1169 /* i. Set "calib_start" to 0x0 */
1281 // i. Set "calib_start" to 0x0
1282 reg_mode_ctrl &= ~MASK_CALIB_START; 1170 reg_mode_ctrl &= ~MASK_CALIB_START;
1283 if( !hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl) )//20060718.1 modify 1171 if (!hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl))/*20060718.1 modify */
1284 return 0; 1172 return 0;
1285 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1173 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1286 1174
@@ -1289,7 +1177,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1289 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1177 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1290 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1178 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1291 1179
1292 // c. 1180 /* c. */
1293 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 1181 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
1294 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 1182 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
1295 1183
@@ -1305,16 +1193,13 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1305 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 1193 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
1306 PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n", 1194 PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n",
1307 iqcal_image_i, iqcal_image_q)); 1195 iqcal_image_i, iqcal_image_q));
1308 if( capture_time == 0) 1196 if (capture_time == 0)
1309 {
1310 continue; 1197 continue;
1311 } 1198 else {
1312 else 1199 iqcal_image_i_avg = (iqcal_image_i_avg*(capture_time-1) + iqcal_image_i)/capture_time;
1313 { 1200 iqcal_image_q_avg = (iqcal_image_q_avg*(capture_time-1) + iqcal_image_q)/capture_time;
1314 iqcal_image_i_avg=( iqcal_image_i_avg*(capture_time-1) +iqcal_image_i)/capture_time; 1201 iqcal_tone_i_avg = (iqcal_tone_i_avg*(capture_time-1) + iqcal_tone_i)/capture_time;
1315 iqcal_image_q_avg=( iqcal_image_q_avg*(capture_time-1) +iqcal_image_q)/capture_time; 1202 iqcal_tone_q_avg = (iqcal_tone_q_avg*(capture_time-1) + iqcal_tone_q)/capture_time;
1316 iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time;
1317 iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time;
1318 } 1203 }
1319 } 1204 }
1320 1205
@@ -1324,7 +1209,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1324 iqcal_tone_i = iqcal_tone_i_avg; 1209 iqcal_tone_i = iqcal_tone_i_avg;
1325 iqcal_tone_q = iqcal_tone_q_avg; 1210 iqcal_tone_q = iqcal_tone_q_avg;
1326 1211
1327 // d. 1212 /* d. */
1328 rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i + 1213 rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i +
1329 iqcal_tone_q * iqcal_tone_q) / 1024; 1214 iqcal_tone_q * iqcal_tone_q) / 1024;
1330 rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) + 1215 rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) +
@@ -1339,9 +1224,8 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1339 PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b)); 1224 PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b));
1340 PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b)); 1225 PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b));
1341 1226
1342 // f. 1227 /* f. */
1343 if (rot_tone_i_b == 0) 1228 if (rot_tone_i_b == 0) {
1344 {
1345 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n")); 1229 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
1346 PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n")); 1230 PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n"));
1347 PHY_DEBUG(("[CAL] ******************************************\n")); 1231 PHY_DEBUG(("[CAL] ******************************************\n"));
@@ -1363,26 +1247,21 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1363 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b)); 1247 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b));
1364 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b)); 1248 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b));
1365 1249
1366 if (cos_2b == 0) 1250 if (cos_2b == 0) {
1367 {
1368 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n")); 1251 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
1369 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n")); 1252 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
1370 PHY_DEBUG(("[CAL] ******************************************\n")); 1253 PHY_DEBUG(("[CAL] ******************************************\n"));
1371 break; 1254 break;
1372 } 1255 }
1373 1256
1374 // 1280 * 32768 = 41943040 1257 /* 1280 * 32768 = 41943040 */
1375 temp1 = (41943040/cos_2b)*cos_b; 1258 temp1 = (41943040/cos_2b)*cos_b;
1376 1259
1377 //temp2 = (41943040/cos_2b)*sin_b*(-1); 1260 /* temp2 = (41943040/cos_2b)*sin_b*(-1); */
1378 if (phw_data->revision == 0x2002) // 1st-cut 1261 if (phw_data->revision == 0x2002)/* 1st-cut */
1379 {
1380 temp2 = (41943040/cos_2b)*sin_b*(-1); 1262 temp2 = (41943040/cos_2b)*sin_b*(-1);
1381 } 1263 else/* 2nd-cut */
1382 else // 2nd-cut
1383 {
1384 temp2 = (41943040*4/cos_2b)*sin_b*(-1); 1264 temp2 = (41943040*4/cos_2b)*sin_b*(-1);
1385 }
1386 1265
1387 rx_cal_flt_b[0] = _floor(temp1/(32768+a_2)); 1266 rx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
1388 rx_cal_flt_b[1] = _floor(temp2/(32768-a_2)); 1267 rx_cal_flt_b[1] = _floor(temp2/(32768-a_2));
@@ -1403,23 +1282,21 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1403 PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal[2])); 1282 PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal[2]));
1404 PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal[3])); 1283 PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal[3]));
1405 1284
1406 // e. 1285 /* e. */
1407 pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q); 1286 pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q);
1408 pwr_image = (iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q)*factor; 1287 pwr_image = (iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q)*factor;
1409 1288
1410 PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone)); 1289 PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone));
1411 PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image)); 1290 PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image));
1412 1291
1413 if (pwr_tone > pwr_image) 1292 if (pwr_tone > pwr_image) {
1414 {
1415 verify_count++; 1293 verify_count++;
1416 1294
1417 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n")); 1295 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n"));
1418 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count)); 1296 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count));
1419 PHY_DEBUG(("[CAL] ******************************************\n")); 1297 PHY_DEBUG(("[CAL] ******************************************\n"));
1420 1298
1421 if (verify_count > 2) 1299 if (verify_count > 2) {
1422 {
1423 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); 1300 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1424 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n")); 1301 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n"));
1425 PHY_DEBUG(("[CAL] **************************************\n")); 1302 PHY_DEBUG(("[CAL] **************************************\n"));
@@ -1428,19 +1305,16 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1428 1305
1429 continue; 1306 continue;
1430 } 1307 }
1431 // g. 1308 /* g. */
1432 hw_get_dxx_reg(phw_data, 0x54, &val); 1309 hw_get_dxx_reg(phw_data, 0x54, &val);
1433 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 1310 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
1434 1311
1435 if (phw_data->revision == 0x2002) // 1st-cut 1312 if (phw_data->revision == 0x2002) /* 1st-cut */{
1436 {
1437 rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12); 1313 rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
1438 rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8); 1314 rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
1439 rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4); 1315 rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
1440 rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F)); 1316 rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
1441 } 1317 } else /* 2nd-cut */{
1442 else // 2nd-cut
1443 {
1444 rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 1318 rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
1445 rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); 1319 rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
1446 rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); 1320 rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
@@ -1452,22 +1326,17 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1452 PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2])); 1326 PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2]));
1453 PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3])); 1327 PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3]));
1454 1328
1455 if (phw_data->revision == 0x2002) // 1st-cut 1329 if (phw_data->revision == 0x2002) /* 1st-cut */{
1456 { 1330 if (((rx_cal_reg[0] == 7) || (rx_cal_reg[0] == (-8))) &&
1457 if (((rx_cal_reg[0]==7) || (rx_cal_reg[0]==(-8))) && 1331 ((rx_cal_reg[3] == 7) || (rx_cal_reg[3] == (-8)))) {
1458 ((rx_cal_reg[3]==7) || (rx_cal_reg[3]==(-8))))
1459 {
1460 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); 1332 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1461 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n")); 1333 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
1462 PHY_DEBUG(("[CAL] **************************************\n")); 1334 PHY_DEBUG(("[CAL] **************************************\n"));
1463 break; 1335 break;
1464 } 1336 }
1465 } 1337 } else /* 2nd-cut */{
1466 else // 2nd-cut 1338 if (((rx_cal_reg[0] == 31) || (rx_cal_reg[0] == (-32))) &&
1467 { 1339 ((rx_cal_reg[3] == 31) || (rx_cal_reg[3] == (-32)))) {
1468 if (((rx_cal_reg[0]==31) || (rx_cal_reg[0]==(-32))) &&
1469 ((rx_cal_reg[3]==31) || (rx_cal_reg[3]==(-32))))
1470 {
1471 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); 1340 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1472 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n")); 1341 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
1473 PHY_DEBUG(("[CAL] **************************************\n")); 1342 PHY_DEBUG(("[CAL] **************************************\n"));
@@ -1485,17 +1354,14 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1485 PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3])); 1354 PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3]));
1486 1355
1487 hw_get_dxx_reg(phw_data, 0x54, &val); 1356 hw_get_dxx_reg(phw_data, 0x54, &val);
1488 if (phw_data->revision == 0x2002) // 1st-cut 1357 if (phw_data->revision == 0x2002) /* 1st-cut */{
1489 {
1490 val &= 0x0000FFFF; 1358 val &= 0x0000FFFF;
1491 val |= ((_s32_to_s4(rx_cal[0]) << 12)| 1359 val |= ((_s32_to_s4(rx_cal[0]) << 12)|
1492 (_s32_to_s4(rx_cal[1]) << 8)| 1360 (_s32_to_s4(rx_cal[1]) << 8)|
1493 (_s32_to_s4(rx_cal[2]) << 4)| 1361 (_s32_to_s4(rx_cal[2]) << 4)|
1494 (_s32_to_s4(rx_cal[3]))); 1362 (_s32_to_s4(rx_cal[3])));
1495 hw_set_dxx_reg(phw_data, 0x54, val); 1363 hw_set_dxx_reg(phw_data, 0x54, val);
1496 } 1364 } else /* 2nd-cut */{
1497 else // 2nd-cut
1498 {
1499 val &= 0x000003FF; 1365 val &= 0x000003FF;
1500 val |= ((_s32_to_s5(rx_cal[0]) << 27)| 1366 val |= ((_s32_to_s5(rx_cal[0]) << 27)|
1501 (_s32_to_s6(rx_cal[1]) << 21)| 1367 (_s32_to_s6(rx_cal[1]) << 21)|
@@ -1503,7 +1369,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1503 (_s32_to_s5(rx_cal[3]) << 10)); 1369 (_s32_to_s5(rx_cal[3]) << 10));
1504 hw_set_dxx_reg(phw_data, 0x54, val); 1370 hw_set_dxx_reg(phw_data, 0x54, val);
1505 1371
1506 if( loop == 3 ) 1372 if (loop == 3)
1507 return 0; 1373 return 0;
1508 } 1374 }
1509 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val)); 1375 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
@@ -1514,12 +1380,12 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
1514 return 1; 1380 return 1;
1515} 1381}
1516 1382
1517////////////////////////////////////////////////////////// 1383/*************************************************/
1518 1384
1519////////////////////////////////////////////////////////////////////////// 1385/***************************************************************/
1520void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency) 1386void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
1521{ 1387{
1522// figo 20050523 marked thsi flag for can't compile for relesase 1388/* figo 20050523 marked this flag for can't compile for relesase */
1523#ifdef _DEBUG 1389#ifdef _DEBUG
1524 s32 rx_cal_reg[4]; 1390 s32 rx_cal_reg[4];
1525 u32 val; 1391 u32 val;
@@ -1528,37 +1394,34 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
1528 u8 result; 1394 u8 result;
1529 1395
1530 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n")); 1396 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n"));
1531// a. Set RFIC to "RX calibration mode" 1397/* a. Set RFIC to "RX calibration mode" */
1532 //; ----- Calibration (7). RX path IQ imbalance calibration loop 1398 /* ; ----- Calibration (7). RX path IQ imbalance calibration loop */
1533 // 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits 1399 /* 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits */
1534 phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2); 1400 phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2);
1535 // 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuit 1401 /* 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuits */
1536 phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6); 1402 phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6);
1537 //0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized 1403 /* 0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized */
1538 phy_set_rf_data(phw_data, 5, (5<<24)| phw_data->txvga_setting_for_cal); 1404 phy_set_rf_data(phw_data, 5, (5<<24) | phw_data->txvga_setting_for_cal);
1539 //0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized 1405 /* 0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized */
1540 phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C); 1406 phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C);
1541 //0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode 1407 /* 0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode */
1542 phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0); 1408 phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0);
1543 1409
1544 // ; [BB-chip]: Calibration (7f). Send test pattern 1410 /* ; [BB-chip]: Calibration (7f). Send test pattern */
1545 // ; [BB-chip]: Calibration (7g). Search RXGCL optimal value 1411 /* ; [BB-chip]: Calibration (7g). Search RXGCL optimal value */
1546 // ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table 1412 /* ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table */
1547 1413
1548 result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency); 1414 result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency);
1549 1415
1550 if (result > 0) 1416 if (result > 0) {
1551 {
1552 _reset_rx_cal(phw_data); 1417 _reset_rx_cal(phw_data);
1553 result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency); 1418 result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency);
1554 1419
1555 if (result > 0) 1420 if (result > 0) {
1556 {
1557 _reset_rx_cal(phw_data); 1421 _reset_rx_cal(phw_data);
1558 result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency); 1422 result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency);
1559 1423
1560 if (result > 0) 1424 if (result > 0) {
1561 {
1562 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n")); 1425 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n"));
1563 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n")); 1426 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n"));
1564 PHY_DEBUG(("[CAL] **************************************\n")); 1427 PHY_DEBUG(("[CAL] **************************************\n"));
@@ -1571,15 +1434,12 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
1571 hw_get_dxx_reg(phw_data, 0x54, &val); 1434 hw_get_dxx_reg(phw_data, 0x54, &val);
1572 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 1435 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
1573 1436
1574 if (phw_data->revision == 0x2002) // 1st-cut 1437 if (phw_data->revision == 0x2002) /* 1st-cut */{
1575 {
1576 rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12); 1438 rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
1577 rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8); 1439 rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
1578 rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4); 1440 rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
1579 rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F)); 1441 rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
1580 } 1442 } else /* 2nd-cut */{
1581 else // 2nd-cut
1582 {
1583 rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 1443 rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
1584 rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); 1444 rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
1585 rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); 1445 rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
@@ -1594,7 +1454,7 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
1594 1454
1595} 1455}
1596 1456
1597//////////////////////////////////////////////////////////////////////// 1457/*******************************************************/
1598void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency) 1458void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency)
1599{ 1459{
1600 u32 reg_mode_ctrl; 1460 u32 reg_mode_ctrl;
@@ -1602,7 +1462,7 @@ void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency)
1602 1462
1603 PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n")); 1463 PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n"));
1604 1464
1605 // 20040701 1.1.25.1000 kevin 1465 /* 20040701 1.1.25.1000 kevin */
1606 hw_get_cxx_reg(phw_data, 0x80, &mac_ctrl); 1466 hw_get_cxx_reg(phw_data, 0x80, &mac_ctrl);
1607 hw_get_cxx_reg(phw_data, 0xE4, &rf_ctrl); 1467 hw_get_cxx_reg(phw_data, 0xE4, &rf_ctrl);
1608 hw_get_dxx_reg(phw_data, 0x58, &iq_alpha); 1468 hw_get_dxx_reg(phw_data, 0x58, &iq_alpha);
@@ -1610,72 +1470,71 @@ void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency)
1610 1470
1611 1471
1612 _rxadc_dc_offset_cancellation_winbond(phw_data, frequency); 1472 _rxadc_dc_offset_cancellation_winbond(phw_data, frequency);
1613 //_txidac_dc_offset_cancellation_winbond(phw_data); 1473 /* _txidac_dc_offset_cancellation_winbond(phw_data); */
1614 //_txqdac_dc_offset_cacellation_winbond(phw_data); 1474 /* _txqdac_dc_offset_cacellation_winbond(phw_data); */
1615 1475
1616 _tx_iq_calibration_winbond(phw_data); 1476 _tx_iq_calibration_winbond(phw_data);
1617 _rx_iq_calibration_winbond(phw_data, frequency); 1477 _rx_iq_calibration_winbond(phw_data, frequency);
1618 1478
1619 //------------------------------------------------------------------------ 1479 /*********************************************************************/
1620 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 1480 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
1621 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); // set when finish 1481 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); /* set when finish */
1622 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1482 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1623 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1483 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1624 1484
1625 // i. Set RFIC to "Normal mode" 1485 /* i. Set RFIC to "Normal mode" */
1626 hw_set_cxx_reg(phw_data, 0x80, mac_ctrl); 1486 hw_set_cxx_reg(phw_data, 0x80, mac_ctrl);
1627 hw_set_cxx_reg(phw_data, 0xE4, rf_ctrl); 1487 hw_set_cxx_reg(phw_data, 0xE4, rf_ctrl);
1628 hw_set_dxx_reg(phw_data, 0x58, iq_alpha); 1488 hw_set_dxx_reg(phw_data, 0x58, iq_alpha);
1629 1489
1630 1490
1631 //------------------------------------------------------------------------ 1491 /*********************************************************************/
1632 phy_init_rf(phw_data); 1492 phy_init_rf(phw_data);
1633 1493
1634} 1494}
1635 1495
1636//=========================== 1496/******************/
1637void phy_set_rf_data( struct hw_data * pHwData, u32 index, u32 value ) 1497void phy_set_rf_data(struct hw_data *pHwData, u32 index, u32 value)
1638{ 1498{
1639 u32 ltmp=0; 1499 u32 ltmpi = 0;
1640 1500
1641 switch( pHwData->phy_type ) 1501 switch (pHwData->phy_type) {
1642 { 1502 case RF_MAXIM_2825:
1643 case RF_MAXIM_2825: 1503 case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
1644 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) 1504 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1645 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); 1505 break;
1646 break; 1506
1647 1507 case RF_MAXIM_2827:
1648 case RF_MAXIM_2827: 1508 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1649 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); 1509 break;
1650 break; 1510
1651 1511 case RF_MAXIM_2828:
1652 case RF_MAXIM_2828: 1512 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1653 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); 1513 break;
1654 break; 1514
1655 1515 case RF_MAXIM_2829:
1656 case RF_MAXIM_2829: 1516 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1657 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); 1517 break;
1658 break; 1518
1659 1519 case RF_AIROHA_2230:
1660 case RF_AIROHA_2230: 1520 case RF_AIROHA_2230S: /* 20060420 Add this */
1661 case RF_AIROHA_2230S: // 20060420 Add this 1521 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(value, 20);
1662 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( value, 20 ); 1522 break;
1663 break; 1523
1664 1524 case RF_AIROHA_7230:
1665 case RF_AIROHA_7230: 1525 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff);
1666 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff); 1526 break;
1667 break; 1527
1668 1528 case RF_WB_242:
1669 case RF_WB_242: 1529 case RF_WB_242_1:/* 20060619.5 Add */
1670 case RF_WB_242_1: // 20060619.5 Add 1530 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(value, 24);
1671 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( value, 24 ); 1531 break;
1672 break; 1532 }
1673 }
1674 1533
1675 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1534 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1676} 1535}
1677 1536
1678// 20060717 modify as Bruce's mail 1537/* 20060717 modify as Bruce's mail */
1679unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data) 1538unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
1680{ 1539{
1681 int init_txvga = 0; 1540 int init_txvga = 0;
@@ -1685,26 +1544,27 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
1685 s32 iqcal_tone_q0; 1544 s32 iqcal_tone_q0;
1686 u32 sqsum; 1545 u32 sqsum;
1687 s32 iq_mag_0_tx; 1546 s32 iq_mag_0_tx;
1688 u8 reg_state; 1547 u8 reg_state;
1689 int current_txvga; 1548 int current_txvga;
1690 1549
1691 1550
1692 reg_state = 0; 1551 reg_state = 0;
1693 for( init_txvga=0; init_txvga<10; init_txvga++) 1552 for (init_txvga = 0; init_txvga < 10; init_txvga++) {
1694 { 1553 current_txvga = (0x24C40A|(init_txvga<<6));
1695 current_txvga = ( 0x24C40A|(init_txvga<<6) ); 1554 phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga));
1696 phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga) );
1697 phw_data->txvga_setting_for_cal = current_txvga; 1555 phw_data->txvga_setting_for_cal = current_txvga;
1698 1556
1699 msleep(30); // 20060612.1.a 1557 msleep(30);/* 20060612.1.a */
1700 1558
1701 if( !hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl) ) // 20060718.1 modify 1559 if (!hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl))/* 20060718.1 modify */
1702 return false; 1560 return false;
1703 1561
1704 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 1562 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
1705 1563
1706 // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to 1564 /*
1707 // enable "IQ alibration Mode II" 1565 * a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
1566 * enable "IQ alibration Mode II"
1567 */
1708 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 1568 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
1709 reg_mode_ctrl &= ~MASK_IQCAL_MODE; 1569 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
1710 reg_mode_ctrl |= (MASK_CALIB_START|0x02); 1570 reg_mode_ctrl |= (MASK_CALIB_START|0x02);
@@ -1712,15 +1572,15 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
1712 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1572 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1713 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1573 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1714 1574
1715 udelay(1); // 20060612.1.a 1575 udelay(1);/* 20060612.1.a */
1716 1576
1717 udelay(300); // 20060612.1.a 1577 udelay(300);/* 20060612.1.a */
1718 1578
1719 // b. 1579 /* b. */
1720 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 1580 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
1721 1581
1722 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 1582 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
1723 udelay(300); // 20060612.1.a 1583 udelay(300);/* 20060612.1.a */
1724 1584
1725 iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF); 1585 iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF);
1726 iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13); 1586 iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13);
@@ -1731,23 +1591,18 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
1731 iq_mag_0_tx = (s32) _sqrt(sqsum); 1591 iq_mag_0_tx = (s32) _sqrt(sqsum);
1732 PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx)); 1592 PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx));
1733 1593
1734 if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 ) 1594 if (iq_mag_0_tx >= 700 && iq_mag_0_tx <= 1750)
1735 break; 1595 break;
1736 else if(iq_mag_0_tx > 1750) 1596 else if (iq_mag_0_tx > 1750) {
1737 { 1597 init_txvga = -2;
1738 init_txvga=-2;
1739 continue; 1598 continue;
1740 } 1599 } else
1741 else
1742 continue; 1600 continue;
1743 1601
1744 } 1602 }
1745 1603
1746 if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 ) 1604 if (iq_mag_0_tx >= 700 && iq_mag_0_tx <= 1750)
1747 return true; 1605 return true;
1748 else 1606 else
1749 return false; 1607 return false;
1750} 1608}
1751
1752
1753
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 10:16:14 -0400