diff options
author | Martyn Welch <martyn.welch@ge.com> | 2010-03-22 10:58:50 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-05-11 14:35:52 -0400 |
commit | 48d9356e7750d3efa3156eb3a76e7a4439774b12 (patch) | |
tree | e11230f5f234271e91b1af2eb891a4fdbf60a4c3 /drivers/staging/vme/bridges | |
parent | ebbfda1e656b9dd69bd606b1dbba28cd53dd227e (diff) |
Staging: vme: Use dev_err rather than printk
Replace instances of printk with dev_err where possible.
Signed-off-by: Martyn Welch <martyn.welch@ge.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/vme/bridges')
-rw-r--r-- | drivers/staging/vme/bridges/vme_ca91cx42.c | 95 | ||||
-rw-r--r-- | drivers/staging/vme/bridges/vme_tsi148.c | 202 |
2 files changed, 171 insertions, 126 deletions
diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index b159ea58adf..589664c4d24 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c | |||
@@ -94,31 +94,35 @@ static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) | |||
94 | return CA91CX42_LINT_SW_IACK; | 94 | return CA91CX42_LINT_SW_IACK; |
95 | } | 95 | } |
96 | 96 | ||
97 | static u32 ca91cx42_VERR_irqhandler(struct ca91cx42_driver *bridge) | 97 | static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge) |
98 | { | 98 | { |
99 | int val; | 99 | int val; |
100 | struct ca91cx42_driver *bridge; | ||
101 | |||
102 | bridge = ca91cx42_bridge->driver_priv; | ||
100 | 103 | ||
101 | val = ioread32(bridge->base + DGCS); | 104 | val = ioread32(bridge->base + DGCS); |
102 | 105 | ||
103 | if (!(val & 0x00000800)) { | 106 | if (!(val & 0x00000800)) { |
104 | printk(KERN_ERR "ca91c042: ca91cx42_VERR_irqhandler DMA Read " | 107 | dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA " |
105 | "Error DGCS=%08X\n", val); | 108 | "Read Error DGCS=%08X\n", val); |
106 | } | 109 | } |
107 | 110 | ||
108 | return CA91CX42_LINT_VERR; | 111 | return CA91CX42_LINT_VERR; |
109 | } | 112 | } |
110 | 113 | ||
111 | static u32 ca91cx42_LERR_irqhandler(struct ca91cx42_driver *bridge) | 114 | static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge) |
112 | { | 115 | { |
113 | int val; | 116 | int val; |
117 | struct ca91cx42_driver *bridge; | ||
114 | 118 | ||
115 | val = ioread32(bridge->base + DGCS); | 119 | bridge = ca91cx42_bridge->driver_priv; |
116 | 120 | ||
117 | if (!(val & 0x00000800)) { | 121 | val = ioread32(bridge->base + DGCS); |
118 | printk(KERN_ERR "ca91c042: ca91cx42_LERR_irqhandler DMA Read " | ||
119 | "Error DGCS=%08X\n", val); | ||
120 | 122 | ||
121 | } | 123 | if (!(val & 0x00000800)) |
124 | dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA " | ||
125 | "Read Error DGCS=%08X\n", val); | ||
122 | 126 | ||
123 | return CA91CX42_LINT_LERR; | 127 | return CA91CX42_LINT_LERR; |
124 | } | 128 | } |
@@ -176,9 +180,9 @@ static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr) | |||
176 | if (stat & CA91CX42_LINT_SW_IACK) | 180 | if (stat & CA91CX42_LINT_SW_IACK) |
177 | serviced |= ca91cx42_IACK_irqhandler(bridge); | 181 | serviced |= ca91cx42_IACK_irqhandler(bridge); |
178 | if (stat & CA91CX42_LINT_VERR) | 182 | if (stat & CA91CX42_LINT_VERR) |
179 | serviced |= ca91cx42_VERR_irqhandler(bridge); | 183 | serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge); |
180 | if (stat & CA91CX42_LINT_LERR) | 184 | if (stat & CA91CX42_LINT_LERR) |
181 | serviced |= ca91cx42_LERR_irqhandler(bridge); | 185 | serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge); |
182 | if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 | | 186 | if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 | |
183 | CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 | | 187 | CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 | |
184 | CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 | | 188 | CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 | |
@@ -326,9 +330,12 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, | |||
326 | unsigned int i, addr = 0, granularity; | 330 | unsigned int i, addr = 0, granularity; |
327 | unsigned int temp_ctl = 0; | 331 | unsigned int temp_ctl = 0; |
328 | unsigned int vme_bound, pci_offset; | 332 | unsigned int vme_bound, pci_offset; |
333 | struct vme_bridge *ca91cx42_bridge; | ||
329 | struct ca91cx42_driver *bridge; | 334 | struct ca91cx42_driver *bridge; |
330 | 335 | ||
331 | bridge = image->parent->driver_priv; | 336 | ca91cx42_bridge = image->parent; |
337 | |||
338 | bridge = ca91cx42_bridge->driver_priv; | ||
332 | 339 | ||
333 | i = image->number; | 340 | i = image->number; |
334 | 341 | ||
@@ -353,7 +360,7 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, | |||
353 | case VME_USER3: | 360 | case VME_USER3: |
354 | case VME_USER4: | 361 | case VME_USER4: |
355 | default: | 362 | default: |
356 | printk(KERN_ERR "Invalid address space\n"); | 363 | dev_err(ca91cx42_bridge->parent, "Invalid address space\n"); |
357 | return -EINVAL; | 364 | return -EINVAL; |
358 | break; | 365 | break; |
359 | } | 366 | } |
@@ -371,15 +378,18 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, | |||
371 | granularity = 0x10000; | 378 | granularity = 0x10000; |
372 | 379 | ||
373 | if (vme_base & (granularity - 1)) { | 380 | if (vme_base & (granularity - 1)) { |
374 | printk(KERN_ERR "Invalid VME base alignment\n"); | 381 | dev_err(ca91cx42_bridge->parent, "Invalid VME base " |
382 | "alignment\n"); | ||
375 | return -EINVAL; | 383 | return -EINVAL; |
376 | } | 384 | } |
377 | if (vme_bound & (granularity - 1)) { | 385 | if (vme_bound & (granularity - 1)) { |
378 | printk(KERN_ERR "Invalid VME bound alignment\n"); | 386 | dev_err(ca91cx42_bridge->parent, "Invalid VME bound " |
387 | "alignment\n"); | ||
379 | return -EINVAL; | 388 | return -EINVAL; |
380 | } | 389 | } |
381 | if (pci_offset & (granularity - 1)) { | 390 | if (pci_offset & (granularity - 1)) { |
382 | printk(KERN_ERR "Invalid PCI Offset alignment\n"); | 391 | dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset " |
392 | "alignment\n"); | ||
383 | return -EINVAL; | 393 | return -EINVAL; |
384 | } | 394 | } |
385 | 395 | ||
@@ -491,7 +501,7 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, | |||
491 | 501 | ||
492 | /* Find pci_dev container of dev */ | 502 | /* Find pci_dev container of dev */ |
493 | if (ca91cx42_bridge->parent == NULL) { | 503 | if (ca91cx42_bridge->parent == NULL) { |
494 | printk(KERN_ERR "Dev entry NULL\n"); | 504 | dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n"); |
495 | return -EINVAL; | 505 | return -EINVAL; |
496 | } | 506 | } |
497 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); | 507 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); |
@@ -515,8 +525,8 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, | |||
515 | if (image->bus_resource.name == NULL) { | 525 | if (image->bus_resource.name == NULL) { |
516 | image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); | 526 | image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); |
517 | if (image->bus_resource.name == NULL) { | 527 | if (image->bus_resource.name == NULL) { |
518 | printk(KERN_ERR "Unable to allocate memory for resource" | 528 | dev_err(ca91cx42_bridge->parent, "Unable to allocate " |
519 | " name\n"); | 529 | "memory for resource name\n"); |
520 | retval = -ENOMEM; | 530 | retval = -ENOMEM; |
521 | goto err_name; | 531 | goto err_name; |
522 | } | 532 | } |
@@ -533,8 +543,8 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, | |||
533 | &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, | 543 | &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, |
534 | 0, NULL, NULL); | 544 | 0, NULL, NULL); |
535 | if (retval) { | 545 | if (retval) { |
536 | printk(KERN_ERR "Failed to allocate mem resource for " | 546 | dev_err(ca91cx42_bridge->parent, "Failed to allocate mem " |
537 | "window %d size 0x%lx start 0x%lx\n", | 547 | "resource for window %d size 0x%lx start 0x%lx\n", |
538 | image->number, (unsigned long)size, | 548 | image->number, (unsigned long)size, |
539 | (unsigned long)image->bus_resource.start); | 549 | (unsigned long)image->bus_resource.start); |
540 | goto err_resource; | 550 | goto err_resource; |
@@ -543,7 +553,7 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, | |||
543 | image->kern_base = ioremap_nocache( | 553 | image->kern_base = ioremap_nocache( |
544 | image->bus_resource.start, size); | 554 | image->bus_resource.start, size); |
545 | if (image->kern_base == NULL) { | 555 | if (image->kern_base == NULL) { |
546 | printk(KERN_ERR "Failed to remap resource\n"); | 556 | dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n"); |
547 | retval = -ENOMEM; | 557 | retval = -ENOMEM; |
548 | goto err_remap; | 558 | goto err_remap; |
549 | } | 559 | } |
@@ -582,9 +592,12 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |||
582 | unsigned int i, granularity = 0; | 592 | unsigned int i, granularity = 0; |
583 | unsigned int temp_ctl = 0; | 593 | unsigned int temp_ctl = 0; |
584 | unsigned long long pci_bound, vme_offset, pci_base; | 594 | unsigned long long pci_bound, vme_offset, pci_base; |
595 | struct vme_bridge *ca91cx42_bridge; | ||
585 | struct ca91cx42_driver *bridge; | 596 | struct ca91cx42_driver *bridge; |
586 | 597 | ||
587 | bridge = image->parent->driver_priv; | 598 | ca91cx42_bridge = image->parent; |
599 | |||
600 | bridge = ca91cx42_bridge->driver_priv; | ||
588 | 601 | ||
589 | i = image->number; | 602 | i = image->number; |
590 | 603 | ||
@@ -595,12 +608,14 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |||
595 | 608 | ||
596 | /* Verify input data */ | 609 | /* Verify input data */ |
597 | if (vme_base & (granularity - 1)) { | 610 | if (vme_base & (granularity - 1)) { |
598 | printk(KERN_ERR "Invalid VME Window alignment\n"); | 611 | dev_err(ca91cx42_bridge->parent, "Invalid VME Window " |
612 | "alignment\n"); | ||
599 | retval = -EINVAL; | 613 | retval = -EINVAL; |
600 | goto err_window; | 614 | goto err_window; |
601 | } | 615 | } |
602 | if (size & (granularity - 1)) { | 616 | if (size & (granularity - 1)) { |
603 | printk(KERN_ERR "Invalid VME Window alignment\n"); | 617 | dev_err(ca91cx42_bridge->parent, "Invalid VME Window " |
618 | "alignment\n"); | ||
604 | retval = -EINVAL; | 619 | retval = -EINVAL; |
605 | goto err_window; | 620 | goto err_window; |
606 | } | 621 | } |
@@ -614,8 +629,8 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |||
614 | retval = ca91cx42_alloc_resource(image, size); | 629 | retval = ca91cx42_alloc_resource(image, size); |
615 | if (retval) { | 630 | if (retval) { |
616 | spin_unlock(&(image->lock)); | 631 | spin_unlock(&(image->lock)); |
617 | printk(KERN_ERR "Unable to allocate memory for resource " | 632 | dev_err(ca91cx42_bridge->parent, "Unable to allocate memory " |
618 | "name\n"); | 633 | "for resource name\n"); |
619 | retval = -ENOMEM; | 634 | retval = -ENOMEM; |
620 | goto err_res; | 635 | goto err_res; |
621 | } | 636 | } |
@@ -658,7 +673,7 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |||
658 | break; | 673 | break; |
659 | default: | 674 | default: |
660 | spin_unlock(&(image->lock)); | 675 | spin_unlock(&(image->lock)); |
661 | printk(KERN_ERR "Invalid data width\n"); | 676 | dev_err(ca91cx42_bridge->parent, "Invalid data width\n"); |
662 | retval = -EINVAL; | 677 | retval = -EINVAL; |
663 | goto err_dwidth; | 678 | goto err_dwidth; |
664 | break; | 679 | break; |
@@ -690,7 +705,7 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |||
690 | case VME_USER4: | 705 | case VME_USER4: |
691 | default: | 706 | default: |
692 | spin_unlock(&(image->lock)); | 707 | spin_unlock(&(image->lock)); |
693 | printk(KERN_ERR "Invalid address space\n"); | 708 | dev_err(ca91cx42_bridge->parent, "Invalid address space\n"); |
694 | retval = -EINVAL; | 709 | retval = -EINVAL; |
695 | goto err_aspace; | 710 | goto err_aspace; |
696 | break; | 711 | break; |
@@ -921,12 +936,15 @@ int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, | |||
921 | struct vme_dma_vme *vme_attr; | 936 | struct vme_dma_vme *vme_attr; |
922 | dma_addr_t desc_ptr; | 937 | dma_addr_t desc_ptr; |
923 | int retval = 0; | 938 | int retval = 0; |
939 | struct device *dev; | ||
940 | |||
941 | dev = list->parent->parent->parent; | ||
924 | 942 | ||
925 | /* XXX descriptor must be aligned on 64-bit boundaries */ | 943 | /* XXX descriptor must be aligned on 64-bit boundaries */ |
926 | entry = (struct ca91cx42_dma_entry *) | 944 | entry = (struct ca91cx42_dma_entry *) |
927 | kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL); | 945 | kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL); |
928 | if (entry == NULL) { | 946 | if (entry == NULL) { |
929 | printk(KERN_ERR "Failed to allocate memory for dma resource " | 947 | dev_err(dev, "Failed to allocate memory for dma resource " |
930 | "structure\n"); | 948 | "structure\n"); |
931 | retval = -ENOMEM; | 949 | retval = -ENOMEM; |
932 | goto err_mem; | 950 | goto err_mem; |
@@ -934,7 +952,7 @@ int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, | |||
934 | 952 | ||
935 | /* Test descriptor alignment */ | 953 | /* Test descriptor alignment */ |
936 | if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) { | 954 | if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) { |
937 | printk("Descriptor not aligned to 16 byte boundary as " | 955 | dev_err(dev, "Descriptor not aligned to 16 byte boundary as " |
938 | "required: %p\n", &(entry->descriptor)); | 956 | "required: %p\n", &(entry->descriptor)); |
939 | retval = -EINVAL; | 957 | retval = -EINVAL; |
940 | goto err_align; | 958 | goto err_align; |
@@ -955,7 +973,7 @@ int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, | |||
955 | if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 | | 973 | if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 | |
956 | VME_USER2)) != 0) { | 974 | VME_USER2)) != 0) { |
957 | 975 | ||
958 | printk(KERN_ERR "Unsupported cycle type\n"); | 976 | dev_err(dev, "Unsupported cycle type\n"); |
959 | retval = -EINVAL; | 977 | retval = -EINVAL; |
960 | goto err_aspace; | 978 | goto err_aspace; |
961 | } | 979 | } |
@@ -963,7 +981,7 @@ int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, | |||
963 | if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER | | 981 | if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER | |
964 | VME_PROG | VME_DATA)) != 0) { | 982 | VME_PROG | VME_DATA)) != 0) { |
965 | 983 | ||
966 | printk(KERN_ERR "Unsupported cycle type\n"); | 984 | dev_err(dev, "Unsupported cycle type\n"); |
967 | retval = -EINVAL; | 985 | retval = -EINVAL; |
968 | goto err_cycle; | 986 | goto err_cycle; |
969 | } | 987 | } |
@@ -972,7 +990,7 @@ int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, | |||
972 | if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) || | 990 | if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) || |
973 | ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) { | 991 | ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) { |
974 | 992 | ||
975 | printk(KERN_ERR "Cannot perform transfer with this " | 993 | dev_err(dev, "Cannot perform transfer with this " |
976 | "source-destination combination\n"); | 994 | "source-destination combination\n"); |
977 | retval = -EINVAL; | 995 | retval = -EINVAL; |
978 | goto err_direct; | 996 | goto err_direct; |
@@ -997,7 +1015,7 @@ int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, | |||
997 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64; | 1015 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64; |
998 | break; | 1016 | break; |
999 | default: | 1017 | default: |
1000 | printk(KERN_ERR "Invalid data width\n"); | 1018 | dev_err(dev, "Invalid data width\n"); |
1001 | return -EINVAL; | 1019 | return -EINVAL; |
1002 | } | 1020 | } |
1003 | 1021 | ||
@@ -1019,7 +1037,7 @@ int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, | |||
1019 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2; | 1037 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2; |
1020 | break; | 1038 | break; |
1021 | default: | 1039 | default: |
1022 | printk(KERN_ERR "Invalid address space\n"); | 1040 | dev_err(dev, "Invalid address space\n"); |
1023 | return -EINVAL; | 1041 | return -EINVAL; |
1024 | break; | 1042 | break; |
1025 | } | 1043 | } |
@@ -1079,12 +1097,13 @@ int ca91cx42_dma_list_exec(struct vme_dma_list *list) | |||
1079 | int retval = 0; | 1097 | int retval = 0; |
1080 | dma_addr_t bus_addr; | 1098 | dma_addr_t bus_addr; |
1081 | u32 val; | 1099 | u32 val; |
1082 | 1100 | struct device *dev; | |
1083 | struct ca91cx42_driver *bridge; | 1101 | struct ca91cx42_driver *bridge; |
1084 | 1102 | ||
1085 | ctrlr = list->parent; | 1103 | ctrlr = list->parent; |
1086 | 1104 | ||
1087 | bridge = ctrlr->parent->driver_priv; | 1105 | bridge = ctrlr->parent->driver_priv; |
1106 | dev = ctrlr->parent->parent; | ||
1088 | 1107 | ||
1089 | mutex_lock(&(ctrlr->mtx)); | 1108 | mutex_lock(&(ctrlr->mtx)); |
1090 | 1109 | ||
@@ -1140,7 +1159,7 @@ int ca91cx42_dma_list_exec(struct vme_dma_list *list) | |||
1140 | if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | | 1159 | if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | |
1141 | CA91CX42_DGCS_PERR)) { | 1160 | CA91CX42_DGCS_PERR)) { |
1142 | 1161 | ||
1143 | printk(KERN_ERR "ca91c042: DMA Error. DGCS=%08X\n", val); | 1162 | dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val); |
1144 | val = ioread32(bridge->base + DCTL); | 1163 | val = ioread32(bridge->base + DCTL); |
1145 | } | 1164 | } |
1146 | 1165 | ||
diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c index 68f24425977..fa0dc4a869e 100644 --- a/drivers/staging/vme/bridges/vme_tsi148.c +++ b/drivers/staging/vme/bridges/vme_tsi148.c | |||
@@ -137,16 +137,20 @@ static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat) | |||
137 | * | 137 | * |
138 | * XXX This functionality is not exposed up though API. | 138 | * XXX This functionality is not exposed up though API. |
139 | */ | 139 | */ |
140 | static u32 tsi148_MB_irqhandler(struct tsi148_driver *bridge, u32 stat) | 140 | static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat) |
141 | { | 141 | { |
142 | int i; | 142 | int i; |
143 | u32 val; | 143 | u32 val; |
144 | u32 serviced = 0; | 144 | u32 serviced = 0; |
145 | struct tsi148_driver *bridge; | ||
146 | |||
147 | bridge = tsi148_bridge->driver_priv; | ||
145 | 148 | ||
146 | for (i = 0; i < 4; i++) { | 149 | for (i = 0; i < 4; i++) { |
147 | if(stat & TSI148_LCSR_INTS_MBS[i]) { | 150 | if(stat & TSI148_LCSR_INTS_MBS[i]) { |
148 | val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); | 151 | val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); |
149 | printk("VME Mailbox %d received: 0x%x\n", i, val); | 152 | dev_err(tsi148_bridge->parent, "VME Mailbox %d received" |
153 | ": 0x%x\n", i, val); | ||
150 | serviced |= TSI148_LCSR_INTC_MBC[i]; | 154 | serviced |= TSI148_LCSR_INTC_MBC[i]; |
151 | } | 155 | } |
152 | } | 156 | } |
@@ -157,19 +161,22 @@ static u32 tsi148_MB_irqhandler(struct tsi148_driver *bridge, u32 stat) | |||
157 | /* | 161 | /* |
158 | * Display error & status message when PERR (PCI) exception interrupt occurs. | 162 | * Display error & status message when PERR (PCI) exception interrupt occurs. |
159 | */ | 163 | */ |
160 | static u32 tsi148_PERR_irqhandler(struct tsi148_driver *bridge) | 164 | static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge) |
161 | { | 165 | { |
162 | printk(KERN_ERR | 166 | struct tsi148_driver *bridge; |
163 | "PCI Exception at address: 0x%08x:%08x, attributes: %08x\n", | 167 | |
168 | bridge = tsi148_bridge->driver_priv; | ||
169 | |||
170 | dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, " | ||
171 | "attributes: %08x\n", | ||
164 | ioread32be(bridge->base + TSI148_LCSR_EDPAU), | 172 | ioread32be(bridge->base + TSI148_LCSR_EDPAU), |
165 | ioread32be(bridge->base + TSI148_LCSR_EDPAL), | 173 | ioread32be(bridge->base + TSI148_LCSR_EDPAL), |
166 | ioread32be(bridge->base + TSI148_LCSR_EDPAT) | 174 | ioread32be(bridge->base + TSI148_LCSR_EDPAT)); |
167 | ); | 175 | |
168 | printk(KERN_ERR | 176 | dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split " |
169 | "PCI-X attribute reg: %08x, PCI-X split completion reg: %08x\n", | 177 | "completion reg: %08x\n", |
170 | ioread32be(bridge->base + TSI148_LCSR_EDPXA), | 178 | ioread32be(bridge->base + TSI148_LCSR_EDPXA), |
171 | ioread32be(bridge->base + TSI148_LCSR_EDPXS) | 179 | ioread32be(bridge->base + TSI148_LCSR_EDPXS)); |
172 | ); | ||
173 | 180 | ||
174 | iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); | 181 | iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); |
175 | 182 | ||
@@ -197,7 +204,8 @@ static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge) | |||
197 | 204 | ||
198 | /* Check for exception register overflow (we have lost error data) */ | 205 | /* Check for exception register overflow (we have lost error data) */ |
199 | if(error_attrib & TSI148_LCSR_VEAT_VEOF) { | 206 | if(error_attrib & TSI148_LCSR_VEAT_VEOF) { |
200 | printk(KERN_ERR "VME Bus Exception Overflow Occurred\n"); | 207 | dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow " |
208 | "Occurred\n"); | ||
201 | } | 209 | } |
202 | 210 | ||
203 | error = (struct vme_bus_error *)kmalloc(sizeof (struct vme_bus_error), | 211 | error = (struct vme_bus_error *)kmalloc(sizeof (struct vme_bus_error), |
@@ -207,11 +215,10 @@ static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge) | |||
207 | error->attributes = error_attrib; | 215 | error->attributes = error_attrib; |
208 | list_add_tail(&(error->list), &(tsi148_bridge->vme_errors)); | 216 | list_add_tail(&(error->list), &(tsi148_bridge->vme_errors)); |
209 | } else { | 217 | } else { |
210 | printk(KERN_ERR | 218 | dev_err(tsi148_bridge->parent, "Unable to alloc memory for " |
211 | "Unable to alloc memory for VMEbus Error reporting\n"); | 219 | "VMEbus Error reporting\n"); |
212 | printk(KERN_ERR | 220 | dev_err(tsi148_bridge->parent, "VME Bus Error at address: " |
213 | "VME Bus Error at address: 0x%llx, attributes: %08x\n", | 221 | "0x%llx, attributes: %08x\n", error_addr, error_attrib); |
214 | error_addr, error_attrib); | ||
215 | } | 222 | } |
216 | 223 | ||
217 | /* Clear Status */ | 224 | /* Clear Status */ |
@@ -298,11 +305,11 @@ static irqreturn_t tsi148_irqhandler(int irq, void *ptr) | |||
298 | /* Mail box irqs */ | 305 | /* Mail box irqs */ |
299 | if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S | | 306 | if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S | |
300 | TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S)) | 307 | TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S)) |
301 | serviced |= tsi148_MB_irqhandler(bridge, stat); | 308 | serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat); |
302 | 309 | ||
303 | /* PCI bus error */ | 310 | /* PCI bus error */ |
304 | if (stat & TSI148_LCSR_INTS_PERRS) | 311 | if (stat & TSI148_LCSR_INTS_PERRS) |
305 | serviced |= tsi148_PERR_irqhandler(bridge); | 312 | serviced |= tsi148_PERR_irqhandler(tsi148_bridge); |
306 | 313 | ||
307 | /* VME bus error */ | 314 | /* VME bus error */ |
308 | if (stat & TSI148_LCSR_INTS_VERRS) | 315 | if (stat & TSI148_LCSR_INTS_VERRS) |
@@ -346,8 +353,8 @@ static int tsi148_irq_init(struct vme_bridge *tsi148_bridge) | |||
346 | IRQF_SHARED, | 353 | IRQF_SHARED, |
347 | driver_name, tsi148_bridge); | 354 | driver_name, tsi148_bridge); |
348 | if (result) { | 355 | if (result) { |
349 | dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n", | 356 | dev_err(tsi148_bridge->parent, "Can't get assigned pci irq " |
350 | pdev->irq); | 357 | "vector %02X\n", pdev->irq); |
351 | return result; | 358 | return result; |
352 | } | 359 | } |
353 | 360 | ||
@@ -568,9 +575,11 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, | |||
568 | unsigned int vme_bound_low, vme_bound_high; | 575 | unsigned int vme_bound_low, vme_bound_high; |
569 | unsigned int pci_offset_low, pci_offset_high; | 576 | unsigned int pci_offset_low, pci_offset_high; |
570 | unsigned long long vme_bound, pci_offset; | 577 | unsigned long long vme_bound, pci_offset; |
578 | struct vme_bridge *tsi148_bridge; | ||
571 | struct tsi148_driver *bridge; | 579 | struct tsi148_driver *bridge; |
572 | 580 | ||
573 | bridge = image->parent->driver_priv; | 581 | tsi148_bridge = image->parent; |
582 | bridge = tsi148_bridge->driver_priv; | ||
574 | 583 | ||
575 | i = image->number; | 584 | i = image->number; |
576 | 585 | ||
@@ -597,7 +606,7 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, | |||
597 | case VME_USER3: | 606 | case VME_USER3: |
598 | case VME_USER4: | 607 | case VME_USER4: |
599 | default: | 608 | default: |
600 | printk("Invalid address space\n"); | 609 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
601 | return -EINVAL; | 610 | return -EINVAL; |
602 | break; | 611 | break; |
603 | } | 612 | } |
@@ -615,15 +624,16 @@ int tsi148_slave_set(struct vme_slave_resource *image, int enabled, | |||
615 | reg_split(pci_offset, &pci_offset_high, &pci_offset_low); | 624 | reg_split(pci_offset, &pci_offset_high, &pci_offset_low); |
616 | 625 | ||
617 | if (vme_base_low & (granularity - 1)) { | 626 | if (vme_base_low & (granularity - 1)) { |
618 | printk("Invalid VME base alignment\n"); | 627 | dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n"); |
619 | return -EINVAL; | 628 | return -EINVAL; |
620 | } | 629 | } |
621 | if (vme_bound_low & (granularity - 1)) { | 630 | if (vme_bound_low & (granularity - 1)) { |
622 | printk("Invalid VME bound alignment\n"); | 631 | dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n"); |
623 | return -EINVAL; | 632 | return -EINVAL; |
624 | } | 633 | } |
625 | if (pci_offset_low & (granularity - 1)) { | 634 | if (pci_offset_low & (granularity - 1)) { |
626 | printk("Invalid PCI Offset alignment\n"); | 635 | dev_err(tsi148_bridge->parent, "Invalid PCI Offset " |
636 | "alignment\n"); | ||
627 | return -EINVAL; | 637 | return -EINVAL; |
628 | } | 638 | } |
629 | 639 | ||
@@ -815,12 +825,7 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, | |||
815 | 825 | ||
816 | tsi148_bridge = image->parent; | 826 | tsi148_bridge = image->parent; |
817 | 827 | ||
818 | /* Find pci_dev container of dev */ | 828 | pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev); |
819 | if (tsi148_bridge->parent == NULL) { | ||
820 | printk("Dev entry NULL\n"); | ||
821 | return -EINVAL; | ||
822 | } | ||
823 | pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev); | ||
824 | 829 | ||
825 | existing_size = (unsigned long long)(image->bus_resource.end - | 830 | existing_size = (unsigned long long)(image->bus_resource.end - |
826 | image->bus_resource.start); | 831 | image->bus_resource.start); |
@@ -846,8 +851,8 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, | |||
846 | if (image->bus_resource.name == NULL) { | 851 | if (image->bus_resource.name == NULL) { |
847 | image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); | 852 | image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); |
848 | if (image->bus_resource.name == NULL) { | 853 | if (image->bus_resource.name == NULL) { |
849 | printk(KERN_ERR "Unable to allocate memory for resource" | 854 | dev_err(tsi148_bridge->parent, "Unable to allocate " |
850 | " name\n"); | 855 | "memory for resource name\n"); |
851 | retval = -ENOMEM; | 856 | retval = -ENOMEM; |
852 | goto err_name; | 857 | goto err_name; |
853 | } | 858 | } |
@@ -864,8 +869,8 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, | |||
864 | &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, | 869 | &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, |
865 | 0, NULL, NULL); | 870 | 0, NULL, NULL); |
866 | if (retval) { | 871 | if (retval) { |
867 | printk(KERN_ERR "Failed to allocate mem resource for " | 872 | dev_err(tsi148_bridge->parent, "Failed to allocate mem " |
868 | "window %d size 0x%lx start 0x%lx\n", | 873 | "resource for window %d size 0x%lx start 0x%lx\n", |
869 | image->number, (unsigned long)size, | 874 | image->number, (unsigned long)size, |
870 | (unsigned long)image->bus_resource.start); | 875 | (unsigned long)image->bus_resource.start); |
871 | goto err_resource; | 876 | goto err_resource; |
@@ -874,7 +879,7 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, | |||
874 | image->kern_base = ioremap_nocache( | 879 | image->kern_base = ioremap_nocache( |
875 | image->bus_resource.start, size); | 880 | image->bus_resource.start, size); |
876 | if (image->kern_base == NULL) { | 881 | if (image->kern_base == NULL) { |
877 | printk(KERN_ERR "Failed to remap resource\n"); | 882 | dev_err(tsi148_bridge->parent, "Failed to remap resource\n"); |
878 | retval = -ENOMEM; | 883 | retval = -ENOMEM; |
879 | goto err_remap; | 884 | goto err_remap; |
880 | } | 885 | } |
@@ -918,19 +923,24 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, | |||
918 | unsigned int pci_bound_low, pci_bound_high; | 923 | unsigned int pci_bound_low, pci_bound_high; |
919 | unsigned int vme_offset_low, vme_offset_high; | 924 | unsigned int vme_offset_low, vme_offset_high; |
920 | unsigned long long pci_bound, vme_offset, pci_base; | 925 | unsigned long long pci_bound, vme_offset, pci_base; |
926 | struct vme_bridge *tsi148_bridge; | ||
921 | struct tsi148_driver *bridge; | 927 | struct tsi148_driver *bridge; |
922 | 928 | ||
923 | bridge = image->parent->driver_priv; | 929 | tsi148_bridge = image->parent; |
930 | |||
931 | bridge = tsi148_bridge->driver_priv; | ||
924 | 932 | ||
925 | /* Verify input data */ | 933 | /* Verify input data */ |
926 | if (vme_base & 0xFFFF) { | 934 | if (vme_base & 0xFFFF) { |
927 | printk(KERN_ERR "Invalid VME Window alignment\n"); | 935 | dev_err(tsi148_bridge->parent, "Invalid VME Window " |
936 | "alignment\n"); | ||
928 | retval = -EINVAL; | 937 | retval = -EINVAL; |
929 | goto err_window; | 938 | goto err_window; |
930 | } | 939 | } |
931 | 940 | ||
932 | if ((size == 0) && (enabled != 0)) { | 941 | if ((size == 0) && (enabled != 0)) { |
933 | printk(KERN_ERR "Size must be non-zero for enabled windows\n"); | 942 | dev_err(tsi148_bridge->parent, "Size must be non-zero for " |
943 | "enabled windows\n"); | ||
934 | retval = -EINVAL; | 944 | retval = -EINVAL; |
935 | goto err_window; | 945 | goto err_window; |
936 | } | 946 | } |
@@ -944,7 +954,7 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, | |||
944 | retval = tsi148_alloc_resource(image, size); | 954 | retval = tsi148_alloc_resource(image, size); |
945 | if (retval) { | 955 | if (retval) { |
946 | spin_unlock(&(image->lock)); | 956 | spin_unlock(&(image->lock)); |
947 | printk(KERN_ERR "Unable to allocate memory for " | 957 | dev_err(tsi148_bridge->parent, "Unable to allocate memory for " |
948 | "resource\n"); | 958 | "resource\n"); |
949 | goto err_res; | 959 | goto err_res; |
950 | } | 960 | } |
@@ -971,19 +981,20 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, | |||
971 | 981 | ||
972 | if (pci_base_low & 0xFFFF) { | 982 | if (pci_base_low & 0xFFFF) { |
973 | spin_unlock(&(image->lock)); | 983 | spin_unlock(&(image->lock)); |
974 | printk(KERN_ERR "Invalid PCI base alignment\n"); | 984 | dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n"); |
975 | retval = -EINVAL; | 985 | retval = -EINVAL; |
976 | goto err_gran; | 986 | goto err_gran; |
977 | } | 987 | } |
978 | if (pci_bound_low & 0xFFFF) { | 988 | if (pci_bound_low & 0xFFFF) { |
979 | spin_unlock(&(image->lock)); | 989 | spin_unlock(&(image->lock)); |
980 | printk(KERN_ERR "Invalid PCI bound alignment\n"); | 990 | dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n"); |
981 | retval = -EINVAL; | 991 | retval = -EINVAL; |
982 | goto err_gran; | 992 | goto err_gran; |
983 | } | 993 | } |
984 | if (vme_offset_low & 0xFFFF) { | 994 | if (vme_offset_low & 0xFFFF) { |
985 | spin_unlock(&(image->lock)); | 995 | spin_unlock(&(image->lock)); |
986 | printk(KERN_ERR "Invalid VME Offset alignment\n"); | 996 | dev_err(tsi148_bridge->parent, "Invalid VME Offset " |
997 | "alignment\n"); | ||
987 | retval = -EINVAL; | 998 | retval = -EINVAL; |
988 | goto err_gran; | 999 | goto err_gran; |
989 | } | 1000 | } |
@@ -1029,8 +1040,8 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, | |||
1029 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST; | 1040 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST; |
1030 | } | 1041 | } |
1031 | if (cycle & VME_2eSSTB) { | 1042 | if (cycle & VME_2eSSTB) { |
1032 | printk(KERN_WARNING "Currently not setting Broadcast Select " | 1043 | dev_warn(tsi148_bridge->parent, "Currently not setting " |
1033 | "Registers\n"); | 1044 | "Broadcast Select Registers\n"); |
1034 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; | 1045 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; |
1035 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB; | 1046 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB; |
1036 | } | 1047 | } |
@@ -1046,7 +1057,7 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, | |||
1046 | break; | 1057 | break; |
1047 | default: | 1058 | default: |
1048 | spin_unlock(&(image->lock)); | 1059 | spin_unlock(&(image->lock)); |
1049 | printk(KERN_ERR "Invalid data width\n"); | 1060 | dev_err(tsi148_bridge->parent, "Invalid data width\n"); |
1050 | retval = -EINVAL; | 1061 | retval = -EINVAL; |
1051 | goto err_dwidth; | 1062 | goto err_dwidth; |
1052 | } | 1063 | } |
@@ -1083,7 +1094,7 @@ int tsi148_master_set( struct vme_master_resource *image, int enabled, | |||
1083 | break; | 1094 | break; |
1084 | default: | 1095 | default: |
1085 | spin_unlock(&(image->lock)); | 1096 | spin_unlock(&(image->lock)); |
1086 | printk(KERN_ERR "Invalid address space\n"); | 1097 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
1087 | retval = -EINVAL; | 1098 | retval = -EINVAL; |
1088 | goto err_aspace; | 1099 | goto err_aspace; |
1089 | break; | 1100 | break; |
@@ -1353,8 +1364,8 @@ ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, | |||
1353 | vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, | 1364 | vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, |
1354 | count); | 1365 | count); |
1355 | if(vme_err != NULL) { | 1366 | if(vme_err != NULL) { |
1356 | printk("First VME write error detected an at address 0x%llx\n", | 1367 | dev_warn(tsi148_bridge->parent, "First VME write error detected" |
1357 | vme_err->address); | 1368 | " an at address 0x%llx\n", vme_err->address); |
1358 | retval = vme_err->address - (vme_base + offset); | 1369 | retval = vme_err->address - (vme_base + offset); |
1359 | /* Clear down save errors in this address range */ | 1370 | /* Clear down save errors in this address range */ |
1360 | tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, | 1371 | tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, |
@@ -1428,8 +1439,8 @@ unsigned int tsi148_master_rmw(struct vme_master_resource *image, | |||
1428 | return result; | 1439 | return result; |
1429 | } | 1440 | } |
1430 | 1441 | ||
1431 | static int tsi148_dma_set_vme_src_attributes (u32 *attr, vme_address_t aspace, | 1442 | static int tsi148_dma_set_vme_src_attributes(struct device *dev, u32 *attr, |
1432 | vme_cycle_t cycle, vme_width_t dwidth) | 1443 | vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) |
1433 | { | 1444 | { |
1434 | /* Setup 2eSST speeds */ | 1445 | /* Setup 2eSST speeds */ |
1435 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { | 1446 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { |
@@ -1461,7 +1472,8 @@ static int tsi148_dma_set_vme_src_attributes (u32 *attr, vme_address_t aspace, | |||
1461 | *attr |= TSI148_LCSR_DSAT_TM_2eSST; | 1472 | *attr |= TSI148_LCSR_DSAT_TM_2eSST; |
1462 | } | 1473 | } |
1463 | if (cycle & VME_2eSSTB) { | 1474 | if (cycle & VME_2eSSTB) { |
1464 | printk("Currently not setting Broadcast Select Registers\n"); | 1475 | dev_err(dev, "Currently not setting Broadcast Select " |
1476 | "Registers\n"); | ||
1465 | *attr |= TSI148_LCSR_DSAT_TM_2eSSTB; | 1477 | *attr |= TSI148_LCSR_DSAT_TM_2eSSTB; |
1466 | } | 1478 | } |
1467 | 1479 | ||
@@ -1474,7 +1486,7 @@ static int tsi148_dma_set_vme_src_attributes (u32 *attr, vme_address_t aspace, | |||
1474 | *attr |= TSI148_LCSR_DSAT_DBW_32; | 1486 | *attr |= TSI148_LCSR_DSAT_DBW_32; |
1475 | break; | 1487 | break; |
1476 | default: | 1488 | default: |
1477 | printk("Invalid data width\n"); | 1489 | dev_err(dev, "Invalid data width\n"); |
1478 | return -EINVAL; | 1490 | return -EINVAL; |
1479 | } | 1491 | } |
1480 | 1492 | ||
@@ -1508,7 +1520,7 @@ static int tsi148_dma_set_vme_src_attributes (u32 *attr, vme_address_t aspace, | |||
1508 | *attr |= TSI148_LCSR_DSAT_AMODE_USER4; | 1520 | *attr |= TSI148_LCSR_DSAT_AMODE_USER4; |
1509 | break; | 1521 | break; |
1510 | default: | 1522 | default: |
1511 | printk("Invalid address space\n"); | 1523 | dev_err(dev, "Invalid address space\n"); |
1512 | return -EINVAL; | 1524 | return -EINVAL; |
1513 | break; | 1525 | break; |
1514 | } | 1526 | } |
@@ -1521,8 +1533,8 @@ static int tsi148_dma_set_vme_src_attributes (u32 *attr, vme_address_t aspace, | |||
1521 | return 0; | 1533 | return 0; |
1522 | } | 1534 | } |
1523 | 1535 | ||
1524 | static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace, | 1536 | static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr, |
1525 | vme_cycle_t cycle, vme_width_t dwidth) | 1537 | vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) |
1526 | { | 1538 | { |
1527 | /* Setup 2eSST speeds */ | 1539 | /* Setup 2eSST speeds */ |
1528 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { | 1540 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { |
@@ -1554,7 +1566,8 @@ static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace, | |||
1554 | *attr |= TSI148_LCSR_DDAT_TM_2eSST; | 1566 | *attr |= TSI148_LCSR_DDAT_TM_2eSST; |
1555 | } | 1567 | } |
1556 | if (cycle & VME_2eSSTB) { | 1568 | if (cycle & VME_2eSSTB) { |
1557 | printk("Currently not setting Broadcast Select Registers\n"); | 1569 | dev_err(dev, "Currently not setting Broadcast Select " |
1570 | "Registers\n"); | ||
1558 | *attr |= TSI148_LCSR_DDAT_TM_2eSSTB; | 1571 | *attr |= TSI148_LCSR_DDAT_TM_2eSSTB; |
1559 | } | 1572 | } |
1560 | 1573 | ||
@@ -1567,7 +1580,7 @@ static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace, | |||
1567 | *attr |= TSI148_LCSR_DDAT_DBW_32; | 1580 | *attr |= TSI148_LCSR_DDAT_DBW_32; |
1568 | break; | 1581 | break; |
1569 | default: | 1582 | default: |
1570 | printk("Invalid data width\n"); | 1583 | dev_err(dev, "Invalid data width\n"); |
1571 | return -EINVAL; | 1584 | return -EINVAL; |
1572 | } | 1585 | } |
1573 | 1586 | ||
@@ -1601,7 +1614,7 @@ static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace, | |||
1601 | *attr |= TSI148_LCSR_DDAT_AMODE_USER4; | 1614 | *attr |= TSI148_LCSR_DDAT_AMODE_USER4; |
1602 | break; | 1615 | break; |
1603 | default: | 1616 | default: |
1604 | printk("Invalid address space\n"); | 1617 | dev_err(dev, "Invalid address space\n"); |
1605 | return -EINVAL; | 1618 | return -EINVAL; |
1606 | break; | 1619 | break; |
1607 | } | 1620 | } |
@@ -1627,21 +1640,25 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src, | |||
1627 | struct vme_dma_vme *vme_attr; | 1640 | struct vme_dma_vme *vme_attr; |
1628 | dma_addr_t desc_ptr; | 1641 | dma_addr_t desc_ptr; |
1629 | int retval = 0; | 1642 | int retval = 0; |
1643 | struct vme_bridge *tsi148_bridge; | ||
1644 | |||
1645 | tsi148_bridge = list->parent->parent; | ||
1630 | 1646 | ||
1631 | /* Descriptor must be aligned on 64-bit boundaries */ | 1647 | /* Descriptor must be aligned on 64-bit boundaries */ |
1632 | entry = (struct tsi148_dma_entry *)kmalloc( | 1648 | entry = (struct tsi148_dma_entry *)kmalloc( |
1633 | sizeof(struct tsi148_dma_entry), GFP_KERNEL); | 1649 | sizeof(struct tsi148_dma_entry), GFP_KERNEL); |
1634 | if (entry == NULL) { | 1650 | if (entry == NULL) { |
1635 | printk("Failed to allocate memory for dma resource " | 1651 | dev_err(tsi148_bridge->parent, "Failed to allocate memory for " |
1636 | "structure\n"); | 1652 | "dma resource structure\n"); |
1637 | retval = -ENOMEM; | 1653 | retval = -ENOMEM; |
1638 | goto err_mem; | 1654 | goto err_mem; |
1639 | } | 1655 | } |
1640 | 1656 | ||
1641 | /* Test descriptor alignment */ | 1657 | /* Test descriptor alignment */ |
1642 | if ((unsigned long)&(entry->descriptor) & 0x7) { | 1658 | if ((unsigned long)&(entry->descriptor) & 0x7) { |
1643 | printk("Descriptor not aligned to 8 byte boundary as " | 1659 | dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 " |
1644 | "required: %p\n", &(entry->descriptor)); | 1660 | "byte boundary as required: %p\n", |
1661 | &(entry->descriptor)); | ||
1645 | retval = -EINVAL; | 1662 | retval = -EINVAL; |
1646 | goto err_align; | 1663 | goto err_align; |
1647 | } | 1664 | } |
@@ -1686,13 +1703,13 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src, | |||
1686 | entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME; | 1703 | entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME; |
1687 | 1704 | ||
1688 | retval = tsi148_dma_set_vme_src_attributes( | 1705 | retval = tsi148_dma_set_vme_src_attributes( |
1689 | &(entry->descriptor.dsat), vme_attr->aspace, | 1706 | tsi148_bridge->parent, &(entry->descriptor.dsat), |
1690 | vme_attr->cycle, vme_attr->dwidth); | 1707 | vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); |
1691 | if(retval < 0 ) | 1708 | if(retval < 0 ) |
1692 | goto err_source; | 1709 | goto err_source; |
1693 | break; | 1710 | break; |
1694 | default: | 1711 | default: |
1695 | printk("Invalid source type\n"); | 1712 | dev_err(tsi148_bridge->parent, "Invalid source type\n"); |
1696 | retval = -EINVAL; | 1713 | retval = -EINVAL; |
1697 | goto err_source; | 1714 | goto err_source; |
1698 | break; | 1715 | break; |
@@ -1724,13 +1741,13 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src, | |||
1724 | entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME; | 1741 | entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME; |
1725 | 1742 | ||
1726 | retval = tsi148_dma_set_vme_dest_attributes( | 1743 | retval = tsi148_dma_set_vme_dest_attributes( |
1727 | &(entry->descriptor.ddat), vme_attr->aspace, | 1744 | tsi148_bridge->parent, &(entry->descriptor.ddat), |
1728 | vme_attr->cycle, vme_attr->dwidth); | 1745 | vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); |
1729 | if(retval < 0 ) | 1746 | if(retval < 0 ) |
1730 | goto err_dest; | 1747 | goto err_dest; |
1731 | break; | 1748 | break; |
1732 | default: | 1749 | default: |
1733 | printk("Invalid destination type\n"); | 1750 | dev_err(tsi148_bridge->parent, "Invalid destination type\n"); |
1734 | retval = -EINVAL; | 1751 | retval = -EINVAL; |
1735 | goto err_dest; | 1752 | goto err_dest; |
1736 | break; | 1753 | break; |
@@ -1795,11 +1812,14 @@ int tsi148_dma_list_exec(struct vme_dma_list *list) | |||
1795 | dma_addr_t bus_addr; | 1812 | dma_addr_t bus_addr; |
1796 | u32 bus_addr_high, bus_addr_low; | 1813 | u32 bus_addr_high, bus_addr_low; |
1797 | u32 val, dctlreg = 0; | 1814 | u32 val, dctlreg = 0; |
1815 | struct vme_bridge *tsi148_bridge; | ||
1798 | struct tsi148_driver *bridge; | 1816 | struct tsi148_driver *bridge; |
1799 | 1817 | ||
1800 | ctrlr = list->parent; | 1818 | ctrlr = list->parent; |
1801 | 1819 | ||
1802 | bridge = ctrlr->parent->driver_priv; | 1820 | tsi148_bridge = ctrlr->parent; |
1821 | |||
1822 | bridge = tsi148_bridge->driver_priv; | ||
1803 | 1823 | ||
1804 | mutex_lock(&(ctrlr->mtx)); | 1824 | mutex_lock(&(ctrlr->mtx)); |
1805 | 1825 | ||
@@ -1847,7 +1867,7 @@ int tsi148_dma_list_exec(struct vme_dma_list *list) | |||
1847 | TSI148_LCSR_OFFSET_DSTA); | 1867 | TSI148_LCSR_OFFSET_DSTA); |
1848 | 1868 | ||
1849 | if (val & TSI148_LCSR_DSTA_VBE) { | 1869 | if (val & TSI148_LCSR_DSTA_VBE) { |
1850 | printk(KERN_ERR "tsi148: DMA Error. DSTA=%08X\n", val); | 1870 | dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val); |
1851 | retval = -EIO; | 1871 | retval = -EIO; |
1852 | } | 1872 | } |
1853 | 1873 | ||
@@ -1891,9 +1911,12 @@ int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, | |||
1891 | { | 1911 | { |
1892 | u32 lm_base_high, lm_base_low, lm_ctl = 0; | 1912 | u32 lm_base_high, lm_base_low, lm_ctl = 0; |
1893 | int i; | 1913 | int i; |
1914 | struct vme_bridge *tsi148_bridge; | ||
1894 | struct tsi148_driver *bridge; | 1915 | struct tsi148_driver *bridge; |
1895 | 1916 | ||
1896 | bridge = lm->parent->driver_priv; | 1917 | tsi148_bridge = lm->parent; |
1918 | |||
1919 | bridge = tsi148_bridge->driver_priv; | ||
1897 | 1920 | ||
1898 | mutex_lock(&(lm->mtx)); | 1921 | mutex_lock(&(lm->mtx)); |
1899 | 1922 | ||
@@ -1901,8 +1924,8 @@ int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, | |||
1901 | for (i = 0; i < lm->monitors; i++) { | 1924 | for (i = 0; i < lm->monitors; i++) { |
1902 | if (bridge->lm_callback[i] != NULL) { | 1925 | if (bridge->lm_callback[i] != NULL) { |
1903 | mutex_unlock(&(lm->mtx)); | 1926 | mutex_unlock(&(lm->mtx)); |
1904 | printk("Location monitor callback attached, can't " | 1927 | dev_err(tsi148_bridge->parent, "Location monitor " |
1905 | "reset\n"); | 1928 | "callback attached, can't reset\n"); |
1906 | return -EBUSY; | 1929 | return -EBUSY; |
1907 | } | 1930 | } |
1908 | } | 1931 | } |
@@ -1922,7 +1945,7 @@ int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, | |||
1922 | break; | 1945 | break; |
1923 | default: | 1946 | default: |
1924 | mutex_unlock(&(lm->mtx)); | 1947 | mutex_unlock(&(lm->mtx)); |
1925 | printk("Invalid address space\n"); | 1948 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
1926 | return -EINVAL; | 1949 | return -EINVAL; |
1927 | break; | 1950 | break; |
1928 | } | 1951 | } |
@@ -2005,9 +2028,12 @@ int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, | |||
2005 | void (*callback)(int)) | 2028 | void (*callback)(int)) |
2006 | { | 2029 | { |
2007 | u32 lm_ctl, tmp; | 2030 | u32 lm_ctl, tmp; |
2031 | struct vme_bridge *tsi148_bridge; | ||
2008 | struct tsi148_driver *bridge; | 2032 | struct tsi148_driver *bridge; |
2009 | 2033 | ||
2010 | bridge = lm->parent->driver_priv; | 2034 | tsi148_bridge = lm->parent; |
2035 | |||
2036 | bridge = tsi148_bridge->driver_priv; | ||
2011 | 2037 | ||
2012 | mutex_lock(&(lm->mtx)); | 2038 | mutex_lock(&(lm->mtx)); |
2013 | 2039 | ||
@@ -2015,14 +2041,15 @@ int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, | |||
2015 | lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); | 2041 | lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); |
2016 | if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) { | 2042 | if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) { |
2017 | mutex_unlock(&(lm->mtx)); | 2043 | mutex_unlock(&(lm->mtx)); |
2018 | printk("Location monitor not properly configured\n"); | 2044 | dev_err(tsi148_bridge->parent, "Location monitor not properly " |
2045 | "configured\n"); | ||
2019 | return -EINVAL; | 2046 | return -EINVAL; |
2020 | } | 2047 | } |
2021 | 2048 | ||
2022 | /* Check that a callback isn't already attached */ | 2049 | /* Check that a callback isn't already attached */ |
2023 | if (bridge->lm_callback[monitor] != NULL) { | 2050 | if (bridge->lm_callback[monitor] != NULL) { |
2024 | mutex_unlock(&(lm->mtx)); | 2051 | mutex_unlock(&(lm->mtx)); |
2025 | printk("Existing callback attached\n"); | 2052 | dev_err(tsi148_bridge->parent, "Existing callback attached\n"); |
2026 | return -EBUSY; | 2053 | return -EBUSY; |
2027 | } | 2054 | } |
2028 | 2055 | ||
@@ -2139,8 +2166,8 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, | |||
2139 | bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, | 2166 | bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, |
2140 | &(bridge->crcsr_bus)); | 2167 | &(bridge->crcsr_bus)); |
2141 | if (bridge->crcsr_kernel == NULL) { | 2168 | if (bridge->crcsr_kernel == NULL) { |
2142 | dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR " | 2169 | dev_err(tsi148_bridge->parent, "Failed to allocate memory for " |
2143 | "image\n"); | 2170 | "CR/CSR image\n"); |
2144 | return -ENOMEM; | 2171 | return -ENOMEM; |
2145 | } | 2172 | } |
2146 | 2173 | ||
@@ -2159,18 +2186,18 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, | |||
2159 | 2186 | ||
2160 | if (cbar != vstat) { | 2187 | if (cbar != vstat) { |
2161 | cbar = vstat; | 2188 | cbar = vstat; |
2162 | dev_info(&pdev->dev, "Setting CR/CSR offset\n"); | 2189 | dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n"); |
2163 | iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); | 2190 | iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); |
2164 | } | 2191 | } |
2165 | dev_info(&pdev->dev, "CR/CSR Offset: %d\n", cbar); | 2192 | dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); |
2166 | 2193 | ||
2167 | crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); | 2194 | crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); |
2168 | if (crat & TSI148_LCSR_CRAT_EN) { | 2195 | if (crat & TSI148_LCSR_CRAT_EN) { |
2169 | dev_info(&pdev->dev, "Enabling CR/CSR space\n"); | 2196 | dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n"); |
2170 | iowrite32be(crat | TSI148_LCSR_CRAT_EN, | 2197 | iowrite32be(crat | TSI148_LCSR_CRAT_EN, |
2171 | bridge->base + TSI148_LCSR_CRAT); | 2198 | bridge->base + TSI148_LCSR_CRAT); |
2172 | } else | 2199 | } else |
2173 | dev_info(&pdev->dev, "CR/CSR already enabled\n"); | 2200 | dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n"); |
2174 | 2201 | ||
2175 | /* If we want flushed, error-checked writes, set up a window | 2202 | /* If we want flushed, error-checked writes, set up a window |
2176 | * over the CR/CSR registers. We read from here to safely flush | 2203 | * over the CR/CSR registers. We read from here to safely flush |
@@ -2181,7 +2208,8 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, | |||
2181 | (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT, | 2208 | (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT, |
2182 | VME_D16); | 2209 | VME_D16); |
2183 | if (retval) | 2210 | if (retval) |
2184 | dev_err(&pdev->dev, "Configuring flush image failed\n"); | 2211 | dev_err(tsi148_bridge->parent, "Configuring flush image" |
2212 | " failed\n"); | ||
2185 | } | 2213 | } |
2186 | 2214 | ||
2187 | return 0; | 2215 | return 0; |
@@ -2623,8 +2651,6 @@ static void tsi148_remove(struct pci_dev *pdev) | |||
2623 | static void __exit tsi148_exit(void) | 2651 | static void __exit tsi148_exit(void) |
2624 | { | 2652 | { |
2625 | pci_unregister_driver(&tsi148_driver); | 2653 | pci_unregister_driver(&tsi148_driver); |
2626 | |||
2627 | printk(KERN_DEBUG "Driver removed.\n"); | ||
2628 | } | 2654 | } |
2629 | 2655 | ||
2630 | MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes"); | 2656 | MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes"); |