diff options
author | Jerry Chuang <jerry-chuang@realtek.com> | 2009-11-03 04:17:11 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-12-11 15:23:22 -0500 |
commit | 8fc8598e61f6f384f3eaf1d9b09500c12af47b37 (patch) | |
tree | 28045c6c72a4e1046feb96e06114eb69b14dacd6 /drivers/staging/rtl8192u/r8192U_hw.h | |
parent | 9b8437574759a4ce165ab20c631cd6e14c3148c2 (diff) |
Staging: Added Realtek rtl8192u driver to staging
Add Realtek linux driver for rtl8192u as provided by Realtek
rtl8192u_linux_2.6.0006.1031.2008.tar.gz, send to me C/C staging ML.
This version won't compile against upstream, doesn't follow
Linux CodingStyle and has their own ieee80211 stack.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/rtl8192u/r8192U_hw.h')
-rw-r--r-- | drivers/staging/rtl8192u/r8192U_hw.h | 746 |
1 files changed, 746 insertions, 0 deletions
diff --git a/drivers/staging/rtl8192u/r8192U_hw.h b/drivers/staging/rtl8192u/r8192U_hw.h new file mode 100644 index 00000000000..1ebacc9c66f --- /dev/null +++ b/drivers/staging/rtl8192u/r8192U_hw.h | |||
@@ -0,0 +1,746 @@ | |||
1 | /* | ||
2 | This is part of rtl8187 OpenSource driver. | ||
3 | Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> | ||
4 | Released under the terms of GPL (General Public Licence) | ||
5 | |||
6 | Parts of this driver are based on the GPL part of the | ||
7 | official Realtek driver. | ||
8 | Parts of this driver are based on the rtl8180 driver skeleton | ||
9 | from Patric Schenke & Andres Salomon. | ||
10 | Parts of this driver are based on the Intel Pro Wireless | ||
11 | 2100 GPL driver. | ||
12 | |||
13 | We want to tanks the Authors of those projects | ||
14 | and the Ndiswrapper project Authors. | ||
15 | */ | ||
16 | |||
17 | /* Mariusz Matuszek added full registers definition with Realtek's name */ | ||
18 | |||
19 | /* this file contains register definitions for the rtl8187 MAC controller */ | ||
20 | #ifndef R8192_HW | ||
21 | #define R8192_HW | ||
22 | |||
23 | typedef enum _VERSION_819xU{ | ||
24 | VERSION_819xU_A, // A-cut | ||
25 | VERSION_819xU_B, // B-cut | ||
26 | VERSION_819xU_C,// C-cut | ||
27 | }VERSION_819xU,*PVERSION_819xU; | ||
28 | //added for different RF type | ||
29 | typedef enum _RT_RF_TYPE_DEF | ||
30 | { | ||
31 | RF_1T2R = 0, | ||
32 | RF_2T4R, | ||
33 | |||
34 | RF_819X_MAX_TYPE | ||
35 | }RT_RF_TYPE_DEF; | ||
36 | |||
37 | |||
38 | typedef enum _BaseBand_Config_Type{ | ||
39 | BaseBand_Config_PHY_REG = 0, //Radio Path A | ||
40 | BaseBand_Config_AGC_TAB = 1, //Radio Path B | ||
41 | }BaseBand_Config_Type, *PBaseBand_Config_Type; | ||
42 | #if 0 | ||
43 | typedef enum _RT_RF_TYPE_819xU{ | ||
44 | RF_TYPE_MIN = 0, | ||
45 | RF_8225, | ||
46 | RF_8256, | ||
47 | RF_8258, | ||
48 | RF_PSEUDO_11N = 4, | ||
49 | }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; | ||
50 | #endif | ||
51 | #define RTL8187_REQT_READ 0xc0 | ||
52 | #define RTL8187_REQT_WRITE 0x40 | ||
53 | #define RTL8187_REQ_GET_REGS 0x05 | ||
54 | #define RTL8187_REQ_SET_REGS 0x05 | ||
55 | |||
56 | #define MAX_TX_URB 5 | ||
57 | #define MAX_RX_URB 16 | ||
58 | |||
59 | #define R8180_MAX_RETRY 255 | ||
60 | //#define MAX_RX_NORMAL_URB 3 | ||
61 | //#define MAX_RX_COMMAND_URB 2 | ||
62 | #define RX_URB_SIZE 9100 | ||
63 | |||
64 | #define BB_ANTATTEN_CHAN14 0x0c | ||
65 | #define BB_ANTENNA_B 0x40 | ||
66 | |||
67 | #define BB_HOST_BANG (1<<30) | ||
68 | #define BB_HOST_BANG_EN (1<<2) | ||
69 | #define BB_HOST_BANG_CLK (1<<1) | ||
70 | #define BB_HOST_BANG_RW (1<<3) | ||
71 | #define BB_HOST_BANG_DATA 1 | ||
72 | |||
73 | //#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920) | ||
74 | #define AFR 0x010 | ||
75 | #define AFR_CardBEn (1<<0) | ||
76 | #define AFR_CLKRUN_SEL (1<<1) | ||
77 | #define AFR_FuncRegEn (1<<2) | ||
78 | #define RTL8190_EEPROM_ID 0x8129 | ||
79 | #define EEPROM_VID 0x02 | ||
80 | #define EEPROM_PID 0x04 | ||
81 | #define EEPROM_NODE_ADDRESS_BYTE_0 0x0C | ||
82 | |||
83 | #define EEPROM_TxPowerDiff 0x1F | ||
84 | #define EEPROM_ThermalMeter 0x20 | ||
85 | #define EEPROM_PwDiff 0x21 //0x21 | ||
86 | #define EEPROM_CrystalCap 0x22 //0x22 | ||
87 | |||
88 | #define EEPROM_TxPwIndex_CCK 0x23 //0x23 | ||
89 | #define EEPROM_TxPwIndex_OFDM_24G 0x24 //0x24~0x26 | ||
90 | #define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B | ||
91 | #define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E | ||
92 | #define EEPROM_TxPwIndex_Ver 0x27 //0x27 | ||
93 | |||
94 | #define EEPROM_Default_TxPowerDiff 0x0 | ||
95 | #define EEPROM_Default_ThermalMeter 0x7 | ||
96 | #define EEPROM_Default_PwDiff 0x4 | ||
97 | #define EEPROM_Default_CrystalCap 0x5 | ||
98 | #define EEPROM_Default_TxPower 0x1010 | ||
99 | #define EEPROM_Customer_ID 0x7B //0x7B:CustomerID | ||
100 | #define EEPROM_ChannelPlan 0x16 //0x7C | ||
101 | #define EEPROM_IC_VER 0x7d //0x7D | ||
102 | #define EEPROM_CRC 0x7e //0x7E~0x7F | ||
103 | |||
104 | #define EEPROM_CID_DEFAULT 0x0 | ||
105 | #define EEPROM_CID_CAMEO 0x1 | ||
106 | #define EEPROM_CID_RUNTOP 0x2 | ||
107 | #define EEPROM_CID_Senao 0x3 | ||
108 | #define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31 | ||
109 | #define EEPROM_CID_NetCore 0x5 | ||
110 | #define EEPROM_CID_Nettronix 0x6 | ||
111 | #define EEPROM_CID_Pronet 0x7 | ||
112 | #define EEPROM_CID_DLINK 0x8 | ||
113 | |||
114 | #define AC_PARAM_TXOP_LIMIT_OFFSET 16 | ||
115 | #define AC_PARAM_ECW_MAX_OFFSET 12 | ||
116 | #define AC_PARAM_ECW_MIN_OFFSET 8 | ||
117 | #define AC_PARAM_AIFS_OFFSET 0 | ||
118 | |||
119 | //#endif | ||
120 | enum _RTL8192Usb_HW { | ||
121 | |||
122 | PCIF = 0x009, // PCI Function Register 0x0009h~0x000bh | ||
123 | #define BB_GLOBAL_RESET_BIT 0x1 | ||
124 | BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register | ||
125 | BSSIDR = 0x02E, // BSSID Register | ||
126 | CMDR = 0x037, // Command register | ||
127 | #define CR_RST 0x10 | ||
128 | #define CR_RE 0x08 | ||
129 | #define CR_TE 0x04 | ||
130 | #define CR_MulRW 0x01 | ||
131 | SIFS = 0x03E, // SIFS register | ||
132 | TCR = 0x040, // Transmit Configuration Register | ||
133 | |||
134 | #define TCR_MXDMA_2048 7 | ||
135 | #define TCR_LRL_OFFSET 0 | ||
136 | #define TCR_SRL_OFFSET 8 | ||
137 | #define TCR_MXDMA_OFFSET 21 | ||
138 | #define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer | ||
139 | RCR = 0x044, // Receive Configuration Register | ||
140 | #define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ | ||
141 | (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) | ||
142 | #define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) | ||
143 | #define RX_FIFO_THRESHOLD_SHIFT 13 | ||
144 | #define RX_FIFO_THRESHOLD_128 3 | ||
145 | #define RX_FIFO_THRESHOLD_256 4 | ||
146 | #define RX_FIFO_THRESHOLD_512 5 | ||
147 | #define RX_FIFO_THRESHOLD_1024 6 | ||
148 | #define RX_FIFO_THRESHOLD_NONE 7 | ||
149 | #define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) | ||
150 | #define RCR_MXDMA_OFFSET 8 | ||
151 | #define RCR_FIFO_OFFSET 13 | ||
152 | #define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size. | ||
153 | #define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2 | ||
154 | #define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1 | ||
155 | #define RCR_ENMBID BIT27 // Enable Multiple BssId. | ||
156 | #define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames | ||
157 | #define RCR_CBSSID BIT23 // Accept BSSID match packet | ||
158 | #define RCR_APWRMGT BIT22 // Accept power management packet | ||
159 | #define RCR_ADD3 BIT21 // Accept address 3 match packet | ||
160 | #define RCR_AMF BIT20 // Accept management type frame | ||
161 | #define RCR_ACF BIT19 // Accept control type frame | ||
162 | #define RCR_ADF BIT18 // Accept data type frame | ||
163 | #define RCR_RXFTH BIT13 // Rx FIFO Threshold | ||
164 | #define RCR_AICV BIT12 // Accept ICV error packet | ||
165 | #define RCR_ACRC32 BIT5 // Accept CRC32 error packet | ||
166 | #define RCR_AB BIT3 // Accept broadcast packet | ||
167 | #define RCR_AM BIT2 // Accept multicast packet | ||
168 | #define RCR_APM BIT1 // Accept physical match packet | ||
169 | #define RCR_AAP BIT0 // Accept all unicast packet | ||
170 | SLOT_TIME = 0x049, // Slot Time Register | ||
171 | ACK_TIMEOUT = 0x04c, // Ack Timeout Register | ||
172 | PIFS_TIME = 0x04d, // PIFS time | ||
173 | USTIME = 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock. | ||
174 | EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE | ||
175 | EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK | ||
176 | EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO | ||
177 | EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI | ||
178 | RFPC = 0x05F, // Rx FIFO Packet Count | ||
179 | CWRR = 0x060, // Contention Window Report Register | ||
180 | BCN_TCFG = 0x062, // Beacon Time Configuration | ||
181 | #define BCN_TCFG_CW_SHIFT 8 | ||
182 | #define BCN_TCFG_IFS 0 | ||
183 | BCN_INTERVAL = 0x070, // Beacon Interval (TU) | ||
184 | ATIMWND = 0x072, // ATIM Window Size (TU) | ||
185 | BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT | ||
186 | BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA | ||
187 | BCN_ERR_THRESH = 0x078, // Beacon Error Threshold | ||
188 | RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd | ||
189 | WCAMI = 0x0A4, // Software write CAM input content | ||
190 | RCAMO = 0x0A8, // Software read/write CAM config | ||
191 | SECR = 0x0B0, //Security Configuration Register | ||
192 | #define SCR_TxUseDK BIT0 //Force Tx Use Default Key | ||
193 | #define SCR_RxUseDK BIT1 //Force Rx Use Default Key | ||
194 | #define SCR_TxEncEnable BIT2 //Enable Tx Encryption | ||
195 | #define SCR_RxDecEnable BIT3 //Enable Rx Decryption | ||
196 | #define SCR_SKByA2 BIT4 //Search kEY BY A2 | ||
197 | #define SCR_NoSKMC BIT5 //No Key Search for Multicast | ||
198 | #define SCR_UseDK 0x01 | ||
199 | #define SCR_TxSecEnable 0x02 | ||
200 | #define SCR_RxSecEnable 0x04 | ||
201 | TPPoll = 0x0fd, // Transmit priority polling register | ||
202 | PSR = 0x0ff, // Page Select Register | ||
203 | #define CPU_CCK_LOOPBACK 0x00030000 | ||
204 | #define CPU_GEN_SYSTEM_RESET 0x00000001 | ||
205 | #define CPU_GEN_FIRMWARE_RESET 0x00000008 | ||
206 | #define CPU_GEN_BOOT_RDY 0x00000010 | ||
207 | #define CPU_GEN_FIRM_RDY 0x00000020 | ||
208 | #define CPU_GEN_PUT_CODE_OK 0x00000080 | ||
209 | #define CPU_GEN_BB_RST 0x00000100 | ||
210 | #define CPU_GEN_PWR_STB_CPU 0x00000004 | ||
211 | #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 | ||
212 | #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 | ||
213 | |||
214 | //---------------------------------------------------------------------------- | ||
215 | // 8190 CPU General Register (offset 0x100, 4 byte) | ||
216 | //---------------------------------------------------------------------------- | ||
217 | #define CPU_CCK_LOOPBACK 0x00030000 | ||
218 | #define CPU_GEN_SYSTEM_RESET 0x00000001 | ||
219 | #define CPU_GEN_FIRMWARE_RESET 0x00000008 | ||
220 | #define CPU_GEN_BOOT_RDY 0x00000010 | ||
221 | #define CPU_GEN_FIRM_RDY 0x00000020 | ||
222 | #define CPU_GEN_PUT_CODE_OK 0x00000080 | ||
223 | #define CPU_GEN_BB_RST 0x00000100 | ||
224 | #define CPU_GEN_PWR_STB_CPU 0x00000004 | ||
225 | #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 | ||
226 | #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 | ||
227 | CPU_GEN = 0x100, // CPU Reset Register | ||
228 | LED1Cfg = 0x154,// LED1 Configuration Register | ||
229 | LED0Cfg = 0x155,// LED0 Configuration Register | ||
230 | |||
231 | AcmAvg = 0x170, // ACM Average Period Register | ||
232 | AcmHwCtrl = 0x171, // ACM Hardware Control Register | ||
233 | //---------------------------------------------------------------------------- | ||
234 | //// | ||
235 | //// 8190 AcmHwCtrl bits (offset 0x171, 1 byte) | ||
236 | ////---------------------------------------------------------------------------- | ||
237 | // | ||
238 | #define AcmHw_HwEn BIT0 | ||
239 | #define AcmHw_BeqEn BIT1 | ||
240 | #define AcmHw_ViqEn BIT2 | ||
241 | #define AcmHw_VoqEn BIT3 | ||
242 | #define AcmHw_BeqStatus BIT4 | ||
243 | #define AcmHw_ViqStatus BIT5 | ||
244 | #define AcmHw_VoqStatus BIT6 | ||
245 | |||
246 | AcmFwCtrl = 0x172, // ACM Firmware Control Register | ||
247 | AES_11N_FIX = 0x173, | ||
248 | VOAdmTime = 0x174, // VO Queue Admitted Time Register | ||
249 | VIAdmTime = 0x178, // VI Queue Admitted Time Register | ||
250 | BEAdmTime = 0x17C, // BE Queue Admitted Time Register | ||
251 | RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk | ||
252 | RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High | ||
253 | RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public, | ||
254 | // QPRR = 0x1E0, // Queue Page Report per TID | ||
255 | QPNR = 0x1D0, //0x1F0, // Queue Packet Number report per TID | ||
256 | BQDA = 0x200, // Beacon Queue Descriptor Address | ||
257 | HQDA = 0x204, // High Priority Queue Descriptor Address | ||
258 | CQDA = 0x208, // Command Queue Descriptor Address | ||
259 | MQDA = 0x20C, // Management Queue Descriptor Address | ||
260 | HCCAQDA = 0x210, // HCCA Queue Descriptor Address | ||
261 | VOQDA = 0x214, // VO Queue Descriptor Address | ||
262 | VIQDA = 0x218, // VI Queue Descriptor Address | ||
263 | BEQDA = 0x21C, // BE Queue Descriptor Address | ||
264 | BKQDA = 0x220, // BK Queue Descriptor Address | ||
265 | RCQDA = 0x224, // Receive command Queue Descriptor Address | ||
266 | RDQDA = 0x228, // Receive Queue Descriptor Start Address | ||
267 | |||
268 | MAR0 = 0x240, // Multicast filter. | ||
269 | MAR4 = 0x244, | ||
270 | |||
271 | CCX_PERIOD = 0x250, // CCX Measurement Period Register, in unit of TU. | ||
272 | CLM_RESULT = 0x251, // CCA Busy fraction register. | ||
273 | NHM_PERIOD = 0x252, // NHM Measurement Period register, in unit of TU. | ||
274 | |||
275 | NHM_THRESHOLD0 = 0x253, // Noise Histogram Meashorement0. | ||
276 | NHM_THRESHOLD1 = 0x254, // Noise Histogram Meashorement1. | ||
277 | NHM_THRESHOLD2 = 0x255, // Noise Histogram Meashorement2. | ||
278 | NHM_THRESHOLD3 = 0x256, // Noise Histogram Meashorement3. | ||
279 | NHM_THRESHOLD4 = 0x257, // Noise Histogram Meashorement4. | ||
280 | NHM_THRESHOLD5 = 0x258, // Noise Histogram Meashorement5. | ||
281 | NHM_THRESHOLD6 = 0x259, // Noise Histogram Meashorement6 | ||
282 | |||
283 | MCTRL = 0x25A, // Measurement Control | ||
284 | |||
285 | NHM_RPI_COUNTER0 = 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0. | ||
286 | NHM_RPI_COUNTER1 = 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1]. | ||
287 | NHM_RPI_COUNTER2 = 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2]. | ||
288 | NHM_RPI_COUNTER3 = 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3]. | ||
289 | NHM_RPI_COUNTER4 = 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4]. | ||
290 | NHM_RPI_COUNTER5 = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5]. | ||
291 | NHM_RPI_COUNTER6 = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6]. | ||
292 | NHM_RPI_COUNTER7 = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7]. | ||
293 | #define BW_OPMODE_11J BIT0 | ||
294 | #define BW_OPMODE_5G BIT1 | ||
295 | #define BW_OPMODE_20MHZ BIT2 | ||
296 | BW_OPMODE = 0x300, // Bandwidth operation mode | ||
297 | MSR = 0x303, // Media Status register | ||
298 | #define MSR_LINK_MASK ((1<<0)|(1<<1)) | ||
299 | #define MSR_LINK_MANAGED 2 | ||
300 | #define MSR_LINK_NONE 0 | ||
301 | #define MSR_LINK_SHIFT 0 | ||
302 | #define MSR_LINK_ADHOC 1 | ||
303 | #define MSR_LINK_MASTER 3 | ||
304 | #define MSR_LINK_ENEDCA (1<<4) | ||
305 | RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long | ||
306 | #define RETRY_LIMIT_SHORT_SHIFT 8 | ||
307 | #define RETRY_LIMIT_LONG_SHIFT 0 | ||
308 | TSFR = 0x308, | ||
309 | RRSR = 0x310, // Response Rate Set | ||
310 | #define RRSR_RSC_OFFSET 21 | ||
311 | #define RRSR_SHORT_OFFSET 23 | ||
312 | #define RRSR_RSC_DUPLICATE 0x600000 | ||
313 | #define RRSR_RSC_LOWSUBCHNL 0x400000 | ||
314 | #define RRSR_RSC_UPSUBCHANL 0x200000 | ||
315 | #define RRSR_SHORT 0x800000 | ||
316 | #define RRSR_1M BIT0 | ||
317 | #define RRSR_2M BIT1 | ||
318 | #define RRSR_5_5M BIT2 | ||
319 | #define RRSR_11M BIT3 | ||
320 | #define RRSR_6M BIT4 | ||
321 | #define RRSR_9M BIT5 | ||
322 | #define RRSR_12M BIT6 | ||
323 | #define RRSR_18M BIT7 | ||
324 | #define RRSR_24M BIT8 | ||
325 | #define RRSR_36M BIT9 | ||
326 | #define RRSR_48M BIT10 | ||
327 | #define RRSR_54M BIT11 | ||
328 | #define RRSR_MCS0 BIT12 | ||
329 | #define RRSR_MCS1 BIT13 | ||
330 | #define RRSR_MCS2 BIT14 | ||
331 | #define RRSR_MCS3 BIT15 | ||
332 | #define RRSR_MCS4 BIT16 | ||
333 | #define RRSR_MCS5 BIT17 | ||
334 | #define RRSR_MCS6 BIT18 | ||
335 | #define RRSR_MCS7 BIT19 | ||
336 | #define BRSR_AckShortPmb BIT23 // CCK ACK: use Short Preamble or not. | ||
337 | RATR0 = 0x320, // Rate Adaptive Table register1 | ||
338 | UFWP = 0x318, | ||
339 | DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI | ||
340 | //---------------------------------------------------------------------------- | ||
341 | // 8190 Rate Adaptive Table Register (offset 0x320, 4 byte) | ||
342 | //---------------------------------------------------------------------------- | ||
343 | //CCK | ||
344 | #define RATR_1M 0x00000001 | ||
345 | #define RATR_2M 0x00000002 | ||
346 | #define RATR_55M 0x00000004 | ||
347 | #define RATR_11M 0x00000008 | ||
348 | //OFDM | ||
349 | #define RATR_6M 0x00000010 | ||
350 | #define RATR_9M 0x00000020 | ||
351 | #define RATR_12M 0x00000040 | ||
352 | #define RATR_18M 0x00000080 | ||
353 | #define RATR_24M 0x00000100 | ||
354 | #define RATR_36M 0x00000200 | ||
355 | #define RATR_48M 0x00000400 | ||
356 | #define RATR_54M 0x00000800 | ||
357 | //MCS 1 Spatial Stream | ||
358 | #define RATR_MCS0 0x00001000 | ||
359 | #define RATR_MCS1 0x00002000 | ||
360 | #define RATR_MCS2 0x00004000 | ||
361 | #define RATR_MCS3 0x00008000 | ||
362 | #define RATR_MCS4 0x00010000 | ||
363 | #define RATR_MCS5 0x00020000 | ||
364 | #define RATR_MCS6 0x00040000 | ||
365 | #define RATR_MCS7 0x00080000 | ||
366 | //MCS 2 Spatial Stream | ||
367 | #define RATR_MCS8 0x00100000 | ||
368 | #define RATR_MCS9 0x00200000 | ||
369 | #define RATR_MCS10 0x00400000 | ||
370 | #define RATR_MCS11 0x00800000 | ||
371 | #define RATR_MCS12 0x01000000 | ||
372 | #define RATR_MCS13 0x02000000 | ||
373 | #define RATR_MCS14 0x04000000 | ||
374 | #define RATR_MCS15 0x08000000 | ||
375 | // ALL CCK Rate | ||
376 | #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M | ||
377 | #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\ | ||
378 | |RATR_36M|RATR_48M|RATR_54M | ||
379 | #define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \ | ||
380 | RATR_MCS4|RATR_MCS5|RATR_MCS6|RATR_MCS7 | ||
381 | #define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \ | ||
382 | RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 | ||
383 | |||
384 | MCS_TXAGC = 0x340, // MCS AGC | ||
385 | CCK_TXAGC = 0x348, // CCK AGC | ||
386 | // ISR = 0x350, // Interrupt Status Register | ||
387 | // IMR = 0x354, // Interrupt Mask Register | ||
388 | // IMR_POLL = 0x360, | ||
389 | MacBlkCtrl = 0x403, // Mac block on/off control register | ||
390 | |||
391 | EPROM_CMD = 0xfe58, | ||
392 | #define Cmd9346CR_9356SEL (1<<4) | ||
393 | #define EPROM_CMD_RESERVED_MASK (1<<5) | ||
394 | #define EPROM_CMD_OPERATING_MODE_SHIFT 6 | ||
395 | #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) | ||
396 | #define EPROM_CMD_CONFIG 0x3 | ||
397 | #define EPROM_CMD_NORMAL 0 | ||
398 | #define EPROM_CMD_LOAD 1 | ||
399 | #define EPROM_CMD_PROGRAM 2 | ||
400 | #define EPROM_CS_SHIFT 3 | ||
401 | #define EPROM_CK_SHIFT 2 | ||
402 | #define EPROM_W_SHIFT 1 | ||
403 | #define EPROM_R_SHIFT 0 | ||
404 | MAC0 = 0x000, | ||
405 | MAC1 = 0x001, | ||
406 | MAC2 = 0x002, | ||
407 | MAC3 = 0x003, | ||
408 | MAC4 = 0x004, | ||
409 | MAC5 = 0x005, | ||
410 | |||
411 | #if 0 | ||
412 | /* 0x0006 - 0x0007 - reserved */ | ||
413 | RXFIFOCOUNT = 0x010, | ||
414 | TXFIFOCOUNT = 0x012, | ||
415 | BQREQ = 0x013, | ||
416 | /* 0x0010 - 0x0017 - reserved */ | ||
417 | TSFTR = 0x018, | ||
418 | TLPDA = 0x020, | ||
419 | TNPDA = 0x024, | ||
420 | THPDA = 0x028, | ||
421 | BSSID = 0x02E, | ||
422 | RESP_RATE = 0x034, | ||
423 | CMD = 0x037, | ||
424 | #define CMD_RST_SHIFT 4 | ||
425 | #define CMD_RESERVED_MASK ((1<<1) | (1<<5) | (1<<6) | (1<<7)) | ||
426 | #define CMD_RX_ENABLE_SHIFT 3 | ||
427 | #define CMD_TX_ENABLE_SHIFT 2 | ||
428 | #define CR_RST ((1<< 4)) | ||
429 | #define CR_RE ((1<< 3)) | ||
430 | #define CR_TE ((1<< 2)) | ||
431 | #define CR_MulRW ((1<< 0)) | ||
432 | |||
433 | INTA_MASK = 0x03c, | ||
434 | INTA = 0x03e, | ||
435 | #define INTA_TXOVERFLOW (1<<15) | ||
436 | #define INTA_TIMEOUT (1<<14) | ||
437 | #define INTA_BEACONTIMEOUT (1<<13) | ||
438 | #define INTA_ATIM (1<<12) | ||
439 | #define INTA_BEACONDESCERR (1<<11) | ||
440 | #define INTA_BEACONDESCOK (1<<10) | ||
441 | #define INTA_HIPRIORITYDESCERR (1<<9) | ||
442 | #define INTA_HIPRIORITYDESCOK (1<<8) | ||
443 | #define INTA_NORMPRIORITYDESCERR (1<<7) | ||
444 | #define INTA_NORMPRIORITYDESCOK (1<<6) | ||
445 | #define INTA_RXOVERFLOW (1<<5) | ||
446 | #define INTA_RXDESCERR (1<<4) | ||
447 | #define INTA_LOWPRIORITYDESCERR (1<<3) | ||
448 | #define INTA_LOWPRIORITYDESCOK (1<<2) | ||
449 | #define INTA_RXCRCERR (1<<1) | ||
450 | #define INTA_RXOK (1) | ||
451 | TX_CONF = 0x040, | ||
452 | #define TX_CONF_HEADER_AUTOICREMENT_SHIFT 30 | ||
453 | #define TX_LOOPBACK_SHIFT 17 | ||
454 | #define TX_LOOPBACK_MAC 1 | ||
455 | #define TX_LOOPBACK_BASEBAND 2 | ||
456 | #define TX_LOOPBACK_NONE 0 | ||
457 | #define TX_LOOPBACK_CONTINUE 3 | ||
458 | #define TX_LOOPBACK_MASK ((1<<17)|(1<<18)) | ||
459 | #define TX_LRLRETRY_SHIFT 0 | ||
460 | #define TX_SRLRETRY_SHIFT 8 | ||
461 | #define TX_NOICV_SHIFT 19 | ||
462 | #define TX_NOCRC_SHIFT 16 | ||
463 | #define TCR_DurProcMode ((1<<30)) | ||
464 | #define TCR_DISReqQsize ((1<<28)) | ||
465 | #define TCR_HWVERID_MASK ((1<<27)|(1<<26)|(1<<25)) | ||
466 | #define TCR_HWVERID_SHIFT 25 | ||
467 | #define TCR_SWPLCPLEN ((1<<24)) | ||
468 | #define TCR_PLCP_LEN TCR_SAT // rtl8180 | ||
469 | #define TCR_MXDMA_MASK ((1<<23)|(1<<22)|(1<<21)) | ||
470 | #define TCR_MXDMA_1024 6 | ||
471 | #define TCR_MXDMA_2048 7 | ||
472 | #define TCR_MXDMA_SHIFT 21 | ||
473 | #define TCR_DISCW ((1<<20)) | ||
474 | #define TCR_ICV ((1<<19)) | ||
475 | #define TCR_LBK ((1<<18)|(1<<17)) | ||
476 | #define TCR_LBK1 ((1<<18)) | ||
477 | #define TCR_LBK0 ((1<<17)) | ||
478 | #define TCR_CRC ((1<<16)) | ||
479 | #define TCR_SRL_MASK ((1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)) | ||
480 | #define TCR_LRL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)) | ||
481 | #define TCR_PROBE_NOTIMESTAMP_SHIFT 29 //rtl8185 | ||
482 | RX_CONF = 0x044, | ||
483 | #define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ | ||
484 | (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) | ||
485 | #define RX_CHECK_BSSID_SHIFT 23 | ||
486 | #define ACCEPT_PWR_FRAME_SHIFT 22 | ||
487 | #define ACCEPT_MNG_FRAME_SHIFT 20 | ||
488 | #define ACCEPT_CTL_FRAME_SHIFT 19 | ||
489 | #define ACCEPT_DATA_FRAME_SHIFT 18 | ||
490 | #define ACCEPT_ICVERR_FRAME_SHIFT 12 | ||
491 | #define ACCEPT_CRCERR_FRAME_SHIFT 5 | ||
492 | #define ACCEPT_BCAST_FRAME_SHIFT 3 | ||
493 | #define ACCEPT_MCAST_FRAME_SHIFT 2 | ||
494 | #define ACCEPT_ALLMAC_FRAME_SHIFT 0 | ||
495 | #define ACCEPT_NICMAC_FRAME_SHIFT 1 | ||
496 | #define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) | ||
497 | #define RX_FIFO_THRESHOLD_SHIFT 13 | ||
498 | #define RX_FIFO_THRESHOLD_128 3 | ||
499 | #define RX_FIFO_THRESHOLD_256 4 | ||
500 | #define RX_FIFO_THRESHOLD_512 5 | ||
501 | #define RX_FIFO_THRESHOLD_1024 6 | ||
502 | #define RX_FIFO_THRESHOLD_NONE 7 | ||
503 | #define RX_AUTORESETPHY_SHIFT 28 | ||
504 | #define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) | ||
505 | #define MAX_RX_DMA_2048 7 | ||
506 | #define MAX_RX_DMA_1024 6 | ||
507 | #define MAX_RX_DMA_SHIFT 10 | ||
508 | #define RCR_ONLYERLPKT ((1<<31)) | ||
509 | #define RCR_CS_SHIFT 29 | ||
510 | #define RCR_CS_MASK ((1<<30) | (1<<29)) | ||
511 | #define RCR_ENMARP ((1<<28)) | ||
512 | #define RCR_CBSSID ((1<<23)) | ||
513 | #define RCR_APWRMGT ((1<<22)) | ||
514 | #define RCR_ADD3 ((1<<21)) | ||
515 | #define RCR_AMF ((1<<20)) | ||
516 | #define RCR_ACF ((1<<19)) | ||
517 | #define RCR_ADF ((1<<18)) | ||
518 | #define RCR_RXFTH ((1<<15)|(1<<14)|(1<<13)) | ||
519 | #define RCR_RXFTH2 ((1<<15)) | ||
520 | #define RCR_RXFTH1 ((1<<14)) | ||
521 | #define RCR_RXFTH0 ((1<<13)) | ||
522 | #define RCR_AICV ((1<<12)) | ||
523 | #define RCR_MXDMA ((1<<10)|(1<< 9)|(1<< 8)) | ||
524 | #define RCR_MXDMA2 ((1<<10)) | ||
525 | #define RCR_MXDMA1 ((1<< 9)) | ||
526 | #define RCR_MXDMA0 ((1<< 8)) | ||
527 | #define RCR_9356SEL ((1<< 6)) | ||
528 | #define RCR_ACRC32 ((1<< 5)) | ||
529 | #define RCR_AB ((1<< 3)) | ||
530 | #define RCR_AM ((1<< 2)) | ||
531 | #define RCR_APM ((1<< 1)) | ||
532 | #define RCR_AAP ((1<< 0)) | ||
533 | INT_TIMEOUT = 0x048, | ||
534 | TX_BEACON_RING_ADDR = 0x04c, | ||
535 | EPROM_CMD = 0x58, | ||
536 | #define EPROM_CMD_RESERVED_MASK ((1<<5)|(1<<4)) | ||
537 | #define EPROM_CMD_OPERATING_MODE_SHIFT 6 | ||
538 | #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) | ||
539 | #define EPROM_CMD_CONFIG 0x3 | ||
540 | #define EPROM_CMD_NORMAL 0 | ||
541 | #define EPROM_CMD_LOAD 1 | ||
542 | #define EPROM_CMD_PROGRAM 2 | ||
543 | #define EPROM_CS_SHIFT 3 | ||
544 | #define EPROM_CK_SHIFT 2 | ||
545 | #define EPROM_W_SHIFT 1 | ||
546 | #define EPROM_R_SHIFT 0 | ||
547 | CONFIG0 = 0x051, | ||
548 | #define CONFIG0_WEP104 ((1<<6)) | ||
549 | #define CONFIG0_LEDGPO_En ((1<<4)) | ||
550 | #define CONFIG0_Aux_Status ((1<<3)) | ||
551 | #define CONFIG0_GL ((1<<1)|(1<<0)) | ||
552 | #define CONFIG0_GL1 ((1<<1)) | ||
553 | #define CONFIG0_GL0 ((1<<0)) | ||
554 | CONFIG1 = 0x052, | ||
555 | #define CONFIG1_LEDS ((1<<7)|(1<<6)) | ||
556 | #define CONFIG1_LEDS1 ((1<<7)) | ||
557 | #define CONFIG1_LEDS0 ((1<<6)) | ||
558 | #define CONFIG1_LWACT ((1<<4)) | ||
559 | #define CONFIG1_MEMMAP ((1<<3)) | ||
560 | #define CONFIG1_IOMAP ((1<<2)) | ||
561 | #define CONFIG1_VPD ((1<<1)) | ||
562 | #define CONFIG1_PMEn ((1<<0)) | ||
563 | CONFIG2 = 0x053, | ||
564 | #define CONFIG2_LCK ((1<<7)) | ||
565 | #define CONFIG2_ANT ((1<<6)) | ||
566 | #define CONFIG2_DPS ((1<<3)) | ||
567 | #define CONFIG2_PAPE_sign ((1<<2)) | ||
568 | #define CONFIG2_PAPE_time ((1<<1)|(1<<0)) | ||
569 | #define CONFIG2_PAPE_time1 ((1<<1)) | ||
570 | #define CONFIG2_PAPE_time0 ((1<<0)) | ||
571 | ANA_PARAM = 0x054, | ||
572 | CONFIG3 = 0x059, | ||
573 | #define CONFIG3_GNTSel ((1<<7)) | ||
574 | #define CONFIG3_PARM_En ((1<<6)) | ||
575 | #define CONFIG3_Magic ((1<<5)) | ||
576 | #define CONFIG3_CardB_En ((1<<3)) | ||
577 | #define CONFIG3_CLKRUN_En ((1<<2)) | ||
578 | #define CONFIG3_FuncRegEn ((1<<1)) | ||
579 | #define CONFIG3_FBtbEn ((1<<0)) | ||
580 | #define CONFIG3_CLKRUN_SHIFT 2 | ||
581 | #define CONFIG3_ANAPARAM_W_SHIFT 6 | ||
582 | CONFIG4 = 0x05a, | ||
583 | #define CONFIG4_VCOPDN ((1<<7)) | ||
584 | #define CONFIG4_PWROFF ((1<<6)) | ||
585 | #define CONFIG4_PWRMGT ((1<<5)) | ||
586 | #define CONFIG4_LWPME ((1<<4)) | ||
587 | #define CONFIG4_LWPTN ((1<<2)) | ||
588 | #define CONFIG4_RFTYPE ((1<<1)|(1<<0)) | ||
589 | #define CONFIG4_RFTYPE1 ((1<<1)) | ||
590 | #define CONFIG4_RFTYPE0 ((1<<0)) | ||
591 | TESTR = 0x05b, | ||
592 | #define TFPC_AC 0x05C | ||
593 | |||
594 | #define SCR 0x05F | ||
595 | PGSELECT = 0x05e, | ||
596 | #define PGSELECT_PG_SHIFT 0 | ||
597 | SECURITY = 0x05f, | ||
598 | #define SECURITY_WEP_TX_ENABLE_SHIFT 1 | ||
599 | #define SECURITY_WEP_RX_ENABLE_SHIFT 0 | ||
600 | #define SECURITY_ENCRYP_104 1 | ||
601 | #define SECURITY_ENCRYP_SHIFT 4 | ||
602 | #define SECURITY_ENCRYP_MASK ((1<<4)|(1<<5)) | ||
603 | ANA_PARAM2 = 0x060, | ||
604 | BEACON_INTERVAL = 0x070, | ||
605 | #define BEACON_INTERVAL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)| \ | ||
606 | (1<<6)|(1<<7)|(1<<8)|(1<<9)) | ||
607 | ATIM_WND = 0x072, | ||
608 | #define ATIM_WND_MASK (0x01FF) | ||
609 | BCN_INTR_ITV = 0x074, | ||
610 | #define BCN_INTR_ITV_MASK (0x01FF) | ||
611 | ATIM_INTR_ITV = 0x076, | ||
612 | #define ATIM_INTR_ITV_MASK (0x01FF) | ||
613 | AckTimeOutReg = 0x079, //ACK timeout register, in unit of 4 us. | ||
614 | PHY_ADR = 0x07c, | ||
615 | PHY_READ = 0x07e, | ||
616 | RFPinsOutput = 0x080, | ||
617 | RFPinsEnable = 0x082, | ||
618 | |||
619 | //Page 0 | ||
620 | RFPinsSelect = 0x084, | ||
621 | #define SW_CONTROL_GPIO 0x400 | ||
622 | RFPinsInput = 0x086, | ||
623 | RF_PARA = 0x088, | ||
624 | RF_TIMING = 0x08c, | ||
625 | GP_ENABLE = 0x090, | ||
626 | GPIO = 0x091, | ||
627 | TX_AGC_CTL = 0x09c, | ||
628 | #define TX_AGC_CTL_PER_PACKET_TXAGC 0x01 | ||
629 | #define TX_AGC_CTL_PERPACKET_GAIN_SHIFT 0 | ||
630 | #define TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT 1 | ||
631 | #define TX_AGC_CTL_FEEDBACK_ANT 2 | ||
632 | #define TXAGC_CTL_PER_PACKET_ANT_SEL 0x02 | ||
633 | OFDM_TXAGC = 0x09e, | ||
634 | ANTSEL = 0x09f, | ||
635 | WPA_CONFIG = 0x0b0, | ||
636 | SIFS = 0x0b4, | ||
637 | DIFS = 0x0b5, | ||
638 | SLOT = 0x0b6, | ||
639 | CW_CONF = 0x0bc, | ||
640 | #define CW_CONF_PERPACKET_RETRY_LIMIT 0x02 | ||
641 | #define CW_CONF_PERPACKET_CW 0x01 | ||
642 | #define CW_CONF_PERPACKET_RETRY_SHIFT 1 | ||
643 | #define CW_CONF_PERPACKET_CW_SHIFT 0 | ||
644 | CW_VAL = 0x0bd, | ||
645 | RATE_FALLBACK = 0x0be, | ||
646 | #define MAX_RESP_RATE_SHIFT 4 | ||
647 | #define MIN_RESP_RATE_SHIFT 0 | ||
648 | #define RATE_FALLBACK_CTL_ENABLE 0x80 | ||
649 | #define RATE_FALLBACK_CTL_AUTO_STEP0 0x00 | ||
650 | ACM_CONTROL = 0x0BF, // ACM Control Registe | ||
651 | //---------------------------------------------------------------------------- | ||
652 | // 8187B ACM_CONTROL bits (Offset 0xBF, 1 Byte) | ||
653 | //---------------------------------------------------------------------------- | ||
654 | #define VOQ_ACM_EN (0x01 << 7) //BIT7 | ||
655 | #define VIQ_ACM_EN (0x01 << 6) //BIT6 | ||
656 | #define BEQ_ACM_EN (0x01 << 5) //BIT5 | ||
657 | #define ACM_HW_EN (0x01 << 4) //BIT4 | ||
658 | #define TXOPSEL (0x01 << 3) //BIT3 | ||
659 | #define VOQ_ACM_CTL (0x01 << 2) //BIT2 // Set to 1 when AC_VO used time reaches or exceeds the admitted time | ||
660 | #define VIQ_ACM_CTL (0x01 << 1) //BIT1 // Set to 1 when AC_VI used time reaches or exceeds the admitted time | ||
661 | #define BEQ_ACM_CTL (0x01 << 0) //BIT0 // Set to 1 when AC_BE used time reaches or exceeds the admitted time | ||
662 | CONFIG5 = 0x0D8, | ||
663 | #define CONFIG5_TX_FIFO_OK ((1<<7)) | ||
664 | #define CONFIG5_RX_FIFO_OK ((1<<6)) | ||
665 | #define CONFIG5_CALON ((1<<5)) | ||
666 | #define CONFIG5_EACPI ((1<<2)) | ||
667 | #define CONFIG5_LANWake ((1<<1)) | ||
668 | #define CONFIG5_PME_STS ((1<<0)) | ||
669 | TX_DMA_POLLING = 0x0d9, | ||
670 | #define TX_DMA_POLLING_BEACON_SHIFT 7 | ||
671 | #define TX_DMA_POLLING_HIPRIORITY_SHIFT 6 | ||
672 | #define TX_DMA_POLLING_NORMPRIORITY_SHIFT 5 | ||
673 | #define TX_DMA_POLLING_LOWPRIORITY_SHIFT 4 | ||
674 | #define TX_DMA_STOP_BEACON_SHIFT 3 | ||
675 | #define TX_DMA_STOP_HIPRIORITY_SHIFT 2 | ||
676 | #define TX_DMA_STOP_NORMPRIORITY_SHIFT 1 | ||
677 | #define TX_DMA_STOP_LOWPRIORITY_SHIFT 0 | ||
678 | CWR = 0x0DC, | ||
679 | RetryCTR = 0x0DE, | ||
680 | INT_MIG = 0x0E2, // Interrupt Migration (0xE2 ~ 0xE3) | ||
681 | TID_AC_MAP = 0x0E8, // TID to AC Mapping Register | ||
682 | ANA_PARAM3 = 0x0EE, | ||
683 | |||
684 | |||
685 | //page 1 | ||
686 | Wakeup0 = 0x084, | ||
687 | Wakeup1 = 0x08C, | ||
688 | Wakeup2LD = 0x094, | ||
689 | Wakeup2HD = 0x09C, | ||
690 | Wakeup3LD = 0x0A4, | ||
691 | Wakeup3HD = 0x0AC, | ||
692 | Wakeup4LD = 0x0B4, | ||
693 | Wakeup4HD = 0x0BC, | ||
694 | CRC0 = 0x0C4, | ||
695 | CRC1 = 0x0C6, | ||
696 | CRC2 = 0x0C8, | ||
697 | CRC3 = 0x0CA, | ||
698 | CRC4 = 0x0CC, | ||
699 | /* 0x00CE - 0x00D3 - reserved */ | ||
700 | |||
701 | RFSW_CTRL = 0x272, // 0x272-0x273. | ||
702 | |||
703 | //Reg Diff between rtl8187 and rtl8187B | ||
704 | /**************************************************************************/ | ||
705 | BRSR_8187 = 0x02C, | ||
706 | BRSR_8187B = 0x034, | ||
707 | #define BRSR_BPLCP ((1<< 8)) | ||
708 | #define BRSR_MBR ((1<< 1)|(1<< 0)) | ||
709 | #define BRSR_MBR_8185 ((1<< 11)|(1<< 10)|(1<< 9)|(1<< 8)|(1<< 7)|(1<< 6)|(1<< 5)|(1<< 4)|(1<< 3)|(1<< 2)|(1<< 1)|(1<< 0)) | ||
710 | #define BRSR_MBR0 ((1<< 0)) | ||
711 | #define BRSR_MBR1 ((1<< 1)) | ||
712 | |||
713 | /**************************************************************************/ | ||
714 | EIFS_8187 = 0x035, | ||
715 | EIFS_8187B = 0x02D, | ||
716 | |||
717 | /**************************************************************************/ | ||
718 | FER = 0x0F0, | ||
719 | FEMR = 0x0F4, | ||
720 | FPSR = 0x0F8, | ||
721 | FFER = 0x0FC, | ||
722 | |||
723 | AC_VO_PARAM = 0x0F0, // AC_VO Parameters Record | ||
724 | AC_VI_PARAM = 0x0F4, // AC_VI Parameters Record | ||
725 | AC_BE_PARAM = 0x0F8, // AC_BE Parameters Record | ||
726 | AC_BK_PARAM = 0x0FC, // AC_BK Parameters Record | ||
727 | TALLY_SEL = 0x0fc, | ||
728 | //---------------------------------------------------------------------------- | ||
729 | // 8187B AC_XX_PARAM bits | ||
730 | //---------------------------------------------------------------------------- | ||
731 | #define AC_PARAM_TXOP_LIMIT_OFFSET 16 | ||
732 | #define AC_PARAM_ECW_MAX_OFFSET 12 | ||
733 | #define AC_PARAM_ECW_MIN_OFFSET 8 | ||
734 | #define AC_PARAM_AIFS_OFFSET 0 | ||
735 | |||
736 | #endif | ||
737 | }; | ||
738 | //---------------------------------------------------------------------------- | ||
739 | // 818xB AnaParm & AnaParm2 Register | ||
740 | //---------------------------------------------------------------------------- | ||
741 | //#define ANAPARM_ASIC_ON 0x45090658 | ||
742 | //#define ANAPARM2_ASIC_ON 0x727f3f52 | ||
743 | #define GPI 0x108 | ||
744 | #define GPO 0x109 | ||
745 | #define GPE 0x10a | ||
746 | #endif | ||