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authorMike McCormack <mikem@ring3k.org>2011-03-03 08:45:08 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-03-07 16:31:43 -0500
commitd9ffa6c2e9752bb3c87995e2d97444c713dbc07f (patch)
tree06cc8722ff24b690740ba3635bf75e789fdaf0d7 /drivers/staging/rtl8192e
parent5aa68752f993b9e411196bbc44a202aadee42de2 (diff)
staging: rtl8192e: Pass r8192e_priv to phy functions
Phy functions shouldn't be associated with net_device. Signed-off-by: Mike McCormack <mikem@ring3k.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/rtl8192e')
-rw-r--r--drivers/staging/rtl8192e/r8190_rtl8256.c89
-rw-r--r--drivers/staging/rtl8192e/r8190_rtl8256.h10
-rw-r--r--drivers/staging/rtl8192e/r8192E_core.c40
-rw-r--r--drivers/staging/rtl8192e/r8192E_dm.c84
-rw-r--r--drivers/staging/rtl8192e/r819xE_phy.c284
-rw-r--r--drivers/staging/rtl8192e/r819xE_phy.h32
6 files changed, 256 insertions, 283 deletions
diff --git a/drivers/staging/rtl8192e/r8190_rtl8256.c b/drivers/staging/rtl8192e/r8190_rtl8256.c
index b4d45d6fd92..3cf96aa8d7c 100644
--- a/drivers/staging/rtl8192e/r8190_rtl8256.c
+++ b/drivers/staging/rtl8192e/r8190_rtl8256.c
@@ -23,15 +23,14 @@
23 * Return: NONE 23 * Return: NONE
24 * Note: 8226 support both 20M and 40 MHz 24 * Note: 8226 support both 20M and 40 MHz
25 *---------------------------------------------------------------------------*/ 25 *---------------------------------------------------------------------------*/
26void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M 26void PHY_SetRF8256Bandwidth(struct r8192_priv *priv, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
27{ 27{
28 u8 eRFPath; 28 u8 eRFPath;
29 struct r8192_priv *priv = ieee80211_priv(dev);
30 29
31 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 30 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
32 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) 31 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
33 { 32 {
34 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 33 if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
35 continue; 34 continue;
36 35
37 switch(Bandwidth) 36 switch(Bandwidth)
@@ -39,9 +38,9 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)
39 case HT_CHANNEL_WIDTH_20: 38 case HT_CHANNEL_WIDTH_20:
40 if(priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later! 39 if(priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later!
41 { 40 {
42 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba 41 rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba
43 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7); 42 rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
44 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021); 43 rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);
45 44
46 //cosa add for sd3's request 01/23/2008 45 //cosa add for sd3's request 01/23/2008
47 //rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab); 46 //rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
@@ -55,9 +54,9 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)
55 case HT_CHANNEL_WIDTH_20_40: 54 case HT_CHANNEL_WIDTH_20_40:
56 if(priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later! 55 if(priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later!
57 { 56 {
58 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba 57 rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba
59 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff); 58 rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff);
60 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1); 59 rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1);
61 60
62 } 61 }
63 else 62 else
@@ -80,43 +79,43 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)
80 * Output: NONE 79 * Output: NONE
81 * Return: NONE 80 * Return: NONE
82 *---------------------------------------------------------------------------*/ 81 *---------------------------------------------------------------------------*/
83RT_STATUS PHY_RF8256_Config(struct net_device* dev) 82RT_STATUS PHY_RF8256_Config(struct r8192_priv *priv)
84{ 83{
85 struct r8192_priv *priv = ieee80211_priv(dev);
86 // Initialize general global value 84 // Initialize general global value
87 // 85 //
88 RT_STATUS rtStatus = RT_STATUS_SUCCESS; 86 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
89 // TODO: Extend RF_PATH_C and RF_PATH_D in the future 87 // TODO: Extend RF_PATH_C and RF_PATH_D in the future
90 priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH; 88 priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
91 // Config BB and RF 89 // Config BB and RF
92 rtStatus = phy_RF8256_Config_ParaFile(dev); 90 rtStatus = phy_RF8256_Config_ParaFile(priv);
93 91
94 return rtStatus; 92 return rtStatus;
95} 93}
94
96/*-------------------------------------------------------------------------- 95/*--------------------------------------------------------------------------
97 * Overview: Interface to config 8256 96 * Overview: Interface to config 8256
98 * Input: struct net_device* dev 97 * Input: struct net_device* dev
99 * Output: NONE 98 * Output: NONE
100 * Return: NONE 99 * Return: NONE
101 *---------------------------------------------------------------------------*/ 100 *---------------------------------------------------------------------------*/
102RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev) 101RT_STATUS phy_RF8256_Config_ParaFile(struct r8192_priv *priv)
103{ 102{
104 u32 u4RegValue = 0; 103 u32 u4RegValue = 0;
105 u8 eRFPath; 104 u8 eRFPath;
106 RT_STATUS rtStatus = RT_STATUS_SUCCESS; 105 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
107 BB_REGISTER_DEFINITION_T *pPhyReg; 106 BB_REGISTER_DEFINITION_T *pPhyReg;
108 struct r8192_priv *priv = ieee80211_priv(dev);
109 u32 RegOffSetToBeCheck = 0x3; 107 u32 RegOffSetToBeCheck = 0x3;
110 u32 RegValueToBeCheck = 0x7f1; 108 u32 RegValueToBeCheck = 0x7f1;
111 u32 RF3_Final_Value = 0; 109 u32 RF3_Final_Value = 0;
112 u8 ConstRetryTimes = 5, RetryTimes = 5; 110 u8 ConstRetryTimes = 5, RetryTimes = 5;
113 u8 ret = 0; 111 u8 ret = 0;
112
114 //3//----------------------------------------------------------------- 113 //3//-----------------------------------------------------------------
115 //3// <2> Initialize RF 114 //3// <2> Initialize RF
116 //3//----------------------------------------------------------------- 115 //3//-----------------------------------------------------------------
117 for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) 116 for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
118 { 117 {
119 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 118 if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
120 continue; 119 continue;
121 120
122 pPhyReg = &priv->PHYRegDef[eRFPath]; 121 pPhyReg = &priv->PHYRegDef[eRFPath];
@@ -126,29 +125,29 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev)
126 { 125 {
127 case RF90_PATH_A: 126 case RF90_PATH_A:
128 case RF90_PATH_C: 127 case RF90_PATH_C:
129 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); 128 u4RegValue = rtl8192_QueryBBReg(priv, pPhyReg->rfintfs, bRFSI_RFENV);
130 break; 129 break;
131 case RF90_PATH_B : 130 case RF90_PATH_B :
132 case RF90_PATH_D: 131 case RF90_PATH_D:
133 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); 132 u4RegValue = rtl8192_QueryBBReg(priv, pPhyReg->rfintfs, bRFSI_RFENV<<16);
134 break; 133 break;
135 } 134 }
136 135
137 /*----Set RF_ENV enable----*/ 136 /*----Set RF_ENV enable----*/
138 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); 137 rtl8192_setBBreg(priv, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
139 138
140 /*----Set RF_ENV output high----*/ 139 /*----Set RF_ENV output high----*/
141 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); 140 rtl8192_setBBreg(priv, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
142 141
143 /* Set bit number of Address and Data for RF register */ 142 /* Set bit number of Address and Data for RF register */
144 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 143 rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
145 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? 144 rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???
146 145
147 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf); 146 rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
148 147
149 /*----Check RF block (for FPGA platform only)----*/ 148 /*----Check RF block (for FPGA platform only)----*/
150 // TODO: this function should be removed on ASIC , Emily 2007.2.2 149 // TODO: this function should be removed on ASIC , Emily 2007.2.2
151 rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath); 150 rtStatus = rtl8192_phy_checkBBAndRF(priv, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath);
152 if(rtStatus!= RT_STATUS_SUCCESS) 151 if(rtStatus!= RT_STATUS_SUCCESS)
153 { 152 {
154 RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath); 153 RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
@@ -163,8 +162,8 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev)
163 case RF90_PATH_A: 162 case RF90_PATH_A:
164 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) 163 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
165 { 164 {
166 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); 165 ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);
167 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); 166 RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
168 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); 167 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
169 RetryTimes--; 168 RetryTimes--;
170 } 169 }
@@ -172,8 +171,8 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev)
172 case RF90_PATH_B: 171 case RF90_PATH_B:
173 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) 172 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
174 { 173 {
175 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); 174 ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);
176 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); 175 RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
177 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); 176 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
178 RetryTimes--; 177 RetryTimes--;
179 } 178 }
@@ -181,8 +180,8 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev)
181 case RF90_PATH_C: 180 case RF90_PATH_C:
182 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) 181 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
183 { 182 {
184 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); 183 ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);
185 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); 184 RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
186 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); 185 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
187 RetryTimes--; 186 RetryTimes--;
188 } 187 }
@@ -190,8 +189,8 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev)
190 case RF90_PATH_D: 189 case RF90_PATH_D:
191 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) 190 while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
192 { 191 {
193 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); 192 ret = rtl8192_phy_ConfigRFWithHeaderFile(priv,(RF90_RADIO_PATH_E)eRFPath);
194 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); 193 RF3_Final_Value = rtl8192_phy_QueryRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
195 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); 194 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
196 RetryTimes--; 195 RetryTimes--;
197 } 196 }
@@ -203,11 +202,11 @@ RT_STATUS phy_RF8256_Config_ParaFile(struct net_device* dev)
203 { 202 {
204 case RF90_PATH_A: 203 case RF90_PATH_A:
205 case RF90_PATH_C: 204 case RF90_PATH_C:
206 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); 205 rtl8192_setBBreg(priv, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
207 break; 206 break;
208 case RF90_PATH_B : 207 case RF90_PATH_B :
209 case RF90_PATH_D: 208 case RF90_PATH_D:
210 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); 209 rtl8192_setBBreg(priv, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
211 break; 210 break;
212 } 211 }
213 212
@@ -227,10 +226,9 @@ phy_RF8256_Config_ParaFile_Fail:
227} 226}
228 227
229 228
230void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel) 229void PHY_SetRF8256CCKTxPower(struct r8192_priv *priv, u8 powerlevel)
231{ 230{
232 u32 TxAGC=0; 231 u32 TxAGC=0;
233 struct r8192_priv *priv = ieee80211_priv(dev);
234 232
235 TxAGC = powerlevel; 233 TxAGC = powerlevel;
236 if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range 234 if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range
@@ -242,13 +240,12 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
242 } 240 }
243 if(TxAGC > 0x24) 241 if(TxAGC > 0x24)
244 TxAGC = 0x24; 242 TxAGC = 0x24;
245 rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); 243 rtl8192_setBBreg(priv, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
246} 244}
247 245
248 246
249void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) 247void PHY_SetRF8256OFDMTxPower(struct r8192_priv *priv, u8 powerlevel)
250{ 248{
251 struct r8192_priv *priv = ieee80211_priv(dev);
252 249
253 u32 writeVal, powerBase0, powerBase1, writeVal_tmp; 250 u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
254 u8 index = 0; 251 u8 index = 0;
@@ -290,7 +287,7 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
290 { 287 {
291 writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; 288 writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
292 } 289 }
293 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); 290 rtl8192_setBBreg(priv, RegOffset[index], 0x7f7f7f7f, writeVal);
294 } 291 }
295} 292}
296 293
@@ -356,22 +353,22 @@ SetRFPowerState8190(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
356 write_nic_byte(priv, ANAPAR, 0x37);//160MHz 353 write_nic_byte(priv, ANAPAR, 0x37);//160MHz
357 mdelay(1); 354 mdelay(1);
358 //enable clock 80/88 MHz 355 //enable clock 80/88 MHz
359 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2] 356 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]
360 priv->bHwRfOffAction = 0; 357 priv->bHwRfOffAction = 0;
361 358
362 //RF-A, RF-B 359 //RF-A, RF-B
363 //enable RF-Chip A/B 360 //enable RF-Chip A/B
364 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] 361 rtl8192_setBBreg(priv, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
365 //analog to digital on 362 //analog to digital on
366 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] 363 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
367 //digital to analog on 364 //digital to analog on
368 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] 365 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
369 //rx antenna on 366 //rx antenna on
370 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] 367 rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
371 //rx antenna on 368 //rx antenna on
372 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] 369 rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
373 //analog to digital part2 on 370 //analog to digital part2 on
374 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] 371 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
375 372
376 } 373 }
377 374
diff --git a/drivers/staging/rtl8192e/r8190_rtl8256.h b/drivers/staging/rtl8192e/r8190_rtl8256.h
index d9347fa4615..e3297ecb37f 100644
--- a/drivers/staging/rtl8192e/r8190_rtl8256.h
+++ b/drivers/staging/rtl8192e/r8190_rtl8256.h
@@ -12,15 +12,15 @@
12 12
13#define RTL819X_TOTAL_RF_PATH 2 /* for 8192E */ 13#define RTL819X_TOTAL_RF_PATH 2 /* for 8192E */
14 14
15void PHY_SetRF8256Bandwidth(struct net_device *dev, 15void PHY_SetRF8256Bandwidth(struct r8192_priv *priv,
16 HT_CHANNEL_WIDTH Bandwidth); 16 HT_CHANNEL_WIDTH Bandwidth);
17 17
18RT_STATUS PHY_RF8256_Config(struct net_device *dev); 18RT_STATUS PHY_RF8256_Config(struct r8192_priv *priv);
19 19
20RT_STATUS phy_RF8256_Config_ParaFile(struct net_device *dev); 20RT_STATUS phy_RF8256_Config_ParaFile(struct r8192_priv *priv);
21 21
22void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel); 22void PHY_SetRF8256CCKTxPower(struct r8192_priv *priv, u8 powerlevel);
23void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel); 23void PHY_SetRF8256OFDMTxPower(struct r8192_priv *priv, u8 powerlevel);
24 24
25bool MgntActSet_RF_State(struct net_device *dev, 25bool MgntActSet_RF_State(struct net_device *dev,
26 RT_RF_POWER_STATE StateToSet, 26 RT_RF_POWER_STATE StateToSet,
diff --git a/drivers/staging/rtl8192e/r8192E_core.c b/drivers/staging/rtl8192e/r8192E_core.c
index 950089864aa..50480ac3513 100644
--- a/drivers/staging/rtl8192e/r8192E_core.c
+++ b/drivers/staging/rtl8192e/r8192E_core.c
@@ -752,18 +752,18 @@ void PHY_SetRtl8192eRfOff(struct net_device* dev)
752 struct r8192_priv *priv = ieee80211_priv(dev); 752 struct r8192_priv *priv = ieee80211_priv(dev);
753 753
754 //disable RF-Chip A/B 754 //disable RF-Chip A/B
755 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); 755 rtl8192_setBBreg(priv, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
756 //analog to digital off, for power save 756 //analog to digital off, for power save
757 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); 757 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x0);
758 //digital to analog off, for power save 758 //digital to analog off, for power save
759 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); 759 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x18, 0x0);
760 //rx antenna off 760 //rx antenna off
761 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); 761 rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0xf, 0x0);
762 //rx antenna off 762 //rx antenna off
763 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); 763 rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0xf, 0x0);
764 //analog to digital part2 off, for power save 764 //analog to digital part2 off, for power save
765 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); 765 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x60, 0x0);
766 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); 766 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x4, 0x0);
767 // Analog parameter!!Change bias and Lbus control. 767 // Analog parameter!!Change bias and Lbus control.
768 write_nic_byte(priv, ANAPAR_FOR_8192PciE, 0x07); 768 write_nic_byte(priv, ANAPAR_FOR_8192PciE, 0x07);
769 769
@@ -2659,7 +2659,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2659 //3// Initialize BB before MAC 2659 //3// Initialize BB before MAC
2660 //3// 2660 //3//
2661 RT_TRACE(COMP_INIT, "BB Config Start!\n"); 2661 RT_TRACE(COMP_INIT, "BB Config Start!\n");
2662 rtStatus = rtl8192_BBConfig(dev); 2662 rtStatus = rtl8192_BBConfig(priv);
2663 if(rtStatus != RT_STATUS_SUCCESS) 2663 if(rtStatus != RT_STATUS_SUCCESS)
2664 { 2664 {
2665 RT_TRACE(COMP_ERR, "BB Config failed\n"); 2665 RT_TRACE(COMP_ERR, "BB Config failed\n");
@@ -2768,11 +2768,11 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2768 //2======================================================= 2768 //2=======================================================
2769 // Set PHY related configuration defined in MAC register bank 2769 // Set PHY related configuration defined in MAC register bank
2770 //2======================================================= 2770 //2=======================================================
2771 rtl8192_phy_configmac(dev); 2771 rtl8192_phy_configmac(priv);
2772 2772
2773 if (priv->card_8192_version > (u8) VERSION_8190_BD) { 2773 if (priv->card_8192_version > (u8) VERSION_8190_BD) {
2774 rtl8192_phy_getTxPower(dev); 2774 rtl8192_phy_getTxPower(priv);
2775 rtl8192_phy_setTxPower(dev, priv->chan); 2775 rtl8192_phy_setTxPower(priv, priv->chan);
2776 } 2776 }
2777 2777
2778 //if D or C cut 2778 //if D or C cut
@@ -2811,7 +2811,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2811 if(priv->ResetProgress == RESET_TYPE_NORESET) 2811 if(priv->ResetProgress == RESET_TYPE_NORESET)
2812 { 2812 {
2813 RT_TRACE(COMP_INIT, "RF Config Started!\n"); 2813 RT_TRACE(COMP_INIT, "RF Config Started!\n");
2814 rtStatus = rtl8192_phy_RFConfig(dev); 2814 rtStatus = rtl8192_phy_RFConfig(priv);
2815 if(rtStatus != RT_STATUS_SUCCESS) 2815 if(rtStatus != RT_STATUS_SUCCESS)
2816 { 2816 {
2817 RT_TRACE(COMP_ERR, "RF Config failed\n"); 2817 RT_TRACE(COMP_ERR, "RF Config failed\n");
@@ -2819,11 +2819,11 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2819 } 2819 }
2820 RT_TRACE(COMP_INIT, "RF Config Finished!\n"); 2820 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
2821 } 2821 }
2822 rtl8192_phy_updateInitGain(dev); 2822 rtl8192_phy_updateInitGain(priv);
2823 2823
2824 /*---- Set CCK and OFDM Block "ON"----*/ 2824 /*---- Set CCK and OFDM Block "ON"----*/
2825 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); 2825 rtl8192_setBBreg(priv, rFPGA0_RFMOD, bCCKEn, 0x1);
2826 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); 2826 rtl8192_setBBreg(priv, rFPGA0_RFMOD, bOFDMEn, 0x1);
2827 2827
2828 //Enable Led 2828 //Enable Led
2829 write_nic_byte(priv, 0x87, 0x0); 2829 write_nic_byte(priv, 0x87, 0x0);
@@ -2864,8 +2864,8 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2864 2864
2865 if(priv->IC_Cut >= IC_VersionCut_D) 2865 if(priv->IC_Cut >= IC_VersionCut_D)
2866 { 2866 {
2867 tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord); 2867 tmpRegA = rtl8192_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord);
2868 tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord); 2868 tmpRegC = rtl8192_QueryBBReg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord);
2869 for(i = 0; i<TxBBGainTableLength; i++) 2869 for(i = 0; i<TxBBGainTableLength; i++)
2870 { 2870 {
2871 if(tmpRegA == priv->txbbgain_table[i].txbbgain_value) 2871 if(tmpRegA == priv->txbbgain_table[i].txbbgain_value)
@@ -2877,7 +2877,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2877 } 2877 }
2878 } 2878 }
2879 2879
2880 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2); 2880 TempCCk = rtl8192_QueryBBReg(priv, rCCK0_TxFilter1, bMaskByte2);
2881 2881
2882 for(i=0 ; i<CCKTxBBGainTableLength ; i++) 2882 for(i=0 ; i<CCKTxBBGainTableLength ; i++)
2883 { 2883 {
@@ -3873,7 +3873,7 @@ static void rtl8192_process_phyinfo(struct r8192_priv * priv, u8* buffer,struct
3873 { 3873 {
3874 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) 3874 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++)
3875 { 3875 {
3876 if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, rfpath)) 3876 if (!rtl8192_phy_CheckIsLegalRFPath(priv, rfpath))
3877 continue; 3877 continue;
3878 RT_TRACE(COMP_DBG, "pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n", pprevious_stats->RxMIMOSignalStrength[rfpath]); 3878 RT_TRACE(COMP_DBG, "pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n", pprevious_stats->RxMIMOSignalStrength[rfpath]);
3879 //Fixed by Jacken 2008-03-20 3879 //Fixed by Jacken 2008-03-20
@@ -4125,7 +4125,7 @@ static void rtl8192_query_rxphystatus(
4125 /*2007.08.30 requested by SD3 Jerry */ 4125 /*2007.08.30 requested by SD3 Jerry */
4126 if (priv->phy_check_reg824 == 0) 4126 if (priv->phy_check_reg824 == 0)
4127 { 4127 {
4128 priv->phy_reg824_bit9 = rtl8192_QueryBBReg(priv->ieee80211->dev, rFPGA0_XA_HSSIParameter2, 0x200); 4128 priv->phy_reg824_bit9 = rtl8192_QueryBBReg(priv, rFPGA0_XA_HSSIParameter2, 0x200);
4129 priv->phy_check_reg824 = 1; 4129 priv->phy_check_reg824 = 1;
4130 } 4130 }
4131 4131
diff --git a/drivers/staging/rtl8192e/r8192E_dm.c b/drivers/staging/rtl8192e/r8192E_dm.c
index 330e9d9e258..22bcc920ef4 100644
--- a/drivers/staging/rtl8192e/r8192E_dm.c
+++ b/drivers/staging/rtl8192e/r8192E_dm.c
@@ -586,20 +586,20 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
586 if(priv->rfa_txpowertrackingindex_real > 4) 586 if(priv->rfa_txpowertrackingindex_real > 4)
587 { 587 {
588 priv->rfa_txpowertrackingindex_real--; 588 priv->rfa_txpowertrackingindex_real--;
589 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); 589 rtl8192_setBBreg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
590 } 590 }
591 591
592 priv->rfc_txpowertrackingindex--; 592 priv->rfc_txpowertrackingindex--;
593 if(priv->rfc_txpowertrackingindex_real > 4) 593 if(priv->rfc_txpowertrackingindex_real > 4)
594 { 594 {
595 priv->rfc_txpowertrackingindex_real--; 595 priv->rfc_txpowertrackingindex_real--;
596 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); 596 rtl8192_setBBreg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
597 } 597 }
598 } 598 }
599 else 599 else
600 { 600 {
601 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value); 601 rtl8192_setBBreg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
602 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value); 602 rtl8192_setBBreg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
603 } 603 }
604 } 604 }
605 else 605 else
@@ -610,11 +610,11 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
610 if(priv->rfc_txpowertrackingindex_real > 4) 610 if(priv->rfc_txpowertrackingindex_real > 4)
611 { 611 {
612 priv->rfc_txpowertrackingindex_real--; 612 priv->rfc_txpowertrackingindex_real--;
613 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); 613 rtl8192_setBBreg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
614 } 614 }
615 } 615 }
616 else 616 else
617 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value); 617 rtl8192_setBBreg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
618 } 618 }
619 } 619 }
620 else 620 else
@@ -625,15 +625,15 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
625 { 625 {
626 priv->rfa_txpowertrackingindex++; 626 priv->rfa_txpowertrackingindex++;
627 priv->rfa_txpowertrackingindex_real++; 627 priv->rfa_txpowertrackingindex_real++;
628 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); 628 rtl8192_setBBreg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
629 priv->rfc_txpowertrackingindex++; 629 priv->rfc_txpowertrackingindex++;
630 priv->rfc_txpowertrackingindex_real++; 630 priv->rfc_txpowertrackingindex_real++;
631 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); 631 rtl8192_setBBreg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
632 } 632 }
633 else 633 else
634 { 634 {
635 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value); 635 rtl8192_setBBreg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
636 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value); 636 rtl8192_setBBreg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
637 } 637 }
638 } 638 }
639 else 639 else
@@ -642,10 +642,10 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
642 { 642 {
643 priv->rfc_txpowertrackingindex++; 643 priv->rfc_txpowertrackingindex++;
644 priv->rfc_txpowertrackingindex_real++; 644 priv->rfc_txpowertrackingindex_real++;
645 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); 645 rtl8192_setBBreg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
646 } 646 }
647 else 647 else
648 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value); 648 rtl8192_setBBreg(priv, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
649 } 649 }
650 } 650 }
651 if (RF_Type == RF_2T4R) 651 if (RF_Type == RF_2T4R)
@@ -721,7 +721,7 @@ static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
721 if(!priv->btxpower_trackingInit) 721 if(!priv->btxpower_trackingInit)
722 { 722 {
723 //Query OFDM default setting 723 //Query OFDM default setting
724 tmpRegA= rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord); 724 tmpRegA = rtl8192_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord);
725 for(i=0; i<OFDM_Table_Length; i++) //find the index 725 for(i=0; i<OFDM_Table_Length; i++) //find the index
726 { 726 {
727 if(tmpRegA == OFDMSwingTable[i]) 727 if(tmpRegA == OFDMSwingTable[i])
@@ -733,7 +733,7 @@ static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
733 } 733 }
734 734
735 //Query CCK default setting From 0xa22 735 //Query CCK default setting From 0xa22
736 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2); 736 TempCCk = rtl8192_QueryBBReg(priv, rCCK0_TxFilter1, bMaskByte2);
737 for(i=0 ; i<CCK_Table_length ; i++) 737 for(i=0 ; i<CCK_Table_length ; i++)
738 { 738 {
739 if(TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) 739 if(TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0])
@@ -750,7 +750,7 @@ static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
750 } 750 }
751 751
752 // read and filter out unreasonable value 752 // read and filter out unreasonable value
753 tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7] 753 tmpRegA = rtl8192_phy_QueryRFReg(priv, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7]
754 RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d\n", tmpRegA); 754 RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d\n", tmpRegA);
755 if(tmpRegA < 3 || tmpRegA > 13) 755 if(tmpRegA < 3 || tmpRegA > 13)
756 return; 756 return;
@@ -817,7 +817,7 @@ static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
817 if(priv->OFDM_index != tmpOFDMindex) 817 if(priv->OFDM_index != tmpOFDMindex)
818 { 818 {
819 priv->OFDM_index = tmpOFDMindex; 819 priv->OFDM_index = tmpOFDMindex;
820 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]); 820 rtl8192_setBBreg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
821 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n", 821 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
822 priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]); 822 priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
823 } 823 }
@@ -1014,10 +1014,10 @@ static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1014 { 1014 {
1015 //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash 1015 //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash
1016 //actually write reg0x02 bit1=0, then bit1=1. 1016 //actually write reg0x02 bit1=0, then bit1=1.
1017 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); 1017 rtl8192_phy_SetRFReg(priv, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1018 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); 1018 rtl8192_phy_SetRFReg(priv, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1019 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); 1019 rtl8192_phy_SetRFReg(priv, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1020 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); 1020 rtl8192_phy_SetRFReg(priv, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1021 TM_Trigger = 1; 1021 TM_Trigger = 1;
1022 return; 1022 return;
1023 } 1023 }
@@ -1049,40 +1049,40 @@ static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14)
1049 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] + 1049 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1050 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ; 1050 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1051 1051
1052 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal); 1052 rtl8192_setBBreg(priv, rCCK0_TxFilter1, bMaskHWord, TempVal);
1053 //Write 0xa24 ~ 0xa27 1053 //Write 0xa24 ~ 0xa27
1054 TempVal = 0; 1054 TempVal = 0;
1055 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] + 1055 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1056 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) + 1056 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1057 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+ 1057 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1058 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24)); 1058 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1059 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal); 1059 rtl8192_setBBreg(priv, rCCK0_TxFilter2, bMaskDWord, TempVal);
1060 //Write 0xa28 0xa29 1060 //Write 0xa28 0xa29
1061 TempVal = 0; 1061 TempVal = 0;
1062 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] + 1062 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1063 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ; 1063 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1064 1064
1065 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal); 1065 rtl8192_setBBreg(priv, rCCK0_DebugPort, bMaskLWord, TempVal);
1066 } 1066 }
1067 else 1067 else
1068 { 1068 {
1069 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] + 1069 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1070 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ; 1070 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1071 1071
1072 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal); 1072 rtl8192_setBBreg(priv, rCCK0_TxFilter1, bMaskHWord, TempVal);
1073 //Write 0xa24 ~ 0xa27 1073 //Write 0xa24 ~ 0xa27
1074 TempVal = 0; 1074 TempVal = 0;
1075 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] + 1075 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1076 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) + 1076 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1077 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+ 1077 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1078 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24)); 1078 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1079 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal); 1079 rtl8192_setBBreg(priv, rCCK0_TxFilter2, bMaskDWord, TempVal);
1080 //Write 0xa28 0xa29 1080 //Write 0xa28 0xa29
1081 TempVal = 0; 1081 TempVal = 0;
1082 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] + 1082 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1083 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ; 1083 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1084 1084
1085 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal); 1085 rtl8192_setBBreg(priv, rCCK0_DebugPort, bMaskLWord, TempVal);
1086 } 1086 }
1087 1087
1088 1088
@@ -1099,7 +1099,7 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH
1099 //Write 0xa22 0xa23 1099 //Write 0xa22 0xa23
1100 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] + 1100 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1101 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ; 1101 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ;
1102 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); 1102 rtl8192_setBBreg(priv, rCCK0_TxFilter1, bMaskHWord, TempVal);
1103 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", 1103 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1104 rCCK0_TxFilter1, TempVal); 1104 rCCK0_TxFilter1, TempVal);
1105 //Write 0xa24 ~ 0xa27 1105 //Write 0xa24 ~ 0xa27
@@ -1108,7 +1108,7 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH
1108 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) + 1108 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1109 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16 )+ 1109 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16 )+
1110 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24); 1110 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1111 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); 1111 rtl8192_setBBreg(priv, rCCK0_TxFilter2, bMaskDWord, TempVal);
1112 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", 1112 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1113 rCCK0_TxFilter2, TempVal); 1113 rCCK0_TxFilter2, TempVal);
1114 //Write 0xa28 0xa29 1114 //Write 0xa28 0xa29
@@ -1116,7 +1116,7 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH
1116 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] + 1116 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1117 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ; 1117 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ;
1118 1118
1119 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); 1119 rtl8192_setBBreg(priv, rCCK0_DebugPort, bMaskLWord, TempVal);
1120 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", 1120 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1121 rCCK0_DebugPort, TempVal); 1121 rCCK0_DebugPort, TempVal);
1122 } 1122 }
@@ -1127,7 +1127,7 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH
1127 TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] + 1127 TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
1128 (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ; 1128 (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ;
1129 1129
1130 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); 1130 rtl8192_setBBreg(priv, rCCK0_TxFilter1, bMaskHWord, TempVal);
1131 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", 1131 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1132 rCCK0_TxFilter1, TempVal); 1132 rCCK0_TxFilter1, TempVal);
1133 //Write 0xa24 ~ 0xa27 1133 //Write 0xa24 ~ 0xa27
@@ -1136,7 +1136,7 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH
1136 (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) + 1136 (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1137 (CCKSwingTable_Ch14[priv->CCK_index][4]<<16 )+ 1137 (CCKSwingTable_Ch14[priv->CCK_index][4]<<16 )+
1138 (CCKSwingTable_Ch14[priv->CCK_index][5]<<24); 1138 (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1139 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); 1139 rtl8192_setBBreg(priv, rCCK0_TxFilter2, bMaskDWord, TempVal);
1140 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", 1140 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1141 rCCK0_TxFilter2, TempVal); 1141 rCCK0_TxFilter2, TempVal);
1142 //Write 0xa28 0xa29 1142 //Write 0xa28 0xa29
@@ -1144,7 +1144,7 @@ static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH
1144 TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] + 1144 TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] +
1145 (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ; 1145 (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ;
1146 1146
1147 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); 1147 rtl8192_setBBreg(priv, rCCK0_DebugPort, bMaskLWord, TempVal);
1148 RT_TRACE(COMP_POWER_TRACKING,"CCK chnl 14, reg 0x%x = 0x%x\n", 1148 RT_TRACE(COMP_POWER_TRACKING,"CCK chnl 14, reg 0x%x = 0x%x\n",
1149 rCCK0_DebugPort, TempVal); 1149 rCCK0_DebugPort, TempVal);
1150 } 1150 }
@@ -1295,7 +1295,7 @@ static void dm_ctrl_initgain_byrssi_by_driverrssi(
1295 if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled 1295 if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled
1296 {// FW DIG Off 1296 {// FW DIG Off
1297 for(i=0; i<3; i++) 1297 for(i=0; i<3; i++)
1298 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. 1298 rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1299 fw_dig++; 1299 fw_dig++;
1300 dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off. 1300 dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off.
1301 } 1301 }
@@ -1332,7 +1332,7 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1332 dm_digtable.dig_state = DM_STA_DIG_MAX; 1332 dm_digtable.dig_state = DM_STA_DIG_MAX;
1333 // Fw DIG On. 1333 // Fw DIG On.
1334 for(i=0; i<3; i++) 1334 for(i=0; i<3; i++)
1335 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite. 1335 rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1336 dm_digtable.dig_algorithm_switch = 0; 1336 dm_digtable.dig_algorithm_switch = 0;
1337 } 1337 }
1338 1338
@@ -1367,7 +1367,7 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1367 dm_digtable.dig_state = DM_STA_DIG_OFF; 1367 dm_digtable.dig_state = DM_STA_DIG_OFF;
1368 1368
1369 // 1.1 DIG Off. 1369 // 1.1 DIG Off.
1370 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. 1370 rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1371 1371
1372 // 1.2 Set initial gain. 1372 // 1.2 Set initial gain.
1373 write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x17); 1373 write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x17);
@@ -1451,7 +1451,7 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1451 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346); 1451 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);
1452 1452
1453 // 2.5 DIG On. 1453 // 2.5 DIG On.
1454 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite. 1454 rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1455 1455
1456 } 1456 }
1457 1457
@@ -2227,8 +2227,8 @@ static void dm_rxpath_sel_byrssi(struct net_device * dev)
2227 //record the enabled rssi threshold 2227 //record the enabled rssi threshold
2228 DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5; 2228 DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
2229 //disable the BB Rx path, OFDM 2229 //disable the BB Rx path, OFDM
2230 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0] 2230 rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0]
2231 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0] 2231 rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0]
2232 disabled_rf_cnt++; 2232 disabled_rf_cnt++;
2233 } 2233 }
2234 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1) 2234 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1)
@@ -2243,7 +2243,7 @@ static void dm_rxpath_sel_byrssi(struct net_device * dev)
2243 if(update_cck_rx_path) 2243 if(update_cck_rx_path)
2244 { 2244 {
2245 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx); 2245 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
2246 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path); 2246 rtl8192_setBBreg(priv, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);
2247 } 2247 }
2248 2248
2249 if(DM_RxPathSelTable.disabledRF) 2249 if(DM_RxPathSelTable.disabledRF)
@@ -2255,8 +2255,8 @@ static void dm_rxpath_sel_byrssi(struct net_device * dev)
2255 if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i]) 2255 if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i])
2256 { 2256 {
2257 //enable the BB Rx path 2257 //enable the BB Rx path
2258 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0] 2258 rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0]
2259 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0] 2259 rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0]
2260 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100; 2260 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2261 disabled_rf_cnt--; 2261 disabled_rf_cnt--;
2262 } 2262 }
@@ -2696,7 +2696,7 @@ static void dm_dynamic_txpower(struct net_device *dev)
2696 RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190() channel = %d\n", priv->ieee80211->current_network.channel); 2696 RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190() channel = %d\n", priv->ieee80211->current_network.channel);
2697 2697
2698 2698
2699 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); 2699 rtl8192_phy_setTxPower(priv, priv->ieee80211->current_network.channel);
2700 2700
2701 } 2701 }
2702 priv->bLastDTPFlag_High = priv->bDynamicTxHighPower; 2702 priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
diff --git a/drivers/staging/rtl8192e/r819xE_phy.c b/drivers/staging/rtl8192e/r819xE_phy.c
index 44e1123797c..e8a8b3424f3 100644
--- a/drivers/staging/rtl8192e/r819xE_phy.c
+++ b/drivers/staging/rtl8192e/r819xE_phy.c
@@ -564,8 +564,9 @@ static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
564 564
565/*************************Define local function prototype**********************/ 565/*************************Define local function prototype**********************/
566 566
567static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset); 567static u32 phy_FwRFSerialRead(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, u32 Offset);
568static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data); 568static void phy_FwRFSerialWrite(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
569
569/*************************Define local function prototype**********************/ 570/*************************Define local function prototype**********************/
570/****************************************************************************** 571/******************************************************************************
571 *function: This function read BB parameters from Header file we gen, 572 *function: This function read BB parameters from Header file we gen,
@@ -590,10 +591,9 @@ static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
590 * output: none 591 * output: none
591 * return: 0(illegal, false), 1(legal,true) 592 * return: 0(illegal, false), 1(legal,true)
592 * ***************************************************************************/ 593 * ***************************************************************************/
593u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) 594u8 rtl8192_phy_CheckIsLegalRFPath(struct r8192_priv *priv, u32 eRFPath)
594{ 595{
595 u8 ret = 1; 596 u8 ret = 1;
596 struct r8192_priv *priv = ieee80211_priv(dev);
597 597
598 if (priv->rf_type == RF_2T4R) 598 if (priv->rf_type == RF_2T4R)
599 ret = 0; 599 ret = 0;
@@ -617,9 +617,8 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
617 * return: none 617 * return: none
618 * notice: 618 * notice:
619 * ****************************************************************************/ 619 * ****************************************************************************/
620void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) 620void rtl8192_setBBreg(struct r8192_priv *priv, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
621{ 621{
622 struct r8192_priv *priv = ieee80211_priv(dev);
623 u32 OriginalValue, BitShift, NewValue; 622 u32 OriginalValue, BitShift, NewValue;
624 623
625 if(dwBitMask!= bMaskDWord) 624 if(dwBitMask!= bMaskDWord)
@@ -640,9 +639,8 @@ void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32
640 * return: u32 Data //the readback register value 639 * return: u32 Data //the readback register value
641 * notice: 640 * notice:
642 * ****************************************************************************/ 641 * ****************************************************************************/
643u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) 642u32 rtl8192_QueryBBReg(struct r8192_priv *priv, u32 dwRegAddr, u32 dwBitMask)
644{ 643{
645 struct r8192_priv *priv = ieee80211_priv(dev);
646 u32 OriginalValue, BitShift; 644 u32 OriginalValue, BitShift;
647 645
648 OriginalValue = read_nic_dword(priv, dwRegAddr); 646 OriginalValue = read_nic_dword(priv, dwRegAddr);
@@ -658,9 +656,9 @@ u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
658 * return: u32 readback value 656 * return: u32 readback value
659 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information. 657 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
660 * ****************************************************************************/ 658 * ****************************************************************************/
661static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset) 659static u32 rtl8192_phy_RFSerialRead(struct r8192_priv *priv,
660 RF90_RADIO_PATH_E eRFPath, u32 Offset)
662{ 661{
663 struct r8192_priv *priv = ieee80211_priv(dev);
664 u32 ret = 0; 662 u32 ret = 0;
665 u32 NewOffset = 0; 663 u32 NewOffset = 0;
666 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath]; 664 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
@@ -670,12 +668,12 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eR
670 668
671 //switch page for 8256 RF IC 669 //switch page for 8256 RF IC
672 //analog to digital off, for protection 670 //analog to digital off, for protection
673 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] 671 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
674 if (Offset >= 31) 672 if (Offset >= 31)
675 { 673 {
676 priv->RfReg0Value[eRFPath] |= 0x140; 674 priv->RfReg0Value[eRFPath] |= 0x140;
677 //Switch to Reg_Mode2 for Reg 31-45 675 //Switch to Reg_Mode2 for Reg 31-45
678 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); 676 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
679 //modify offset 677 //modify offset
680 NewOffset = Offset -30; 678 NewOffset = Offset -30;
681 } 679 }
@@ -684,7 +682,7 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eR
684 priv->RfReg0Value[eRFPath] |= 0x100; 682 priv->RfReg0Value[eRFPath] |= 0x100;
685 priv->RfReg0Value[eRFPath] &= (~0x40); 683 priv->RfReg0Value[eRFPath] &= (~0x40);
686 //Switch to Reg_Mode 1 for Reg16-30 684 //Switch to Reg_Mode 1 for Reg16-30
687 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); 685 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
688 686
689 NewOffset = Offset - 15; 687 NewOffset = Offset - 15;
690 } 688 }
@@ -692,30 +690,30 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eR
692 NewOffset = Offset; 690 NewOffset = Offset;
693 691
694 //put desired read addr to LSSI control Register 692 //put desired read addr to LSSI control Register
695 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); 693 rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
696 //Issue a posedge trigger 694 //Issue a posedge trigger
697 // 695 //
698 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); 696 rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
699 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); 697 rtl8192_setBBreg(priv, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
700 698
701 699
702 // TODO: we should not delay such a long time. Ask help from SD3 700 // TODO: we should not delay such a long time. Ask help from SD3
703 msleep(1); 701 msleep(1);
704 702
705 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); 703 ret = rtl8192_QueryBBReg(priv, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
706 704
707 705
708 // Switch back to Reg_Mode0; 706 // Switch back to Reg_Mode0;
709 priv->RfReg0Value[eRFPath] &= 0xebf; 707 priv->RfReg0Value[eRFPath] &= 0xebf;
710 708
711 rtl8192_setBBreg( 709 rtl8192_setBBreg(
712 dev, 710 priv,
713 pPhyReg->rf3wireOffset, 711 pPhyReg->rf3wireOffset,
714 bMaskDWord, 712 bMaskDWord,
715 (priv->RfReg0Value[eRFPath] << 16)); 713 (priv->RfReg0Value[eRFPath] << 16));
716 714
717 //analog to digital on 715 //analog to digital on
718 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] 716 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
719 717
720 return ret; 718 return ret;
721} 719}
@@ -740,28 +738,29 @@ static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eR
740 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) 738 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
741 *------------------------------------------------------------------ 739 *------------------------------------------------------------------
742 * ****************************************************************************/ 740 * ****************************************************************************/
743static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) 741static void rtl8192_phy_RFSerialWrite(struct r8192_priv *priv,
742 RF90_RADIO_PATH_E eRFPath, u32 Offset,
743 u32 Data)
744{ 744{
745 struct r8192_priv *priv = ieee80211_priv(dev);
746 u32 DataAndAddr = 0, NewOffset = 0; 745 u32 DataAndAddr = 0, NewOffset = 0;
747 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; 746 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
748 747
749 Offset &= 0x3f; 748 Offset &= 0x3f;
750 749
751 //analog to digital off, for protection 750 //analog to digital off, for protection
752 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] 751 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
753 752
754 if (Offset >= 31) 753 if (Offset >= 31)
755 { 754 {
756 priv->RfReg0Value[eRFPath] |= 0x140; 755 priv->RfReg0Value[eRFPath] |= 0x140;
757 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); 756 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
758 NewOffset = Offset - 30; 757 NewOffset = Offset - 30;
759 } 758 }
760 else if (Offset >= 16) 759 else if (Offset >= 16)
761 { 760 {
762 priv->RfReg0Value[eRFPath] |= 0x100; 761 priv->RfReg0Value[eRFPath] |= 0x100;
763 priv->RfReg0Value[eRFPath] &= (~0x40); 762 priv->RfReg0Value[eRFPath] &= (~0x40);
764 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); 763 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
765 NewOffset = Offset - 15; 764 NewOffset = Offset - 15;
766 } 765 }
767 else 766 else
@@ -771,7 +770,7 @@ static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E
771 DataAndAddr = (Data<<16) | (NewOffset&0x3f); 770 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
772 771
773 // Write Operation 772 // Write Operation
774 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 773 rtl8192_setBBreg(priv, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
775 774
776 775
777 if(Offset==0x0) 776 if(Offset==0x0)
@@ -782,19 +781,18 @@ static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E
782 { 781 {
783 priv->RfReg0Value[eRFPath] &= 0xebf; 782 priv->RfReg0Value[eRFPath] &= 0xebf;
784 rtl8192_setBBreg( 783 rtl8192_setBBreg(
785 dev, 784 priv,
786 pPhyReg->rf3wireOffset, 785 pPhyReg->rf3wireOffset,
787 bMaskDWord, 786 bMaskDWord,
788 (priv->RfReg0Value[eRFPath] << 16)); 787 (priv->RfReg0Value[eRFPath] << 16));
789 } 788 }
790 //analog to digital on 789 //analog to digital on
791 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] 790 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
792} 791}
793 792
794/****************************************************************************** 793/******************************************************************************
795 *function: This function set specific bits to RF register 794 *function: This function set specific bits to RF register
796 * input: net_device dev 795 * input: RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
797 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
798 * u32 RegAddr //target addr to be modified 796 * u32 RegAddr //target addr to be modified
799 * u32 BitMask //taget bit pos in the addr to be modified 797 * u32 BitMask //taget bit pos in the addr to be modified
800 * u32 Data //value to be write 798 * u32 Data //value to be write
@@ -802,13 +800,13 @@ static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E
802 * return: none 800 * return: none
803 * notice: 801 * notice:
804 * ****************************************************************************/ 802 * ****************************************************************************/
805void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) 803void rtl8192_phy_SetRFReg(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath,
804 u32 RegAddr, u32 BitMask, u32 Data)
806{ 805{
807 struct r8192_priv *priv = ieee80211_priv(dev);
808 u32 Original_Value, BitShift, New_Value; 806 u32 Original_Value, BitShift, New_Value;
809// u8 time = 0; 807// u8 time = 0;
810 808
811 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 809 if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
812 return; 810 return;
813 if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter) 811 if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter)
814 return; 812 return;
@@ -819,13 +817,13 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32
819 { 817 {
820 if (BitMask != bMask12Bits) // RF data is 12 bits only 818 if (BitMask != bMask12Bits) // RF data is 12 bits only
821 { 819 {
822 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); 820 Original_Value = phy_FwRFSerialRead(priv, eRFPath, RegAddr);
823 BitShift = rtl8192_CalculateBitShift(BitMask); 821 BitShift = rtl8192_CalculateBitShift(BitMask);
824 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); 822 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
825 823
826 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); 824 phy_FwRFSerialWrite(priv, eRFPath, RegAddr, New_Value);
827 }else 825 }else
828 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); 826 phy_FwRFSerialWrite(priv, eRFPath, RegAddr, Data);
829 udelay(200); 827 udelay(200);
830 828
831 } 829 }
@@ -833,13 +831,13 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32
833 { 831 {
834 if (BitMask != bMask12Bits) // RF data is 12 bits only 832 if (BitMask != bMask12Bits) // RF data is 12 bits only
835 { 833 {
836 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); 834 Original_Value = rtl8192_phy_RFSerialRead(priv, eRFPath, RegAddr);
837 BitShift = rtl8192_CalculateBitShift(BitMask); 835 BitShift = rtl8192_CalculateBitShift(BitMask);
838 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); 836 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
839 837
840 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); 838 rtl8192_phy_RFSerialWrite(priv, eRFPath, RegAddr, New_Value);
841 }else 839 }else
842 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); 840 rtl8192_phy_RFSerialWrite(priv, eRFPath, RegAddr, Data);
843 } 841 }
844 //up(&priv->rf_sem); 842 //up(&priv->rf_sem);
845} 843}
@@ -853,23 +851,24 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32
853 * return: u32 Data //the readback register value 851 * return: u32 Data //the readback register value
854 * notice: 852 * notice:
855 * ****************************************************************************/ 853 * ****************************************************************************/
856u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) 854u32 rtl8192_phy_QueryRFReg(struct r8192_priv *priv, RF90_RADIO_PATH_E eRFPath,
855 u32 RegAddr, u32 BitMask)
857{ 856{
858 u32 Original_Value, Readback_Value, BitShift; 857 u32 Original_Value, Readback_Value, BitShift;
859 struct r8192_priv *priv = ieee80211_priv(dev); 858
860 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 859 if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
861 return 0; 860 return 0;
862 if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter) 861 if (priv->eRFPowerState != eRfOn && !priv->being_init_adapter)
863 return 0; 862 return 0;
864 down(&priv->rf_sem); 863 down(&priv->rf_sem);
865 if (priv->Rf_Mode == RF_OP_By_FW) 864 if (priv->Rf_Mode == RF_OP_By_FW)
866 { 865 {
867 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); 866 Original_Value = phy_FwRFSerialRead(priv, eRFPath, RegAddr);
868 udelay(200); 867 udelay(200);
869 } 868 }
870 else 869 else
871 { 870 {
872 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); 871 Original_Value = rtl8192_phy_RFSerialRead(priv, eRFPath, RegAddr);
873 872
874 } 873 }
875 BitShift = rtl8192_CalculateBitShift(BitMask); 874 BitShift = rtl8192_CalculateBitShift(BitMask);
@@ -886,12 +885,9 @@ u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u3
886 * return: none 885 * return: none
887 * notice: 886 * notice:
888 * ***************************************************************************/ 887 * ***************************************************************************/
889static u32 phy_FwRFSerialRead( 888static u32 phy_FwRFSerialRead(struct r8192_priv *priv,
890 struct net_device* dev, 889 RF90_RADIO_PATH_E eRFPath, u32 Offset)
891 RF90_RADIO_PATH_E eRFPath,
892 u32 Offset )
893{ 890{
894 struct r8192_priv *priv = ieee80211_priv(dev);
895 u32 Data = 0; 891 u32 Data = 0;
896 u8 time = 0; 892 u8 time = 0;
897 //DbgPrint("FW RF CTRL\n\r"); 893 //DbgPrint("FW RF CTRL\n\r");
@@ -944,14 +940,9 @@ static u32 phy_FwRFSerialRead(
944 * return: none 940 * return: none
945 * notice: 941 * notice:
946 * ***************************************************************************/ 942 * ***************************************************************************/
947static void 943static void phy_FwRFSerialWrite(struct r8192_priv *priv,
948phy_FwRFSerialWrite( 944 RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
949 struct net_device* dev,
950 RF90_RADIO_PATH_E eRFPath,
951 u32 Offset,
952 u32 Data )
953{ 945{
954 struct r8192_priv *priv = ieee80211_priv(dev);
955 u8 time = 0; 946 u8 time = 0;
956 947
957 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); 948 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
@@ -1002,11 +993,10 @@ phy_FwRFSerialWrite(
1002 * notice: BB parameters may change all the time, so please make 993 * notice: BB parameters may change all the time, so please make
1003 * sure it has been synced with the newest. 994 * sure it has been synced with the newest.
1004 * ***************************************************************************/ 995 * ***************************************************************************/
1005void rtl8192_phy_configmac(struct net_device* dev) 996void rtl8192_phy_configmac(struct r8192_priv *priv)
1006{ 997{
1007 u32 dwArrayLen = 0, i = 0; 998 u32 dwArrayLen = 0, i = 0;
1008 u32* pdwArray = NULL; 999 u32* pdwArray = NULL;
1009 struct r8192_priv *priv = ieee80211_priv(dev);
1010#ifdef TO_DO_LIST 1000#ifdef TO_DO_LIST
1011if(Adapter->bInHctTest) 1001if(Adapter->bInHctTest)
1012 { 1002 {
@@ -1038,7 +1028,7 @@ if(Adapter->bInHctTest)
1038 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n", 1028 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1039 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]); 1029 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1040 } 1030 }
1041 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); 1031 rtl8192_setBBreg(priv, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1042 } 1032 }
1043} 1033}
1044 1034
@@ -1051,14 +1041,13 @@ if(Adapter->bInHctTest)
1051 * sure it has been synced with the newest. 1041 * sure it has been synced with the newest.
1052 * ***************************************************************************/ 1042 * ***************************************************************************/
1053 1043
1054void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType) 1044void rtl8192_phyConfigBB(struct r8192_priv *priv, u8 ConfigType)
1055{ 1045{
1056 int i; 1046 int i;
1057 //u8 ArrayLength; 1047 //u8 ArrayLength;
1058 u32* Rtl819XPHY_REGArray_Table = NULL; 1048 u32* Rtl819XPHY_REGArray_Table = NULL;
1059 u32* Rtl819XAGCTAB_Array_Table = NULL; 1049 u32* Rtl819XAGCTAB_Array_Table = NULL;
1060 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; 1050 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
1061 struct r8192_priv *priv = ieee80211_priv(dev);
1062#ifdef TO_DO_LIST 1051#ifdef TO_DO_LIST
1063 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; 1052 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
1064 if(Adapter->bInHctTest) 1053 if(Adapter->bInHctTest)
@@ -1098,7 +1087,7 @@ void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
1098 { 1087 {
1099 for (i=0; i<PHY_REGArrayLen; i+=2) 1088 for (i=0; i<PHY_REGArrayLen; i+=2)
1100 { 1089 {
1101 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); 1090 rtl8192_setBBreg(priv, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1102 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]); 1091 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1103 } 1092 }
1104 } 1093 }
@@ -1106,7 +1095,7 @@ void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
1106 { 1095 {
1107 for (i=0; i<AGCTAB_ArrayLen; i+=2) 1096 for (i=0; i<AGCTAB_ArrayLen; i+=2)
1108 { 1097 {
1109 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]); 1098 rtl8192_setBBreg(priv, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1110 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]); 1099 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
1111 } 1100 }
1112 } 1101 }
@@ -1119,9 +1108,8 @@ void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
1119 * return: none 1108 * return: none
1120 * notice: Initialization value here is constant and it should never be changed 1109 * notice: Initialization value here is constant and it should never be changed
1121 * ***************************************************************************/ 1110 * ***************************************************************************/
1122static void rtl8192_InitBBRFRegDef(struct net_device* dev) 1111static void rtl8192_InitBBRFRegDef(struct r8192_priv *priv)
1123{ 1112{
1124 struct r8192_priv *priv = ieee80211_priv(dev);
1125// RF Interface Sowrtware Control 1113// RF Interface Sowrtware Control
1126 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 1114 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
1127 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) 1115 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
@@ -1234,9 +1222,10 @@ static void rtl8192_InitBBRFRegDef(struct net_device* dev)
1234 * return: return whether BB and RF is ok(0:OK; 1:Fail) 1222 * return: return whether BB and RF is ok(0:OK; 1:Fail)
1235 * notice: This function may be removed in the ASIC 1223 * notice: This function may be removed in the ASIC
1236 * ***************************************************************************/ 1224 * ***************************************************************************/
1237RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) 1225RT_STATUS rtl8192_phy_checkBBAndRF(struct r8192_priv *priv,
1226 HW90_BLOCK_E CheckBlock,
1227 RF90_RADIO_PATH_E eRFPath)
1238{ 1228{
1239 struct r8192_priv *priv = ieee80211_priv(dev);
1240// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; 1229// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1241 RT_STATUS ret = RT_STATUS_SUCCESS; 1230 RT_STATUS ret = RT_STATUS_SUCCESS;
1242 u32 i, CheckTimes = 4, dwRegRead = 0; 1231 u32 i, CheckTimes = 4, dwRegRead = 0;
@@ -1268,10 +1257,10 @@ RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlo
1268 1257
1269 case HW90_BLOCK_RF: 1258 case HW90_BLOCK_RF:
1270 WriteData[i] &= 0xfff; 1259 WriteData[i] &= 0xfff;
1271 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); 1260 rtl8192_phy_SetRFReg(priv, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
1272 // TODO: we should not delay for such a long time. Ask SD3 1261 // TODO: we should not delay for such a long time. Ask SD3
1273 mdelay(10); 1262 mdelay(10);
1274 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); 1263 dwRegRead = rtl8192_phy_QueryRFReg(priv, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1275 mdelay(10); 1264 mdelay(10);
1276 break; 1265 break;
1277 1266
@@ -1304,10 +1293,10 @@ RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlo
1304 * notice: Initialization value may change all the time, so please make 1293 * notice: Initialization value may change all the time, so please make
1305 * sure it has been synced with the newest. 1294 * sure it has been synced with the newest.
1306 * ***************************************************************************/ 1295 * ***************************************************************************/
1307static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev) 1296static RT_STATUS rtl8192_BB_Config_ParaFile(struct r8192_priv *priv)
1308{ 1297{
1309 struct r8192_priv *priv = ieee80211_priv(dev);
1310 RT_STATUS rtStatus = RT_STATUS_SUCCESS; 1298 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1299
1311 u8 bRegValue = 0, eCheckItem = 0; 1300 u8 bRegValue = 0, eCheckItem = 0;
1312 u32 dwRegValue = 0; 1301 u32 dwRegValue = 0;
1313 /************************************** 1302 /**************************************
@@ -1326,7 +1315,7 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
1326 // TODO: this function should be removed on ASIC , Emily 2007.2.2 1315 // TODO: this function should be removed on ASIC , Emily 2007.2.2
1327 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) 1316 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
1328 { 1317 {
1329 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path 1318 rtStatus = rtl8192_phy_checkBBAndRF(priv, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
1330 if(rtStatus != RT_STATUS_SUCCESS) 1319 if(rtStatus != RT_STATUS_SUCCESS)
1331 { 1320 {
1332 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); 1321 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
@@ -1334,10 +1323,10 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
1334 } 1323 }
1335 } 1324 }
1336 /*---- Set CCK and OFDM Block "OFF"----*/ 1325 /*---- Set CCK and OFDM Block "OFF"----*/
1337 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); 1326 rtl8192_setBBreg(priv, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
1338 /*----BB Register Initilazation----*/ 1327 /*----BB Register Initilazation----*/
1339 //==m==>Set PHY REG From Header<==m== 1328 //==m==>Set PHY REG From Header<==m==
1340 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); 1329 rtl8192_phyConfigBB(priv, BaseBand_Config_PHY_REG);
1341 1330
1342 /*----Set BB reset de-Active----*/ 1331 /*----Set BB reset de-Active----*/
1343 dwRegValue = read_nic_dword(priv, CPU_GEN); 1332 dwRegValue = read_nic_dword(priv, CPU_GEN);
@@ -1345,7 +1334,7 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
1345 1334
1346 /*----BB AGC table Initialization----*/ 1335 /*----BB AGC table Initialization----*/
1347 //==m==>Set PHY REG From Header<==m== 1336 //==m==>Set PHY REG From Header<==m==
1348 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); 1337 rtl8192_phyConfigBB(priv, BaseBand_Config_AGC_TAB);
1349 1338
1350 if (priv->card_8192_version > VERSION_8190_BD) 1339 if (priv->card_8192_version > VERSION_8190_BD)
1351 { 1340 {
@@ -1358,13 +1347,13 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
1358 } 1347 }
1359 else 1348 else
1360 dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R. 1349 dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R.
1361 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, 1350 rtl8192_setBBreg(priv, rFPGA0_TxGainStage,
1362 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); 1351 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
1363 1352
1364 1353
1365 //XSTALLCap 1354 //XSTALLCap
1366 dwRegValue = priv->CrystalCap; 1355 dwRegValue = priv->CrystalCap;
1367 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); 1356 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
1368 } 1357 }
1369 1358
1370 // Check if the CCK HighPower is turned ON. 1359 // Check if the CCK HighPower is turned ON.
@@ -1380,12 +1369,12 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
1380 * notice: Initialization value may change all the time, so please make 1369 * notice: Initialization value may change all the time, so please make
1381 * sure it has been synced with the newest. 1370 * sure it has been synced with the newest.
1382 * ***************************************************************************/ 1371 * ***************************************************************************/
1383RT_STATUS rtl8192_BBConfig(struct net_device* dev) 1372RT_STATUS rtl8192_BBConfig(struct r8192_priv *priv)
1384{ 1373{
1385 rtl8192_InitBBRFRegDef(dev); 1374 rtl8192_InitBBRFRegDef(priv);
1386 //config BB&RF. As hardCode based initialization has not been well 1375 //config BB&RF. As hardCode based initialization has not been well
1387 //implemented, so use file first.FIXME:should implement it for hardcode? 1376 //implemented, so use file first.FIXME:should implement it for hardcode?
1388 return rtl8192_BB_Config_ParaFile(dev); 1377 return rtl8192_BB_Config_ParaFile(priv);
1389} 1378}
1390 1379
1391/****************************************************************************** 1380/******************************************************************************
@@ -1394,10 +1383,8 @@ RT_STATUS rtl8192_BBConfig(struct net_device* dev)
1394 * output: none 1383 * output: none
1395 * return: none 1384 * return: none
1396 * ***************************************************************************/ 1385 * ***************************************************************************/
1397void rtl8192_phy_getTxPower(struct net_device* dev) 1386void rtl8192_phy_getTxPower(struct r8192_priv *priv)
1398{ 1387{
1399 struct r8192_priv *priv = ieee80211_priv(dev);
1400
1401 priv->MCSTxPowerLevelOriginalOffset[0] = 1388 priv->MCSTxPowerLevelOriginalOffset[0] =
1402 read_nic_dword(priv, rTxAGC_Rate18_06); 1389 read_nic_dword(priv, rTxAGC_Rate18_06);
1403 priv->MCSTxPowerLevelOriginalOffset[1] = 1390 priv->MCSTxPowerLevelOriginalOffset[1] =
@@ -1435,9 +1422,8 @@ void rtl8192_phy_getTxPower(struct net_device* dev)
1435 * output: none 1422 * output: none
1436 * return: none 1423 * return: none
1437 * ***************************************************************************/ 1424 * ***************************************************************************/
1438void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) 1425void rtl8192_phy_setTxPower(struct r8192_priv *priv, u8 channel)
1439{ 1426{
1440 struct r8192_priv *priv = ieee80211_priv(dev);
1441 u8 powerlevel = 0,powerlevelOFDM24G = 0; 1427 u8 powerlevel = 0,powerlevelOFDM24G = 0;
1442 char ant_pwr_diff; 1428 char ant_pwr_diff;
1443 u32 u4RegValue; 1429 u32 u4RegValue;
@@ -1477,7 +1463,7 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
1477 priv->AntennaTxPwDiff[1]<<4 | 1463 priv->AntennaTxPwDiff[1]<<4 |
1478 priv->AntennaTxPwDiff[0]); 1464 priv->AntennaTxPwDiff[0]);
1479 1465
1480 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, 1466 rtl8192_setBBreg(priv, rFPGA0_TxGainStage,
1481 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); 1467 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1482 } 1468 }
1483 } 1469 }
@@ -1532,8 +1518,8 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
1532 pHalData->CurrentCckTxPwrIdx = powerlevel; 1518 pHalData->CurrentCckTxPwrIdx = powerlevel;
1533 pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G; 1519 pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
1534#endif 1520#endif
1535 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement 1521 PHY_SetRF8256CCKTxPower(priv, powerlevel); //need further implement
1536 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); 1522 PHY_SetRF8256OFDMTxPower(priv, powerlevelOFDM24G);
1537} 1523}
1538 1524
1539/****************************************************************************** 1525/******************************************************************************
@@ -1542,9 +1528,9 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
1542 * output: none 1528 * output: none
1543 * return: only 8256 is supported 1529 * return: only 8256 is supported
1544 * ***************************************************************************/ 1530 * ***************************************************************************/
1545RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev) 1531RT_STATUS rtl8192_phy_RFConfig(struct r8192_priv *priv)
1546{ 1532{
1547 return PHY_RF8256_Config(dev); 1533 return PHY_RF8256_Config(priv);
1548} 1534}
1549 1535
1550/****************************************************************************** 1536/******************************************************************************
@@ -1553,7 +1539,7 @@ RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev)
1553 * output: none 1539 * output: none
1554 * return: As Windows has not implemented this, wait for complement 1540 * return: As Windows has not implemented this, wait for complement
1555 * ***************************************************************************/ 1541 * ***************************************************************************/
1556void rtl8192_phy_updateInitGain(struct net_device* dev) 1542void rtl8192_phy_updateInitGain(struct r8192_priv *priv)
1557{ 1543{
1558} 1544}
1559 1545
@@ -1564,7 +1550,8 @@ void rtl8192_phy_updateInitGain(struct net_device* dev)
1564 * return: return code show if RF configuration is successful(0:pass, 1:fail) 1550 * return: return code show if RF configuration is successful(0:pass, 1:fail)
1565 * Note: Delay may be required for RF configuration 1551 * Note: Delay may be required for RF configuration
1566 * ***************************************************************************/ 1552 * ***************************************************************************/
1567u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath) 1553u8 rtl8192_phy_ConfigRFWithHeaderFile(struct r8192_priv *priv,
1554 RF90_RADIO_PATH_E eRFPath)
1568{ 1555{
1569 1556
1570 int i; 1557 int i;
@@ -1579,7 +1566,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E
1579 msleep(100); 1566 msleep(100);
1580 continue; 1567 continue;
1581 } 1568 }
1582 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]); 1569 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
1583 //msleep(1); 1570 //msleep(1);
1584 1571
1585 } 1572 }
@@ -1591,7 +1578,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E
1591 msleep(100); 1578 msleep(100);
1592 continue; 1579 continue;
1593 } 1580 }
1594 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]); 1581 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
1595 //msleep(1); 1582 //msleep(1);
1596 1583
1597 } 1584 }
@@ -1603,7 +1590,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E
1603 msleep(100); 1590 msleep(100);
1604 continue; 1591 continue;
1605 } 1592 }
1606 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]); 1593 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
1607 //msleep(1); 1594 //msleep(1);
1608 1595
1609 } 1596 }
@@ -1615,7 +1602,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E
1615 msleep(100); 1602 msleep(100);
1616 continue; 1603 continue;
1617 } 1604 }
1618 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]); 1605 rtl8192_phy_SetRFReg(priv, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
1619 //msleep(1); 1606 //msleep(1);
1620 1607
1621 } 1608 }
@@ -1635,14 +1622,13 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E
1635 * return: none 1622 * return: none
1636 * Note: 1623 * Note:
1637 * ***************************************************************************/ 1624 * ***************************************************************************/
1638static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) 1625static void rtl8192_SetTxPowerLevel(struct r8192_priv *priv, u8 channel)
1639{ 1626{
1640 struct r8192_priv *priv = ieee80211_priv(dev);
1641 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 1627 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1642 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 1628 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1643 1629
1644 PHY_SetRF8256CCKTxPower(dev, powerlevel); 1630 PHY_SetRF8256CCKTxPower(priv, powerlevel);
1645 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); 1631 PHY_SetRF8256OFDMTxPower(priv, powerlevelOFDM24G);
1646} 1632}
1647 1633
1648/**************************************************************************************** 1634/****************************************************************************************
@@ -1701,9 +1687,9 @@ static u8 rtl8192_phy_SetSwChnlCmdArray(
1701 * return: true if finished, false otherwise 1687 * return: true if finished, false otherwise
1702 * Note: Wait for simpler function to replace it //wb 1688 * Note: Wait for simpler function to replace it //wb
1703 * ***************************************************************************/ 1689 * ***************************************************************************/
1704static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay) 1690static u8 rtl8192_phy_SwChnlStepByStep(struct r8192_priv *priv, u8 channel,
1691 u8* stage, u8* step, u32* delay)
1705{ 1692{
1706 struct r8192_priv *priv = ieee80211_priv(dev);
1707// PCHANNEL_ACCESS_SETTING pChnlAccessSetting; 1693// PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
1708 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; 1694 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1709 u32 PreCommonCmdCnt; 1695 u32 PreCommonCmdCnt;
@@ -1792,7 +1778,7 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* s
1792 { 1778 {
1793 case CmdID_SetTxPowerLevel: 1779 case CmdID_SetTxPowerLevel:
1794 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later! 1780 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later!
1795 rtl8192_SetTxPowerLevel(dev,channel); 1781 rtl8192_SetTxPowerLevel(priv, channel);
1796 break; 1782 break;
1797 case CmdID_WritePortUlong: 1783 case CmdID_WritePortUlong:
1798 write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2); 1784 write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2);
@@ -1805,7 +1791,7 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* s
1805 break; 1791 break;
1806 case CmdID_RF_WriteReg: 1792 case CmdID_RF_WriteReg:
1807 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) 1793 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
1808 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7); 1794 rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
1809 break; 1795 break;
1810 default: 1796 default:
1811 break; 1797 break;
@@ -1828,12 +1814,11 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* s
1828 * return: noin 1814 * return: noin
1829 * Note: We should not call this function directly 1815 * Note: We should not call this function directly
1830 * ***************************************************************************/ 1816 * ***************************************************************************/
1831static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) 1817static void rtl8192_phy_FinishSwChnlNow(struct r8192_priv *priv, u8 channel)
1832{ 1818{
1833 struct r8192_priv *priv = ieee80211_priv(dev);
1834 u32 delay = 0; 1819 u32 delay = 0;
1835 1820
1836 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) 1821 while (!rtl8192_phy_SwChnlStepByStep(priv, channel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
1837 { 1822 {
1838 if(delay>0) 1823 if(delay>0)
1839 msleep(delay);//or mdelay? need further consideration 1824 msleep(delay);//or mdelay? need further consideration
@@ -1848,16 +1833,13 @@ static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1848 * output: none 1833 * output: none
1849 * return: noin 1834 * return: noin
1850 * ***************************************************************************/ 1835 * ***************************************************************************/
1851void rtl8192_SwChnl_WorkItem(struct net_device *dev) 1836void rtl8192_SwChnl_WorkItem(struct r8192_priv *priv)
1852{ 1837{
1853
1854 struct r8192_priv *priv = ieee80211_priv(dev);
1855
1856 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); 1838 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1857 1839
1858 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv); 1840 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv);
1859 1841
1860 rtl8192_phy_FinishSwChnlNow(dev , priv->chan); 1842 rtl8192_phy_FinishSwChnlNow(priv, priv->chan);
1861 1843
1862 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); 1844 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1863} 1845}
@@ -1916,19 +1898,16 @@ u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
1916 1898
1917 priv->SwChnlStage=0; 1899 priv->SwChnlStage=0;
1918 priv->SwChnlStep=0; 1900 priv->SwChnlStep=0;
1919// schedule_work(&(priv->SwChnlWorkItem)); 1901 if (priv->up)
1920// rtl8192_SwChnl_WorkItem(dev); 1902 rtl8192_SwChnl_WorkItem(priv);
1921 if(priv->up) { 1903
1922// queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
1923 rtl8192_SwChnl_WorkItem(dev);
1924 }
1925 priv->SwChnlInProgress = false; 1904 priv->SwChnlInProgress = false;
1926 return true; 1905 return true;
1927} 1906}
1928 1907
1929static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev ) 1908static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct r8192_priv *priv)
1930{ 1909{
1931 struct r8192_priv *priv = ieee80211_priv(dev); 1910 struct net_device *dev = priv->ieee80211->dev;
1932 1911
1933 switch(priv->CurrentChannelBW) 1912 switch(priv->CurrentChannelBW)
1934 { 1913 {
@@ -1987,9 +1966,9 @@ static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev )
1987 } 1966 }
1988} 1967}
1989 1968
1990static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) 1969static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct r8192_priv *priv)
1991{ 1970{
1992 struct r8192_priv *priv = ieee80211_priv(dev); 1971 struct net_device *dev = priv->ieee80211->dev;
1993 1972
1994 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) 1973 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1995 priv->bcck_in_ch14 = TRUE; 1974 priv->bcck_in_ch14 = TRUE;
@@ -2016,15 +1995,14 @@ static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
2016 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1995 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
2017} 1996}
2018 1997
2019static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev) 1998static void CCK_Tx_Power_Track_BW_Switch(struct r8192_priv *priv)
2020{ 1999{
2021 struct r8192_priv *priv = ieee80211_priv(dev);
2022 2000
2023 //if(pHalData->bDcut == TRUE) 2001 //if(pHalData->bDcut == TRUE)
2024 if(priv->IC_Cut >= IC_VersionCut_D) 2002 if(priv->IC_Cut >= IC_VersionCut_D)
2025 CCK_Tx_Power_Track_BW_Switch_TSSI(dev); 2003 CCK_Tx_Power_Track_BW_Switch_TSSI(priv);
2026 else 2004 else
2027 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev); 2005 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(priv);
2028} 2006}
2029 2007
2030 2008
@@ -2039,10 +2017,8 @@ static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
2039 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can 2017 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
2040 * test whether current work in the queue or not.//do I? 2018 * test whether current work in the queue or not.//do I?
2041 * ***************************************************************************/ 2019 * ***************************************************************************/
2042void rtl8192_SetBWModeWorkItem(struct net_device *dev) 2020void rtl8192_SetBWModeWorkItem(struct r8192_priv *priv)
2043{ 2021{
2044
2045 struct r8192_priv *priv = ieee80211_priv(dev);
2046 u8 regBwOpMode; 2022 u8 regBwOpMode;
2047 2023
2048 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", 2024 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n",
@@ -2081,8 +2057,8 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
2081 { 2057 {
2082 case HT_CHANNEL_WIDTH_20: 2058 case HT_CHANNEL_WIDTH_20:
2083 // Add by Vivi 20071119 2059 // Add by Vivi 20071119
2084 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); 2060 rtl8192_setBBreg(priv, rFPGA0_RFMOD, bRFMOD, 0x0);
2085 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); 2061 rtl8192_setBBreg(priv, rFPGA1_RFMOD, bRFMOD, 0x0);
2086// rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 2062// rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
2087 2063
2088 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 2064 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
@@ -2096,14 +2072,14 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
2096 write_nic_dword(priv, rCCK0_DebugPort, 0x00000204); 2072 write_nic_dword(priv, rCCK0_DebugPort, 0x00000204);
2097 } 2073 }
2098 else 2074 else
2099 CCK_Tx_Power_Track_BW_Switch(dev); 2075 CCK_Tx_Power_Track_BW_Switch(priv);
2100 2076
2101 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 2077 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x00100000, 1);
2102 break; 2078 break;
2103 case HT_CHANNEL_WIDTH_20_40: 2079 case HT_CHANNEL_WIDTH_20_40:
2104 // Add by Vivi 20071119 2080 // Add by Vivi 20071119
2105 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); 2081 rtl8192_setBBreg(priv, rFPGA0_RFMOD, bRFMOD, 0x1);
2106 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); 2082 rtl8192_setBBreg(priv, rFPGA1_RFMOD, bRFMOD, 0x1);
2107 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); 2083 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2108 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 2084 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
2109 //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); 2085 //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
@@ -2119,14 +2095,14 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
2119 write_nic_dword(priv, rCCK0_DebugPort, 0x00000409); 2095 write_nic_dword(priv, rCCK0_DebugPort, 0x00000409);
2120 } 2096 }
2121 else 2097 else
2122 CCK_Tx_Power_Track_BW_Switch(dev); 2098 CCK_Tx_Power_Track_BW_Switch(priv);
2123 2099
2124 // Set Control channel to upper or lower. These settings are required only for 40MHz 2100 // Set Control channel to upper or lower. These settings are required only for 40MHz
2125 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); 2101 rtl8192_setBBreg(priv, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2126 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); 2102 rtl8192_setBBreg(priv, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2127 2103
2128 2104
2129 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 2105 rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x00100000, 0);
2130 break; 2106 break;
2131 default: 2107 default:
2132 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); 2108 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
@@ -2136,7 +2112,7 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
2136 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 2112 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2137 2113
2138 //<3>Set RF related register 2114 //<3>Set RF related register
2139 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); 2115 PHY_SetRF8256Bandwidth(priv, priv->CurrentChannelBW);
2140 2116
2141 atomic_dec(&(priv->ieee80211->atm_swbw)); 2117 atomic_dec(&(priv->ieee80211->atm_swbw));
2142 priv->SetBWModeInProgress= false; 2118 priv->SetBWModeInProgress= false;
@@ -2176,7 +2152,7 @@ void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EX
2176 2152
2177 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem)); 2153 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
2178 // schedule_work(&(priv->SetBWModeWorkItem)); 2154 // schedule_work(&(priv->SetBWModeWorkItem));
2179 rtl8192_SetBWModeWorkItem(dev); 2155 rtl8192_SetBWModeWorkItem(priv);
2180 2156
2181} 2157}
2182 2158
@@ -2198,13 +2174,13 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation)
2198 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];// 2174 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];//
2199 BitMask = bMaskByte0; 2175 BitMask = bMaskByte0;
2200 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 2176 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2201 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF 2177 rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // FW DIG OFF
2202 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); 2178 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XAAGCCore1, BitMask);
2203 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); 2179 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XBAGCCore1, BitMask);
2204 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); 2180 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XCAGCCore1, BitMask);
2205 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); 2181 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(priv, rOFDM0_XDAGCCore1, BitMask);
2206 BitMask = bMaskByte2; 2182 BitMask = bMaskByte2;
2207 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); 2183 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(priv, rCCK0_CCA, BitMask);
2208 2184
2209 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); 2185 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2210 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); 2186 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
@@ -2224,14 +2200,14 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation)
2224 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); 2200 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
2225 BitMask = 0x7f; //Bit0~ Bit6 2201 BitMask = 0x7f; //Bit0~ Bit6
2226 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 2202 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2227 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF 2203 rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x8); // FW DIG OFF
2228 2204
2229 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); 2205 rtl8192_setBBreg(priv, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
2230 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); 2206 rtl8192_setBBreg(priv, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
2231 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); 2207 rtl8192_setBBreg(priv, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
2232 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); 2208 rtl8192_setBBreg(priv, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
2233 BitMask = bMaskByte2; 2209 BitMask = bMaskByte2;
2234 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); 2210 rtl8192_setBBreg(priv, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
2235 2211
2236 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); 2212 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2237 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); 2213 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
@@ -2239,11 +2215,11 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation)
2239 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); 2215 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2240 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); 2216 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
2241 2217
2242 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); 2218 rtl8192_phy_setTxPower(priv, priv->ieee80211->current_network.channel);
2243 2219
2244 2220
2245 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 2221 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2246 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON 2222 rtl8192_setBBreg(priv, UFWP, bMaskByte1, 0x1); // FW DIG ON
2247 break; 2223 break;
2248 default: 2224 default:
2249 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); 2225 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
diff --git a/drivers/staging/rtl8192e/r819xE_phy.h b/drivers/staging/rtl8192e/r819xE_phy.h
index c676c3ad0c8..46008eee512 100644
--- a/drivers/staging/rtl8192e/r819xE_phy.h
+++ b/drivers/staging/rtl8192e/r819xE_phy.h
@@ -82,39 +82,39 @@ typedef enum _RF90_RADIO_PATH {
82#define bMaskLWord 0x0000ffff 82#define bMaskLWord 0x0000ffff
83#define bMaskDWord 0xffffffff 83#define bMaskDWord 0xffffffff
84 84
85u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath); 85u8 rtl8192_phy_CheckIsLegalRFPath(struct r8192_priv *priv, u32 eRFPath);
86 86
87void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, 87void rtl8192_setBBreg(struct r8192_priv *priv, u32 dwRegAddr,
88 u32 dwBitMask, u32 dwData); 88 u32 dwBitMask, u32 dwData);
89 89
90u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, 90u32 rtl8192_QueryBBReg(struct r8192_priv *priv, u32 dwRegAddr,
91 u32 dwBitMask); 91 u32 dwBitMask);
92 92
93void rtl8192_phy_SetRFReg(struct net_device *dev, 93void rtl8192_phy_SetRFReg(struct r8192_priv *priv,
94 RF90_RADIO_PATH_E eRFPath, u32 RegAddr, 94 RF90_RADIO_PATH_E eRFPath, u32 RegAddr,
95 u32 BitMask, u32 Data); 95 u32 BitMask, u32 Data);
96 96
97u32 rtl8192_phy_QueryRFReg(struct net_device *dev, 97u32 rtl8192_phy_QueryRFReg(struct r8192_priv *priv,
98 RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask); 98 RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
99 99
100void rtl8192_phy_configmac(struct net_device *dev); 100void rtl8192_phy_configmac(struct r8192_priv *priv);
101 101
102void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType); 102void rtl8192_phyConfigBB(struct r8192_priv *priv, u8 ConfigType);
103 103
104RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device *dev, 104RT_STATUS rtl8192_phy_checkBBAndRF(struct r8192_priv *priv,
105 HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath); 105 HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
106 106
107RT_STATUS rtl8192_BBConfig(struct net_device *dev); 107RT_STATUS rtl8192_BBConfig(struct r8192_priv *priv);
108 108
109void rtl8192_phy_getTxPower(struct net_device *dev); 109void rtl8192_phy_getTxPower(struct r8192_priv *priv);
110 110
111void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel); 111void rtl8192_phy_setTxPower(struct r8192_priv *priv, u8 channel);
112 112
113RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev); 113RT_STATUS rtl8192_phy_RFConfig(struct r8192_priv *priv);
114 114
115void rtl8192_phy_updateInitGain(struct net_device* dev); 115void rtl8192_phy_updateInitGain(struct r8192_priv *priv);
116 116
117u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, 117u8 rtl8192_phy_ConfigRFWithHeaderFile(struct r8192_priv *priv,
118 RF90_RADIO_PATH_E eRFPath); 118 RF90_RADIO_PATH_E eRFPath);
119 119
120u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel); 120u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel);
@@ -122,9 +122,9 @@ u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel);
122void rtl8192_SetBWMode(struct net_device *dev, 122void rtl8192_SetBWMode(struct net_device *dev,
123 HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); 123 HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
124 124
125void rtl8192_SwChnl_WorkItem(struct net_device *dev); 125void rtl8192_SwChnl_WorkItem(struct r8192_priv *priv);
126 126
127void rtl8192_SetBWModeWorkItem(struct net_device *dev); 127void rtl8192_SetBWModeWorkItem(struct r8192_priv *priv);
128 128
129void InitialGain819xPci(struct net_device *dev, u8 Operation); 129void InitialGain819xPci(struct net_device *dev, u8 Operation);
130 130
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 16:08:27 -0400