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authorMike McCormack <mikem@ring3k.org>2011-02-06 08:53:26 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-02-09 14:50:17 -0500
commit3f9ab1ee8a44240e280f511a219ed101b9095697 (patch)
tree8f5aa7af278f93e243f0831703f7aaf0eadd4920 /drivers/staging/rtl8192e
parent427bf120b67a098f0ab4ebb84ee238afcfc0c689 (diff)
staging: rtl8192e: Use private structure in IO functions
The current ieee80211 library does not pass net_device structures around. Switch code to use private data structure to get I/O addresses. Signed-off-by: Mike McCormack <mikem@ring3k.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/rtl8192e')
-rw-r--r--drivers/staging/rtl8192e/r8180_93cx6.c58
-rw-r--r--drivers/staging/rtl8192e/r8190_rtl8256.c36
-rw-r--r--drivers/staging/rtl8192e/r8192E.h18
-rw-r--r--drivers/staging/rtl8192e/r8192E_core.c282
-rw-r--r--drivers/staging/rtl8192e/r8192E_dm.c236
-rw-r--r--drivers/staging/rtl8192e/r8192E_wx.c2
-rw-r--r--drivers/staging/rtl8192e/r8192_pm.c20
-rw-r--r--drivers/staging/rtl8192e/r819xE_firmware.c12
-rw-r--r--drivers/staging/rtl8192e/r819xE_phy.c109
9 files changed, 397 insertions, 376 deletions
diff --git a/drivers/staging/rtl8192e/r8180_93cx6.c b/drivers/staging/rtl8192e/r8180_93cx6.c
index c38dd176987..ba4712f482a 100644
--- a/drivers/staging/rtl8192e/r8180_93cx6.c
+++ b/drivers/staging/rtl8192e/r8180_93cx6.c
@@ -20,49 +20,49 @@
20 20
21#include "r8180_93cx6.h" 21#include "r8180_93cx6.h"
22 22
23static void eprom_cs(struct net_device *dev, short bit) 23static void eprom_cs(struct r8192_priv *priv, short bit)
24{ 24{
25 if (bit) 25 if (bit)
26 write_nic_byte(dev, EPROM_CMD, 26 write_nic_byte(priv, EPROM_CMD,
27 (1<<EPROM_CS_SHIFT) | 27 (1<<EPROM_CS_SHIFT) |
28 read_nic_byte(dev, EPROM_CMD)); //enable EPROM 28 read_nic_byte(priv, EPROM_CMD)); //enable EPROM
29 else 29 else
30 write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD) 30 write_nic_byte(priv, EPROM_CMD, read_nic_byte(priv, EPROM_CMD)
31 &~(1<<EPROM_CS_SHIFT)); //disable EPROM 31 &~(1<<EPROM_CS_SHIFT)); //disable EPROM
32 32
33 udelay(EPROM_DELAY); 33 udelay(EPROM_DELAY);
34} 34}
35 35
36 36
37static void eprom_ck_cycle(struct net_device *dev) 37static void eprom_ck_cycle(struct r8192_priv *priv)
38{ 38{
39 write_nic_byte(dev, EPROM_CMD, 39 write_nic_byte(priv, EPROM_CMD,
40 (1<<EPROM_CK_SHIFT) | read_nic_byte(dev, EPROM_CMD)); 40 (1<<EPROM_CK_SHIFT) | read_nic_byte(priv, EPROM_CMD));
41 udelay(EPROM_DELAY); 41 udelay(EPROM_DELAY);
42 write_nic_byte(dev, EPROM_CMD, 42 write_nic_byte(priv, EPROM_CMD,
43 read_nic_byte(dev, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT)); 43 read_nic_byte(priv, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT));
44 udelay(EPROM_DELAY); 44 udelay(EPROM_DELAY);
45} 45}
46 46
47 47
48static void eprom_w(struct net_device *dev, short bit) 48static void eprom_w(struct r8192_priv *priv, short bit)
49{ 49{
50 if (bit) 50 if (bit)
51 write_nic_byte(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) | 51 write_nic_byte(priv, EPROM_CMD, (1<<EPROM_W_SHIFT) |
52 read_nic_byte(dev, EPROM_CMD)); 52 read_nic_byte(priv, EPROM_CMD));
53 else 53 else
54 write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD) 54 write_nic_byte(priv, EPROM_CMD, read_nic_byte(priv, EPROM_CMD)
55 &~(1<<EPROM_W_SHIFT)); 55 &~(1<<EPROM_W_SHIFT));
56 56
57 udelay(EPROM_DELAY); 57 udelay(EPROM_DELAY);
58} 58}
59 59
60 60
61static short eprom_r(struct net_device *dev) 61static short eprom_r(struct r8192_priv *priv)
62{ 62{
63 short bit; 63 short bit;
64 64
65 bit = (read_nic_byte(dev, EPROM_CMD) & (1<<EPROM_R_SHIFT)); 65 bit = (read_nic_byte(priv, EPROM_CMD) & (1<<EPROM_R_SHIFT));
66 udelay(EPROM_DELAY); 66 udelay(EPROM_DELAY);
67 67
68 if (bit) 68 if (bit)
@@ -71,13 +71,13 @@ static short eprom_r(struct net_device *dev)
71} 71}
72 72
73 73
74static void eprom_send_bits_string(struct net_device *dev, short b[], int len) 74static void eprom_send_bits_string(struct r8192_priv *priv, short b[], int len)
75{ 75{
76 int i; 76 int i;
77 77
78 for (i = 0; i < len; i++) { 78 for (i = 0; i < len; i++) {
79 eprom_w(dev, b[i]); 79 eprom_w(priv, b[i]);
80 eprom_ck_cycle(dev); 80 eprom_ck_cycle(priv);
81 } 81 }
82} 82}
83 83
@@ -93,7 +93,7 @@ u32 eprom_read(struct net_device *dev, u32 addr)
93 93
94 ret = 0; 94 ret = 0;
95 //enable EPROM programming 95 //enable EPROM programming
96 write_nic_byte(dev, EPROM_CMD, 96 write_nic_byte(priv, EPROM_CMD,
97 (EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT)); 97 (EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT));
98 udelay(EPROM_DELAY); 98 udelay(EPROM_DELAY);
99 99
@@ -116,27 +116,27 @@ u32 eprom_read(struct net_device *dev, u32 addr)
116 addr_str[0] = addr & (1<<5); 116 addr_str[0] = addr & (1<<5);
117 addr_len = 6; 117 addr_len = 6;
118 } 118 }
119 eprom_cs(dev, 1); 119 eprom_cs(priv, 1);
120 eprom_ck_cycle(dev); 120 eprom_ck_cycle(priv);
121 eprom_send_bits_string(dev, read_cmd, 3); 121 eprom_send_bits_string(priv, read_cmd, 3);
122 eprom_send_bits_string(dev, addr_str, addr_len); 122 eprom_send_bits_string(priv, addr_str, addr_len);
123 123
124 //keep chip pin D to low state while reading. 124 //keep chip pin D to low state while reading.
125 //I'm unsure if it is necessary, but anyway shouldn't hurt 125 //I'm unsure if it is necessary, but anyway shouldn't hurt
126 eprom_w(dev, 0); 126 eprom_w(priv, 0);
127 127
128 for (i = 0; i < 16; i++) { 128 for (i = 0; i < 16; i++) {
129 //eeprom needs a clk cycle between writing opcode&adr 129 //eeprom needs a clk cycle between writing opcode&adr
130 //and reading data. (eeprom outs a dummy 0) 130 //and reading data. (eeprom outs a dummy 0)
131 eprom_ck_cycle(dev); 131 eprom_ck_cycle(priv);
132 ret |= (eprom_r(dev)<<(15-i)); 132 ret |= (eprom_r(priv)<<(15-i));
133 } 133 }
134 134
135 eprom_cs(dev, 0); 135 eprom_cs(priv, 0);
136 eprom_ck_cycle(dev); 136 eprom_ck_cycle(priv);
137 137
138 //disable EPROM programming 138 //disable EPROM programming
139 write_nic_byte(dev, EPROM_CMD, 139 write_nic_byte(priv, EPROM_CMD,
140 (EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT)); 140 (EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT));
141 return ret; 141 return ret;
142} 142}
diff --git a/drivers/staging/rtl8192e/r8190_rtl8256.c b/drivers/staging/rtl8192e/r8190_rtl8256.c
index 4ad4b062c5c..d911eddd057 100644
--- a/drivers/staging/rtl8192e/r8190_rtl8256.c
+++ b/drivers/staging/rtl8192e/r8190_rtl8256.c
@@ -273,7 +273,7 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
273 } 273 }
274 } 274 }
275 TxAGC = (byte1<<8) |byte0; 275 TxAGC = (byte1<<8) |byte0;
276 write_nic_dword(dev, CCK_TXAGC, TxAGC); 276 write_nic_dword(priv, CCK_TXAGC, TxAGC);
277#else 277#else
278 #ifdef RTL8192E 278 #ifdef RTL8192E
279 279
@@ -364,8 +364,8 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
364 //DbgPrint("TxAGC2_tmp = 0x%x\n", TxAGC2_tmp); 364 //DbgPrint("TxAGC2_tmp = 0x%x\n", TxAGC2_tmp);
365 365
366 //DbgPrint("TxAGC1/TxAGC2 = 0x%x/0x%x\n", TxAGC1, TxAGC2); 366 //DbgPrint("TxAGC1/TxAGC2 = 0x%x/0x%x\n", TxAGC1, TxAGC2);
367 write_nic_dword(dev, MCS_TXAGC, TxAGC1); 367 write_nic_dword(priv, MCS_TXAGC, TxAGC1);
368 write_nic_dword(dev, MCS_TXAGC+4, TxAGC2); 368 write_nic_dword(priv, MCS_TXAGC+4, TxAGC2);
369#else 369#else
370#ifdef RTL8192E 370#ifdef RTL8192E
371 u32 writeVal, powerBase0, powerBase1, writeVal_tmp; 371 u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
@@ -513,8 +513,8 @@ SetRFPowerState8190(
513 513
514 RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); 514 RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
515 } else { 515 } else {
516 write_nic_byte(dev, ANAPAR, 0x37);//160MHz 516 write_nic_byte(priv, ANAPAR, 0x37);//160MHz
517 //write_nic_byte(dev, MacBlkCtrl, 0x17); // 0x403 517 //write_nic_byte(priv, MacBlkCtrl, 0x17); // 0x403
518 mdelay(1); 518 mdelay(1);
519 //enable clock 80/88 MHz 519 //enable clock 80/88 MHz
520 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2] 520 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]
@@ -536,7 +536,7 @@ SetRFPowerState8190(
536 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] 536 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
537 537
538 // Baseband reset 2008.09.30 add 538 // Baseband reset 2008.09.30 add
539 //write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0)); 539 //write_nic_byte(priv, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0));
540 540
541 //2 AFE 541 //2 AFE
542 // 2008.09.30 add 542 // 2008.09.30 add
@@ -774,12 +774,12 @@ MgntDisconnectIBSS(
774// PlatformZeroMemory( pMgntInfo->Bssid, 6 ); 774// PlatformZeroMemory( pMgntInfo->Bssid, 6 );
775 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i]= 0x55; 775 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i]= 0x55;
776 priv->OpMode = RT_OP_MODE_NO_LINK; 776 priv->OpMode = RT_OP_MODE_NO_LINK;
777 write_nic_word(dev, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]); 777 write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
778 write_nic_dword(dev, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]); 778 write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
779 { 779 {
780 RT_OP_MODE OpMode = priv->OpMode; 780 RT_OP_MODE OpMode = priv->OpMode;
781 //LED_CTL_MODE LedAction = LED_CTL_NO_LINK; 781 //LED_CTL_MODE LedAction = LED_CTL_NO_LINK;
782 u8 btMsr = read_nic_byte(dev, MSR); 782 u8 btMsr = read_nic_byte(priv, MSR);
783 783
784 btMsr &= 0xfc; 784 btMsr &= 0xfc;
785 785
@@ -805,7 +805,7 @@ MgntDisconnectIBSS(
805 break; 805 break;
806 } 806 }
807 807
808 write_nic_byte(dev, MSR, btMsr); 808 write_nic_byte(priv, MSR, btMsr);
809 809
810 // LED control 810 // LED control
811 //Adapter->HalFunc.LedControlHandler(Adapter, LedAction); 811 //Adapter->HalFunc.LedControlHandler(Adapter, LedAction);
@@ -817,7 +817,7 @@ MgntDisconnectIBSS(
817 { 817 {
818 u32 RegRCR, Type; 818 u32 RegRCR, Type;
819 Type = bFilterOutNonAssociatedBSSID; 819 Type = bFilterOutNonAssociatedBSSID;
820 RegRCR = read_nic_dword(dev,RCR); 820 RegRCR = read_nic_dword(priv, RCR);
821 priv->ReceiveConfig = RegRCR; 821 priv->ReceiveConfig = RegRCR;
822 if (Type == true) 822 if (Type == true)
823 RegRCR |= (RCR_CBSSID); 823 RegRCR |= (RCR_CBSSID);
@@ -825,7 +825,7 @@ MgntDisconnectIBSS(
825 RegRCR &= (~RCR_CBSSID); 825 RegRCR &= (~RCR_CBSSID);
826 826
827 { 827 {
828 write_nic_dword(dev, RCR,RegRCR); 828 write_nic_dword(priv, RCR, RegRCR);
829 priv->ReceiveConfig = RegRCR; 829 priv->ReceiveConfig = RegRCR;
830 } 830 }
831 831
@@ -862,7 +862,7 @@ MlmeDisassociateRequest(
862 { 862 {
863 RT_OP_MODE OpMode = priv->OpMode; 863 RT_OP_MODE OpMode = priv->OpMode;
864 //LED_CTL_MODE LedAction = LED_CTL_NO_LINK; 864 //LED_CTL_MODE LedAction = LED_CTL_NO_LINK;
865 u8 btMsr = read_nic_byte(dev, MSR); 865 u8 btMsr = read_nic_byte(priv, MSR);
866 866
867 btMsr &= 0xfc; 867 btMsr &= 0xfc;
868 868
@@ -888,15 +888,15 @@ MlmeDisassociateRequest(
888 break; 888 break;
889 } 889 }
890 890
891 write_nic_byte(dev, MSR, btMsr); 891 write_nic_byte(priv, MSR, btMsr);
892 892
893 // LED control 893 // LED control
894 //Adapter->HalFunc.LedControlHandler(Adapter, LedAction); 894 //Adapter->HalFunc.LedControlHandler(Adapter, LedAction);
895 } 895 }
896 ieee80211_disassociate(priv->ieee80211); 896 ieee80211_disassociate(priv->ieee80211);
897 897
898 write_nic_word(dev, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]); 898 write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
899 write_nic_dword(dev, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]); 899 write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
900 900
901 } 901 }
902 902
@@ -935,7 +935,7 @@ MgntDisconnectAP(
935 935
936 Type = bFilterOutNonAssociatedBSSID; 936 Type = bFilterOutNonAssociatedBSSID;
937 //Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RCR, (pu1Byte)(&RegRCR)); 937 //Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RCR, (pu1Byte)(&RegRCR));
938 RegRCR = read_nic_dword(dev,RCR); 938 RegRCR = read_nic_dword(priv, RCR);
939 priv->ReceiveConfig = RegRCR; 939 priv->ReceiveConfig = RegRCR;
940 940
941 if (Type == true) 941 if (Type == true)
@@ -943,7 +943,7 @@ MgntDisconnectAP(
943 else if (Type == false) 943 else if (Type == false)
944 RegRCR &= (~RCR_CBSSID); 944 RegRCR &= (~RCR_CBSSID);
945 945
946 write_nic_dword(dev, RCR,RegRCR); 946 write_nic_dword(priv, RCR, RegRCR);
947 priv->ReceiveConfig = RegRCR; 947 priv->ReceiveConfig = RegRCR;
948 948
949 949
diff --git a/drivers/staging/rtl8192e/r8192E.h b/drivers/staging/rtl8192e/r8192E.h
index 515f492b214..b2c44a7af0c 100644
--- a/drivers/staging/rtl8192e/r8192E.h
+++ b/drivers/staging/rtl8192e/r8192E.h
@@ -1052,16 +1052,16 @@ typedef struct r8192_priv
1052 1052
1053bool init_firmware(struct net_device *dev); 1053bool init_firmware(struct net_device *dev);
1054short rtl8192_tx(struct net_device *dev, struct sk_buff* skb); 1054short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1055u32 read_cam(struct net_device *dev, u8 addr); 1055u32 read_cam(struct r8192_priv *priv, u8 addr);
1056void write_cam(struct net_device *dev, u8 addr, u32 data); 1056void write_cam(struct r8192_priv *priv, u8 addr, u32 data);
1057u8 read_nic_byte(struct net_device *dev, int x); 1057u8 read_nic_byte(struct r8192_priv *priv, int x);
1058u8 read_nic_byte_E(struct net_device *dev, int x); 1058u8 read_nic_byte_E(struct net_device *dev, int x);
1059u32 read_nic_dword(struct net_device *dev, int x); 1059u32 read_nic_dword(struct r8192_priv *priv, int x);
1060u16 read_nic_word(struct net_device *dev, int x) ; 1060u16 read_nic_word(struct r8192_priv *priv, int x) ;
1061void write_nic_byte(struct net_device *dev, int x,u8 y); 1061void write_nic_byte(struct r8192_priv *priv, int x,u8 y);
1062void write_nic_byte_E(struct net_device *dev, int x,u8 y); 1062void write_nic_byte_E(struct net_device *priv, int x,u8 y);
1063void write_nic_word(struct net_device *dev, int x,u16 y); 1063void write_nic_word(struct r8192_priv *priv, int x,u16 y);
1064void write_nic_dword(struct net_device *dev, int x,u32 y); 1064void write_nic_dword(struct r8192_priv *priv, int x,u32 y);
1065 1065
1066void rtl8192_halt_adapter(struct net_device *dev, bool reset); 1066void rtl8192_halt_adapter(struct net_device *dev, bool reset);
1067void rtl8192_rx_enable(struct net_device *); 1067void rtl8192_rx_enable(struct net_device *);
diff --git a/drivers/staging/rtl8192e/r8192E_core.c b/drivers/staging/rtl8192e/r8192E_core.c
index 2c17b57aac8..6190cdd3fb3 100644
--- a/drivers/staging/rtl8192e/r8192E_core.c
+++ b/drivers/staging/rtl8192e/r8192E_core.c
@@ -247,84 +247,97 @@ static inline bool rx_hal_is_cck_rate(prx_fwinfo_819x_pci pdrvinfo)
247 247
248void CamResetAllEntry(struct net_device *dev) 248void CamResetAllEntry(struct net_device *dev)
249{ 249{
250 write_nic_dword(dev, RWCAM, BIT31|BIT30); 250 struct r8192_priv* priv = ieee80211_priv(dev);
251 write_nic_dword(priv, RWCAM, BIT31|BIT30);
251} 252}
252 253
253 254void write_cam(struct r8192_priv *priv, u8 addr, u32 data)
254void write_cam(struct net_device *dev, u8 addr, u32 data)
255{ 255{
256 write_nic_dword(dev, WCAMI, data); 256 write_nic_dword(priv, WCAMI, data);
257 write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff) ); 257 write_nic_dword(priv, RWCAM, BIT31|BIT16|(addr&0xff) );
258} 258}
259u32 read_cam(struct net_device *dev, u8 addr) 259
260u32 read_cam(struct r8192_priv *priv, u8 addr)
260{ 261{
261 write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff) ); 262 write_nic_dword(priv, RWCAM, 0x80000000|(addr&0xff) );
262 return read_nic_dword(dev, 0xa8); 263 return read_nic_dword(priv, 0xa8);
263} 264}
264 265
265#ifdef CONFIG_RTL8180_IO_MAP 266#ifdef CONFIG_RTL8180_IO_MAP
266 267
267u8 read_nic_byte(struct net_device *dev, int x) 268u8 read_nic_byte(struct r8192_priv *priv, int x)
268{ 269{
270 struct net_device *dev = priv->ieee80211->dev;
269 return 0xff&inb(dev->base_addr +x); 271 return 0xff&inb(dev->base_addr +x);
270} 272}
271 273
272u32 read_nic_dword(struct net_device *dev, int x) 274u32 read_nic_dword(struct r8192_priv *priv, int x)
273{ 275{
276 struct net_device *dev = priv->ieee80211->dev;
274 return inl(dev->base_addr +x); 277 return inl(dev->base_addr +x);
275} 278}
276 279
277u16 read_nic_word(struct net_device *dev, int x) 280u16 read_nic_word(struct r8192_priv *priv, int x)
278{ 281{
282 struct net_device *dev = priv->ieee80211->dev;
279 return inw(dev->base_addr +x); 283 return inw(dev->base_addr +x);
280} 284}
281 285
282void write_nic_byte(struct net_device *dev, int x,u8 y) 286void write_nic_byte(struct r8192_priv *priv, int x,u8 y)
283{ 287{
288 struct net_device *dev = priv->ieee80211->dev;
284 outb(y&0xff,dev->base_addr +x); 289 outb(y&0xff,dev->base_addr +x);
285} 290}
286 291
287void write_nic_word(struct net_device *dev, int x,u16 y) 292void write_nic_word(struct r8192_priv *priv, int x,u16 y)
288{ 293{
294 struct net_device *dev = priv->ieee80211->dev;
289 outw(y,dev->base_addr +x); 295 outw(y,dev->base_addr +x);
290} 296}
291 297
292void write_nic_dword(struct net_device *dev, int x,u32 y) 298void write_nic_dword(struct r8192_priv *priv, int x,u32 y)
293{ 299{
300 struct net_device *dev = priv->ieee80211->dev;
294 outl(y,dev->base_addr +x); 301 outl(y,dev->base_addr +x);
295} 302}
296 303
297#else /* RTL_IO_MAP */ 304#else /* RTL_IO_MAP */
298 305
299u8 read_nic_byte(struct net_device *dev, int x) 306u8 read_nic_byte(struct r8192_priv *priv, int x)
300{ 307{
308 struct net_device *dev = priv->ieee80211->dev;
301 return 0xff&readb((u8*)dev->mem_start +x); 309 return 0xff&readb((u8*)dev->mem_start +x);
302} 310}
303 311
304u32 read_nic_dword(struct net_device *dev, int x) 312u32 read_nic_dword(struct r8192_priv *priv, int x)
305{ 313{
314 struct net_device *dev = priv->ieee80211->dev;
306 return readl((u8*)dev->mem_start +x); 315 return readl((u8*)dev->mem_start +x);
307} 316}
308 317
309u16 read_nic_word(struct net_device *dev, int x) 318u16 read_nic_word(struct r8192_priv *priv, int x)
310{ 319{
320 struct net_device *dev = priv->ieee80211->dev;
311 return readw((u8*)dev->mem_start +x); 321 return readw((u8*)dev->mem_start +x);
312} 322}
313 323
314void write_nic_byte(struct net_device *dev, int x,u8 y) 324void write_nic_byte(struct r8192_priv *priv, int x,u8 y)
315{ 325{
326 struct net_device *dev = priv->ieee80211->dev;
316 writeb(y,(u8*)dev->mem_start +x); 327 writeb(y,(u8*)dev->mem_start +x);
317 udelay(20); 328 udelay(20);
318} 329}
319 330
320void write_nic_dword(struct net_device *dev, int x,u32 y) 331void write_nic_dword(struct r8192_priv *priv, int x,u32 y)
321{ 332{
333 struct net_device *dev = priv->ieee80211->dev;
322 writel(y,(u8*)dev->mem_start +x); 334 writel(y,(u8*)dev->mem_start +x);
323 udelay(20); 335 udelay(20);
324} 336}
325 337
326void write_nic_word(struct net_device *dev, int x,u16 y) 338void write_nic_word(struct r8192_priv *priv, int x,u16 y)
327{ 339{
340 struct net_device *dev = priv->ieee80211->dev;
328 writew(y,(u8*)dev->mem_start +x); 341 writew(y,(u8*)dev->mem_start +x);
329 udelay(20); 342 udelay(20);
330} 343}
@@ -370,14 +383,14 @@ rtl8192e_SetHwReg(struct net_device *dev,u8 variable,u8* val)
370 { 383 {
371 384
372 case HW_VAR_BSSID: 385 case HW_VAR_BSSID:
373 write_nic_dword(dev, BSSIDR, ((u32*)(val))[0]); 386 write_nic_dword(priv, BSSIDR, ((u32*)(val))[0]);
374 write_nic_word(dev, BSSIDR+2, ((u16*)(val+2))[0]); 387 write_nic_word(priv, BSSIDR+2, ((u16*)(val+2))[0]);
375 break; 388 break;
376 389
377 case HW_VAR_MEDIA_STATUS: 390 case HW_VAR_MEDIA_STATUS:
378 { 391 {
379 RT_OP_MODE OpMode = *((RT_OP_MODE *)(val)); 392 RT_OP_MODE OpMode = *((RT_OP_MODE *)(val));
380 u8 btMsr = read_nic_byte(dev, MSR); 393 u8 btMsr = read_nic_byte(priv, MSR);
381 394
382 btMsr &= 0xfc; 395 btMsr &= 0xfc;
383 396
@@ -400,7 +413,7 @@ rtl8192e_SetHwReg(struct net_device *dev,u8 variable,u8* val)
400 break; 413 break;
401 } 414 }
402 415
403 write_nic_byte(dev, MSR, btMsr); 416 write_nic_byte(priv, MSR, btMsr);
404 } 417 }
405 break; 418 break;
406 419
@@ -409,7 +422,7 @@ rtl8192e_SetHwReg(struct net_device *dev,u8 variable,u8* val)
409 u32 RegRCR, Type; 422 u32 RegRCR, Type;
410 423
411 Type = ((u8*)(val))[0]; 424 Type = ((u8*)(val))[0];
412 RegRCR = read_nic_dword(dev,RCR); 425 RegRCR = read_nic_dword(priv, RCR);
413 priv->ReceiveConfig = RegRCR; 426 priv->ReceiveConfig = RegRCR;
414 427
415 if (Type == true) 428 if (Type == true)
@@ -417,7 +430,7 @@ rtl8192e_SetHwReg(struct net_device *dev,u8 variable,u8* val)
417 else if (Type == false) 430 else if (Type == false)
418 RegRCR &= (~RCR_CBSSID); 431 RegRCR &= (~RCR_CBSSID);
419 432
420 write_nic_dword(dev, RCR,RegRCR); 433 write_nic_dword(priv, RCR,RegRCR);
421 priv->ReceiveConfig = RegRCR; 434 priv->ReceiveConfig = RegRCR;
422 435
423 } 436 }
@@ -426,7 +439,7 @@ rtl8192e_SetHwReg(struct net_device *dev,u8 variable,u8* val)
426 case HW_VAR_SLOT_TIME: 439 case HW_VAR_SLOT_TIME:
427 { 440 {
428 priv->slot_time = val[0]; 441 priv->slot_time = val[0];
429 write_nic_byte(dev, SLOT_TIME, val[0]); 442 write_nic_byte(priv, SLOT_TIME, val[0]);
430 443
431 } 444 }
432 break; 445 break;
@@ -438,12 +451,12 @@ rtl8192e_SetHwReg(struct net_device *dev,u8 variable,u8* val)
438 regTmp = priv->basic_rate; 451 regTmp = priv->basic_rate;
439 if (priv->short_preamble) 452 if (priv->short_preamble)
440 regTmp |= BRSR_AckShortPmb; 453 regTmp |= BRSR_AckShortPmb;
441 write_nic_dword(dev, RRSR, regTmp); 454 write_nic_dword(priv, RRSR, regTmp);
442 } 455 }
443 break; 456 break;
444 457
445 case HW_VAR_CPU_RST: 458 case HW_VAR_CPU_RST:
446 write_nic_dword(dev, CPU_GEN, ((u32*)(val))[0]); 459 write_nic_dword(priv, CPU_GEN, ((u32*)(val))[0]);
447 break; 460 break;
448 461
449 default: 462 default:
@@ -489,6 +502,7 @@ static int proc_get_registers(char *page, char **start,
489 int *eof, void *data) 502 int *eof, void *data)
490{ 503{
491 struct net_device *dev = data; 504 struct net_device *dev = data;
505 struct r8192_priv *priv = ieee80211_priv(dev);
492 int len = 0; 506 int len = 0;
493 int i,n; 507 int i,n;
494 int max=0xff; 508 int max=0xff;
@@ -504,7 +518,7 @@ static int proc_get_registers(char *page, char **start,
504 518
505 for(i=0;i<16 && n<=max;i++,n++) 519 for(i=0;i<16 && n<=max;i++,n++)
506 len += snprintf(page + len, count - len, 520 len += snprintf(page + len, count - len,
507 "%2x ",read_nic_byte(dev,n)); 521 "%2x ",read_nic_byte(priv,n));
508 } 522 }
509 len += snprintf(page + len, count - len,"\n"); 523 len += snprintf(page + len, count - len,"\n");
510 len += snprintf(page + len, count - len, 524 len += snprintf(page + len, count - len,
@@ -516,7 +530,7 @@ static int proc_get_registers(char *page, char **start,
516 530
517 for(i=0;i<16 && n<=max;i++,n++) 531 for(i=0;i<16 && n<=max;i++,n++)
518 len += snprintf(page + len, count - len, 532 len += snprintf(page + len, count - len,
519 "%2x ",read_nic_byte(dev,0x100|n)); 533 "%2x ",read_nic_byte(priv,0x100|n));
520 } 534 }
521 535
522 len += snprintf(page + len, count - len, 536 len += snprintf(page + len, count - len,
@@ -528,7 +542,7 @@ static int proc_get_registers(char *page, char **start,
528 542
529 for(i=0;i<16 && n<=max;i++,n++) 543 for(i=0;i<16 && n<=max;i++,n++)
530 len += snprintf(page + len, count - len, 544 len += snprintf(page + len, count - len,
531 "%2x ",read_nic_byte(dev,0x300|n)); 545 "%2x ",read_nic_byte(priv,0x300|n));
532 } 546 }
533 547
534 *eof = 1; 548 *eof = 1;
@@ -705,14 +719,14 @@ static void rtl8192_irq_enable(struct net_device *dev)
705{ 719{
706 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); 720 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
707 priv->irq_enabled = 1; 721 priv->irq_enabled = 1;
708 write_nic_dword(dev,INTA_MASK, priv->irq_mask); 722 write_nic_dword(priv, INTA_MASK, priv->irq_mask);
709} 723}
710 724
711void rtl8192_irq_disable(struct net_device *dev) 725void rtl8192_irq_disable(struct net_device *dev)
712{ 726{
713 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); 727 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
714 728
715 write_nic_dword(dev,INTA_MASK,0); 729 write_nic_dword(priv, INTA_MASK, 0);
716 priv->irq_enabled = 0; 730 priv->irq_enabled = 0;
717} 731}
718 732
@@ -721,7 +735,7 @@ void rtl8192_update_msr(struct net_device *dev)
721 struct r8192_priv *priv = ieee80211_priv(dev); 735 struct r8192_priv *priv = ieee80211_priv(dev);
722 u8 msr; 736 u8 msr;
723 737
724 msr = read_nic_byte(dev, MSR); 738 msr = read_nic_byte(priv, MSR);
725 msr &= ~ MSR_LINK_MASK; 739 msr &= ~ MSR_LINK_MASK;
726 740
727 /* do not change in link_state != WLAN_LINK_ASSOCIATED. 741 /* do not change in link_state != WLAN_LINK_ASSOCIATED.
@@ -741,7 +755,7 @@ void rtl8192_update_msr(struct net_device *dev)
741 }else 755 }else
742 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT); 756 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
743 757
744 write_nic_byte(dev, MSR, msr); 758 write_nic_byte(priv, MSR, msr);
745} 759}
746 760
747void rtl8192_set_chan(struct net_device *dev,short ch) 761void rtl8192_set_chan(struct net_device *dev,short ch)
@@ -760,7 +774,7 @@ void rtl8192_rx_enable(struct net_device *dev)
760{ 774{
761 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); 775 struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
762 776
763 write_nic_dword(dev, RDQDA,priv->rx_ring_dma); 777 write_nic_dword(priv, RDQDA,priv->rx_ring_dma);
764} 778}
765 779
766/* the TX_DESC_BASE setting is according to the following queue index 780/* the TX_DESC_BASE setting is according to the following queue index
@@ -781,7 +795,7 @@ void rtl8192_tx_enable(struct net_device *dev)
781 u32 i; 795 u32 i;
782 796
783 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) 797 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
784 write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma); 798 write_nic_dword(priv, TX_DESC_BASE[i], priv->tx_ring[i].dma);
785 799
786 ieee80211_reset_queue(priv->ieee80211); 800 ieee80211_reset_queue(priv->ieee80211);
787} 801}
@@ -830,6 +844,8 @@ static void rtl8192_free_tx_ring(struct net_device *dev, unsigned int prio)
830 844
831void PHY_SetRtl8192eRfOff(struct net_device* dev) 845void PHY_SetRtl8192eRfOff(struct net_device* dev)
832{ 846{
847 struct r8192_priv *priv = ieee80211_priv(dev);
848
833 //disable RF-Chip A/B 849 //disable RF-Chip A/B
834 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); 850 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
835 //analog to digital off, for power save 851 //analog to digital off, for power save
@@ -844,7 +860,7 @@ void PHY_SetRtl8192eRfOff(struct net_device* dev)
844 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); 860 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
845 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); 861 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
846 // Analog parameter!!Change bias and Lbus control. 862 // Analog parameter!!Change bias and Lbus control.
847 write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07); 863 write_nic_byte(priv, ANAPAR_FOR_8192PciE, 0x07);
848 864
849} 865}
850 866
@@ -863,7 +879,7 @@ void rtl8192_halt_adapter(struct net_device *dev, bool reset)
863 * disable tx/rx. In 8185 we write 0x10 (Reset bit), 879 * disable tx/rx. In 8185 we write 0x10 (Reset bit),
864 * but here we make reference to WMAC and wirte 0x0 880 * but here we make reference to WMAC and wirte 0x0
865 */ 881 */
866 write_nic_byte(dev, CMDR, 0); 882 write_nic_byte(priv, CMDR, 0);
867 } 883 }
868 884
869 mdelay(20); 885 mdelay(20);
@@ -881,19 +897,19 @@ void rtl8192_halt_adapter(struct net_device *dev, bool reset)
881 */ 897 */
882 if (!priv->ieee80211->bSupportRemoteWakeUp) { 898 if (!priv->ieee80211->bSupportRemoteWakeUp) {
883 PHY_SetRtl8192eRfOff(dev); 899 PHY_SetRtl8192eRfOff(dev);
884 ulRegRead = read_nic_dword(dev,CPU_GEN); 900 ulRegRead = read_nic_dword(priv, CPU_GEN);
885 ulRegRead |= CPU_GEN_SYSTEM_RESET; 901 ulRegRead |= CPU_GEN_SYSTEM_RESET;
886 write_nic_dword(dev,CPU_GEN, ulRegRead); 902 write_nic_dword(priv,CPU_GEN, ulRegRead);
887 } else { 903 } else {
888 /* for WOL */ 904 /* for WOL */
889 write_nic_dword(dev, WFCRC0, 0xffffffff); 905 write_nic_dword(priv, WFCRC0, 0xffffffff);
890 write_nic_dword(dev, WFCRC1, 0xffffffff); 906 write_nic_dword(priv, WFCRC1, 0xffffffff);
891 write_nic_dword(dev, WFCRC2, 0xffffffff); 907 write_nic_dword(priv, WFCRC2, 0xffffffff);
892 908
893 /* Write PMR register */ 909 /* Write PMR register */
894 write_nic_byte(dev, PMR, 0x5); 910 write_nic_byte(priv, PMR, 0x5);
895 /* Disable tx, enanble rx */ 911 /* Disable tx, enanble rx */
896 write_nic_byte(dev, MacBlkCtrl, 0xa); 912 write_nic_byte(priv, MacBlkCtrl, 0xa);
897 } 913 }
898 } 914 }
899 915
@@ -1102,7 +1118,7 @@ static void rtl8192_update_cap(struct net_device* dev, u16 cap)
1102 tmp = priv->basic_rate; 1118 tmp = priv->basic_rate;
1103 if (priv->short_preamble) 1119 if (priv->short_preamble)
1104 tmp |= BRSR_AckShortPmb; 1120 tmp |= BRSR_AckShortPmb;
1105 write_nic_dword(dev, RRSR, tmp); 1121 write_nic_dword(priv, RRSR, tmp);
1106 1122
1107 if (net->mode & (IEEE_G|IEEE_N_24G)) 1123 if (net->mode & (IEEE_G|IEEE_N_24G))
1108 { 1124 {
@@ -1114,7 +1130,7 @@ static void rtl8192_update_cap(struct net_device* dev, u16 cap)
1114 else //long slot time 1130 else //long slot time
1115 slot_time = NON_SHORT_SLOT_TIME; 1131 slot_time = NON_SHORT_SLOT_TIME;
1116 priv->slot_time = slot_time; 1132 priv->slot_time = slot_time;
1117 write_nic_byte(dev, SLOT_TIME, slot_time); 1133 write_nic_byte(priv, SLOT_TIME, slot_time);
1118 } 1134 }
1119 1135
1120} 1136}
@@ -1139,25 +1155,25 @@ static void rtl8192_net_update(struct net_device *dev)
1139 priv->basic_rate = rate_config &= 0x15f; 1155 priv->basic_rate = rate_config &= 0x15f;
1140 1156
1141 /* BSSID */ 1157 /* BSSID */
1142 write_nic_dword(dev, BSSIDR, ((u32 *)net->bssid)[0]); 1158 write_nic_dword(priv, BSSIDR, ((u32 *)net->bssid)[0]);
1143 write_nic_word(dev, BSSIDR+4, ((u16 *)net->bssid)[2]); 1159 write_nic_word(priv, BSSIDR+4, ((u16 *)net->bssid)[2]);
1144 1160
1145 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC) 1161 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
1146 { 1162 {
1147 write_nic_word(dev, ATIMWND, 2); 1163 write_nic_word(priv, ATIMWND, 2);
1148 write_nic_word(dev, BCN_DMATIME, 256); 1164 write_nic_word(priv, BCN_DMATIME, 256);
1149 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval); 1165 write_nic_word(priv, BCN_INTERVAL, net->beacon_interval);
1150 /* 1166 /*
1151 * BIT15 of BCN_DRV_EARLY_INT will indicate 1167 * BIT15 of BCN_DRV_EARLY_INT will indicate
1152 * whether software beacon or hw beacon is applied. 1168 * whether software beacon or hw beacon is applied.
1153 */ 1169 */
1154 write_nic_word(dev, BCN_DRV_EARLY_INT, 10); 1170 write_nic_word(priv, BCN_DRV_EARLY_INT, 10);
1155 write_nic_byte(dev, BCN_ERR_THRESH, 100); 1171 write_nic_byte(priv, BCN_ERR_THRESH, 100);
1156 1172
1157 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT); 1173 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
1158 /* TODO: BcnIFS may required to be changed on ASIC */ 1174 /* TODO: BcnIFS may required to be changed on ASIC */
1159 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; 1175 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
1160 write_nic_word(dev, BCN_TCFG, BcnTimeCfg); 1176 write_nic_word(priv, BCN_TCFG, BcnTimeCfg);
1161 } 1177 }
1162} 1178}
1163 1179
@@ -1200,7 +1216,7 @@ void rtl819xE_tx_cmd(struct net_device *dev, struct sk_buff *skb)
1200 __skb_queue_tail(&ring->queue, skb); 1216 __skb_queue_tail(&ring->queue, skb);
1201 spin_unlock_irqrestore(&priv->irq_th_lock,flags); 1217 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
1202 1218
1203 write_nic_byte(dev, TPPoll, TPPoll_CQ); 1219 write_nic_byte(priv, TPPoll, TPPoll_CQ);
1204 1220
1205 return; 1221 return;
1206} 1222}
@@ -1465,7 +1481,7 @@ short rtl8192_tx(struct net_device *dev, struct sk_buff* skb)
1465 pdesc->OWN = 1; 1481 pdesc->OWN = 1;
1466 spin_unlock_irqrestore(&priv->irq_th_lock, flags); 1482 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
1467 dev->trans_start = jiffies; 1483 dev->trans_start = jiffies;
1468 write_nic_word(dev, TPPoll, 0x01<<tcb_desc->queue_index); 1484 write_nic_word(priv, TPPoll, 0x01<<tcb_desc->queue_index);
1469 return 0; 1485 return 0;
1470} 1486}
1471 1487
@@ -1601,7 +1617,7 @@ static void rtl8192_link_change(struct net_device *dev)
1601{ 1617{
1602 struct r8192_priv *priv = ieee80211_priv(dev); 1618 struct r8192_priv *priv = ieee80211_priv(dev);
1603 struct ieee80211_device* ieee = priv->ieee80211; 1619 struct ieee80211_device* ieee = priv->ieee80211;
1604 //write_nic_word(dev, BCN_INTR_ITV, net->beacon_interval); 1620 //write_nic_word(priv, BCN_INTR_ITV, net->beacon_interval);
1605 if (ieee->state == IEEE80211_LINKED) 1621 if (ieee->state == IEEE80211_LINKED)
1606 { 1622 {
1607 rtl8192_net_update(dev); 1623 rtl8192_net_update(dev);
@@ -1613,7 +1629,7 @@ static void rtl8192_link_change(struct net_device *dev)
1613 } 1629 }
1614 else 1630 else
1615 { 1631 {
1616 write_nic_byte(dev, 0x173, 0); 1632 write_nic_byte(priv, 0x173, 0);
1617 } 1633 }
1618 /*update timing params*/ 1634 /*update timing params*/
1619 //rtl8192_set_chan(dev, priv->chan); 1635 //rtl8192_set_chan(dev, priv->chan);
@@ -1625,12 +1641,12 @@ static void rtl8192_link_change(struct net_device *dev)
1625 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) 1641 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC)
1626 { 1642 {
1627 u32 reg = 0; 1643 u32 reg = 0;
1628 reg = read_nic_dword(dev, RCR); 1644 reg = read_nic_dword(priv, RCR);
1629 if (priv->ieee80211->state == IEEE80211_LINKED) 1645 if (priv->ieee80211->state == IEEE80211_LINKED)
1630 priv->ReceiveConfig = reg |= RCR_CBSSID; 1646 priv->ReceiveConfig = reg |= RCR_CBSSID;
1631 else 1647 else
1632 priv->ReceiveConfig = reg &= ~RCR_CBSSID; 1648 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1633 write_nic_dword(dev, RCR, reg); 1649 write_nic_dword(priv, RCR, reg);
1634 } 1650 }
1635} 1651}
1636 1652
@@ -1663,7 +1679,6 @@ static const int WDCAPARA_ADD[] = {EDCAPARA_BE,EDCAPARA_BK,EDCAPARA_VI,EDCAPARA_
1663static void rtl8192_qos_activate(struct work_struct * work) 1679static void rtl8192_qos_activate(struct work_struct * work)
1664{ 1680{
1665 struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate); 1681 struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate);
1666 struct net_device *dev = priv->ieee80211->dev;
1667 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters; 1682 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
1668 u8 mode = priv->ieee80211->current_network.mode; 1683 u8 mode = priv->ieee80211->current_network.mode;
1669 u8 u1bAIFS; 1684 u8 u1bAIFS;
@@ -1684,8 +1699,8 @@ static void rtl8192_qos_activate(struct work_struct * work)
1684 (((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)| 1699 (((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)|
1685 (((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)| 1700 (((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)|
1686 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET)); 1701 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
1687 write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam); 1702 write_nic_dword(priv, WDCAPARA_ADD[i], u4bAcParam);
1688 //write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332); 1703 //write_nic_dword(priv, WDCAPARA_ADD[i], 0x005e4332);
1689 } 1704 }
1690 1705
1691success: 1706success:
@@ -1855,8 +1870,8 @@ static void rtl8192_update_ratr_table(struct net_device* dev)
1855 }else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){ 1870 }else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){
1856 ratr_value |= 0x80000000; 1871 ratr_value |= 0x80000000;
1857 } 1872 }
1858 write_nic_dword(dev, RATR0+rate_index*4, ratr_value); 1873 write_nic_dword(priv, RATR0+rate_index*4, ratr_value);
1859 write_nic_byte(dev, UFWP, 1); 1874 write_nic_byte(priv, UFWP, 1);
1860} 1875}
1861 1876
1862static bool GetNmodeSupportBySecCfg8190Pci(struct net_device*dev) 1877static bool GetNmodeSupportBySecCfg8190Pci(struct net_device*dev)
@@ -2255,7 +2270,7 @@ static void rtl8192_get_eeprom_size(struct net_device* dev)
2255 u16 curCR = 0; 2270 u16 curCR = 0;
2256 struct r8192_priv *priv = ieee80211_priv(dev); 2271 struct r8192_priv *priv = ieee80211_priv(dev);
2257 RT_TRACE(COMP_INIT, "===========>%s()\n", __FUNCTION__); 2272 RT_TRACE(COMP_INIT, "===========>%s()\n", __FUNCTION__);
2258 curCR = read_nic_dword(dev, EPROM_CMD); 2273 curCR = read_nic_dword(priv, EPROM_CMD);
2259 RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD, curCR); 2274 RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD, curCR);
2260 //whether need I consider BIT5? 2275 //whether need I consider BIT5?
2261 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EPROM_93c56 : EPROM_93c46; 2276 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EPROM_93c56 : EPROM_93c46;
@@ -2266,10 +2281,9 @@ static void rtl8192_get_eeprom_size(struct net_device* dev)
2266 * Adapter->EEPROMAddressSize should be set before this function call. 2281 * Adapter->EEPROMAddressSize should be set before this function call.
2267 * EEPROM address size can be got through GetEEPROMSize8185() 2282 * EEPROM address size can be got through GetEEPROMSize8185()
2268 */ 2283 */
2269static void rtl8192_read_eeprom_info(struct net_device* dev) 2284static void rtl8192_read_eeprom_info(struct r8192_priv *priv)
2270{ 2285{
2271 struct r8192_priv *priv = ieee80211_priv(dev); 2286 struct net_device *dev = priv->ieee80211->dev;
2272
2273 u8 tempval; 2287 u8 tempval;
2274#ifdef RTL8192E 2288#ifdef RTL8192E
2275 u8 ICVer8192, ICVer8256; 2289 u8 ICVer8192, ICVer8256;
@@ -2794,7 +2808,7 @@ static short rtl8192_init(struct net_device *dev)
2794 rtl8192_init_priv_lock(priv); 2808 rtl8192_init_priv_lock(priv);
2795 rtl8192_init_priv_task(dev); 2809 rtl8192_init_priv_task(dev);
2796 rtl8192_get_eeprom_size(dev); 2810 rtl8192_get_eeprom_size(dev);
2797 rtl8192_read_eeprom_info(dev); 2811 rtl8192_read_eeprom_info(priv);
2798 rtl8192_get_channel_map(dev); 2812 rtl8192_get_channel_map(dev);
2799 init_hal_dm(dev); 2813 init_hal_dm(dev);
2800 init_timer(&priv->watch_dog_timer); 2814 init_timer(&priv->watch_dog_timer);
@@ -2862,7 +2876,7 @@ static void rtl8192_hwconfig(struct net_device* dev)
2862 break; 2876 break;
2863 } 2877 }
2864 2878
2865 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 2879 write_nic_byte(priv, BW_OPMODE, regBwOpMode);
2866 { 2880 {
2867 u32 ratr_value = 0; 2881 u32 ratr_value = 0;
2868 ratr_value = regRATR; 2882 ratr_value = regRATR;
@@ -2870,17 +2884,17 @@ static void rtl8192_hwconfig(struct net_device* dev)
2870 { 2884 {
2871 ratr_value &= ~(RATE_ALL_OFDM_2SS); 2885 ratr_value &= ~(RATE_ALL_OFDM_2SS);
2872 } 2886 }
2873 write_nic_dword(dev, RATR0, ratr_value); 2887 write_nic_dword(priv, RATR0, ratr_value);
2874 write_nic_byte(dev, UFWP, 1); 2888 write_nic_byte(priv, UFWP, 1);
2875 } 2889 }
2876 regTmp = read_nic_byte(dev, 0x313); 2890 regTmp = read_nic_byte(priv, 0x313);
2877 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff); 2891 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
2878 write_nic_dword(dev, RRSR, regRRSR); 2892 write_nic_dword(priv, RRSR, regRRSR);
2879 2893
2880 // 2894 //
2881 // Set Retry Limit here 2895 // Set Retry Limit here
2882 // 2896 //
2883 write_nic_word(dev, RETRY_LIMIT, 2897 write_nic_word(priv, RETRY_LIMIT,
2884 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | 2898 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
2885 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT); 2899 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
2886 // Set Contention Window here 2900 // Set Contention Window here
@@ -2922,7 +2936,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2922 //dPLL on 2936 //dPLL on
2923 if(priv->ResetProgress == RESET_TYPE_NORESET) 2937 if(priv->ResetProgress == RESET_TYPE_NORESET)
2924 { 2938 {
2925 write_nic_byte(dev, ANAPAR, 0x37); 2939 write_nic_byte(priv, ANAPAR, 0x37);
2926 // Accordign to designer's explain, LBUS active will never > 10ms. We delay 10ms 2940 // Accordign to designer's explain, LBUS active will never > 10ms. We delay 10ms
2927 // Joseph increae the time to prevent firmware download fail 2941 // Joseph increae the time to prevent firmware download fail
2928 mdelay(500); 2942 mdelay(500);
@@ -2936,7 +2950,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2936 //3 //Config CPUReset Register 2950 //3 //Config CPUReset Register
2937 //3// 2951 //3//
2938 //3 Firmware Reset Or Not 2952 //3 Firmware Reset Or Not
2939 ulRegRead = read_nic_dword(dev, CPU_GEN); 2953 ulRegRead = read_nic_dword(priv, CPU_GEN);
2940 if(priv->pFirmware->firmware_status == FW_STATUS_0_INIT) 2954 if(priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
2941 { //called from MPInitialized. do nothing 2955 { //called from MPInitialized. do nothing
2942 ulRegRead |= CPU_GEN_SYSTEM_RESET; 2956 ulRegRead |= CPU_GEN_SYSTEM_RESET;
@@ -2950,7 +2964,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2950 ulRegRead &= (~(CPU_GEN_GPIO_UART)); 2964 ulRegRead &= (~(CPU_GEN_GPIO_UART));
2951#endif 2965#endif
2952 2966
2953 write_nic_dword(dev, CPU_GEN, ulRegRead); 2967 write_nic_dword(priv, CPU_GEN, ulRegRead);
2954 //mdelay(100); 2968 //mdelay(100);
2955 2969
2956#ifdef RTL8192E 2970#ifdef RTL8192E
@@ -2959,18 +2973,18 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2959 //3 //Fix the issue of E-cut high temperature issue 2973 //3 //Fix the issue of E-cut high temperature issue
2960 //3// 2974 //3//
2961 // TODO: E cut only 2975 // TODO: E cut only
2962 ICVersion = read_nic_byte(dev, IC_VERRSION); 2976 ICVersion = read_nic_byte(priv, IC_VERRSION);
2963 if(ICVersion >= 0x4) //E-cut only 2977 if(ICVersion >= 0x4) //E-cut only
2964 { 2978 {
2965 // HW SD suggest that we should not wirte this register too often, so driver 2979 // HW SD suggest that we should not wirte this register too often, so driver
2966 // should readback this register. This register will be modified only when 2980 // should readback this register. This register will be modified only when
2967 // power on reset 2981 // power on reset
2968 SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR); 2982 SwitchingRegulatorOutput = read_nic_byte(priv, SWREGULATOR);
2969 if(SwitchingRegulatorOutput != 0xb8) 2983 if(SwitchingRegulatorOutput != 0xb8)
2970 { 2984 {
2971 write_nic_byte(dev, SWREGULATOR, 0xa8); 2985 write_nic_byte(priv, SWREGULATOR, 0xa8);
2972 mdelay(1); 2986 mdelay(1);
2973 write_nic_byte(dev, SWREGULATOR, 0xb8); 2987 write_nic_byte(priv, SWREGULATOR, 0xb8);
2974 } 2988 }
2975 } 2989 }
2976#endif 2990#endif
@@ -2997,7 +3011,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
2997 //priv->LoopbackMode = RTL819X_MAC_LOOPBACK; 3011 //priv->LoopbackMode = RTL819X_MAC_LOOPBACK;
2998 if(priv->ResetProgress == RESET_TYPE_NORESET) 3012 if(priv->ResetProgress == RESET_TYPE_NORESET)
2999 { 3013 {
3000 ulRegRead = read_nic_dword(dev, CPU_GEN); 3014 ulRegRead = read_nic_dword(priv, CPU_GEN);
3001 if(priv->LoopbackMode == RTL819X_NO_LOOPBACK) 3015 if(priv->LoopbackMode == RTL819X_NO_LOOPBACK)
3002 { 3016 {
3003 ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET); 3017 ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET);
@@ -3013,7 +3027,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3013 3027
3014 //2008.06.03, for WOL 3028 //2008.06.03, for WOL
3015 //ulRegRead &= (~(CPU_GEN_GPIO_UART)); 3029 //ulRegRead &= (~(CPU_GEN_GPIO_UART));
3016 write_nic_dword(dev, CPU_GEN, ulRegRead); 3030 write_nic_dword(priv, CPU_GEN, ulRegRead);
3017 3031
3018 // 2006.11.29. After reset cpu, we sholud wait for a second, otherwise, it may fail to write registers. Emily 3032 // 2006.11.29. After reset cpu, we sholud wait for a second, otherwise, it may fail to write registers. Emily
3019 udelay(500); 3033 udelay(500);
@@ -3025,24 +3039,24 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3025 //2======================================================= 3039 //2=======================================================
3026 // If there is changes, please make sure it applies to all of the FPGA version 3040 // If there is changes, please make sure it applies to all of the FPGA version
3027 //3 Turn on Tx/Rx 3041 //3 Turn on Tx/Rx
3028 write_nic_byte(dev, CMDR, CR_RE|CR_TE); 3042 write_nic_byte(priv, CMDR, CR_RE|CR_TE);
3029 3043
3030 //2Set Tx dma burst 3044 //2Set Tx dma burst
3031#ifdef RTL8190P 3045#ifdef RTL8190P
3032 write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) | 3046 write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
3033 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) | 3047 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) |
3034 (1<<MULRW_SHIFT))); 3048 (1<<MULRW_SHIFT)));
3035#else 3049#else
3036 #ifdef RTL8192E 3050 #ifdef RTL8192E
3037 write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) | 3051 write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
3038 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) )); 3052 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) ));
3039 #endif 3053 #endif
3040#endif 3054#endif
3041 //set IDR0 here 3055 //set IDR0 here
3042 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]); 3056 write_nic_dword(priv, MAC0, ((u32*)dev->dev_addr)[0]);
3043 write_nic_word(dev, MAC4, ((u16*)(dev->dev_addr + 4))[0]); 3057 write_nic_word(priv, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
3044 //set RCR 3058 //set RCR
3045 write_nic_dword(dev, RCR, priv->ReceiveConfig); 3059 write_nic_dword(priv, RCR, priv->ReceiveConfig);
3046 3060
3047 //3 Initialize Number of Reserved Pages in Firmware Queue 3061 //3 Initialize Number of Reserved Pages in Firmware Queue
3048 #ifdef TO_DO_LIST 3062 #ifdef TO_DO_LIST
@@ -3060,12 +3074,12 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3060 else 3074 else
3061 #endif 3075 #endif
3062 { 3076 {
3063 write_nic_dword(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT | 3077 write_nic_dword(priv, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT |
3064 NUM_OF_PAGE_IN_FW_QUEUE_BE << RSVD_FW_QUEUE_PAGE_BE_SHIFT | 3078 NUM_OF_PAGE_IN_FW_QUEUE_BE << RSVD_FW_QUEUE_PAGE_BE_SHIFT |
3065 NUM_OF_PAGE_IN_FW_QUEUE_VI << RSVD_FW_QUEUE_PAGE_VI_SHIFT | 3079 NUM_OF_PAGE_IN_FW_QUEUE_VI << RSVD_FW_QUEUE_PAGE_VI_SHIFT |
3066 NUM_OF_PAGE_IN_FW_QUEUE_VO <<RSVD_FW_QUEUE_PAGE_VO_SHIFT); 3080 NUM_OF_PAGE_IN_FW_QUEUE_VO <<RSVD_FW_QUEUE_PAGE_VO_SHIFT);
3067 write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT); 3081 write_nic_dword(priv, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
3068 write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW| 3082 write_nic_dword(priv, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW|
3069 NUM_OF_PAGE_IN_FW_QUEUE_BCN<<RSVD_FW_QUEUE_PAGE_BCN_SHIFT| 3083 NUM_OF_PAGE_IN_FW_QUEUE_BCN<<RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
3070 NUM_OF_PAGE_IN_FW_QUEUE_PUB<<RSVD_FW_QUEUE_PAGE_PUB_SHIFT); 3084 NUM_OF_PAGE_IN_FW_QUEUE_PUB<<RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
3071 } 3085 }
@@ -3075,13 +3089,13 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3075 //3Set Response Rate Setting Register 3089 //3Set Response Rate Setting Register
3076 // CCK rate is supported by default. 3090 // CCK rate is supported by default.
3077 // CCK rate will be filtered out only when associated AP does not support it. 3091 // CCK rate will be filtered out only when associated AP does not support it.
3078 ulRegRead = (0xFFF00000 & read_nic_dword(dev, RRSR)) | RATE_ALL_OFDM_AG | RATE_ALL_CCK; 3092 ulRegRead = (0xFFF00000 & read_nic_dword(priv, RRSR)) | RATE_ALL_OFDM_AG | RATE_ALL_CCK;
3079 write_nic_dword(dev, RRSR, ulRegRead); 3093 write_nic_dword(priv, RRSR, ulRegRead);
3080 write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK)); 3094 write_nic_dword(priv, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
3081 3095
3082 //2Set AckTimeout 3096 //2Set AckTimeout
3083 // TODO: (it value is only for FPGA version). need to be changed!!2006.12.18, by Emily 3097 // TODO: (it value is only for FPGA version). need to be changed!!2006.12.18, by Emily
3084 write_nic_byte(dev, ACK_TIMEOUT, 0x30); 3098 write_nic_byte(priv, ACK_TIMEOUT, 0x30);
3085 3099
3086 //rtl8192_actset_wirelessmode(dev,priv->RegWirelessMode); 3100 //rtl8192_actset_wirelessmode(dev,priv->RegWirelessMode);
3087 if(priv->ResetProgress == RESET_TYPE_NORESET) 3101 if(priv->ResetProgress == RESET_TYPE_NORESET)
@@ -3097,19 +3111,19 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3097 SECR_value |= SCR_TxEncEnable; 3111 SECR_value |= SCR_TxEncEnable;
3098 SECR_value |= SCR_RxDecEnable; 3112 SECR_value |= SCR_RxDecEnable;
3099 SECR_value |= SCR_NoSKMC; 3113 SECR_value |= SCR_NoSKMC;
3100 write_nic_byte(dev, SECR, SECR_value); 3114 write_nic_byte(priv, SECR, SECR_value);
3101 } 3115 }
3102 //3Beacon related 3116 //3Beacon related
3103 write_nic_word(dev, ATIMWND, 2); 3117 write_nic_word(priv, ATIMWND, 2);
3104 write_nic_word(dev, BCN_INTERVAL, 100); 3118 write_nic_word(priv, BCN_INTERVAL, 100);
3105 for (i=0; i<QOS_QUEUE_NUM; i++) 3119 for (i=0; i<QOS_QUEUE_NUM; i++)
3106 write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332); 3120 write_nic_dword(priv, WDCAPARA_ADD[i], 0x005e4332);
3107 // 3121 //
3108 // Switching regulator controller: This is set temporarily. 3122 // Switching regulator controller: This is set temporarily.
3109 // It's not sure if this can be removed in the future. 3123 // It's not sure if this can be removed in the future.
3110 // PJ advised to leave it by default. 3124 // PJ advised to leave it by default.
3111 // 3125 //
3112 write_nic_byte(dev, 0xbe, 0xc0); 3126 write_nic_byte(priv, 0xbe, 0xc0);
3113 3127
3114 //2======================================================= 3128 //2=======================================================
3115 // Set PHY related configuration defined in MAC register bank 3129 // Set PHY related configuration defined in MAC register bank
@@ -3122,7 +3136,7 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3122 } 3136 }
3123 3137
3124 //if D or C cut 3138 //if D or C cut
3125 tmpvalue = read_nic_byte(dev, IC_VERRSION); 3139 tmpvalue = read_nic_byte(priv, IC_VERRSION);
3126 priv->IC_Cut = tmpvalue; 3140 priv->IC_Cut = tmpvalue;
3127 RT_TRACE(COMP_INIT, "priv->IC_Cut = 0x%x\n", priv->IC_Cut); 3141 RT_TRACE(COMP_INIT, "priv->IC_Cut = 0x%x\n", priv->IC_Cut);
3128 if(priv->IC_Cut >= IC_VersionCut_D) 3142 if(priv->IC_Cut >= IC_VersionCut_D)
@@ -3173,17 +3187,17 @@ static RT_STATUS rtl8192_adapter_start(struct net_device *dev)
3173 3187
3174#ifdef RTL8192E 3188#ifdef RTL8192E
3175 //Enable Led 3189 //Enable Led
3176 write_nic_byte(dev, 0x87, 0x0); 3190 write_nic_byte(priv, 0x87, 0x0);
3177#endif 3191#endif
3178#ifdef RTL8190P 3192#ifdef RTL8190P
3179 //2008.06.03, for WOL 3193 //2008.06.03, for WOL
3180 ucRegRead = read_nic_byte(dev, GPE); 3194 ucRegRead = read_nic_byte(priv, GPE);
3181 ucRegRead |= BIT0; 3195 ucRegRead |= BIT0;
3182 write_nic_byte(dev, GPE, ucRegRead); 3196 write_nic_byte(priv, GPE, ucRegRead);
3183 3197
3184 ucRegRead = read_nic_byte(dev, GPO); 3198 ucRegRead = read_nic_byte(priv, GPO);
3185 ucRegRead &= ~BIT0; 3199 ucRegRead &= ~BIT0;
3186 write_nic_byte(dev, GPO, ucRegRead); 3200 write_nic_byte(priv, GPO, ucRegRead);
3187#endif 3201#endif
3188 3202
3189 //2======================================================= 3203 //2=======================================================
@@ -3376,34 +3390,34 @@ static void rtl8192_start_beacon(struct net_device *dev)
3376 //rtl8192_beacon_tx_enable(dev); 3390 //rtl8192_beacon_tx_enable(dev);
3377 3391
3378 /* ATIM window */ 3392 /* ATIM window */
3379 write_nic_word(dev, ATIMWND, 2); 3393 write_nic_word(priv, ATIMWND, 2);
3380 3394
3381 /* Beacon interval (in unit of TU) */ 3395 /* Beacon interval (in unit of TU) */
3382 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval); 3396 write_nic_word(priv, BCN_INTERVAL, net->beacon_interval);
3383 3397
3384 /* 3398 /*
3385 * DrvErlyInt (in unit of TU). 3399 * DrvErlyInt (in unit of TU).
3386 * (Time to send interrupt to notify driver to c 3400 * (Time to send interrupt to notify driver to c
3387 * hange beacon content) 3401 * hange beacon content)
3388 * */ 3402 * */
3389 write_nic_word(dev, BCN_DRV_EARLY_INT, 10); 3403 write_nic_word(priv, BCN_DRV_EARLY_INT, 10);
3390 3404
3391 /* 3405 /*
3392 * BcnDMATIM(in unit of us). 3406 * BcnDMATIM(in unit of us).
3393 * Indicates the time before TBTT to perform beacon queue DMA 3407 * Indicates the time before TBTT to perform beacon queue DMA
3394 * */ 3408 * */
3395 write_nic_word(dev, BCN_DMATIME, 256); 3409 write_nic_word(priv, BCN_DMATIME, 256);
3396 3410
3397 /* 3411 /*
3398 * Force beacon frame transmission even after receiving 3412 * Force beacon frame transmission even after receiving
3399 * beacon frame from other ad hoc STA 3413 * beacon frame from other ad hoc STA
3400 * */ 3414 * */
3401 write_nic_byte(dev, BCN_ERR_THRESH, 100); 3415 write_nic_byte(priv, BCN_ERR_THRESH, 100);
3402 3416
3403 /* Set CW and IFS */ 3417 /* Set CW and IFS */
3404 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT; 3418 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
3405 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; 3419 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
3406 write_nic_word(dev, BCN_TCFG, BcnTimeCfg); 3420 write_nic_word(priv, BCN_TCFG, BcnTimeCfg);
3407 3421
3408 3422
3409 /* enable the interrupt for ad-hoc process */ 3423 /* enable the interrupt for ad-hoc process */
@@ -3412,8 +3426,8 @@ static void rtl8192_start_beacon(struct net_device *dev)
3412 3426
3413static bool HalTxCheckStuck8190Pci(struct net_device *dev) 3427static bool HalTxCheckStuck8190Pci(struct net_device *dev)
3414{ 3428{
3415 u16 RegTxCounter = read_nic_word(dev, 0x128);
3416 struct r8192_priv *priv = ieee80211_priv(dev); 3429 struct r8192_priv *priv = ieee80211_priv(dev);
3430 u16 RegTxCounter = read_nic_word(priv, 0x128);
3417 bool bStuck = FALSE; 3431 bool bStuck = FALSE;
3418 RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter); 3432 RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter);
3419 if(priv->TxCounter==RegTxCounter) 3433 if(priv->TxCounter==RegTxCounter)
@@ -3467,7 +3481,7 @@ TxCheckStuck(struct net_device *dev)
3467static bool HalRxCheckStuck8190Pci(struct net_device *dev) 3481static bool HalRxCheckStuck8190Pci(struct net_device *dev)
3468{ 3482{
3469 struct r8192_priv *priv = ieee80211_priv(dev); 3483 struct r8192_priv *priv = ieee80211_priv(dev);
3470 u16 RegRxCounter = read_nic_word(dev, 0x130); 3484 u16 RegRxCounter = read_nic_word(priv, 0x130);
3471 bool bStuck = FALSE; 3485 bool bStuck = FALSE;
3472 3486
3473 RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter); 3487 RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter);
@@ -3829,7 +3843,7 @@ RESET_START:
3829 priv->bResetInProgress = false; 3843 priv->bResetInProgress = false;
3830 3844
3831 // For test --> force write UFWP. 3845 // For test --> force write UFWP.
3832 write_nic_byte(dev, UFWP, 1); 3846 write_nic_byte(priv, UFWP, 1);
3833 RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", priv->reset_count); 3847 RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", priv->reset_count);
3834 } 3848 }
3835} 3849}
@@ -4463,7 +4477,7 @@ static int rtl8192_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4463 setKey(dev, ipw->u.crypt.idx, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key); 4477 setKey(dev, ipw->u.crypt.idx, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
4464 } 4478 }
4465 if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){ 4479 if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){
4466 write_nic_byte(dev, 0x173, 1); //fix aes bug 4480 write_nic_byte(priv, 0x173, 1); //fix aes bug
4467 } 4481 }
4468 4482
4469 } 4483 }
@@ -5419,7 +5433,7 @@ static void rtl8192_rx(struct net_device *dev)
5419 stats.bFirstMPDU = (pDrvInfo->PartAggr==1) && (pDrvInfo->FirstAGGR==1); 5433 stats.bFirstMPDU = (pDrvInfo->PartAggr==1) && (pDrvInfo->FirstAGGR==1);
5420 5434
5421 stats.TimeStampLow = pDrvInfo->TSFL; 5435 stats.TimeStampLow = pDrvInfo->TSFL;
5422 stats.TimeStampHigh = read_nic_dword(dev, TSFR+4); 5436 stats.TimeStampHigh = read_nic_dword(priv, TSFR+4);
5423 5437
5424 UpdateRxPktTimeStamp8190(dev, &stats); 5438 UpdateRxPktTimeStamp8190(dev, &stats);
5425 5439
@@ -5490,7 +5504,7 @@ static void rtl8192_irq_rx_tasklet(struct r8192_priv *priv)
5490{ 5504{
5491 rtl8192_rx(priv->ieee80211->dev); 5505 rtl8192_rx(priv->ieee80211->dev);
5492 /* unmask RDU */ 5506 /* unmask RDU */
5493 write_nic_dword(priv->ieee80211->dev, INTA_MASK,read_nic_dword(priv->ieee80211->dev, INTA_MASK) | IMR_RDU); 5507 write_nic_dword(priv, INTA_MASK, read_nic_dword(priv, INTA_MASK) | IMR_RDU);
5494} 5508}
5495 5509
5496static const struct net_device_ops rtl8192_netdev_ops = { 5510static const struct net_device_ops rtl8192_netdev_ops = {
@@ -5810,8 +5824,8 @@ static irqreturn_t rtl8192_interrupt(int irq, void *netdev)
5810 5824
5811 /* ISR: 4bytes */ 5825 /* ISR: 4bytes */
5812 5826
5813 inta = read_nic_dword(dev, ISR); /* & priv->IntrMask; */ 5827 inta = read_nic_dword(priv, ISR); /* & priv->IntrMask; */
5814 write_nic_dword(dev, ISR, inta); /* reset int situation */ 5828 write_nic_dword(priv, ISR, inta); /* reset int situation */
5815 5829
5816 if (!inta) { 5830 if (!inta) {
5817 /* 5831 /*
@@ -5867,7 +5881,7 @@ static irqreturn_t rtl8192_interrupt(int irq, void *netdev)
5867 RT_TRACE(COMP_INTR, "rx descriptor unavailable!\n"); 5881 RT_TRACE(COMP_INTR, "rx descriptor unavailable!\n");
5868 priv->stats.rxrdu++; 5882 priv->stats.rxrdu++;
5869 /* reset int situation */ 5883 /* reset int situation */
5870 write_nic_dword(dev, INTA_MASK, read_nic_dword(dev, INTA_MASK) & ~IMR_RDU); 5884 write_nic_dword(priv, INTA_MASK, read_nic_dword(priv, INTA_MASK) & ~IMR_RDU);
5871 tasklet_schedule(&priv->irq_rx_tasklet); 5885 tasklet_schedule(&priv->irq_rx_tasklet);
5872 } 5886 }
5873 5887
@@ -5945,7 +5959,7 @@ void EnableHWSecurityConfig8192(struct net_device *dev)
5945 RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__, 5959 RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__,
5946 ieee->hwsec_active, ieee->pairwise_key_type, SECR_value); 5960 ieee->hwsec_active, ieee->pairwise_key_type, SECR_value);
5947 { 5961 {
5948 write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK ); 5962 write_nic_byte(priv, SECR, SECR_value);//SECR_value | SCR_UseDK );
5949 } 5963 }
5950 5964
5951} 5965}
@@ -6005,22 +6019,22 @@ void setKey( struct net_device *dev,
6005 (u32)(*(MacAddr+1)) << 24| 6019 (u32)(*(MacAddr+1)) << 24|
6006 (u32)usConfig; 6020 (u32)usConfig;
6007 6021
6008 write_nic_dword(dev, WCAMI, TargetContent); 6022 write_nic_dword(priv, WCAMI, TargetContent);
6009 write_nic_dword(dev, RWCAM, TargetCommand); 6023 write_nic_dword(priv, RWCAM, TargetCommand);
6010 } 6024 }
6011 else if(i==1){//MAC 6025 else if(i==1){//MAC
6012 TargetContent = (u32)(*(MacAddr+2)) | 6026 TargetContent = (u32)(*(MacAddr+2)) |
6013 (u32)(*(MacAddr+3)) << 8| 6027 (u32)(*(MacAddr+3)) << 8|
6014 (u32)(*(MacAddr+4)) << 16| 6028 (u32)(*(MacAddr+4)) << 16|
6015 (u32)(*(MacAddr+5)) << 24; 6029 (u32)(*(MacAddr+5)) << 24;
6016 write_nic_dword(dev, WCAMI, TargetContent); 6030 write_nic_dword(priv, WCAMI, TargetContent);
6017 write_nic_dword(dev, RWCAM, TargetCommand); 6031 write_nic_dword(priv, RWCAM, TargetCommand);
6018 } 6032 }
6019 else { //Key Material 6033 else { //Key Material
6020 if(KeyContent != NULL) 6034 if(KeyContent != NULL)
6021 { 6035 {
6022 write_nic_dword(dev, WCAMI, (u32)(*(KeyContent+i-2)) ); 6036 write_nic_dword(priv, WCAMI, (u32)(*(KeyContent+i-2)) );
6023 write_nic_dword(dev, RWCAM, TargetCommand); 6037 write_nic_dword(priv, RWCAM, TargetCommand);
6024 } 6038 }
6025 } 6039 }
6026 } 6040 }
diff --git a/drivers/staging/rtl8192e/r8192E_dm.c b/drivers/staging/rtl8192e/r8192E_dm.c
index 01a7ba61340..d328d6766a7 100644
--- a/drivers/staging/rtl8192e/r8192E_dm.c
+++ b/drivers/staging/rtl8192e/r8192E_dm.c
@@ -198,7 +198,7 @@ void dm_CheckRxAggregation(struct net_device *dev) {
198 198
199 if(curTxOkCnt > 4*curRxOkCnt) { 199 if(curTxOkCnt > 4*curRxOkCnt) {
200 if (priv->bCurrentRxAggrEnable) { 200 if (priv->bCurrentRxAggrEnable) {
201 write_nic_dword(dev, 0x1a8, 0); 201 write_nic_dword(priv, 0x1a8, 0);
202 priv->bCurrentRxAggrEnable = false; 202 priv->bCurrentRxAggrEnable = false;
203 } 203 }
204 }else{ 204 }else{
@@ -211,7 +211,7 @@ void dm_CheckRxAggregation(struct net_device *dev) {
211 * when anyone of three threshold conditions above is reached, 211 * when anyone of three threshold conditions above is reached,
212 * firmware will send aggregated packet to driver. 212 * firmware will send aggregated packet to driver.
213 */ 213 */
214 write_nic_dword(dev, 0x1a8, ulValue); 214 write_nic_dword(priv, 0x1a8, ulValue);
215 priv->bCurrentRxAggrEnable = true; 215 priv->bCurrentRxAggrEnable = true;
216 } 216 }
217 } 217 }
@@ -450,7 +450,7 @@ static void dm_check_rate_adaptive(struct net_device * dev)
450 // 450 //
451 // Check whether updating of RATR0 is required 451 // Check whether updating of RATR0 is required
452 // 452 //
453 currentRATR = read_nic_dword(dev, RATR0); 453 currentRATR = read_nic_dword(priv, RATR0);
454 if( targetRATR != currentRATR ) 454 if( targetRATR != currentRATR )
455 { 455 {
456 u32 ratr_value; 456 u32 ratr_value;
@@ -460,8 +460,8 @@ static void dm_check_rate_adaptive(struct net_device * dev)
460 { 460 {
461 ratr_value &= ~(RATE_ALL_OFDM_2SS); 461 ratr_value &= ~(RATE_ALL_OFDM_2SS);
462 } 462 }
463 write_nic_dword(dev, RATR0, ratr_value); 463 write_nic_dword(priv, RATR0, ratr_value);
464 write_nic_byte(dev, UFWP, 1); 464 write_nic_byte(priv, UFWP, 1);
465 465
466 pra->last_ratr = targetRATR; 466 pra->last_ratr = targetRATR;
467 } 467 }
@@ -580,9 +580,9 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
580// bool rtStatus = true; 580// bool rtStatus = true;
581 u32 delta=0; 581 u32 delta=0;
582 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__); 582 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
583// write_nic_byte(dev, 0x1ba, 0); 583// write_nic_byte(priv, 0x1ba, 0);
584 write_nic_byte(dev, Pw_Track_Flag, 0); 584 write_nic_byte(priv, Pw_Track_Flag, 0);
585 write_nic_byte(dev, FW_Busy_Flag, 0); 585 write_nic_byte(priv, FW_Busy_Flag, 0);
586 priv->ieee80211->bdynamic_txpower_enable = false; 586 priv->ieee80211->bdynamic_txpower_enable = false;
587 bHighpowerstate = priv->bDynamicTxHighPower; 587 bHighpowerstate = priv->bDynamicTxHighPower;
588 588
@@ -611,7 +611,7 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
611 611
612 for(i = 0;i <= 30; i++) 612 for(i = 0;i <= 30; i++)
613 { 613 {
614 Pwr_Flag = read_nic_byte(dev, Pw_Track_Flag); 614 Pwr_Flag = read_nic_byte(priv, Pw_Track_Flag);
615 615
616 if (Pwr_Flag == 0) 616 if (Pwr_Flag == 0)
617 { 617 {
@@ -619,21 +619,21 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
619 continue; 619 continue;
620 } 620 }
621 621
622 Avg_TSSI_Meas = read_nic_word(dev, Tssi_Mea_Value); 622 Avg_TSSI_Meas = read_nic_word(priv, Tssi_Mea_Value);
623 623
624 if(Avg_TSSI_Meas == 0) 624 if(Avg_TSSI_Meas == 0)
625 { 625 {
626 write_nic_byte(dev, Pw_Track_Flag, 0); 626 write_nic_byte(priv, Pw_Track_Flag, 0);
627 write_nic_byte(dev, FW_Busy_Flag, 0); 627 write_nic_byte(priv, FW_Busy_Flag, 0);
628 return; 628 return;
629 } 629 }
630 630
631 for(k = 0;k < 5; k++) 631 for(k = 0;k < 5; k++)
632 { 632 {
633 if(k !=4) 633 if(k !=4)
634 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value1+k); 634 tmp_report[k] = read_nic_byte(priv, Tssi_Report_Value1+k);
635 else 635 else
636 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value2); 636 tmp_report[k] = read_nic_byte(priv, Tssi_Report_Value2);
637 637
638 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]); 638 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
639 } 639 }
@@ -649,7 +649,7 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
649 } 649 }
650 if(viviflag ==TRUE) 650 if(viviflag ==TRUE)
651 { 651 {
652 write_nic_byte(dev, Pw_Track_Flag, 0); 652 write_nic_byte(priv, Pw_Track_Flag, 0);
653 viviflag = FALSE; 653 viviflag = FALSE;
654 RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n"); 654 RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n");
655 for(k = 0;k < 5; k++) 655 for(k = 0;k < 5; k++)
@@ -677,8 +677,8 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
677 if(delta <= E_FOR_TX_POWER_TRACK) 677 if(delta <= E_FOR_TX_POWER_TRACK)
678 { 678 {
679 priv->ieee80211->bdynamic_txpower_enable = TRUE; 679 priv->ieee80211->bdynamic_txpower_enable = TRUE;
680 write_nic_byte(dev, Pw_Track_Flag, 0); 680 write_nic_byte(priv, Pw_Track_Flag, 0);
681 write_nic_byte(dev, FW_Busy_Flag, 0); 681 write_nic_byte(priv, FW_Busy_Flag, 0);
682 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n"); 682 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
683 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex); 683 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
684 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real); 684 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
@@ -811,24 +811,24 @@ static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
811 if (priv->CCKPresentAttentuation_difference <= -12||priv->CCKPresentAttentuation_difference >= 24) 811 if (priv->CCKPresentAttentuation_difference <= -12||priv->CCKPresentAttentuation_difference >= 24)
812 { 812 {
813 priv->ieee80211->bdynamic_txpower_enable = TRUE; 813 priv->ieee80211->bdynamic_txpower_enable = TRUE;
814 write_nic_byte(dev, Pw_Track_Flag, 0); 814 write_nic_byte(priv, Pw_Track_Flag, 0);
815 write_nic_byte(dev, FW_Busy_Flag, 0); 815 write_nic_byte(priv, FW_Busy_Flag, 0);
816 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n"); 816 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
817 return; 817 return;
818 } 818 }
819 819
820 820
821 } 821 }
822 write_nic_byte(dev, Pw_Track_Flag, 0); 822 write_nic_byte(priv, Pw_Track_Flag, 0);
823 Avg_TSSI_Meas_from_driver = 0; 823 Avg_TSSI_Meas_from_driver = 0;
824 for(k = 0;k < 5; k++) 824 for(k = 0;k < 5; k++)
825 tmp_report[k] = 0; 825 tmp_report[k] = 0;
826 break; 826 break;
827 } 827 }
828 write_nic_byte(dev, FW_Busy_Flag, 0); 828 write_nic_byte(priv, FW_Busy_Flag, 0);
829} 829}
830 priv->ieee80211->bdynamic_txpower_enable = TRUE; 830 priv->ieee80211->bdynamic_txpower_enable = TRUE;
831 write_nic_byte(dev, Pw_Track_Flag, 0); 831 write_nic_byte(priv, Pw_Track_Flag, 0);
832} 832}
833#ifndef RTL8190P 833#ifndef RTL8190P
834static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev) 834static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
@@ -1114,7 +1114,7 @@ static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1114 struct r8192_priv *priv = ieee80211_priv(dev); 1114 struct r8192_priv *priv = ieee80211_priv(dev);
1115 static u32 tx_power_track_counter = 0; 1115 static u32 tx_power_track_counter = 0;
1116 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__); 1116 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
1117 if(read_nic_byte(dev, 0x11e) ==1) 1117 if(read_nic_byte(priv, 0x11e) ==1)
1118 return; 1118 return;
1119 if(!priv->btxpower_tracking) 1119 if(!priv->btxpower_tracking)
1120 return; 1120 return;
@@ -1360,8 +1360,8 @@ void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1360 { 1360 {
1361 ratr_value &=~ (RATE_ALL_OFDM_2SS); 1361 ratr_value &=~ (RATE_ALL_OFDM_2SS);
1362 } 1362 }
1363 write_nic_dword(dev, RATR0, ratr_value); 1363 write_nic_dword(priv, RATR0, ratr_value);
1364 write_nic_byte(dev, UFWP, 1); 1364 write_nic_byte(priv, UFWP, 1);
1365 } 1365 }
1366 //Resore TX Power Tracking Index 1366 //Resore TX Power Tracking Index
1367 if(priv->btxpower_trackingInit && priv->btxpower_tracking){ 1367 if(priv->btxpower_trackingInit && priv->btxpower_tracking){
@@ -1653,10 +1653,10 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1653 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. 1653 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1654 1654
1655 // 1.2 Set initial gain. 1655 // 1.2 Set initial gain.
1656 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); 1656 write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x17);
1657 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17); 1657 write_nic_byte(priv, rOFDM0_XBAGCCore1, 0x17);
1658 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17); 1658 write_nic_byte(priv, rOFDM0_XCAGCCore1, 0x17);
1659 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17); 1659 write_nic_byte(priv, rOFDM0_XDAGCCore1, 0x17);
1660 1660
1661 // 1.3 Lower PD_TH for OFDM. 1661 // 1.3 Lower PD_TH for OFDM.
1662 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) 1662 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
@@ -1664,9 +1664,9 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1664 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ 1664 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1665 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. 1665 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1666 #ifdef RTL8190P 1666 #ifdef RTL8190P
1667 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); 1667 write_nic_byte(priv, rOFDM0_RxDetector1, 0x40);
1668 #else 1668 #else
1669 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); 1669 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
1670 #endif 1670 #endif
1671 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) 1671 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1672 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40); 1672 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
@@ -1678,10 +1678,10 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1678 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40); 1678 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1679 } 1679 }
1680 else 1680 else
1681 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); 1681 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1682 1682
1683 // 1.4 Lower CS ratio for CCK. 1683 // 1.4 Lower CS ratio for CCK.
1684 write_nic_byte(dev, 0xa0a, 0x08); 1684 write_nic_byte(priv, 0xa0a, 0x08);
1685 1685
1686 // 1.5 Higher EDCCA. 1686 // 1.5 Higher EDCCA.
1687 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325); 1687 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
@@ -1715,17 +1715,17 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1715 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment. 1715 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
1716 if (reset_flag == 1) 1716 if (reset_flag == 1)
1717 { 1717 {
1718 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); 1718 write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x2c);
1719 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c); 1719 write_nic_byte(priv, rOFDM0_XBAGCCore1, 0x2c);
1720 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c); 1720 write_nic_byte(priv, rOFDM0_XCAGCCore1, 0x2c);
1721 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c); 1721 write_nic_byte(priv, rOFDM0_XDAGCCore1, 0x2c);
1722 } 1722 }
1723 else 1723 else
1724 { 1724 {
1725 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); 1725 write_nic_byte(priv, rOFDM0_XAAGCCore1, 0x20);
1726 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20); 1726 write_nic_byte(priv, rOFDM0_XBAGCCore1, 0x20);
1727 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20); 1727 write_nic_byte(priv, rOFDM0_XCAGCCore1, 0x20);
1728 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20); 1728 write_nic_byte(priv, rOFDM0_XDAGCCore1, 0x20);
1729 } 1729 }
1730 1730
1731 // 2.2 Higher PD_TH for OFDM. 1731 // 2.2 Higher PD_TH for OFDM.
@@ -1734,9 +1734,9 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1734 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ 1734 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1735 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. 1735 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1736 #ifdef RTL8190P 1736 #ifdef RTL8190P
1737 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); 1737 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1738 #else 1738 #else
1739 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); 1739 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
1740 #endif 1740 #endif
1741 /* 1741 /*
1742 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) 1742 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
@@ -1748,10 +1748,10 @@ static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1748 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42); 1748 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
1749 } 1749 }
1750 else 1750 else
1751 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); 1751 write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
1752 1752
1753 // 2.3 Higher CS ratio for CCK. 1753 // 2.3 Higher CS ratio for CCK.
1754 write_nic_byte(dev, 0xa0a, 0xcd); 1754 write_nic_byte(priv, 0xa0a, 0xcd);
1755 1755
1756 // 2.4 Lower EDCCA. 1756 // 2.4 Lower EDCCA.
1757 /* 2008/01/11 MH 90/92 series are the same. */ 1757 /* 2008/01/11 MH 90/92 series are the same. */
@@ -1794,18 +1794,18 @@ static void dm_ctrl_initgain_byrssi_highpwr(
1794 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) 1794 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1795 { 1795 {
1796 #ifdef RTL8190P 1796 #ifdef RTL8190P
1797 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); 1797 write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
1798 #else 1798 #else
1799 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); 1799 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
1800 #endif 1800 #endif
1801 1801
1802 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) 1802 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1803 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); 1803 write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
1804 */ 1804 */
1805 1805
1806 } 1806 }
1807 else 1807 else
1808 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); 1808 write_nic_byte(priv, rOFDM0_RxDetector1, 0x43);
1809 } 1809 }
1810 else 1810 else
1811 { 1811 {
@@ -1822,17 +1822,17 @@ static void dm_ctrl_initgain_byrssi_highpwr(
1822 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) 1822 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1823 { 1823 {
1824 #ifdef RTL8190P 1824 #ifdef RTL8190P
1825 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); 1825 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1826 #else 1826 #else
1827 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); 1827 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
1828 #endif 1828 #endif
1829 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) 1829 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1830 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); 1830 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1831 */ 1831 */
1832 1832
1833 } 1833 }
1834 else 1834 else
1835 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); 1835 write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
1836 } 1836 }
1837 } 1837 }
1838 1838
@@ -1887,7 +1887,7 @@ static void dm_initial_gain(
1887 reset_cnt = priv->reset_count; 1887 reset_cnt = priv->reset_count;
1888 } 1888 }
1889 1889
1890 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1)) 1890 if(dm_digtable.pre_ig_value != read_nic_byte(priv, rOFDM0_XAAGCCore1))
1891 force_write = 1; 1891 force_write = 1;
1892 1892
1893 { 1893 {
@@ -1896,10 +1896,10 @@ static void dm_initial_gain(
1896 { 1896 {
1897 initial_gain = (u8)dm_digtable.cur_ig_value; 1897 initial_gain = (u8)dm_digtable.cur_ig_value;
1898 // Set initial gain. 1898 // Set initial gain.
1899 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 1899 write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);
1900 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); 1900 write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);
1901 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); 1901 write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);
1902 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); 1902 write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);
1903 dm_digtable.pre_ig_value = dm_digtable.cur_ig_value; 1903 dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
1904 initialized = 1; 1904 initialized = 1;
1905 force_write = 0; 1905 force_write = 0;
@@ -1963,16 +1963,16 @@ static void dm_pd_th(
1963 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ 1963 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1964 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. 1964 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1965 #ifdef RTL8190P 1965 #ifdef RTL8190P
1966 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); 1966 write_nic_byte(priv, rOFDM0_RxDetector1, 0x40);
1967 #else 1967 #else
1968 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); 1968 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x00);
1969 #endif 1969 #endif
1970 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) 1970 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1971 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); 1971 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
1972 */ 1972 */
1973 } 1973 }
1974 else 1974 else
1975 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); 1975 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1976 } 1976 }
1977 else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) 1977 else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER)
1978 { 1978 {
@@ -1982,16 +1982,16 @@ static void dm_pd_th(
1982 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ 1982 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1983 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. 1983 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1984 #ifdef RTL8190P 1984 #ifdef RTL8190P
1985 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); 1985 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1986 #else 1986 #else
1987 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); 1987 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x20);
1988 #endif 1988 #endif
1989 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) 1989 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1990 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); 1990 write_nic_byte(priv, rOFDM0_RxDetector1, 0x42);
1991 */ 1991 */
1992 } 1992 }
1993 else 1993 else
1994 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); 1994 write_nic_byte(priv, rOFDM0_RxDetector1, 0x44);
1995 } 1995 }
1996 else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) 1996 else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER)
1997 { 1997 {
@@ -1999,16 +1999,16 @@ static void dm_pd_th(
1999 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) 1999 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2000 { 2000 {
2001 #ifdef RTL8190P 2001 #ifdef RTL8190P
2002 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); 2002 write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
2003 #else 2003 #else
2004 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); 2004 write_nic_byte(priv, (rOFDM0_XATxAFE+3), 0x10);
2005 #endif 2005 #endif
2006 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) 2006 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2007 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); 2007 write_nic_byte(priv, rOFDM0_RxDetector1, 0x41);
2008 */ 2008 */
2009 } 2009 }
2010 else 2010 else
2011 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); 2011 write_nic_byte(priv, rOFDM0_RxDetector1, 0x43);
2012 } 2012 }
2013 dm_digtable.prepd_thstate = dm_digtable.curpd_thstate; 2013 dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2014 if(initialized <= 3) 2014 if(initialized <= 3)
@@ -2066,12 +2066,12 @@ static void dm_cs_ratio(
2066 if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) 2066 if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)
2067 { 2067 {
2068 // Lower CS ratio for CCK. 2068 // Lower CS ratio for CCK.
2069 write_nic_byte(dev, 0xa0a, 0x08); 2069 write_nic_byte(priv, 0xa0a, 0x08);
2070 } 2070 }
2071 else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER) 2071 else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)
2072 { 2072 {
2073 // Higher CS ratio for CCK. 2073 // Higher CS ratio for CCK.
2074 write_nic_byte(dev, 0xa0a, 0xcd); 2074 write_nic_byte(priv, 0xa0a, 0xcd);
2075 } 2075 }
2076 dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state; 2076 dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2077 initialized = 1; 2077 initialized = 1;
@@ -2124,7 +2124,7 @@ static void dm_check_edca_turbo(
2124 { 2124 {
2125 if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) 2125 if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2126 { 2126 {
2127 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]); 2127 write_nic_dword(priv, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2128 priv->bis_cur_rdlstate = true; 2128 priv->bis_cur_rdlstate = true;
2129 } 2129 }
2130 } 2130 }
@@ -2132,7 +2132,7 @@ static void dm_check_edca_turbo(
2132 { 2132 {
2133 if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) 2133 if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2134 { 2134 {
2135 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]); 2135 write_nic_dword(priv, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2136 priv->bis_cur_rdlstate = false; 2136 priv->bis_cur_rdlstate = false;
2137 } 2137 }
2138 2138
@@ -2164,7 +2164,7 @@ static void dm_check_edca_turbo(
2164 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET)); 2164 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
2165 printk("===>u4bAcParam:%x, ", u4bAcParam); 2165 printk("===>u4bAcParam:%x, ", u4bAcParam);
2166 //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam); 2166 //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
2167 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam); 2167 write_nic_dword(priv, EDCAPARA_BE, u4bAcParam);
2168 2168
2169 // Check ACM bit. 2169 // Check ACM bit.
2170 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. 2170 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
@@ -2172,7 +2172,7 @@ static void dm_check_edca_turbo(
2172 // TODO: Modified this part and try to set acm control in only 1 IO processing!! 2172 // TODO: Modified this part and try to set acm control in only 1 IO processing!!
2173 2173
2174 PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]); 2174 PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
2175 u8 AcmCtrl = read_nic_byte( dev, AcmHwCtrl ); 2175 u8 AcmCtrl = read_nic_byte(priv, AcmHwCtrl );
2176 if( pAciAifsn->f.ACM ) 2176 if( pAciAifsn->f.ACM )
2177 { // ACM bit is 1. 2177 { // ACM bit is 1.
2178 AcmCtrl |= AcmHw_BeqEn; 2178 AcmCtrl |= AcmHw_BeqEn;
@@ -2183,7 +2183,7 @@ static void dm_check_edca_turbo(
2183 } 2183 }
2184 2184
2185 RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ; 2185 RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ;
2186 write_nic_byte(dev, AcmHwCtrl, AcmCtrl ); 2186 write_nic_byte(priv, AcmHwCtrl, AcmCtrl );
2187 } 2187 }
2188 } 2188 }
2189 priv->bcurrent_turbo_EDCA = false; 2189 priv->bcurrent_turbo_EDCA = false;
@@ -2292,7 +2292,7 @@ static void dm_check_pbc_gpio(struct net_device *dev)
2292 u8 tmp1byte; 2292 u8 tmp1byte;
2293 2293
2294 2294
2295 tmp1byte = read_nic_byte(dev,GPI); 2295 tmp1byte = read_nic_byte(priv, GPI);
2296 if(tmp1byte == 0xff) 2296 if(tmp1byte == 0xff)
2297 return; 2297 return;
2298 2298
@@ -2323,7 +2323,7 @@ void dm_gpio_change_rf_callback(struct work_struct *work)
2323 } else { 2323 } else {
2324 // 0x108 GPIO input register is read only 2324 // 0x108 GPIO input register is read only
2325 //set 0x108 B1= 1: RF-ON; 0: RF-OFF. 2325 //set 0x108 B1= 1: RF-ON; 0: RF-OFF.
2326 tmp1byte = read_nic_byte(dev,GPI); 2326 tmp1byte = read_nic_byte(priv, GPI);
2327 2327
2328 eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff; 2328 eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff;
2329 2329
@@ -2362,7 +2362,7 @@ void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
2362 2362
2363 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will 2363 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
2364 always be the same. We only read 0xc04 now. */ 2364 always be the same. We only read 0xc04 now. */
2365 rfpath = read_nic_byte(dev, 0xc04); 2365 rfpath = read_nic_byte(priv, 0xc04);
2366 2366
2367 // Check Bit 0-3, it means if RF A-D is enabled. 2367 // Check Bit 0-3, it means if RF A-D is enabled.
2368 for (i = 0; i < RF90_PATH_MAX; i++) 2368 for (i = 0; i < RF90_PATH_MAX; i++)
@@ -2418,12 +2418,12 @@ static void dm_rxpath_sel_byrssi(struct net_device * dev)
2418 2418
2419 if(!cck_Rx_Path_initialized) 2419 if(!cck_Rx_Path_initialized)
2420 { 2420 {
2421 DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf); 2421 DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(priv, 0xa07)&0xf);
2422 cck_Rx_Path_initialized = 1; 2422 cck_Rx_Path_initialized = 1;
2423 } 2423 }
2424 2424
2425 DM_RxPathSelTable.disabledRF = 0xf; 2425 DM_RxPathSelTable.disabledRF = 0xf;
2426 DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04)); 2426 DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(priv, 0xc04));
2427 2427
2428 if(priv->ieee80211->mode == WIRELESS_MODE_B) 2428 if(priv->ieee80211->mode == WIRELESS_MODE_B)
2429 { 2429 {
@@ -2700,7 +2700,6 @@ static void dm_deInit_fsync(struct net_device *dev)
2700 2700
2701void dm_fsync_timer_callback(unsigned long data) 2701void dm_fsync_timer_callback(unsigned long data)
2702{ 2702{
2703 struct net_device *dev = (struct net_device *)data;
2704 struct r8192_priv *priv = ieee80211_priv((struct net_device *)data); 2703 struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);
2705 u32 rate_index, rate_count = 0, rate_count_diff=0; 2704 u32 rate_index, rate_count = 0, rate_count_diff=0;
2706 bool bSwitchFromCountDiff = false; 2705 bool bSwitchFromCountDiff = false;
@@ -2763,20 +2762,20 @@ void dm_fsync_timer_callback(unsigned long data)
2763 if(priv->bswitch_fsync) 2762 if(priv->bswitch_fsync)
2764 { 2763 {
2765 #ifdef RTL8190P 2764 #ifdef RTL8190P
2766 write_nic_byte(dev,0xC36, 0x00); 2765 write_nic_byte(priv,0xC36, 0x00);
2767 #else 2766 #else
2768 write_nic_byte(dev,0xC36, 0x1c); 2767 write_nic_byte(priv,0xC36, 0x1c);
2769 #endif 2768 #endif
2770 write_nic_byte(dev, 0xC3e, 0x90); 2769 write_nic_byte(priv, 0xC3e, 0x90);
2771 } 2770 }
2772 else 2771 else
2773 { 2772 {
2774 #ifdef RTL8190P 2773 #ifdef RTL8190P
2775 write_nic_byte(dev, 0xC36, 0x40); 2774 write_nic_byte(priv, 0xC36, 0x40);
2776 #else 2775 #else
2777 write_nic_byte(dev, 0xC36, 0x5c); 2776 write_nic_byte(priv, 0xC36, 0x5c);
2778 #endif 2777 #endif
2779 write_nic_byte(dev, 0xC3e, 0x96); 2778 write_nic_byte(priv, 0xC3e, 0x96);
2780 } 2779 }
2781 } 2780 }
2782 else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold) 2781 else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold)
@@ -2785,11 +2784,11 @@ void dm_fsync_timer_callback(unsigned long data)
2785 { 2784 {
2786 priv->bswitch_fsync = false; 2785 priv->bswitch_fsync = false;
2787 #ifdef RTL8190P 2786 #ifdef RTL8190P
2788 write_nic_byte(dev, 0xC36, 0x40); 2787 write_nic_byte(priv, 0xC36, 0x40);
2789 #else 2788 #else
2790 write_nic_byte(dev, 0xC36, 0x5c); 2789 write_nic_byte(priv, 0xC36, 0x5c);
2791 #endif 2790 #endif
2792 write_nic_byte(dev, 0xC3e, 0x96); 2791 write_nic_byte(priv, 0xC3e, 0x96);
2793 } 2792 }
2794 } 2793 }
2795 if(bDoubleTimeInterval){ 2794 if(bDoubleTimeInterval){
@@ -2812,17 +2811,17 @@ void dm_fsync_timer_callback(unsigned long data)
2812 { 2811 {
2813 priv->bswitch_fsync = false; 2812 priv->bswitch_fsync = false;
2814 #ifdef RTL8190P 2813 #ifdef RTL8190P
2815 write_nic_byte(dev, 0xC36, 0x40); 2814 write_nic_byte(priv, 0xC36, 0x40);
2816 #else 2815 #else
2817 write_nic_byte(dev, 0xC36, 0x5c); 2816 write_nic_byte(priv, 0xC36, 0x5c);
2818 #endif 2817 #endif
2819 write_nic_byte(dev, 0xC3e, 0x96); 2818 write_nic_byte(priv, 0xC3e, 0x96);
2820 } 2819 }
2821 priv->ContiuneDiffCount = 0; 2820 priv->ContiuneDiffCount = 0;
2822 #ifdef RTL8190P 2821 #ifdef RTL8190P
2823 write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd); 2822 write_nic_dword(priv, rOFDM0_RxDetector2, 0x164052cd);
2824 #else 2823 #else
2825 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); 2824 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
2826 #endif 2825 #endif
2827 } 2826 }
2828 RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount); 2827 RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
@@ -2831,9 +2830,11 @@ void dm_fsync_timer_callback(unsigned long data)
2831 2830
2832static void dm_StartHWFsync(struct net_device *dev) 2831static void dm_StartHWFsync(struct net_device *dev)
2833{ 2832{
2833 struct r8192_priv *priv = ieee80211_priv(dev);
2834
2834 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__); 2835 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
2835 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf); 2836 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c12cf);
2836 write_nic_byte(dev, 0xc3b, 0x41); 2837 write_nic_byte(priv, 0xc3b, 0x41);
2837} 2838}
2838 2839
2839static void dm_EndSWFsync(struct net_device *dev) 2840static void dm_EndSWFsync(struct net_device *dev)
@@ -2849,17 +2850,17 @@ static void dm_EndSWFsync(struct net_device *dev)
2849 priv->bswitch_fsync = false; 2850 priv->bswitch_fsync = false;
2850 2851
2851 #ifdef RTL8190P 2852 #ifdef RTL8190P
2852 write_nic_byte(dev, 0xC36, 0x40); 2853 write_nic_byte(priv, 0xC36, 0x40);
2853 #else 2854 #else
2854 write_nic_byte(dev, 0xC36, 0x5c); 2855 write_nic_byte(priv, 0xC36, 0x5c);
2855#endif 2856#endif
2856 2857
2857 write_nic_byte(dev, 0xC3e, 0x96); 2858 write_nic_byte(priv, 0xC3e, 0x96);
2858 } 2859 }
2859 2860
2860 priv->ContiuneDiffCount = 0; 2861 priv->ContiuneDiffCount = 0;
2861#ifndef RTL8190P 2862#ifndef RTL8190P
2862 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); 2863 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
2863#endif 2864#endif
2864 2865
2865} 2866}
@@ -2900,17 +2901,18 @@ static void dm_StartSWFsync(struct net_device *dev)
2900 add_timer(&priv->fsync_timer); 2901 add_timer(&priv->fsync_timer);
2901 2902
2902#ifndef RTL8190P 2903#ifndef RTL8190P
2903 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd); 2904 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c12cd);
2904#endif 2905#endif
2905 2906
2906} 2907}
2907 2908
2908static void dm_EndHWFsync(struct net_device *dev) 2909static void dm_EndHWFsync(struct net_device *dev)
2909{ 2910{
2910 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__); 2911 struct r8192_priv *priv = ieee80211_priv(dev);
2911 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2912 write_nic_byte(dev, 0xc3b, 0x49);
2913 2912
2913 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
2914 write_nic_dword(priv, rOFDM0_RxDetector2, 0x465c52cd);
2915 write_nic_byte(priv, 0xc3b, 0x49);
2914} 2916}
2915 2917
2916void dm_check_fsync(struct net_device *dev) 2918void dm_check_fsync(struct net_device *dev)
@@ -2971,9 +2973,9 @@ void dm_check_fsync(struct net_device *dev)
2971 if(reg_c38_State != RegC38_Fsync_AP_BCM) 2973 if(reg_c38_State != RegC38_Fsync_AP_BCM)
2972 { //For broadcom AP we write different default value 2974 { //For broadcom AP we write different default value
2973 #ifdef RTL8190P 2975 #ifdef RTL8190P
2974 write_nic_byte(dev, rOFDM0_RxDetector3, 0x15); 2976 write_nic_byte(priv, rOFDM0_RxDetector3, 0x15);
2975 #else 2977 #else
2976 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95); 2978 write_nic_byte(priv, rOFDM0_RxDetector3, 0x95);
2977 #endif 2979 #endif
2978 2980
2979 reg_c38_State = RegC38_Fsync_AP_BCM; 2981 reg_c38_State = RegC38_Fsync_AP_BCM;
@@ -3006,9 +3008,9 @@ void dm_check_fsync(struct net_device *dev)
3006 if(reg_c38_State != RegC38_NonFsync_Other_AP) 3008 if(reg_c38_State != RegC38_NonFsync_Other_AP)
3007 { 3009 {
3008 #ifdef RTL8190P 3010 #ifdef RTL8190P
3009 write_nic_byte(dev, rOFDM0_RxDetector3, 0x10); 3011 write_nic_byte(priv, rOFDM0_RxDetector3, 0x10);
3010 #else 3012 #else
3011 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90); 3013 write_nic_byte(priv, rOFDM0_RxDetector3, 0x90);
3012 #endif 3014 #endif
3013 3015
3014 reg_c38_State = RegC38_NonFsync_Other_AP; 3016 reg_c38_State = RegC38_NonFsync_Other_AP;
@@ -3018,7 +3020,7 @@ void dm_check_fsync(struct net_device *dev)
3018 { 3020 {
3019 if(reg_c38_State) 3021 if(reg_c38_State)
3020 { 3022 {
3021 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); 3023 write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);
3022 reg_c38_State = RegC38_Default; 3024 reg_c38_State = RegC38_Default;
3023 } 3025 }
3024 } 3026 }
@@ -3027,7 +3029,7 @@ void dm_check_fsync(struct net_device *dev)
3027 { 3029 {
3028 if(reg_c38_State) 3030 if(reg_c38_State)
3029 { 3031 {
3030 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); 3032 write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);
3031 reg_c38_State = RegC38_Default; 3033 reg_c38_State = RegC38_Default;
3032 } 3034 }
3033 } 3035 }
@@ -3037,7 +3039,7 @@ void dm_check_fsync(struct net_device *dev)
3037 { 3039 {
3038 if(priv->reset_count != reset_cnt) 3040 if(priv->reset_count != reset_cnt)
3039 { //After silent reset, the reg_c38_State will be returned to default value 3041 { //After silent reset, the reg_c38_State will be returned to default value
3040 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); 3042 write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);
3041 reg_c38_State = RegC38_Default; 3043 reg_c38_State = RegC38_Default;
3042 reset_cnt = priv->reset_count; 3044 reset_cnt = priv->reset_count;
3043 } 3045 }
@@ -3046,7 +3048,7 @@ void dm_check_fsync(struct net_device *dev)
3046 { 3048 {
3047 if(reg_c38_State) 3049 if(reg_c38_State)
3048 { 3050 {
3049 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); 3051 write_nic_byte(priv, rOFDM0_RxDetector3, priv->framesync);
3050 reg_c38_State = RegC38_Default; 3052 reg_c38_State = RegC38_Default;
3051 } 3053 }
3052 } 3054 }
@@ -3143,9 +3145,9 @@ static void dm_check_txrateandretrycount(struct net_device * dev)
3143 struct r8192_priv *priv = ieee80211_priv(dev); 3145 struct r8192_priv *priv = ieee80211_priv(dev);
3144 struct ieee80211_device* ieee = priv->ieee80211; 3146 struct ieee80211_device* ieee = priv->ieee80211;
3145 //for initial tx rate 3147 //for initial tx rate
3146 ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg); 3148 ieee->softmac_stats.last_packet_rate = read_nic_byte(priv ,Initial_Tx_Rate_Reg);
3147 //for tx tx retry count 3149 //for tx tx retry count
3148 ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg); 3150 ieee->softmac_stats.txretrycount = read_nic_dword(priv, Tx_Retry_Count_Reg);
3149} 3151}
3150 3152
3151static void dm_send_rssi_tofw(struct net_device *dev) 3153static void dm_send_rssi_tofw(struct net_device *dev)
@@ -3156,7 +3158,7 @@ static void dm_send_rssi_tofw(struct net_device *dev)
3156 // If we test chariot, we should stop the TX command ? 3158 // If we test chariot, we should stop the TX command ?
3157 // Because 92E will always silent reset when we send tx command. We use register 3159 // Because 92E will always silent reset when we send tx command. We use register
3158 // 0x1e0(byte) to botify driver. 3160 // 0x1e0(byte) to botify driver.
3159 write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb); 3161 write_nic_byte(priv, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
3160 return; 3162 return;
3161#if 1 3163#if 1
3162 tx_cmd.Op = TXCMD_SET_RX_RSSI; 3164 tx_cmd.Op = TXCMD_SET_RX_RSSI;
diff --git a/drivers/staging/rtl8192e/r8192E_wx.c b/drivers/staging/rtl8192e/r8192E_wx.c
index 7b5ac0d2681..c6239bba10e 100644
--- a/drivers/staging/rtl8192e/r8192E_wx.c
+++ b/drivers/staging/rtl8192e/r8192E_wx.c
@@ -985,7 +985,7 @@ static int r8192_wx_set_enc_ext(struct net_device *dev,
985 else //pairwise key 985 else //pairwise key
986 { 986 {
987 if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){ 987 if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){
988 write_nic_byte(dev, 0x173, 1); //fix aes bug 988 write_nic_byte(priv, 0x173, 1); //fix aes bug
989 } 989 }
990 setKey( dev, 990 setKey( dev,
991 4,//EntryNo 991 4,//EntryNo
diff --git a/drivers/staging/rtl8192e/r8192_pm.c b/drivers/staging/rtl8192e/r8192_pm.c
index c691bc9d88b..75e16289d7f 100644
--- a/drivers/staging/rtl8192e/r8192_pm.c
+++ b/drivers/staging/rtl8192e/r8192_pm.c
@@ -43,7 +43,7 @@ int rtl8192E_suspend (struct pci_dev *pdev, pm_message_t state)
43 43
44 ieee80211_softmac_stop_protocol(priv->ieee80211); 44 ieee80211_softmac_stop_protocol(priv->ieee80211);
45 45
46 write_nic_byte(dev,MSR,(read_nic_byte(dev,MSR)&0xfc)|MSR_LINK_NONE); 46 write_nic_byte(priv, MSR,(read_nic_byte(dev,MSR)&0xfc)|MSR_LINK_NONE);
47 if(!priv->ieee80211->bSupportRemoteWakeUp) { 47 if(!priv->ieee80211->bSupportRemoteWakeUp) {
48 /* disable tx/rx. In 8185 we write 0x10 (Reset bit), 48 /* disable tx/rx. In 8185 we write 0x10 (Reset bit),
49 * but here we make reference to WMAC and wirte 0x0. 49 * but here we make reference to WMAC and wirte 0x0.
@@ -76,24 +76,24 @@ pHalData->bHwRfOffAction = 2;
76 if(!priv->ieee80211->bSupportRemoteWakeUp) { 76 if(!priv->ieee80211->bSupportRemoteWakeUp) {
77 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT); 77 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT);
78 // 2006.11.30. System reset bit 78 // 2006.11.30. System reset bit
79 ulRegRead = read_nic_dword(dev, CPU_GEN); 79 ulRegRead = read_nic_dword(priv, CPU_GEN);
80 ulRegRead|=CPU_GEN_SYSTEM_RESET; 80 ulRegRead|=CPU_GEN_SYSTEM_RESET;
81 write_nic_dword(dev, CPU_GEN, ulRegRead); 81 write_nic_dword(priv, CPU_GEN, ulRegRead);
82 } else { 82 } else {
83 //2008.06.03 for WOL 83 //2008.06.03 for WOL
84 write_nic_dword(dev, WFCRC0, 0xffffffff); 84 write_nic_dword(priv, WFCRC0, 0xffffffff);
85 write_nic_dword(dev, WFCRC1, 0xffffffff); 85 write_nic_dword(priv, WFCRC1, 0xffffffff);
86 write_nic_dword(dev, WFCRC2, 0xffffffff); 86 write_nic_dword(priv, WFCRC2, 0xffffffff);
87#ifdef RTL8190P 87#ifdef RTL8190P
88 //GPIO 0 = TRUE 88 //GPIO 0 = TRUE
89 ucRegRead = read_nic_byte(dev, GPO); 89 ucRegRead = read_nic_byte(priv, GPO);
90 ucRegRead |= BIT0; 90 ucRegRead |= BIT0;
91 write_nic_byte(dev, GPO, ucRegRead); 91 write_nic_byte(priv, GPO, ucRegRead);
92#endif 92#endif
93 //Write PMR register 93 //Write PMR register
94 write_nic_byte(dev, PMR, 0x5); 94 write_nic_byte(priv, PMR, 0x5);
95 //Disable tx, enanble rx 95 //Disable tx, enanble rx
96 write_nic_byte(dev, MacBlkCtrl, 0xa); 96 write_nic_byte(priv, MacBlkCtrl, 0xa);
97 } 97 }
98 98
99out_pci_suspend: 99out_pci_suspend:
diff --git a/drivers/staging/rtl8192e/r819xE_firmware.c b/drivers/staging/rtl8192e/r819xE_firmware.c
index e335b815ca0..d1da2697cfe 100644
--- a/drivers/staging/rtl8192e/r819xE_firmware.c
+++ b/drivers/staging/rtl8192e/r819xE_firmware.c
@@ -115,6 +115,7 @@ static bool fw_download_code(struct net_device *dev, u8 *code_virtual_address,
115 */ 115 */
116static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev) 116static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
117{ 117{
118 struct r8192_priv *priv = ieee80211_priv(dev);
118 unsigned long timeout; 119 unsigned long timeout;
119 bool rt_status = true; 120 bool rt_status = true;
120 u32 CPU_status = 0; 121 u32 CPU_status = 0;
@@ -122,7 +123,7 @@ static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
122 /* Check whether put code OK */ 123 /* Check whether put code OK */
123 timeout = jiffies + msecs_to_jiffies(20); 124 timeout = jiffies + msecs_to_jiffies(20);
124 while (time_before(jiffies, timeout)) { 125 while (time_before(jiffies, timeout)) {
125 CPU_status = read_nic_dword(dev, CPU_GEN); 126 CPU_status = read_nic_dword(priv, CPU_GEN);
126 127
127 if (CPU_status & CPU_GEN_PUT_CODE_OK) 128 if (CPU_status & CPU_GEN_PUT_CODE_OK)
128 break; 129 break;
@@ -137,15 +138,15 @@ static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
137 } 138 }
138 139
139 /* Turn On CPU */ 140 /* Turn On CPU */
140 CPU_status = read_nic_dword(dev, CPU_GEN); 141 CPU_status = read_nic_dword(priv, CPU_GEN);
141 write_nic_byte(dev, CPU_GEN, 142 write_nic_byte(priv, CPU_GEN,
142 (u8)((CPU_status | CPU_GEN_PWR_STB_CPU) & 0xff)); 143 (u8)((CPU_status | CPU_GEN_PWR_STB_CPU) & 0xff));
143 mdelay(1); 144 mdelay(1);
144 145
145 /* Check whether CPU boot OK */ 146 /* Check whether CPU boot OK */
146 timeout = jiffies + msecs_to_jiffies(20); 147 timeout = jiffies + msecs_to_jiffies(20);
147 while (time_before(jiffies, timeout)) { 148 while (time_before(jiffies, timeout)) {
148 CPU_status = read_nic_dword(dev, CPU_GEN); 149 CPU_status = read_nic_dword(priv, CPU_GEN);
149 150
150 if (CPU_status & CPU_GEN_BOOT_RDY) 151 if (CPU_status & CPU_GEN_BOOT_RDY)
151 break; 152 break;
@@ -167,6 +168,7 @@ CPUCheckMainCodeOKAndTurnOnCPU_Fail:
167 168
168static bool CPUcheck_firmware_ready(struct net_device *dev) 169static bool CPUcheck_firmware_ready(struct net_device *dev)
169{ 170{
171 struct r8192_priv *priv = ieee80211_priv(dev);
170 unsigned long timeout; 172 unsigned long timeout;
171 bool rt_status = true; 173 bool rt_status = true;
172 u32 CPU_status = 0; 174 u32 CPU_status = 0;
@@ -174,7 +176,7 @@ static bool CPUcheck_firmware_ready(struct net_device *dev)
174 /* Check Firmware Ready */ 176 /* Check Firmware Ready */
175 timeout = jiffies + msecs_to_jiffies(20); 177 timeout = jiffies + msecs_to_jiffies(20);
176 while (time_before(jiffies, timeout)) { 178 while (time_before(jiffies, timeout)) {
177 CPU_status = read_nic_dword(dev, CPU_GEN); 179 CPU_status = read_nic_dword(priv, CPU_GEN);
178 180
179 if (CPU_status & CPU_GEN_FIRM_RDY) 181 if (CPU_status & CPU_GEN_FIRM_RDY)
180 break; 182 break;
diff --git a/drivers/staging/rtl8192e/r819xE_phy.c b/drivers/staging/rtl8192e/r819xE_phy.c
index f75c907fd00..bcd1eda7795 100644
--- a/drivers/staging/rtl8192e/r819xE_phy.c
+++ b/drivers/staging/rtl8192e/r819xE_phy.c
@@ -1466,17 +1466,17 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
1466 * ****************************************************************************/ 1466 * ****************************************************************************/
1467void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) 1467void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
1468{ 1468{
1469 1469 struct r8192_priv *priv = ieee80211_priv(dev);
1470 u32 OriginalValue, BitShift, NewValue; 1470 u32 OriginalValue, BitShift, NewValue;
1471 1471
1472 if(dwBitMask!= bMaskDWord) 1472 if(dwBitMask!= bMaskDWord)
1473 {//if not "double word" write 1473 {//if not "double word" write
1474 OriginalValue = read_nic_dword(dev, dwRegAddr); 1474 OriginalValue = read_nic_dword(priv, dwRegAddr);
1475 BitShift = rtl8192_CalculateBitShift(dwBitMask); 1475 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1476 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); 1476 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
1477 write_nic_dword(dev, dwRegAddr, NewValue); 1477 write_nic_dword(priv, dwRegAddr, NewValue);
1478 }else 1478 }else
1479 write_nic_dword(dev, dwRegAddr, dwData); 1479 write_nic_dword(priv, dwRegAddr, dwData);
1480} 1480}
1481/****************************************************************************** 1481/******************************************************************************
1482 *function: This function reads specific bits from BB register 1482 *function: This function reads specific bits from BB register
@@ -1489,9 +1489,10 @@ void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32
1489 * ****************************************************************************/ 1489 * ****************************************************************************/
1490u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) 1490u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
1491{ 1491{
1492 struct r8192_priv *priv = ieee80211_priv(dev);
1492 u32 OriginalValue, BitShift; 1493 u32 OriginalValue, BitShift;
1493 1494
1494 OriginalValue = read_nic_dword(dev, dwRegAddr); 1495 OriginalValue = read_nic_dword(priv, dwRegAddr);
1495 BitShift = rtl8192_CalculateBitShift(dwBitMask); 1496 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1496 return (OriginalValue & dwBitMask) >> BitShift; 1497 return (OriginalValue & dwBitMask) >> BitShift;
1497} 1498}
@@ -1808,6 +1809,7 @@ static u32 phy_FwRFSerialRead(
1808 RF90_RADIO_PATH_E eRFPath, 1809 RF90_RADIO_PATH_E eRFPath,
1809 u32 Offset ) 1810 u32 Offset )
1810{ 1811{
1812 struct r8192_priv *priv = ieee80211_priv(dev);
1811 u32 Data = 0; 1813 u32 Data = 0;
1812 u8 time = 0; 1814 u8 time = 0;
1813 //DbgPrint("FW RF CTRL\n\r"); 1815 //DbgPrint("FW RF CTRL\n\r");
@@ -1825,7 +1827,7 @@ static u32 phy_FwRFSerialRead(
1825 // 5. Trigger Fw to operate the command. bit 31 1827 // 5. Trigger Fw to operate the command. bit 31
1826 Data |= 0x80000000; 1828 Data |= 0x80000000;
1827 // 6. We can not execute read operation if bit 31 is 1. 1829 // 6. We can not execute read operation if bit 31 is 1.
1828 while (read_nic_dword(dev, QPNR)&0x80000000) 1830 while (read_nic_dword(priv, QPNR)&0x80000000)
1829 { 1831 {
1830 // If FW can not finish RF-R/W for more than ?? times. We must reset FW. 1832 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1831 if (time++ < 100) 1833 if (time++ < 100)
@@ -1837,9 +1839,9 @@ static u32 phy_FwRFSerialRead(
1837 break; 1839 break;
1838 } 1840 }
1839 // 7. Execute read operation. 1841 // 7. Execute read operation.
1840 write_nic_dword(dev, QPNR, Data); 1842 write_nic_dword(priv, QPNR, Data);
1841 // 8. Check if firmawre send back RF content. 1843 // 8. Check if firmawre send back RF content.
1842 while (read_nic_dword(dev, QPNR)&0x80000000) 1844 while (read_nic_dword(priv, QPNR)&0x80000000)
1843 { 1845 {
1844 // If FW can not finish RF-R/W for more than ?? times. We must reset FW. 1846 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1845 if (time++ < 100) 1847 if (time++ < 100)
@@ -1850,7 +1852,7 @@ static u32 phy_FwRFSerialRead(
1850 else 1852 else
1851 return 0; 1853 return 0;
1852 } 1854 }
1853 return read_nic_dword(dev, RF_DATA); 1855 return read_nic_dword(priv, RF_DATA);
1854} 1856}
1855 1857
1856/****************************************************************************** 1858/******************************************************************************
@@ -1867,6 +1869,7 @@ phy_FwRFSerialWrite(
1867 u32 Offset, 1869 u32 Offset,
1868 u32 Data ) 1870 u32 Data )
1869{ 1871{
1872 struct r8192_priv *priv = ieee80211_priv(dev);
1870 u8 time = 0; 1873 u8 time = 0;
1871 1874
1872 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); 1875 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
@@ -1886,7 +1889,7 @@ phy_FwRFSerialWrite(
1886 Data |= 0x80000000; 1889 Data |= 0x80000000;
1887 1890
1888 // 6. Write operation. We can not write if bit 31 is 1. 1891 // 6. Write operation. We can not write if bit 31 is 1.
1889 while (read_nic_dword(dev, QPNR)&0x80000000) 1892 while (read_nic_dword(priv, QPNR)&0x80000000)
1890 { 1893 {
1891 // If FW can not finish RF-R/W for more than ?? times. We must reset FW. 1894 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1892 if (time++ < 100) 1895 if (time++ < 100)
@@ -1899,7 +1902,7 @@ phy_FwRFSerialWrite(
1899 } 1902 }
1900 // 7. No matter check bit. We always force the write. Because FW will 1903 // 7. No matter check bit. We always force the write. Because FW will
1901 // not accept the command. 1904 // not accept the command.
1902 write_nic_dword(dev, QPNR, Data); 1905 write_nic_dword(priv, QPNR, Data);
1903 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware 1906 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
1904 to finish RF write operation. */ 1907 to finish RF write operation. */
1905 /* 2008/01/17 MH We support delay in firmware side now. */ 1908 /* 2008/01/17 MH We support delay in firmware side now. */
@@ -2151,7 +2154,7 @@ static void rtl8192_InitBBRFRegDef(struct net_device* dev)
2151 * ***************************************************************************/ 2154 * ***************************************************************************/
2152RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) 2155RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
2153{ 2156{
2154 //struct r8192_priv *priv = ieee80211_priv(dev); 2157 struct r8192_priv *priv = ieee80211_priv(dev);
2155// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; 2158// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
2156 RT_STATUS ret = RT_STATUS_SUCCESS; 2159 RT_STATUS ret = RT_STATUS_SUCCESS;
2157 u32 i, CheckTimes = 4, dwRegRead = 0; 2160 u32 i, CheckTimes = 4, dwRegRead = 0;
@@ -2177,8 +2180,8 @@ RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlo
2177 2180
2178 case HW90_BLOCK_PHY0: 2181 case HW90_BLOCK_PHY0:
2179 case HW90_BLOCK_PHY1: 2182 case HW90_BLOCK_PHY1:
2180 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); 2183 write_nic_dword(priv, WriteAddr[CheckBlock], WriteData[i]);
2181 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); 2184 dwRegRead = read_nic_dword(priv, WriteAddr[CheckBlock]);
2182 break; 2185 break;
2183 2186
2184 case HW90_BLOCK_RF: 2187 case HW90_BLOCK_RF:
@@ -2230,12 +2233,12 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
2230 **************************************/ 2233 **************************************/
2231 2234
2232 /*--set BB Global Reset--*/ 2235 /*--set BB Global Reset--*/
2233 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); 2236 bRegValue = read_nic_byte(priv, BB_GLOBAL_RESET);
2234 write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); 2237 write_nic_byte(priv, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
2235 2238
2236 /*---set BB reset Active---*/ 2239 /*---set BB reset Active---*/
2237 dwRegValue = read_nic_dword(dev, CPU_GEN); 2240 dwRegValue = read_nic_dword(priv, CPU_GEN);
2238 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); 2241 write_nic_dword(priv, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
2239 2242
2240 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ 2243 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
2241 // TODO: this function should be removed on ASIC , Emily 2007.2.2 2244 // TODO: this function should be removed on ASIC , Emily 2007.2.2
@@ -2255,8 +2258,8 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
2255 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); 2258 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
2256 2259
2257 /*----Set BB reset de-Active----*/ 2260 /*----Set BB reset de-Active----*/
2258 dwRegValue = read_nic_dword(dev, CPU_GEN); 2261 dwRegValue = read_nic_dword(priv, CPU_GEN);
2259 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); 2262 write_nic_dword(priv, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
2260 2263
2261 /*----BB AGC table Initialization----*/ 2264 /*----BB AGC table Initialization----*/
2262 //==m==>Set PHY REG From Header<==m== 2265 //==m==>Set PHY REG From Header<==m==
@@ -2324,44 +2327,44 @@ void rtl8192_phy_getTxPower(struct net_device* dev)
2324 struct r8192_priv *priv = ieee80211_priv(dev); 2327 struct r8192_priv *priv = ieee80211_priv(dev);
2325#ifdef RTL8190P 2328#ifdef RTL8190P
2326 priv->MCSTxPowerLevelOriginalOffset[0] = 2329 priv->MCSTxPowerLevelOriginalOffset[0] =
2327 read_nic_dword(dev, MCS_TXAGC); 2330 read_nic_dword(priv, MCS_TXAGC);
2328 priv->MCSTxPowerLevelOriginalOffset[1] = 2331 priv->MCSTxPowerLevelOriginalOffset[1] =
2329 read_nic_dword(dev, (MCS_TXAGC+4)); 2332 read_nic_dword(priv, (MCS_TXAGC+4));
2330 priv->CCKTxPowerLevelOriginalOffset = 2333 priv->CCKTxPowerLevelOriginalOffset =
2331 read_nic_dword(dev, CCK_TXAGC); 2334 read_nic_dword(priv, CCK_TXAGC);
2332#else 2335#else
2333 #ifdef RTL8192E 2336 #ifdef RTL8192E
2334 priv->MCSTxPowerLevelOriginalOffset[0] = 2337 priv->MCSTxPowerLevelOriginalOffset[0] =
2335 read_nic_dword(dev, rTxAGC_Rate18_06); 2338 read_nic_dword(priv, rTxAGC_Rate18_06);
2336 priv->MCSTxPowerLevelOriginalOffset[1] = 2339 priv->MCSTxPowerLevelOriginalOffset[1] =
2337 read_nic_dword(dev, rTxAGC_Rate54_24); 2340 read_nic_dword(priv, rTxAGC_Rate54_24);
2338 priv->MCSTxPowerLevelOriginalOffset[2] = 2341 priv->MCSTxPowerLevelOriginalOffset[2] =
2339 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); 2342 read_nic_dword(priv, rTxAGC_Mcs03_Mcs00);
2340 priv->MCSTxPowerLevelOriginalOffset[3] = 2343 priv->MCSTxPowerLevelOriginalOffset[3] =
2341 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); 2344 read_nic_dword(priv, rTxAGC_Mcs07_Mcs04);
2342 priv->MCSTxPowerLevelOriginalOffset[4] = 2345 priv->MCSTxPowerLevelOriginalOffset[4] =
2343 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); 2346 read_nic_dword(priv, rTxAGC_Mcs11_Mcs08);
2344 priv->MCSTxPowerLevelOriginalOffset[5] = 2347 priv->MCSTxPowerLevelOriginalOffset[5] =
2345 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); 2348 read_nic_dword(priv, rTxAGC_Mcs15_Mcs12);
2346 #endif 2349 #endif
2347#endif 2350#endif
2348 2351
2349 // read rx initial gain 2352 // read rx initial gain
2350 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); 2353 priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1);
2351 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); 2354 priv->DefaultInitialGain[1] = read_nic_byte(priv, rOFDM0_XBAGCCore1);
2352 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); 2355 priv->DefaultInitialGain[2] = read_nic_byte(priv, rOFDM0_XCAGCCore1);
2353 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); 2356 priv->DefaultInitialGain[3] = read_nic_byte(priv, rOFDM0_XDAGCCore1);
2354 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", 2357 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2355 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], 2358 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
2356 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); 2359 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
2357 2360
2358 // read framesync 2361 // read framesync
2359 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); 2362 priv->framesync = read_nic_byte(priv, rOFDM0_RxDetector3);
2360 priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); 2363 priv->framesyncC34 = read_nic_dword(priv, rOFDM0_RxDetector2);
2361 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", 2364 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
2362 rOFDM0_RxDetector3, priv->framesync); 2365 rOFDM0_RxDetector3, priv->framesync);
2363 // read SIFS (save the value read fome MACPHY_REG.txt) 2366 // read SIFS (save the value read fome MACPHY_REG.txt)
2364 priv->SifsTime = read_nic_word(dev, SIFS); 2367 priv->SifsTime = read_nic_word(priv, SIFS);
2365} 2368}
2366 2369
2367/****************************************************************************** 2370/******************************************************************************
@@ -2807,13 +2810,13 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* s
2807 rtl8192_SetTxPowerLevel(dev,channel); 2810 rtl8192_SetTxPowerLevel(dev,channel);
2808 break; 2811 break;
2809 case CmdID_WritePortUlong: 2812 case CmdID_WritePortUlong:
2810 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); 2813 write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2);
2811 break; 2814 break;
2812 case CmdID_WritePortUshort: 2815 case CmdID_WritePortUshort:
2813 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); 2816 write_nic_word(priv, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2814 break; 2817 break;
2815 case CmdID_WritePortUchar: 2818 case CmdID_WritePortUchar:
2816 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); 2819 write_nic_byte(priv, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2817 break; 2820 break;
2818 case CmdID_RF_WriteReg: 2821 case CmdID_RF_WriteReg:
2819 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) 2822 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
@@ -3080,20 +3083,20 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3080 return; 3083 return;
3081 } 3084 }
3082 //<1>Set MAC register 3085 //<1>Set MAC register
3083 regBwOpMode = read_nic_byte(dev, BW_OPMODE); 3086 regBwOpMode = read_nic_byte(priv, BW_OPMODE);
3084 3087
3085 switch(priv->CurrentChannelBW) 3088 switch(priv->CurrentChannelBW)
3086 { 3089 {
3087 case HT_CHANNEL_WIDTH_20: 3090 case HT_CHANNEL_WIDTH_20:
3088 regBwOpMode |= BW_OPMODE_20MHZ; 3091 regBwOpMode |= BW_OPMODE_20MHZ;
3089 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works 3092 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3090 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 3093 write_nic_byte(priv, BW_OPMODE, regBwOpMode);
3091 break; 3094 break;
3092 3095
3093 case HT_CHANNEL_WIDTH_20_40: 3096 case HT_CHANNEL_WIDTH_20_40:
3094 regBwOpMode &= ~BW_OPMODE_20MHZ; 3097 regBwOpMode &= ~BW_OPMODE_20MHZ;
3095 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works 3098 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3096 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 3099 write_nic_byte(priv, BW_OPMODE, regBwOpMode);
3097 break; 3100 break;
3098 3101
3099 default: 3102 default:
@@ -3116,9 +3119,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3116// write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); 3119// write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3117 if(!priv->btxpower_tracking) 3120 if(!priv->btxpower_tracking)
3118 { 3121 {
3119 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); 3122 write_nic_dword(priv, rCCK0_TxFilter1, 0x1a1b0000);
3120 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); 3123 write_nic_dword(priv, rCCK0_TxFilter2, 0x090e1317);
3121 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); 3124 write_nic_dword(priv, rCCK0_DebugPort, 0x00000204);
3122 } 3125 }
3123 else 3126 else
3124 CCK_Tx_Power_Track_BW_Switch(dev); 3127 CCK_Tx_Power_Track_BW_Switch(dev);
@@ -3147,9 +3150,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3147 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); 3150 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3148 if(!priv->btxpower_tracking) 3151 if(!priv->btxpower_tracking)
3149 { 3152 {
3150 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); 3153 write_nic_dword(priv, rCCK0_TxFilter1, 0x35360000);
3151 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); 3154 write_nic_dword(priv, rCCK0_TxFilter2, 0x121c252e);
3152 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); 3155 write_nic_dword(priv, rCCK0_DebugPort, 0x00000409);
3153 } 3156 }
3154 else 3157 else
3155 CCK_Tx_Power_Track_BW_Switch(dev); 3158 CCK_Tx_Power_Track_BW_Switch(dev);
@@ -3288,12 +3291,12 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation)
3288 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); 3291 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
3289 3292
3290 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); 3293 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3291 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 3294 write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);
3292 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); 3295 write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);
3293 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); 3296 write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);
3294 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); 3297 write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);
3295 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); 3298 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3296 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); 3299 write_nic_byte(priv, 0xa0a, POWER_DETECTION_TH);
3297 break; 3300 break;
3298 case IG_Restore: 3301 case IG_Restore:
3299 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); 3302 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 20:06:12 -0400