Staging: poch: Rx control register init

Added Rx control register definition. Flush Rx FIFO on init, and set
continuous DMA mode.

Signed-off-by: Vijay Kumar <vijaykumar@bravegnu.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 10 insertions, 3 deletions

diff --git a/drivers/staging/poch/poch.c b/drivers/staging/poch/poch.c
index b54760f41a4..0a3eca14075 100644
--- a/drivers/staging/poch/poch.c
+++ b/drivers/staging/poch/poch.c
@@ -126,9 +126,11 @@
 #define FPGA_INT_TX_ACQ_DONE            (0x1 << 1)
 #define FPGA_INT_RX_ACQ_DONE            (0x1)
 
-#define FPGA_RX_ADC_CTL_REG             0x214
-#define FPGA_RX_ADC_CTL_CONT_CAP        (0x0)
-#define FPGA_RX_ADC_CTL_SNAP_CAP        (0x1)
+#define FPGA_RX_CTL_REG                 0x214
+#define FPGA_RX_CTL_FIFO_FLUSH          (0x1 << 9)
+#define FPGA_RX_CTL_SYNTH_DATA          (0x1 << 8)
+#define FPGA_RX_CTL_CONT_CAP            (0x0 << 1)
+#define FPGA_RX_CTL_SNAP_CAP            (0x1 << 1)
 
 #define FPGA_RX_ARM_REG                 0x21C
 
@@ -819,6 +821,11 @@ static int poch_open(struct inode *inode, struct file *filp)
                 iowrite32(FPGA_TX_CTL_FIFO_FLUSH
                           | FPGA_TX_CTL_OUTPUT_CARDBUS,
                           fpga + FPGA_TX_CTL_REG);
+        } else {
+                /* Flush RX FIFO and output data to cardbus. */
+                iowrite32(FPGA_RX_CTL_CONT_CAP
+                          | FPGA_RX_CTL_FIFO_FLUSH,
+                          fpga + FPGA_RX_CTL_REG);
         }
 
         atomic_inc(&channel->inited);