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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/staging/cx25821
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/staging/cx25821')
-rw-r--r--drivers/staging/cx25821/Kconfig34
-rw-r--r--drivers/staging/cx25821/Makefile13
-rw-r--r--drivers/staging/cx25821/README6
-rw-r--r--drivers/staging/cx25821/cx25821-alsa.c795
-rw-r--r--drivers/staging/cx25821/cx25821-audio-upstream.c799
-rw-r--r--drivers/staging/cx25821/cx25821-audio-upstream.h57
-rw-r--r--drivers/staging/cx25821/cx25821-audio.h59
-rw-r--r--drivers/staging/cx25821/cx25821-biffuncs.h45
-rw-r--r--drivers/staging/cx25821/cx25821-cards.c72
-rw-r--r--drivers/staging/cx25821/cx25821-core.c1518
-rw-r--r--drivers/staging/cx25821/cx25821-gpio.c97
-rw-r--r--drivers/staging/cx25821/cx25821-gpio.h2
-rw-r--r--drivers/staging/cx25821/cx25821-i2c.c425
-rw-r--r--drivers/staging/cx25821/cx25821-medusa-defines.h42
-rw-r--r--drivers/staging/cx25821/cx25821-medusa-reg.h455
-rw-r--r--drivers/staging/cx25821/cx25821-medusa-video.c872
-rw-r--r--drivers/staging/cx25821/cx25821-medusa-video.h49
-rw-r--r--drivers/staging/cx25821/cx25821-reg.h1592
-rw-r--r--drivers/staging/cx25821/cx25821-sram.h261
-rw-r--r--drivers/staging/cx25821/cx25821-video-upstream-ch2.c836
-rw-r--r--drivers/staging/cx25821/cx25821-video-upstream-ch2.h101
-rw-r--r--drivers/staging/cx25821/cx25821-video-upstream.c889
-rw-r--r--drivers/staging/cx25821/cx25821-video-upstream.h109
-rw-r--r--drivers/staging/cx25821/cx25821-video.c2008
-rw-r--r--drivers/staging/cx25821/cx25821-video.h177
-rw-r--r--drivers/staging/cx25821/cx25821.h614
26 files changed, 11927 insertions, 0 deletions
diff --git a/drivers/staging/cx25821/Kconfig b/drivers/staging/cx25821/Kconfig
new file mode 100644
index 00000000000..5f6b5421371
--- /dev/null
+++ b/drivers/staging/cx25821/Kconfig
@@ -0,0 +1,34 @@
1config VIDEO_CX25821
2 tristate "Conexant cx25821 support"
3 depends on DVB_CORE && VIDEO_DEV && PCI && I2C
4 select I2C_ALGOBIT
5 select VIDEO_BTCX
6 select VIDEO_TVEEPROM
7 depends on RC_CORE
8 select VIDEOBUF_DVB
9 select VIDEOBUF_DMA_SG
10 select VIDEO_CX25840
11 select VIDEO_CX2341X
12 ---help---
13 This is a video4linux driver for Conexant 25821 based
14 TV cards.
15
16 To compile this driver as a module, choose M here: the
17 module will be called cx25821
18
19config VIDEO_CX25821_ALSA
20 tristate "Conexant 25821 DMA audio support"
21 depends on VIDEO_CX25821 && SND && EXPERIMENTAL
22 select SND_PCM
23 ---help---
24 This is a video4linux driver for direct (DMA) audio on
25 Conexant 25821 based capture cards using ALSA.
26
27 It only works with boards with function 01 enabled.
28 To check if your board supports, use lspci -n.
29 If supported, you should see 14f1:8801 or 14f1:8811
30 PCI device.
31
32 To compile this driver as a module, choose M here: the
33 module will be called cx25821-alsa.
34
diff --git a/drivers/staging/cx25821/Makefile b/drivers/staging/cx25821/Makefile
new file mode 100644
index 00000000000..aedde18c68f
--- /dev/null
+++ b/drivers/staging/cx25821/Makefile
@@ -0,0 +1,13 @@
1cx25821-y := cx25821-core.o cx25821-cards.o cx25821-i2c.o \
2 cx25821-gpio.o cx25821-medusa-video.o \
3 cx25821-video.o cx25821-video-upstream.o \
4 cx25821-video-upstream-ch2.o \
5 cx25821-audio-upstream.o
6
7obj-$(CONFIG_VIDEO_CX25821) += cx25821.o
8obj-$(CONFIG_VIDEO_CX25821_ALSA) += cx25821-alsa.o
9
10ccflags-y := -Idrivers/media/video
11ccflags-y += -Idrivers/media/common/tuners
12ccflags-y += -Idrivers/media/dvb/dvb-core
13ccflags-y += -Idrivers/media/dvb/frontends
diff --git a/drivers/staging/cx25821/README b/drivers/staging/cx25821/README
new file mode 100644
index 00000000000..a9ba50b9888
--- /dev/null
+++ b/drivers/staging/cx25821/README
@@ -0,0 +1,6 @@
1Todo:
2 - checkpatch.pl cleanups
3 - sparse cleanups
4
5Please send patches to linux-media@vger.kernel.org
6
diff --git a/drivers/staging/cx25821/cx25821-alsa.c b/drivers/staging/cx25821/cx25821-alsa.c
new file mode 100644
index 00000000000..ebdba7c65bc
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-alsa.c
@@ -0,0 +1,795 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on SAA713x ALSA driver and CX88 driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, version 2
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24
25#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/device.h>
28#include <linux/interrupt.h>
29#include <linux/vmalloc.h>
30#include <linux/dma-mapping.h>
31#include <linux/pci.h>
32#include <linux/slab.h>
33
34#include <linux/delay.h>
35#include <sound/core.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/control.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include "cx25821.h"
43#include "cx25821-reg.h"
44
45#define AUDIO_SRAM_CHANNEL SRAM_CH08
46
47#define dprintk(level, fmt, arg...) \
48do { \
49 if (debug >= level) \
50 pr_info("%s/1: " fmt, chip->dev->name, ##arg); \
51} while (0)
52#define dprintk_core(level, fmt, arg...) \
53do { \
54 if (debug >= level) \
55 printk(KERN_DEBUG "%s/1: " fmt, chip->dev->name, ##arg); \
56} while (0)
57
58/****************************************************************************
59 Data type declarations - Can be moded to a header file later
60 ****************************************************************************/
61
62static struct snd_card *snd_cx25821_cards[SNDRV_CARDS];
63static int devno;
64
65struct cx25821_audio_buffer {
66 unsigned int bpl;
67 struct btcx_riscmem risc;
68 struct videobuf_dmabuf dma;
69};
70
71struct cx25821_audio_dev {
72 struct cx25821_dev *dev;
73 struct cx25821_dmaqueue q;
74
75 /* pci i/o */
76 struct pci_dev *pci;
77
78 /* audio controls */
79 int irq;
80
81 struct snd_card *card;
82
83 unsigned long iobase;
84 spinlock_t reg_lock;
85 atomic_t count;
86
87 unsigned int dma_size;
88 unsigned int period_size;
89 unsigned int num_periods;
90
91 struct videobuf_dmabuf *dma_risc;
92
93 struct cx25821_audio_buffer *buf;
94
95 struct snd_pcm_substream *substream;
96};
97
98
99/****************************************************************************
100 Module global static vars
101 ****************************************************************************/
102
103static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
104static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
105static int enable[SNDRV_CARDS] = { 1, [1 ... (SNDRV_CARDS - 1)] = 1 };
106
107module_param_array(enable, bool, NULL, 0444);
108MODULE_PARM_DESC(enable, "Enable cx25821 soundcard. default enabled.");
109
110module_param_array(index, int, NULL, 0444);
111MODULE_PARM_DESC(index, "Index value for cx25821 capture interface(s).");
112
113/****************************************************************************
114 Module macros
115 ****************************************************************************/
116
117MODULE_DESCRIPTION("ALSA driver module for cx25821 based capture cards");
118MODULE_AUTHOR("Hiep Huynh");
119MODULE_LICENSE("GPL");
120MODULE_SUPPORTED_DEVICE("{{Conexant,25821}"); /* "{{Conexant,23881}," */
121
122static unsigned int debug;
123module_param(debug, int, 0644);
124MODULE_PARM_DESC(debug, "enable debug messages");
125
126/****************************************************************************
127 Module specific funtions
128 ****************************************************************************/
129/* Constants taken from cx88-reg.h */
130#define AUD_INT_DN_RISCI1 (1 << 0)
131#define AUD_INT_UP_RISCI1 (1 << 1)
132#define AUD_INT_RDS_DN_RISCI1 (1 << 2)
133#define AUD_INT_DN_RISCI2 (1 << 4) /* yes, 3 is skipped */
134#define AUD_INT_UP_RISCI2 (1 << 5)
135#define AUD_INT_RDS_DN_RISCI2 (1 << 6)
136#define AUD_INT_DN_SYNC (1 << 12)
137#define AUD_INT_UP_SYNC (1 << 13)
138#define AUD_INT_RDS_DN_SYNC (1 << 14)
139#define AUD_INT_OPC_ERR (1 << 16)
140#define AUD_INT_BER_IRQ (1 << 20)
141#define AUD_INT_MCHG_IRQ (1 << 21)
142#define GP_COUNT_CONTROL_RESET 0x3
143
144#define PCI_MSK_AUD_EXT (1 << 4)
145#define PCI_MSK_AUD_INT (1 << 3)
146/*
147 * BOARD Specific: Sets audio DMA
148 */
149
150static int _cx25821_start_audio_dma(struct cx25821_audio_dev *chip)
151{
152 struct cx25821_audio_buffer *buf = chip->buf;
153 struct cx25821_dev *dev = chip->dev;
154 struct sram_channel *audio_ch =
155 &cx25821_sram_channels[AUDIO_SRAM_CHANNEL];
156 u32 tmp = 0;
157
158 /* enable output on the GPIO 0 for the MCLK ADC (Audio) */
159 cx25821_set_gpiopin_direction(chip->dev, 0, 0);
160
161 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */
162 cx_clear(AUD_INT_DMA_CTL,
163 FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN);
164
165 /* setup fifo + format - out channel */
166 cx25821_sram_channel_setup_audio(chip->dev, audio_ch, buf->bpl,
167 buf->risc.dma);
168
169 /* sets bpl size */
170 cx_write(AUD_A_LNGTH, buf->bpl);
171
172 /* reset counter */
173 /* GP_COUNT_CONTROL_RESET = 0x3 */
174 cx_write(AUD_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET);
175 atomic_set(&chip->count, 0);
176
177 /* Set the input mode to 16-bit */
178 tmp = cx_read(AUD_A_CFG);
179 cx_write(AUD_A_CFG,
180 tmp | FLD_AUD_DST_PK_MODE | FLD_AUD_DST_ENABLE |
181 FLD_AUD_CLK_ENABLE);
182
183 /*
184 pr_info("DEBUG: Start audio DMA, %d B/line, cmds_start(0x%x)= %d lines/FIFO, %d periods, %d byte buffer\n",
185 buf->bpl, audio_ch->cmds_start,
186 cx_read(audio_ch->cmds_start + 12)>>1,
187 chip->num_periods, buf->bpl * chip->num_periods);
188 */
189
190 /* Enables corresponding bits at AUD_INT_STAT */
191 cx_write(AUD_A_INT_MSK,
192 FLD_AUD_DST_RISCI1 | FLD_AUD_DST_OF | FLD_AUD_DST_SYNC |
193 FLD_AUD_DST_OPC_ERR);
194
195 /* Clean any pending interrupt bits already set */
196 cx_write(AUD_A_INT_STAT, ~0);
197
198 /* enable audio irqs */
199 cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT);
200
201 /* Turn on audio downstream fifo and risc enable 0x101 */
202 tmp = cx_read(AUD_INT_DMA_CTL);
203 cx_set(AUD_INT_DMA_CTL,
204 tmp | (FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN));
205
206 mdelay(100);
207 return 0;
208}
209
210/*
211 * BOARD Specific: Resets audio DMA
212 */
213static int _cx25821_stop_audio_dma(struct cx25821_audio_dev *chip)
214{
215 struct cx25821_dev *dev = chip->dev;
216
217 /* stop dma */
218 cx_clear(AUD_INT_DMA_CTL,
219 FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN);
220
221 /* disable irqs */
222 cx_clear(PCI_INT_MSK, PCI_MSK_AUD_INT);
223 cx_clear(AUD_A_INT_MSK,
224 AUD_INT_OPC_ERR | AUD_INT_DN_SYNC | AUD_INT_DN_RISCI2 |
225 AUD_INT_DN_RISCI1);
226
227 return 0;
228}
229
230#define MAX_IRQ_LOOP 50
231
232/*
233 * BOARD Specific: IRQ dma bits
234 */
235static char *cx25821_aud_irqs[32] = {
236 "dn_risci1", "up_risci1", "rds_dn_risc1", /* 0-2 */
237 NULL, /* reserved */
238 "dn_risci2", "up_risci2", "rds_dn_risc2", /* 4-6 */
239 NULL, /* reserved */
240 "dnf_of", "upf_uf", "rds_dnf_uf", /* 8-10 */
241 NULL, /* reserved */
242 "dn_sync", "up_sync", "rds_dn_sync", /* 12-14 */
243 NULL, /* reserved */
244 "opc_err", "par_err", "rip_err", /* 16-18 */
245 "pci_abort", "ber_irq", "mchg_irq" /* 19-21 */
246};
247
248/*
249 * BOARD Specific: Threats IRQ audio specific calls
250 */
251static void cx25821_aud_irq(struct cx25821_audio_dev *chip, u32 status,
252 u32 mask)
253{
254 struct cx25821_dev *dev = chip->dev;
255
256 if (0 == (status & mask))
257 return;
258
259 cx_write(AUD_A_INT_STAT, status);
260 if (debug > 1 || (status & mask & ~0xff))
261 cx25821_print_irqbits(dev->name, "irq aud",
262 cx25821_aud_irqs,
263 ARRAY_SIZE(cx25821_aud_irqs), status,
264 mask);
265
266 /* risc op code error */
267 if (status & AUD_INT_OPC_ERR) {
268 pr_warn("WARNING %s/1: Audio risc op code error\n", dev->name);
269
270 cx_clear(AUD_INT_DMA_CTL,
271 FLD_AUD_DST_A_RISC_EN | FLD_AUD_DST_A_FIFO_EN);
272 cx25821_sram_channel_dump_audio(dev,
273 &cx25821_sram_channels
274 [AUDIO_SRAM_CHANNEL]);
275 }
276 if (status & AUD_INT_DN_SYNC) {
277 pr_warn("WARNING %s: Downstream sync error!\n", dev->name);
278 cx_write(AUD_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET);
279 return;
280 }
281
282 /* risc1 downstream */
283 if (status & AUD_INT_DN_RISCI1) {
284 atomic_set(&chip->count, cx_read(AUD_A_GPCNT));
285 snd_pcm_period_elapsed(chip->substream);
286 }
287}
288
289/*
290 * BOARD Specific: Handles IRQ calls
291 */
292static irqreturn_t cx25821_irq(int irq, void *dev_id)
293{
294 struct cx25821_audio_dev *chip = dev_id;
295 struct cx25821_dev *dev = chip->dev;
296 u32 status, pci_status;
297 u32 audint_status, audint_mask;
298 int loop, handled = 0;
299 int audint_count = 0;
300
301 audint_status = cx_read(AUD_A_INT_STAT);
302 audint_mask = cx_read(AUD_A_INT_MSK);
303 audint_count = cx_read(AUD_A_GPCNT);
304 status = cx_read(PCI_INT_STAT);
305
306 for (loop = 0; loop < 1; loop++) {
307 status = cx_read(PCI_INT_STAT);
308 if (0 == status) {
309 status = cx_read(PCI_INT_STAT);
310 audint_status = cx_read(AUD_A_INT_STAT);
311 audint_mask = cx_read(AUD_A_INT_MSK);
312
313 if (status) {
314 handled = 1;
315 cx_write(PCI_INT_STAT, status);
316
317 cx25821_aud_irq(chip, audint_status,
318 audint_mask);
319 break;
320 } else
321 goto out;
322 }
323
324 handled = 1;
325 cx_write(PCI_INT_STAT, status);
326
327 cx25821_aud_irq(chip, audint_status, audint_mask);
328 }
329
330 pci_status = cx_read(PCI_INT_STAT);
331
332 if (handled)
333 cx_write(PCI_INT_STAT, pci_status);
334
335out:
336 return IRQ_RETVAL(handled);
337}
338
339static int dsp_buffer_free(struct cx25821_audio_dev *chip)
340{
341 BUG_ON(!chip->dma_size);
342
343 dprintk(2, "Freeing buffer\n");
344 videobuf_dma_unmap(&chip->pci->dev, chip->dma_risc);
345 videobuf_dma_free(chip->dma_risc);
346 btcx_riscmem_free(chip->pci, &chip->buf->risc);
347 kfree(chip->buf);
348
349 chip->dma_risc = NULL;
350 chip->dma_size = 0;
351
352 return 0;
353}
354
355/****************************************************************************
356 ALSA PCM Interface
357 ****************************************************************************/
358
359/*
360 * Digital hardware definition
361 */
362#define DEFAULT_FIFO_SIZE 384
363static struct snd_pcm_hardware snd_cx25821_digital_hw = {
364 .info = SNDRV_PCM_INFO_MMAP |
365 SNDRV_PCM_INFO_INTERLEAVED |
366 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID,
367 .formats = SNDRV_PCM_FMTBIT_S16_LE,
368
369 .rates = SNDRV_PCM_RATE_48000,
370 .rate_min = 48000,
371 .rate_max = 48000,
372 .channels_min = 2,
373 .channels_max = 2,
374 /* Analog audio output will be full of clicks and pops if there
375 are not exactly four lines in the SRAM FIFO buffer. */
376 .period_bytes_min = DEFAULT_FIFO_SIZE / 3,
377 .period_bytes_max = DEFAULT_FIFO_SIZE / 3,
378 .periods_min = 1,
379 .periods_max = AUDIO_LINE_SIZE,
380 /* 128 * 128 = 16384 = 1024 * 16 */
381 .buffer_bytes_max = (AUDIO_LINE_SIZE * AUDIO_LINE_SIZE),
382};
383
384/*
385 * audio pcm capture open callback
386 */
387static int snd_cx25821_pcm_open(struct snd_pcm_substream *substream)
388{
389 struct cx25821_audio_dev *chip = snd_pcm_substream_chip(substream);
390 struct snd_pcm_runtime *runtime = substream->runtime;
391 int err;
392 unsigned int bpl = 0;
393
394 if (!chip) {
395 pr_err("DEBUG: cx25821 can't find device struct. Can't proceed with open\n");
396 return -ENODEV;
397 }
398
399 err =
400 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIODS);
401 if (err < 0)
402 goto _error;
403
404 chip->substream = substream;
405
406 runtime->hw = snd_cx25821_digital_hw;
407
408 if (cx25821_sram_channels[AUDIO_SRAM_CHANNEL].fifo_size !=
409 DEFAULT_FIFO_SIZE) {
410 /* since there are 3 audio Clusters */
411 bpl = cx25821_sram_channels[AUDIO_SRAM_CHANNEL].fifo_size / 3;
412 bpl &= ~7; /* must be multiple of 8 */
413
414 if (bpl > AUDIO_LINE_SIZE)
415 bpl = AUDIO_LINE_SIZE;
416
417 runtime->hw.period_bytes_min = bpl;
418 runtime->hw.period_bytes_max = bpl;
419 }
420
421 return 0;
422_error:
423 dprintk(1, "Error opening PCM!\n");
424 return err;
425}
426
427/*
428 * audio close callback
429 */
430static int snd_cx25821_close(struct snd_pcm_substream *substream)
431{
432 return 0;
433}
434
435/*
436 * hw_params callback
437 */
438static int snd_cx25821_hw_params(struct snd_pcm_substream *substream,
439 struct snd_pcm_hw_params *hw_params)
440{
441 struct cx25821_audio_dev *chip = snd_pcm_substream_chip(substream);
442 struct videobuf_dmabuf *dma;
443
444 struct cx25821_audio_buffer *buf;
445 int ret;
446
447 if (substream->runtime->dma_area) {
448 dsp_buffer_free(chip);
449 substream->runtime->dma_area = NULL;
450 }
451
452 chip->period_size = params_period_bytes(hw_params);
453 chip->num_periods = params_periods(hw_params);
454 chip->dma_size = chip->period_size * params_periods(hw_params);
455
456 BUG_ON(!chip->dma_size);
457 BUG_ON(chip->num_periods & (chip->num_periods - 1));
458
459 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
460 if (NULL == buf)
461 return -ENOMEM;
462
463 if (chip->period_size > AUDIO_LINE_SIZE)
464 chip->period_size = AUDIO_LINE_SIZE;
465
466 buf->bpl = chip->period_size;
467
468 dma = &buf->dma;
469 videobuf_dma_init(dma);
470 ret = videobuf_dma_init_kernel(dma, PCI_DMA_FROMDEVICE,
471 (PAGE_ALIGN(chip->dma_size) >>
472 PAGE_SHIFT));
473 if (ret < 0)
474 goto error;
475
476 ret = videobuf_dma_map(&chip->pci->dev, dma);
477 if (ret < 0)
478 goto error;
479
480 ret =
481 cx25821_risc_databuffer_audio(chip->pci, &buf->risc, dma->sglist,
482 chip->period_size, chip->num_periods,
483 1);
484 if (ret < 0) {
485 pr_info("DEBUG: ERROR after cx25821_risc_databuffer_audio()\n");
486 goto error;
487 }
488
489 /* Loop back to start of program */
490 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
491 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
492 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
493
494 chip->buf = buf;
495 chip->dma_risc = dma;
496
497 substream->runtime->dma_area = chip->dma_risc->vaddr;
498 substream->runtime->dma_bytes = chip->dma_size;
499 substream->runtime->dma_addr = 0;
500
501 return 0;
502
503error:
504 kfree(buf);
505 return ret;
506}
507
508/*
509 * hw free callback
510 */
511static int snd_cx25821_hw_free(struct snd_pcm_substream *substream)
512{
513 struct cx25821_audio_dev *chip = snd_pcm_substream_chip(substream);
514
515 if (substream->runtime->dma_area) {
516 dsp_buffer_free(chip);
517 substream->runtime->dma_area = NULL;
518 }
519
520 return 0;
521}
522
523/*
524 * prepare callback
525 */
526static int snd_cx25821_prepare(struct snd_pcm_substream *substream)
527{
528 return 0;
529}
530
531/*
532 * trigger callback
533 */
534static int snd_cx25821_card_trigger(struct snd_pcm_substream *substream,
535 int cmd)
536{
537 struct cx25821_audio_dev *chip = snd_pcm_substream_chip(substream);
538 int err = 0;
539
540 /* Local interrupts are already disabled by ALSA */
541 spin_lock(&chip->reg_lock);
542
543 switch (cmd) {
544 case SNDRV_PCM_TRIGGER_START:
545 err = _cx25821_start_audio_dma(chip);
546 break;
547 case SNDRV_PCM_TRIGGER_STOP:
548 err = _cx25821_stop_audio_dma(chip);
549 break;
550 default:
551 err = -EINVAL;
552 break;
553 }
554
555 spin_unlock(&chip->reg_lock);
556
557 return err;
558}
559
560/*
561 * pointer callback
562 */
563static snd_pcm_uframes_t snd_cx25821_pointer(struct snd_pcm_substream
564 *substream)
565{
566 struct cx25821_audio_dev *chip = snd_pcm_substream_chip(substream);
567 struct snd_pcm_runtime *runtime = substream->runtime;
568 u16 count;
569
570 count = atomic_read(&chip->count);
571
572 return runtime->period_size * (count & (runtime->periods - 1));
573}
574
575/*
576 * page callback (needed for mmap)
577 */
578static struct page *snd_cx25821_page(struct snd_pcm_substream *substream,
579 unsigned long offset)
580{
581 void *pageptr = substream->runtime->dma_area + offset;
582
583 return vmalloc_to_page(pageptr);
584}
585
586/*
587 * operators
588 */
589static struct snd_pcm_ops snd_cx25821_pcm_ops = {
590 .open = snd_cx25821_pcm_open,
591 .close = snd_cx25821_close,
592 .ioctl = snd_pcm_lib_ioctl,
593 .hw_params = snd_cx25821_hw_params,
594 .hw_free = snd_cx25821_hw_free,
595 .prepare = snd_cx25821_prepare,
596 .trigger = snd_cx25821_card_trigger,
597 .pointer = snd_cx25821_pointer,
598 .page = snd_cx25821_page,
599};
600
601/*
602 * ALSA create a PCM device: Called when initializing the board.
603 * Sets up the name and hooks up the callbacks
604 */
605static int snd_cx25821_pcm(struct cx25821_audio_dev *chip, int device,
606 char *name)
607{
608 struct snd_pcm *pcm;
609 int err;
610
611 err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm);
612 if (err < 0) {
613 pr_info("ERROR: FAILED snd_pcm_new() in %s\n", __func__);
614 return err;
615 }
616 pcm->private_data = chip;
617 pcm->info_flags = 0;
618 strcpy(pcm->name, name);
619 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cx25821_pcm_ops);
620
621 return 0;
622}
623
624/****************************************************************************
625 Basic Flow for Sound Devices
626 ****************************************************************************/
627
628/*
629 * PCI ID Table - 14f1:8801 and 14f1:8811 means function 1: Audio
630 * Only boards with eeprom and byte 1 at eeprom=1 have it
631 */
632
633static DEFINE_PCI_DEVICE_TABLE(cx25821_audio_pci_tbl) = {
634 {0x14f1, 0x0920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
635 {0,}
636};
637
638MODULE_DEVICE_TABLE(pci, cx25821_audio_pci_tbl);
639
640/*
641 * Not used in the function snd_cx25821_dev_free so removing
642 * from the file.
643 */
644/*
645static int snd_cx25821_free(struct cx25821_audio_dev *chip)
646{
647 if (chip->irq >= 0)
648 free_irq(chip->irq, chip);
649
650 cx25821_dev_unregister(chip->dev);
651 pci_disable_device(chip->pci);
652
653 return 0;
654}
655*/
656
657/*
658 * Component Destructor
659 */
660static void snd_cx25821_dev_free(struct snd_card *card)
661{
662 struct cx25821_audio_dev *chip = card->private_data;
663
664 /* snd_cx25821_free(chip); */
665 snd_card_free(chip->card);
666}
667
668/*
669 * Alsa Constructor - Component probe
670 */
671static int cx25821_audio_initdev(struct cx25821_dev *dev)
672{
673 struct snd_card *card;
674 struct cx25821_audio_dev *chip;
675 int err;
676
677 if (devno >= SNDRV_CARDS) {
678 pr_info("DEBUG ERROR: devno >= SNDRV_CARDS %s\n", __func__);
679 return -ENODEV;
680 }
681
682 if (!enable[devno]) {
683 ++devno;
684 pr_info("DEBUG ERROR: !enable[devno] %s\n", __func__);
685 return -ENOENT;
686 }
687
688 err = snd_card_create(index[devno], id[devno], THIS_MODULE,
689 sizeof(struct cx25821_audio_dev), &card);
690 if (err < 0) {
691 pr_info("DEBUG ERROR: cannot create snd_card_new in %s\n",
692 __func__);
693 return err;
694 }
695
696 strcpy(card->driver, "cx25821");
697
698 /* Card "creation" */
699 card->private_free = snd_cx25821_dev_free;
700 chip = card->private_data;
701 spin_lock_init(&chip->reg_lock);
702
703 chip->dev = dev;
704 chip->card = card;
705 chip->pci = dev->pci;
706 chip->iobase = pci_resource_start(dev->pci, 0);
707
708 chip->irq = dev->pci->irq;
709
710 err = request_irq(dev->pci->irq, cx25821_irq,
711 IRQF_SHARED | IRQF_DISABLED, chip->dev->name, chip);
712
713 if (err < 0) {
714 pr_err("ERROR %s: can't get IRQ %d for ALSA\n",
715 chip->dev->name, dev->pci->irq);
716 goto error;
717 }
718
719 err = snd_cx25821_pcm(chip, 0, "cx25821 Digital");
720 if (err < 0) {
721 pr_info("DEBUG ERROR: cannot create snd_cx25821_pcm %s\n",
722 __func__);
723 goto error;
724 }
725
726 snd_card_set_dev(card, &chip->pci->dev);
727
728 strcpy(card->shortname, "cx25821");
729 sprintf(card->longname, "%s at 0x%lx irq %d", chip->dev->name,
730 chip->iobase, chip->irq);
731 strcpy(card->mixername, "CX25821");
732
733 pr_info("%s/%i: ALSA support for cx25821 boards\n",
734 card->driver, devno);
735
736 err = snd_card_register(card);
737 if (err < 0) {
738 pr_info("DEBUG ERROR: cannot register sound card %s\n",
739 __func__);
740 goto error;
741 }
742
743 snd_cx25821_cards[devno] = card;
744
745 devno++;
746 return 0;
747
748error:
749 snd_card_free(card);
750 return err;
751}
752
753/****************************************************************************
754 LINUX MODULE INIT
755 ****************************************************************************/
756static void cx25821_audio_fini(void)
757{
758 snd_card_free(snd_cx25821_cards[0]);
759}
760
761/*
762 * Module initializer
763 *
764 * Loops through present saa7134 cards, and assigns an ALSA device
765 * to each one
766 *
767 */
768static int cx25821_alsa_init(void)
769{
770 struct cx25821_dev *dev = NULL;
771 struct list_head *list;
772
773 mutex_lock(&cx25821_devlist_mutex);
774 list_for_each(list, &cx25821_devlist) {
775 dev = list_entry(list, struct cx25821_dev, devlist);
776 cx25821_audio_initdev(dev);
777 }
778 mutex_unlock(&cx25821_devlist_mutex);
779
780 if (dev == NULL)
781 pr_info("ERROR ALSA: no cx25821 cards found\n");
782
783 return 0;
784
785}
786
787late_initcall(cx25821_alsa_init);
788module_exit(cx25821_audio_fini);
789
790/* ----------------------------------------------------------- */
791/*
792 * Local variables:
793 * c-basic-offset: 8
794 * End:
795 */
diff --git a/drivers/staging/cx25821/cx25821-audio-upstream.c b/drivers/staging/cx25821/cx25821-audio-upstream.c
new file mode 100644
index 00000000000..0f9ca777bd4
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-audio-upstream.c
@@ -0,0 +1,799 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24
25#include "cx25821-video.h"
26#include "cx25821-audio-upstream.h"
27
28#include <linux/fs.h>
29#include <linux/errno.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <linux/module.h>
33#include <linux/syscalls.h>
34#include <linux/file.h>
35#include <linux/fcntl.h>
36#include <linux/delay.h>
37#include <linux/slab.h>
38#include <linux/uaccess.h>
39
40MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
41MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
42MODULE_LICENSE("GPL");
43
44static int _intr_msk = FLD_AUD_SRC_RISCI1 | FLD_AUD_SRC_OF |
45 FLD_AUD_SRC_SYNC | FLD_AUD_SRC_OPC_ERR;
46
47int cx25821_sram_channel_setup_upstream_audio(struct cx25821_dev *dev,
48 struct sram_channel *ch,
49 unsigned int bpl, u32 risc)
50{
51 unsigned int i, lines;
52 u32 cdt;
53
54 if (ch->cmds_start == 0) {
55 cx_write(ch->ptr1_reg, 0);
56 cx_write(ch->ptr2_reg, 0);
57 cx_write(ch->cnt2_reg, 0);
58 cx_write(ch->cnt1_reg, 0);
59 return 0;
60 }
61
62 bpl = (bpl + 7) & ~7; /* alignment */
63 cdt = ch->cdt;
64 lines = ch->fifo_size / bpl;
65
66 if (lines > 3)
67 lines = 3;
68
69 BUG_ON(lines < 2);
70
71 /* write CDT */
72 for (i = 0; i < lines; i++) {
73 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
74 cx_write(cdt + 16 * i + 4, 0);
75 cx_write(cdt + 16 * i + 8, 0);
76 cx_write(cdt + 16 * i + 12, 0);
77 }
78
79 /* write CMDS */
80 cx_write(ch->cmds_start + 0, risc);
81
82 cx_write(ch->cmds_start + 4, 0);
83 cx_write(ch->cmds_start + 8, cdt);
84 cx_write(ch->cmds_start + 12, AUDIO_CDT_SIZE_QW);
85 cx_write(ch->cmds_start + 16, ch->ctrl_start);
86
87 /* IQ size */
88 cx_write(ch->cmds_start + 20, AUDIO_IQ_SIZE_DW);
89
90 for (i = 24; i < 80; i += 4)
91 cx_write(ch->cmds_start + i, 0);
92
93 /* fill registers */
94 cx_write(ch->ptr1_reg, ch->fifo_start);
95 cx_write(ch->ptr2_reg, cdt);
96 cx_write(ch->cnt2_reg, AUDIO_CDT_SIZE_QW);
97 cx_write(ch->cnt1_reg, AUDIO_CLUSTER_SIZE_QW - 1);
98
99 return 0;
100}
101
102static __le32 *cx25821_risc_field_upstream_audio(struct cx25821_dev *dev,
103 __le32 *rp,
104 dma_addr_t databuf_phys_addr,
105 unsigned int bpl,
106 int fifo_enable)
107{
108 unsigned int line;
109 struct sram_channel *sram_ch =
110 dev->channels[dev->_audio_upstream_channel_select].sram_channels;
111 int offset = 0;
112
113 /* scan lines */
114 for (line = 0; line < LINES_PER_AUDIO_BUFFER; line++) {
115 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
116 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
117 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
118
119 /* Check if we need to enable the FIFO
120 * after the first 3 lines.
121 * For the upstream audio channel,
122 * the risc engine will enable the FIFO */
123 if (fifo_enable && line == 2) {
124 *(rp++) = RISC_WRITECR;
125 *(rp++) = sram_ch->dma_ctl;
126 *(rp++) = sram_ch->fld_aud_fifo_en;
127 *(rp++) = 0x00000020;
128 }
129
130 offset += AUDIO_LINE_SIZE;
131 }
132
133 return rp;
134}
135
136int cx25821_risc_buffer_upstream_audio(struct cx25821_dev *dev,
137 struct pci_dev *pci,
138 unsigned int bpl, unsigned int lines)
139{
140 __le32 *rp;
141 int fifo_enable = 0;
142 int frame = 0, i = 0;
143 int frame_size = AUDIO_DATA_BUF_SZ;
144 int databuf_offset = 0;
145 int risc_flag = RISC_CNT_INC;
146 dma_addr_t risc_phys_jump_addr;
147
148 /* Virtual address of Risc buffer program */
149 rp = dev->_risc_virt_addr;
150
151 /* sync instruction */
152 *(rp++) = cpu_to_le32(RISC_RESYNC | AUDIO_SYNC_LINE);
153
154 for (frame = 0; frame < NUM_AUDIO_FRAMES; frame++) {
155 databuf_offset = frame_size * frame;
156
157 if (frame == 0) {
158 fifo_enable = 1;
159 risc_flag = RISC_CNT_RESET;
160 } else {
161 fifo_enable = 0;
162 risc_flag = RISC_CNT_INC;
163 }
164
165 /* Calculate physical jump address */
166 if ((frame + 1) == NUM_AUDIO_FRAMES) {
167 risc_phys_jump_addr =
168 dev->_risc_phys_start_addr +
169 RISC_SYNC_INSTRUCTION_SIZE;
170 } else {
171 risc_phys_jump_addr =
172 dev->_risc_phys_start_addr +
173 RISC_SYNC_INSTRUCTION_SIZE +
174 AUDIO_RISC_DMA_BUF_SIZE * (frame + 1);
175 }
176
177 rp = cx25821_risc_field_upstream_audio(dev, rp,
178 dev->
179 _audiodata_buf_phys_addr
180 + databuf_offset, bpl,
181 fifo_enable);
182
183 if (USE_RISC_NOOP_AUDIO) {
184 for (i = 0; i < NUM_NO_OPS; i++)
185 *(rp++) = cpu_to_le32(RISC_NOOP);
186 }
187
188 /* Loop to (Nth)FrameRISC or to Start of Risc program &
189 * generate IRQ */
190 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
191 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
192 *(rp++) = cpu_to_le32(0);
193
194 /* Recalculate virtual address based on frame index */
195 rp = dev->_risc_virt_addr + RISC_SYNC_INSTRUCTION_SIZE / 4 +
196 (AUDIO_RISC_DMA_BUF_SIZE * (frame + 1) / 4);
197 }
198
199 return 0;
200}
201
202void cx25821_free_memory_audio(struct cx25821_dev *dev)
203{
204 if (dev->_risc_virt_addr) {
205 pci_free_consistent(dev->pci, dev->_audiorisc_size,
206 dev->_risc_virt_addr, dev->_risc_phys_addr);
207 dev->_risc_virt_addr = NULL;
208 }
209
210 if (dev->_audiodata_buf_virt_addr) {
211 pci_free_consistent(dev->pci, dev->_audiodata_buf_size,
212 dev->_audiodata_buf_virt_addr,
213 dev->_audiodata_buf_phys_addr);
214 dev->_audiodata_buf_virt_addr = NULL;
215 }
216}
217
218void cx25821_stop_upstream_audio(struct cx25821_dev *dev)
219{
220 struct sram_channel *sram_ch =
221 dev->channels[AUDIO_UPSTREAM_SRAM_CHANNEL_B].sram_channels;
222 u32 tmp = 0;
223
224 if (!dev->_audio_is_running) {
225 printk(KERN_DEBUG
226 pr_fmt("No audio file is currently running so return!\n"));
227 return;
228 }
229 /* Disable RISC interrupts */
230 cx_write(sram_ch->int_msk, 0);
231
232 /* Turn OFF risc and fifo enable in AUD_DMA_CNTRL */
233 tmp = cx_read(sram_ch->dma_ctl);
234 cx_write(sram_ch->dma_ctl,
235 tmp & ~(sram_ch->fld_aud_fifo_en | sram_ch->fld_aud_risc_en));
236
237 /* Clear data buffer memory */
238 if (dev->_audiodata_buf_virt_addr)
239 memset(dev->_audiodata_buf_virt_addr, 0,
240 dev->_audiodata_buf_size);
241
242 dev->_audio_is_running = 0;
243 dev->_is_first_audio_frame = 0;
244 dev->_audioframe_count = 0;
245 dev->_audiofile_status = END_OF_FILE;
246
247 kfree(dev->_irq_audio_queues);
248 dev->_irq_audio_queues = NULL;
249
250 kfree(dev->_audiofilename);
251}
252
253void cx25821_free_mem_upstream_audio(struct cx25821_dev *dev)
254{
255 if (dev->_audio_is_running)
256 cx25821_stop_upstream_audio(dev);
257
258 cx25821_free_memory_audio(dev);
259}
260
261int cx25821_get_audio_data(struct cx25821_dev *dev,
262 struct sram_channel *sram_ch)
263{
264 struct file *myfile;
265 int frame_index_temp = dev->_audioframe_index;
266 int i = 0;
267 int line_size = AUDIO_LINE_SIZE;
268 int frame_size = AUDIO_DATA_BUF_SZ;
269 int frame_offset = frame_size * frame_index_temp;
270 ssize_t vfs_read_retval = 0;
271 char mybuf[line_size];
272 loff_t file_offset = dev->_audioframe_count * frame_size;
273 loff_t pos;
274 mm_segment_t old_fs;
275
276 if (dev->_audiofile_status == END_OF_FILE)
277 return 0;
278
279 myfile = filp_open(dev->_audiofilename, O_RDONLY | O_LARGEFILE, 0);
280
281 if (IS_ERR(myfile)) {
282 const int open_errno = -PTR_ERR(myfile);
283 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
284 __func__, dev->_audiofilename, open_errno);
285 return PTR_ERR(myfile);
286 } else {
287 if (!(myfile->f_op)) {
288 pr_err("%s(): File has no file operations registered!\n",
289 __func__);
290 filp_close(myfile, NULL);
291 return -EIO;
292 }
293
294 if (!myfile->f_op->read) {
295 pr_err("%s(): File has no READ operations registered!\n",
296 __func__);
297 filp_close(myfile, NULL);
298 return -EIO;
299 }
300
301 pos = myfile->f_pos;
302 old_fs = get_fs();
303 set_fs(KERNEL_DS);
304
305 for (i = 0; i < dev->_audio_lines_count; i++) {
306 pos = file_offset;
307
308 vfs_read_retval =
309 vfs_read(myfile, mybuf, line_size, &pos);
310
311 if (vfs_read_retval > 0 && vfs_read_retval == line_size
312 && dev->_audiodata_buf_virt_addr != NULL) {
313 memcpy((void *)(dev->_audiodata_buf_virt_addr +
314 frame_offset / 4), mybuf,
315 vfs_read_retval);
316 }
317
318 file_offset += vfs_read_retval;
319 frame_offset += vfs_read_retval;
320
321 if (vfs_read_retval < line_size) {
322 pr_info("Done: exit %s() since no more bytes to read from Audio file\n",
323 __func__);
324 break;
325 }
326 }
327
328 if (i > 0)
329 dev->_audioframe_count++;
330
331 dev->_audiofile_status =
332 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
333
334 set_fs(old_fs);
335 filp_close(myfile, NULL);
336 }
337
338 return 0;
339}
340
341static void cx25821_audioups_handler(struct work_struct *work)
342{
343 struct cx25821_dev *dev =
344 container_of(work, struct cx25821_dev, _audio_work_entry);
345
346 if (!dev) {
347 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
348 __func__);
349 return;
350 }
351
352 cx25821_get_audio_data(dev,
353 dev->channels[dev->
354 _audio_upstream_channel_select].
355 sram_channels);
356}
357
358int cx25821_openfile_audio(struct cx25821_dev *dev,
359 struct sram_channel *sram_ch)
360{
361 struct file *myfile;
362 int i = 0, j = 0;
363 int line_size = AUDIO_LINE_SIZE;
364 ssize_t vfs_read_retval = 0;
365 char mybuf[line_size];
366 loff_t pos;
367 loff_t offset = (unsigned long)0;
368 mm_segment_t old_fs;
369
370 myfile = filp_open(dev->_audiofilename, O_RDONLY | O_LARGEFILE, 0);
371
372 if (IS_ERR(myfile)) {
373 const int open_errno = -PTR_ERR(myfile);
374 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
375 __func__, dev->_audiofilename, open_errno);
376 return PTR_ERR(myfile);
377 } else {
378 if (!(myfile->f_op)) {
379 pr_err("%s(): File has no file operations registered!\n",
380 __func__);
381 filp_close(myfile, NULL);
382 return -EIO;
383 }
384
385 if (!myfile->f_op->read) {
386 pr_err("%s(): File has no READ operations registered!\n",
387 __func__);
388 filp_close(myfile, NULL);
389 return -EIO;
390 }
391
392 pos = myfile->f_pos;
393 old_fs = get_fs();
394 set_fs(KERNEL_DS);
395
396 for (j = 0; j < NUM_AUDIO_FRAMES; j++) {
397 for (i = 0; i < dev->_audio_lines_count; i++) {
398 pos = offset;
399
400 vfs_read_retval =
401 vfs_read(myfile, mybuf, line_size, &pos);
402
403 if (vfs_read_retval > 0
404 && vfs_read_retval == line_size
405 && dev->_audiodata_buf_virt_addr != NULL) {
406 memcpy((void *)(dev->
407 _audiodata_buf_virt_addr
408 + offset / 4), mybuf,
409 vfs_read_retval);
410 }
411
412 offset += vfs_read_retval;
413
414 if (vfs_read_retval < line_size) {
415 pr_info("Done: exit %s() since no more bytes to read from Audio file\n",
416 __func__);
417 break;
418 }
419 }
420
421 if (i > 0)
422 dev->_audioframe_count++;
423
424 if (vfs_read_retval < line_size)
425 break;
426 }
427
428 dev->_audiofile_status =
429 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
430
431 set_fs(old_fs);
432 myfile->f_pos = 0;
433 filp_close(myfile, NULL);
434 }
435
436 return 0;
437}
438
439static int cx25821_audio_upstream_buffer_prepare(struct cx25821_dev *dev,
440 struct sram_channel *sram_ch,
441 int bpl)
442{
443 int ret = 0;
444 dma_addr_t dma_addr;
445 dma_addr_t data_dma_addr;
446
447 cx25821_free_memory_audio(dev);
448
449 dev->_risc_virt_addr =
450 pci_alloc_consistent(dev->pci, dev->audio_upstream_riscbuf_size,
451 &dma_addr);
452 dev->_risc_virt_start_addr = dev->_risc_virt_addr;
453 dev->_risc_phys_start_addr = dma_addr;
454 dev->_risc_phys_addr = dma_addr;
455 dev->_audiorisc_size = dev->audio_upstream_riscbuf_size;
456
457 if (!dev->_risc_virt_addr) {
458 printk(KERN_DEBUG
459 pr_fmt("ERROR: pci_alloc_consistent() FAILED to allocate memory for RISC program! Returning\n"));
460 return -ENOMEM;
461 }
462 /* Clear out memory at address */
463 memset(dev->_risc_virt_addr, 0, dev->_audiorisc_size);
464
465 /* For Audio Data buffer allocation */
466 dev->_audiodata_buf_virt_addr =
467 pci_alloc_consistent(dev->pci, dev->audio_upstream_databuf_size,
468 &data_dma_addr);
469 dev->_audiodata_buf_phys_addr = data_dma_addr;
470 dev->_audiodata_buf_size = dev->audio_upstream_databuf_size;
471
472 if (!dev->_audiodata_buf_virt_addr) {
473 printk(KERN_DEBUG
474 pr_fmt("ERROR: pci_alloc_consistent() FAILED to allocate memory for data buffer! Returning\n"));
475 return -ENOMEM;
476 }
477 /* Clear out memory at address */
478 memset(dev->_audiodata_buf_virt_addr, 0, dev->_audiodata_buf_size);
479
480 ret = cx25821_openfile_audio(dev, sram_ch);
481 if (ret < 0)
482 return ret;
483
484 /* Creating RISC programs */
485 ret =
486 cx25821_risc_buffer_upstream_audio(dev, dev->pci, bpl,
487 dev->_audio_lines_count);
488 if (ret < 0) {
489 printk(KERN_DEBUG
490 pr_fmt("ERROR creating audio upstream RISC programs!\n"));
491 goto error;
492 }
493
494 return 0;
495
496error:
497 return ret;
498}
499
500int cx25821_audio_upstream_irq(struct cx25821_dev *dev, int chan_num,
501 u32 status)
502{
503 int i = 0;
504 u32 int_msk_tmp;
505 struct sram_channel *channel = dev->channels[chan_num].sram_channels;
506 dma_addr_t risc_phys_jump_addr;
507 __le32 *rp;
508
509 if (status & FLD_AUD_SRC_RISCI1) {
510 /* Get interrupt_index of the program that interrupted */
511 u32 prog_cnt = cx_read(channel->gpcnt);
512
513 /* Since we've identified our IRQ, clear our bits from the
514 * interrupt mask and interrupt status registers */
515 cx_write(channel->int_msk, 0);
516 cx_write(channel->int_stat, cx_read(channel->int_stat));
517
518 spin_lock(&dev->slock);
519
520 while (prog_cnt != dev->_last_index_irq) {
521 /* Update _last_index_irq */
522 if (dev->_last_index_irq < (NUMBER_OF_PROGRAMS - 1))
523 dev->_last_index_irq++;
524 else
525 dev->_last_index_irq = 0;
526
527 dev->_audioframe_index = dev->_last_index_irq;
528
529 queue_work(dev->_irq_audio_queues,
530 &dev->_audio_work_entry);
531 }
532
533 if (dev->_is_first_audio_frame) {
534 dev->_is_first_audio_frame = 0;
535
536 if (dev->_risc_virt_start_addr != NULL) {
537 risc_phys_jump_addr =
538 dev->_risc_phys_start_addr +
539 RISC_SYNC_INSTRUCTION_SIZE +
540 AUDIO_RISC_DMA_BUF_SIZE;
541
542 rp = cx25821_risc_field_upstream_audio(dev,
543 dev->
544 _risc_virt_start_addr
545 + 1,
546 dev->
547 _audiodata_buf_phys_addr,
548 AUDIO_LINE_SIZE,
549 FIFO_DISABLE);
550
551 if (USE_RISC_NOOP_AUDIO) {
552 for (i = 0; i < NUM_NO_OPS; i++) {
553 *(rp++) =
554 cpu_to_le32(RISC_NOOP);
555 }
556 }
557 /* Jump to 2nd Audio Frame */
558 *(rp++) =
559 cpu_to_le32(RISC_JUMP | RISC_IRQ1 |
560 RISC_CNT_RESET);
561 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
562 *(rp++) = cpu_to_le32(0);
563 }
564 }
565
566 spin_unlock(&dev->slock);
567 } else {
568 if (status & FLD_AUD_SRC_OF)
569 pr_warn("%s(): Audio Received Overflow Error Interrupt!\n",
570 __func__);
571
572 if (status & FLD_AUD_SRC_SYNC)
573 pr_warn("%s(): Audio Received Sync Error Interrupt!\n",
574 __func__);
575
576 if (status & FLD_AUD_SRC_OPC_ERR)
577 pr_warn("%s(): Audio Received OpCode Error Interrupt!\n",
578 __func__);
579
580 /* Read and write back the interrupt status register to clear
581 * our bits */
582 cx_write(channel->int_stat, cx_read(channel->int_stat));
583 }
584
585 if (dev->_audiofile_status == END_OF_FILE) {
586 pr_warn("EOF Channel Audio Framecount = %d\n",
587 dev->_audioframe_count);
588 return -1;
589 }
590 /* ElSE, set the interrupt mask register, re-enable irq. */
591 int_msk_tmp = cx_read(channel->int_msk);
592 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
593
594 return 0;
595}
596
597static irqreturn_t cx25821_upstream_irq_audio(int irq, void *dev_id)
598{
599 struct cx25821_dev *dev = dev_id;
600 u32 msk_stat, audio_status;
601 int handled = 0;
602 struct sram_channel *sram_ch;
603
604 if (!dev)
605 return -1;
606
607 sram_ch = dev->channels[dev->_audio_upstream_channel_select].sram_channels;
608
609 msk_stat = cx_read(sram_ch->int_mstat);
610 audio_status = cx_read(sram_ch->int_stat);
611
612 /* Only deal with our interrupt */
613 if (audio_status) {
614 handled =
615 cx25821_audio_upstream_irq(dev,
616 dev->
617 _audio_upstream_channel_select,
618 audio_status);
619 }
620
621 if (handled < 0)
622 cx25821_stop_upstream_audio(dev);
623 else
624 handled += handled;
625
626 return IRQ_RETVAL(handled);
627}
628
629static void cx25821_wait_fifo_enable(struct cx25821_dev *dev,
630 struct sram_channel *sram_ch)
631{
632 int count = 0;
633 u32 tmp;
634
635 do {
636 /* Wait 10 microsecond before checking to see if the FIFO is
637 * turned ON. */
638 udelay(10);
639
640 tmp = cx_read(sram_ch->dma_ctl);
641
642 /* 10 millisecond timeout */
643 if (count++ > 1000) {
644 pr_err("ERROR: %s() fifo is NOT turned on. Timeout!\n",
645 __func__);
646 return;
647 }
648
649 } while (!(tmp & sram_ch->fld_aud_fifo_en));
650
651}
652
653int cx25821_start_audio_dma_upstream(struct cx25821_dev *dev,
654 struct sram_channel *sram_ch)
655{
656 u32 tmp = 0;
657 int err = 0;
658
659 /* Set the physical start address of the RISC program in the initial
660 * program counter(IPC) member of the CMDS. */
661 cx_write(sram_ch->cmds_start + 0, dev->_risc_phys_addr);
662 /* Risc IPC High 64 bits 63-32 */
663 cx_write(sram_ch->cmds_start + 4, 0);
664
665 /* reset counter */
666 cx_write(sram_ch->gpcnt_ctl, 3);
667
668 /* Set the line length (It looks like we do not need to set the
669 * line length) */
670 cx_write(sram_ch->aud_length, AUDIO_LINE_SIZE & FLD_AUD_DST_LN_LNGTH);
671
672 /* Set the input mode to 16-bit */
673 tmp = cx_read(sram_ch->aud_cfg);
674 tmp |=
675 FLD_AUD_SRC_ENABLE | FLD_AUD_DST_PK_MODE | FLD_AUD_CLK_ENABLE |
676 FLD_AUD_MASTER_MODE | FLD_AUD_CLK_SELECT_PLL_D | FLD_AUD_SONY_MODE;
677 cx_write(sram_ch->aud_cfg, tmp);
678
679 /* Read and write back the interrupt status register to clear it */
680 tmp = cx_read(sram_ch->int_stat);
681 cx_write(sram_ch->int_stat, tmp);
682
683 /* Clear our bits from the interrupt status register. */
684 cx_write(sram_ch->int_stat, _intr_msk);
685
686 /* Set the interrupt mask register, enable irq. */
687 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
688 tmp = cx_read(sram_ch->int_msk);
689 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
690
691 err =
692 request_irq(dev->pci->irq, cx25821_upstream_irq_audio,
693 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
694 if (err < 0) {
695 pr_err("%s: can't get upstream IRQ %d\n",
696 dev->name, dev->pci->irq);
697 goto fail_irq;
698 }
699
700 /* Start the DMA engine */
701 tmp = cx_read(sram_ch->dma_ctl);
702 cx_set(sram_ch->dma_ctl, tmp | sram_ch->fld_aud_risc_en);
703
704 dev->_audio_is_running = 1;
705 dev->_is_first_audio_frame = 1;
706
707 /* The fifo_en bit turns on by the first Risc program */
708 cx25821_wait_fifo_enable(dev, sram_ch);
709
710 return 0;
711
712fail_irq:
713 cx25821_dev_unregister(dev);
714 return err;
715}
716
717int cx25821_audio_upstream_init(struct cx25821_dev *dev, int channel_select)
718{
719 struct sram_channel *sram_ch;
720 int retval = 0;
721 int err = 0;
722 int str_length = 0;
723
724 if (dev->_audio_is_running) {
725 pr_warn("Audio Channel is still running so return!\n");
726 return 0;
727 }
728
729 dev->_audio_upstream_channel_select = channel_select;
730 sram_ch = dev->channels[channel_select].sram_channels;
731
732 /* Work queue */
733 INIT_WORK(&dev->_audio_work_entry, cx25821_audioups_handler);
734 dev->_irq_audio_queues =
735 create_singlethread_workqueue("cx25821_audioworkqueue");
736
737 if (!dev->_irq_audio_queues) {
738 printk(KERN_DEBUG
739 pr_fmt("ERROR: create_singlethread_workqueue() for Audio FAILED!\n"));
740 return -ENOMEM;
741 }
742
743 dev->_last_index_irq = 0;
744 dev->_audio_is_running = 0;
745 dev->_audioframe_count = 0;
746 dev->_audiofile_status = RESET_STATUS;
747 dev->_audio_lines_count = LINES_PER_AUDIO_BUFFER;
748 _line_size = AUDIO_LINE_SIZE;
749
750 if (dev->input_audiofilename) {
751 str_length = strlen(dev->input_audiofilename);
752 dev->_audiofilename = kmalloc(str_length + 1, GFP_KERNEL);
753
754 if (!dev->_audiofilename)
755 goto error;
756
757 memcpy(dev->_audiofilename, dev->input_audiofilename,
758 str_length + 1);
759
760 /* Default if filename is empty string */
761 if (strcmp(dev->input_audiofilename, "") == 0)
762 dev->_audiofilename = "/root/audioGOOD.wav";
763 } else {
764 str_length = strlen(_defaultAudioName);
765 dev->_audiofilename = kmalloc(str_length + 1, GFP_KERNEL);
766
767 if (!dev->_audiofilename)
768 goto error;
769
770 memcpy(dev->_audiofilename, _defaultAudioName, str_length + 1);
771 }
772
773 retval =
774 cx25821_sram_channel_setup_upstream_audio(dev, sram_ch, _line_size,
775 0);
776
777 dev->audio_upstream_riscbuf_size =
778 AUDIO_RISC_DMA_BUF_SIZE * NUM_AUDIO_PROGS +
779 RISC_SYNC_INSTRUCTION_SIZE;
780 dev->audio_upstream_databuf_size = AUDIO_DATA_BUF_SZ * NUM_AUDIO_PROGS;
781
782 /* Allocating buffers and prepare RISC program */
783 retval =
784 cx25821_audio_upstream_buffer_prepare(dev, sram_ch, _line_size);
785 if (retval < 0) {
786 pr_err("%s: Failed to set up Audio upstream buffers!\n",
787 dev->name);
788 goto error;
789 }
790 /* Start RISC engine */
791 cx25821_start_audio_dma_upstream(dev, sram_ch);
792
793 return 0;
794
795error:
796 cx25821_dev_unregister(dev);
797
798 return err;
799}
diff --git a/drivers/staging/cx25821/cx25821-audio-upstream.h b/drivers/staging/cx25821/cx25821-audio-upstream.h
new file mode 100644
index 00000000000..668a4f11e80
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-audio-upstream.h
@@ -0,0 +1,57 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/mutex.h>
24#include <linux/workqueue.h>
25
26#define NUM_AUDIO_PROGS 8
27#define NUM_AUDIO_FRAMES 8
28#define END_OF_FILE 0
29#define IN_PROGRESS 1
30#define RESET_STATUS -1
31#define FIFO_DISABLE 0
32#define FIFO_ENABLE 1
33#define NUM_NO_OPS 4
34
35#define RISC_READ_INSTRUCTION_SIZE 12
36#define RISC_JUMP_INSTRUCTION_SIZE 12
37#define RISC_WRITECR_INSTRUCTION_SIZE 16
38#define RISC_SYNC_INSTRUCTION_SIZE 4
39#define DWORD_SIZE 4
40#define AUDIO_SYNC_LINE 4
41
42#define LINES_PER_AUDIO_BUFFER 15
43#define AUDIO_LINE_SIZE 128
44#define AUDIO_DATA_BUF_SZ (AUDIO_LINE_SIZE * LINES_PER_AUDIO_BUFFER)
45
46#define USE_RISC_NOOP_AUDIO 1
47
48#ifdef USE_RISC_NOOP_AUDIO
49#define AUDIO_RISC_DMA_BUF_SIZE (LINES_PER_AUDIO_BUFFER*RISC_READ_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE + RISC_JUMP_INSTRUCTION_SIZE)
50#endif
51
52#ifndef USE_RISC_NOOP_AUDIO
53#define AUDIO_RISC_DMA_BUF_SIZE (LINES_PER_AUDIO_BUFFER*RISC_READ_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + RISC_JUMP_INSTRUCTION_SIZE)
54#endif
55
56static int _line_size;
57char *_defaultAudioName = "/root/audioGOOD.wav";
diff --git a/drivers/staging/cx25821/cx25821-audio.h b/drivers/staging/cx25821/cx25821-audio.h
new file mode 100644
index 00000000000..27717253227
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-audio.h
@@ -0,0 +1,59 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __CX25821_AUDIO_H__
24#define __CX25821_AUDIO_H__
25
26#define USE_RISC_NOOP 1
27#define LINES_PER_BUFFER 15
28#define AUDIO_LINE_SIZE 128
29
30/* Number of buffer programs to use at once. */
31#define NUMBER_OF_PROGRAMS 8
32
33/*
34 * Max size of the RISC program for a buffer. - worst case is 2 writes per line
35 * Space is also added for the 4 no-op instructions added on the end.
36 */
37#ifndef USE_RISC_NOOP
38#define MAX_BUFFER_PROGRAM_SIZE \
39 (2*LINES_PER_BUFFER*RISC_WRITE_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE*4)
40#endif
41
42/* MAE 12 July 2005 Try to use NOOP RISC instruction instead */
43#ifdef USE_RISC_NOOP
44#define MAX_BUFFER_PROGRAM_SIZE \
45 (2*LINES_PER_BUFFER*RISC_WRITE_INSTRUCTION_SIZE + RISC_NOOP_INSTRUCTION_SIZE*4)
46#endif
47
48/* Sizes of various instructions in bytes. Used when adding instructions. */
49#define RISC_WRITE_INSTRUCTION_SIZE 12
50#define RISC_JUMP_INSTRUCTION_SIZE 12
51#define RISC_SKIP_INSTRUCTION_SIZE 4
52#define RISC_SYNC_INSTRUCTION_SIZE 4
53#define RISC_WRITECR_INSTRUCTION_SIZE 16
54#define RISC_NOOP_INSTRUCTION_SIZE 4
55
56#define MAX_AUDIO_DMA_BUFFER_SIZE \
57(MAX_BUFFER_PROGRAM_SIZE * NUMBER_OF_PROGRAMS + RISC_SYNC_INSTRUCTION_SIZE)
58
59#endif
diff --git a/drivers/staging/cx25821/cx25821-biffuncs.h b/drivers/staging/cx25821/cx25821-biffuncs.h
new file mode 100644
index 00000000000..9326a7c729e
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-biffuncs.h
@@ -0,0 +1,45 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _BITFUNCS_H
24#define _BITFUNCS_H
25
26#define SetBit(Bit) (1 << Bit)
27
28inline u8 getBit(u32 sample, u8 index)
29{
30 return (u8) ((sample >> index) & 1);
31}
32
33inline u32 clearBitAtPos(u32 value, u8 bit)
34{
35 return value & ~(1 << bit);
36}
37
38inline u32 setBitAtPos(u32 sample, u8 bit)
39{
40 sample |= (1 << bit);
41 return sample;
42
43}
44
45#endif
diff --git a/drivers/staging/cx25821/cx25821-cards.c b/drivers/staging/cx25821/cx25821-cards.c
new file mode 100644
index 00000000000..94e8d685c88
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-cards.c
@@ -0,0 +1,72 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 *
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/init.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <media/cx25840.h>
31
32#include "cx25821.h"
33#include "tuner-xc2028.h"
34
35/* board config info */
36
37struct cx25821_board cx25821_boards[] = {
38 [UNKNOWN_BOARD] = {
39 .name = "UNKNOWN/GENERIC",
40 /* Ensure safe default for unknown boards */
41 .clk_freq = 0,
42 },
43
44 [CX25821_BOARD] = {
45 .name = "CX25821",
46 .portb = CX25821_RAW,
47 .portc = CX25821_264,
48 .input[0].type = CX25821_VMUX_COMPOSITE,
49 },
50
51};
52
53const unsigned int cx25821_bcount = ARRAY_SIZE(cx25821_boards);
54
55struct cx25821_subid cx25821_subids[] = {
56 {
57 .subvendor = 0x14f1,
58 .subdevice = 0x0920,
59 .card = CX25821_BOARD,
60 },
61};
62
63void cx25821_card_setup(struct cx25821_dev *dev)
64{
65 static u8 eeprom[256];
66
67 if (dev->i2c_bus[0].i2c_rc == 0) {
68 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
69 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom,
70 sizeof(eeprom));
71 }
72}
diff --git a/drivers/staging/cx25821/cx25821-core.c b/drivers/staging/cx25821/cx25821-core.c
new file mode 100644
index 00000000000..523ac5e16c1
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-core.c
@@ -0,0 +1,1518 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 *
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/i2c.h>
27#include <linux/slab.h>
28#include "cx25821.h"
29#include "cx25821-sram.h"
30#include "cx25821-video.h"
31
32MODULE_DESCRIPTION("Driver for Athena cards");
33MODULE_AUTHOR("Shu Lin - Hiep Huynh");
34MODULE_LICENSE("GPL");
35
36static unsigned int debug;
37module_param(debug, int, 0644);
38MODULE_PARM_DESC(debug, "enable debug messages");
39
40static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
41module_param_array(card, int, NULL, 0444);
42MODULE_PARM_DESC(card, "card type");
43
44static unsigned int cx25821_devcount;
45
46DEFINE_MUTEX(cx25821_devlist_mutex);
47EXPORT_SYMBOL(cx25821_devlist_mutex);
48LIST_HEAD(cx25821_devlist);
49EXPORT_SYMBOL(cx25821_devlist);
50
51struct sram_channel cx25821_sram_channels[] = {
52 [SRAM_CH00] = {
53 .i = SRAM_CH00,
54 .name = "VID A",
55 .cmds_start = VID_A_DOWN_CMDS,
56 .ctrl_start = VID_A_IQ,
57 .cdt = VID_A_CDT,
58 .fifo_start = VID_A_DOWN_CLUSTER_1,
59 .fifo_size = (VID_CLUSTER_SIZE << 2),
60 .ptr1_reg = DMA1_PTR1,
61 .ptr2_reg = DMA1_PTR2,
62 .cnt1_reg = DMA1_CNT1,
63 .cnt2_reg = DMA1_CNT2,
64 .int_msk = VID_A_INT_MSK,
65 .int_stat = VID_A_INT_STAT,
66 .int_mstat = VID_A_INT_MSTAT,
67 .dma_ctl = VID_DST_A_DMA_CTL,
68 .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
69 .gpcnt = VID_DST_A_GPCNT,
70 .vip_ctl = VID_DST_A_VIP_CTL,
71 .pix_frmt = VID_DST_A_PIX_FRMT,
72 },
73
74 [SRAM_CH01] = {
75 .i = SRAM_CH01,
76 .name = "VID B",
77 .cmds_start = VID_B_DOWN_CMDS,
78 .ctrl_start = VID_B_IQ,
79 .cdt = VID_B_CDT,
80 .fifo_start = VID_B_DOWN_CLUSTER_1,
81 .fifo_size = (VID_CLUSTER_SIZE << 2),
82 .ptr1_reg = DMA2_PTR1,
83 .ptr2_reg = DMA2_PTR2,
84 .cnt1_reg = DMA2_CNT1,
85 .cnt2_reg = DMA2_CNT2,
86 .int_msk = VID_B_INT_MSK,
87 .int_stat = VID_B_INT_STAT,
88 .int_mstat = VID_B_INT_MSTAT,
89 .dma_ctl = VID_DST_B_DMA_CTL,
90 .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
91 .gpcnt = VID_DST_B_GPCNT,
92 .vip_ctl = VID_DST_B_VIP_CTL,
93 .pix_frmt = VID_DST_B_PIX_FRMT,
94 },
95
96 [SRAM_CH02] = {
97 .i = SRAM_CH02,
98 .name = "VID C",
99 .cmds_start = VID_C_DOWN_CMDS,
100 .ctrl_start = VID_C_IQ,
101 .cdt = VID_C_CDT,
102 .fifo_start = VID_C_DOWN_CLUSTER_1,
103 .fifo_size = (VID_CLUSTER_SIZE << 2),
104 .ptr1_reg = DMA3_PTR1,
105 .ptr2_reg = DMA3_PTR2,
106 .cnt1_reg = DMA3_CNT1,
107 .cnt2_reg = DMA3_CNT2,
108 .int_msk = VID_C_INT_MSK,
109 .int_stat = VID_C_INT_STAT,
110 .int_mstat = VID_C_INT_MSTAT,
111 .dma_ctl = VID_DST_C_DMA_CTL,
112 .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
113 .gpcnt = VID_DST_C_GPCNT,
114 .vip_ctl = VID_DST_C_VIP_CTL,
115 .pix_frmt = VID_DST_C_PIX_FRMT,
116 },
117
118 [SRAM_CH03] = {
119 .i = SRAM_CH03,
120 .name = "VID D",
121 .cmds_start = VID_D_DOWN_CMDS,
122 .ctrl_start = VID_D_IQ,
123 .cdt = VID_D_CDT,
124 .fifo_start = VID_D_DOWN_CLUSTER_1,
125 .fifo_size = (VID_CLUSTER_SIZE << 2),
126 .ptr1_reg = DMA4_PTR1,
127 .ptr2_reg = DMA4_PTR2,
128 .cnt1_reg = DMA4_CNT1,
129 .cnt2_reg = DMA4_CNT2,
130 .int_msk = VID_D_INT_MSK,
131 .int_stat = VID_D_INT_STAT,
132 .int_mstat = VID_D_INT_MSTAT,
133 .dma_ctl = VID_DST_D_DMA_CTL,
134 .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
135 .gpcnt = VID_DST_D_GPCNT,
136 .vip_ctl = VID_DST_D_VIP_CTL,
137 .pix_frmt = VID_DST_D_PIX_FRMT,
138 },
139
140 [SRAM_CH04] = {
141 .i = SRAM_CH04,
142 .name = "VID E",
143 .cmds_start = VID_E_DOWN_CMDS,
144 .ctrl_start = VID_E_IQ,
145 .cdt = VID_E_CDT,
146 .fifo_start = VID_E_DOWN_CLUSTER_1,
147 .fifo_size = (VID_CLUSTER_SIZE << 2),
148 .ptr1_reg = DMA5_PTR1,
149 .ptr2_reg = DMA5_PTR2,
150 .cnt1_reg = DMA5_CNT1,
151 .cnt2_reg = DMA5_CNT2,
152 .int_msk = VID_E_INT_MSK,
153 .int_stat = VID_E_INT_STAT,
154 .int_mstat = VID_E_INT_MSTAT,
155 .dma_ctl = VID_DST_E_DMA_CTL,
156 .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
157 .gpcnt = VID_DST_E_GPCNT,
158 .vip_ctl = VID_DST_E_VIP_CTL,
159 .pix_frmt = VID_DST_E_PIX_FRMT,
160 },
161
162 [SRAM_CH05] = {
163 .i = SRAM_CH05,
164 .name = "VID F",
165 .cmds_start = VID_F_DOWN_CMDS,
166 .ctrl_start = VID_F_IQ,
167 .cdt = VID_F_CDT,
168 .fifo_start = VID_F_DOWN_CLUSTER_1,
169 .fifo_size = (VID_CLUSTER_SIZE << 2),
170 .ptr1_reg = DMA6_PTR1,
171 .ptr2_reg = DMA6_PTR2,
172 .cnt1_reg = DMA6_CNT1,
173 .cnt2_reg = DMA6_CNT2,
174 .int_msk = VID_F_INT_MSK,
175 .int_stat = VID_F_INT_STAT,
176 .int_mstat = VID_F_INT_MSTAT,
177 .dma_ctl = VID_DST_F_DMA_CTL,
178 .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
179 .gpcnt = VID_DST_F_GPCNT,
180 .vip_ctl = VID_DST_F_VIP_CTL,
181 .pix_frmt = VID_DST_F_PIX_FRMT,
182 },
183
184 [SRAM_CH06] = {
185 .i = SRAM_CH06,
186 .name = "VID G",
187 .cmds_start = VID_G_DOWN_CMDS,
188 .ctrl_start = VID_G_IQ,
189 .cdt = VID_G_CDT,
190 .fifo_start = VID_G_DOWN_CLUSTER_1,
191 .fifo_size = (VID_CLUSTER_SIZE << 2),
192 .ptr1_reg = DMA7_PTR1,
193 .ptr2_reg = DMA7_PTR2,
194 .cnt1_reg = DMA7_CNT1,
195 .cnt2_reg = DMA7_CNT2,
196 .int_msk = VID_G_INT_MSK,
197 .int_stat = VID_G_INT_STAT,
198 .int_mstat = VID_G_INT_MSTAT,
199 .dma_ctl = VID_DST_G_DMA_CTL,
200 .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
201 .gpcnt = VID_DST_G_GPCNT,
202 .vip_ctl = VID_DST_G_VIP_CTL,
203 .pix_frmt = VID_DST_G_PIX_FRMT,
204 },
205
206 [SRAM_CH07] = {
207 .i = SRAM_CH07,
208 .name = "VID H",
209 .cmds_start = VID_H_DOWN_CMDS,
210 .ctrl_start = VID_H_IQ,
211 .cdt = VID_H_CDT,
212 .fifo_start = VID_H_DOWN_CLUSTER_1,
213 .fifo_size = (VID_CLUSTER_SIZE << 2),
214 .ptr1_reg = DMA8_PTR1,
215 .ptr2_reg = DMA8_PTR2,
216 .cnt1_reg = DMA8_CNT1,
217 .cnt2_reg = DMA8_CNT2,
218 .int_msk = VID_H_INT_MSK,
219 .int_stat = VID_H_INT_STAT,
220 .int_mstat = VID_H_INT_MSTAT,
221 .dma_ctl = VID_DST_H_DMA_CTL,
222 .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
223 .gpcnt = VID_DST_H_GPCNT,
224 .vip_ctl = VID_DST_H_VIP_CTL,
225 .pix_frmt = VID_DST_H_PIX_FRMT,
226 },
227
228 [SRAM_CH08] = {
229 .name = "audio from",
230 .cmds_start = AUD_A_DOWN_CMDS,
231 .ctrl_start = AUD_A_IQ,
232 .cdt = AUD_A_CDT,
233 .fifo_start = AUD_A_DOWN_CLUSTER_1,
234 .fifo_size = AUDIO_CLUSTER_SIZE * 3,
235 .ptr1_reg = DMA17_PTR1,
236 .ptr2_reg = DMA17_PTR2,
237 .cnt1_reg = DMA17_CNT1,
238 .cnt2_reg = DMA17_CNT2,
239 },
240
241 [SRAM_CH09] = {
242 .i = SRAM_CH09,
243 .name = "VID Upstream I",
244 .cmds_start = VID_I_UP_CMDS,
245 .ctrl_start = VID_I_IQ,
246 .cdt = VID_I_CDT,
247 .fifo_start = VID_I_UP_CLUSTER_1,
248 .fifo_size = (VID_CLUSTER_SIZE << 2),
249 .ptr1_reg = DMA15_PTR1,
250 .ptr2_reg = DMA15_PTR2,
251 .cnt1_reg = DMA15_CNT1,
252 .cnt2_reg = DMA15_CNT2,
253 .int_msk = VID_I_INT_MSK,
254 .int_stat = VID_I_INT_STAT,
255 .int_mstat = VID_I_INT_MSTAT,
256 .dma_ctl = VID_SRC_I_DMA_CTL,
257 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
258 .gpcnt = VID_SRC_I_GPCNT,
259
260 .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
261 .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
262 .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
263 .vid_cdt_size = VID_SRC_I_CDT_SZ,
264 .irq_bit = 8,
265 },
266
267 [SRAM_CH10] = {
268 .i = SRAM_CH10,
269 .name = "VID Upstream J",
270 .cmds_start = VID_J_UP_CMDS,
271 .ctrl_start = VID_J_IQ,
272 .cdt = VID_J_CDT,
273 .fifo_start = VID_J_UP_CLUSTER_1,
274 .fifo_size = (VID_CLUSTER_SIZE << 2),
275 .ptr1_reg = DMA16_PTR1,
276 .ptr2_reg = DMA16_PTR2,
277 .cnt1_reg = DMA16_CNT1,
278 .cnt2_reg = DMA16_CNT2,
279 .int_msk = VID_J_INT_MSK,
280 .int_stat = VID_J_INT_STAT,
281 .int_mstat = VID_J_INT_MSTAT,
282 .dma_ctl = VID_SRC_J_DMA_CTL,
283 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
284 .gpcnt = VID_SRC_J_GPCNT,
285
286 .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
287 .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
288 .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
289 .vid_cdt_size = VID_SRC_J_CDT_SZ,
290 .irq_bit = 9,
291 },
292
293 [SRAM_CH11] = {
294 .i = SRAM_CH11,
295 .name = "Audio Upstream Channel B",
296 .cmds_start = AUD_B_UP_CMDS,
297 .ctrl_start = AUD_B_IQ,
298 .cdt = AUD_B_CDT,
299 .fifo_start = AUD_B_UP_CLUSTER_1,
300 .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
301 .ptr1_reg = DMA22_PTR1,
302 .ptr2_reg = DMA22_PTR2,
303 .cnt1_reg = DMA22_CNT1,
304 .cnt2_reg = DMA22_CNT2,
305 .int_msk = AUD_B_INT_MSK,
306 .int_stat = AUD_B_INT_STAT,
307 .int_mstat = AUD_B_INT_MSTAT,
308 .dma_ctl = AUD_INT_DMA_CTL,
309 .gpcnt_ctl = AUD_B_GPCNT_CTL,
310 .gpcnt = AUD_B_GPCNT,
311 .aud_length = AUD_B_LNGTH,
312 .aud_cfg = AUD_B_CFG,
313 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
314 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
315 .irq_bit = 11,
316 },
317};
318EXPORT_SYMBOL(cx25821_sram_channels);
319
320struct sram_channel *channel0 = &cx25821_sram_channels[SRAM_CH00];
321struct sram_channel *channel1 = &cx25821_sram_channels[SRAM_CH01];
322struct sram_channel *channel2 = &cx25821_sram_channels[SRAM_CH02];
323struct sram_channel *channel3 = &cx25821_sram_channels[SRAM_CH03];
324struct sram_channel *channel4 = &cx25821_sram_channels[SRAM_CH04];
325struct sram_channel *channel5 = &cx25821_sram_channels[SRAM_CH05];
326struct sram_channel *channel6 = &cx25821_sram_channels[SRAM_CH06];
327struct sram_channel *channel7 = &cx25821_sram_channels[SRAM_CH07];
328struct sram_channel *channel9 = &cx25821_sram_channels[SRAM_CH09];
329struct sram_channel *channel10 = &cx25821_sram_channels[SRAM_CH10];
330struct sram_channel *channel11 = &cx25821_sram_channels[SRAM_CH11];
331
332struct cx25821_dmaqueue mpegq;
333
334static int cx25821_risc_decode(u32 risc)
335{
336 static const char * const instr[16] = {
337 [RISC_SYNC >> 28] = "sync",
338 [RISC_WRITE >> 28] = "write",
339 [RISC_WRITEC >> 28] = "writec",
340 [RISC_READ >> 28] = "read",
341 [RISC_READC >> 28] = "readc",
342 [RISC_JUMP >> 28] = "jump",
343 [RISC_SKIP >> 28] = "skip",
344 [RISC_WRITERM >> 28] = "writerm",
345 [RISC_WRITECM >> 28] = "writecm",
346 [RISC_WRITECR >> 28] = "writecr",
347 };
348 static const int incr[16] = {
349 [RISC_WRITE >> 28] = 3,
350 [RISC_JUMP >> 28] = 3,
351 [RISC_SKIP >> 28] = 1,
352 [RISC_SYNC >> 28] = 1,
353 [RISC_WRITERM >> 28] = 3,
354 [RISC_WRITECM >> 28] = 3,
355 [RISC_WRITECR >> 28] = 4,
356 };
357 static const char * const bits[] = {
358 "12", "13", "14", "resync",
359 "cnt0", "cnt1", "18", "19",
360 "20", "21", "22", "23",
361 "irq1", "irq2", "eol", "sol",
362 };
363 int i;
364
365 pr_cont("0x%08x [ %s",
366 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
367 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
368 if (risc & (1 << (i + 12)))
369 pr_cont(" %s", bits[i]);
370 }
371 pr_cont(" count=%d ]\n", risc & 0xfff);
372 return incr[risc >> 28] ? incr[risc >> 28] : 1;
373}
374
375static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
376{
377 struct cx25821_i2c *bus = i2c_adap->algo_data;
378 struct cx25821_dev *dev = bus->dev;
379 return cx_read(bus->reg_stat) & 0x01;
380}
381
382void cx_i2c_read_print(struct cx25821_dev *dev, u32 reg, const char *reg_string)
383{
384 int tmp = 0;
385 u32 value = 0;
386
387 value = cx25821_i2c_read(&dev->i2c_bus[0], reg, &tmp);
388}
389
390static void cx25821_registers_init(struct cx25821_dev *dev)
391{
392 u32 tmp;
393
394 /* enable RUN_RISC in Pecos */
395 cx_write(DEV_CNTRL2, 0x20);
396
397 /* Set the master PCI interrupt masks to enable video, audio, MBIF,
398 * and GPIO interrupts
399 * I2C interrupt masking is handled by the I2C objects themselves. */
400 cx_write(PCI_INT_MSK, 0x2001FFFF);
401
402 tmp = cx_read(RDR_TLCTL0);
403 tmp &= ~FLD_CFG_RCB_CK_EN; /* Clear the RCB_CK_EN bit */
404 cx_write(RDR_TLCTL0, tmp);
405
406 /* PLL-A setting for the Audio Master Clock */
407 cx_write(PLL_A_INT_FRAC, 0x9807A58B);
408
409 /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
410 cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
411
412 /* clear reset bit [31] */
413 tmp = cx_read(PLL_A_INT_FRAC);
414 cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
415
416 /* PLL-B setting for Mobilygen Host Bus Interface */
417 cx_write(PLL_B_INT_FRAC, 0x9883A86F);
418
419 /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
420 cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
421
422 /* clear reset bit [31] */
423 tmp = cx_read(PLL_B_INT_FRAC);
424 cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
425
426 /* PLL-C setting for video upstream channel */
427 cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
428
429 /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
430 cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
431
432 /* clear reset bit [31] */
433 tmp = cx_read(PLL_C_INT_FRAC);
434 cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
435
436 /* PLL-D setting for audio upstream channel */
437 cx_write(PLL_D_INT_FRAC, 0x98757F5B);
438
439 /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
440 cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
441
442 /* clear reset bit [31] */
443 tmp = cx_read(PLL_D_INT_FRAC);
444 cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
445
446 /* This selects the PLL C clock source for the video upstream channel
447 * I and J */
448 tmp = cx_read(VID_CH_CLK_SEL);
449 cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
450
451 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
452 * channel A-C
453 * select 656/VIP DST for downstream Channel A - C */
454 tmp = cx_read(VID_CH_MODE_SEL);
455 /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
456 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
457
458 /* enables 656 port I and J as output */
459 tmp = cx_read(CLK_RST);
460 /* use external ALT_PLL_REF pin as its reference clock instead */
461 tmp |= FLD_USE_ALT_PLL_REF;
462 cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
463
464 mdelay(100);
465}
466
467int cx25821_sram_channel_setup(struct cx25821_dev *dev,
468 struct sram_channel *ch,
469 unsigned int bpl, u32 risc)
470{
471 unsigned int i, lines;
472 u32 cdt;
473
474 if (ch->cmds_start == 0) {
475 cx_write(ch->ptr1_reg, 0);
476 cx_write(ch->ptr2_reg, 0);
477 cx_write(ch->cnt2_reg, 0);
478 cx_write(ch->cnt1_reg, 0);
479 return 0;
480 }
481
482 bpl = (bpl + 7) & ~7; /* alignment */
483 cdt = ch->cdt;
484 lines = ch->fifo_size / bpl;
485
486 if (lines > 4)
487 lines = 4;
488
489 BUG_ON(lines < 2);
490
491 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
492 cx_write(8 + 4, 8);
493 cx_write(8 + 8, 0);
494
495 /* write CDT */
496 for (i = 0; i < lines; i++) {
497 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
498 cx_write(cdt + 16 * i + 4, 0);
499 cx_write(cdt + 16 * i + 8, 0);
500 cx_write(cdt + 16 * i + 12, 0);
501 }
502
503 /* init the first cdt buffer */
504 for (i = 0; i < 128; i++)
505 cx_write(ch->fifo_start + 4 * i, i);
506
507 /* write CMDS */
508 if (ch->jumponly)
509 cx_write(ch->cmds_start + 0, 8);
510 else
511 cx_write(ch->cmds_start + 0, risc);
512
513 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
514 cx_write(ch->cmds_start + 8, cdt);
515 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
516 cx_write(ch->cmds_start + 16, ch->ctrl_start);
517
518 if (ch->jumponly)
519 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
520 else
521 cx_write(ch->cmds_start + 20, 64 >> 2);
522
523 for (i = 24; i < 80; i += 4)
524 cx_write(ch->cmds_start + i, 0);
525
526 /* fill registers */
527 cx_write(ch->ptr1_reg, ch->fifo_start);
528 cx_write(ch->ptr2_reg, cdt);
529 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
530 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
531
532 return 0;
533}
534EXPORT_SYMBOL(cx25821_sram_channel_setup);
535
536int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
537 struct sram_channel *ch,
538 unsigned int bpl, u32 risc)
539{
540 unsigned int i, lines;
541 u32 cdt;
542
543 if (ch->cmds_start == 0) {
544 cx_write(ch->ptr1_reg, 0);
545 cx_write(ch->ptr2_reg, 0);
546 cx_write(ch->cnt2_reg, 0);
547 cx_write(ch->cnt1_reg, 0);
548 return 0;
549 }
550
551 bpl = (bpl + 7) & ~7; /* alignment */
552 cdt = ch->cdt;
553 lines = ch->fifo_size / bpl;
554
555 if (lines > 3)
556 lines = 3; /* for AUDIO */
557
558 BUG_ON(lines < 2);
559
560 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
561 cx_write(8 + 4, 8);
562 cx_write(8 + 8, 0);
563
564 /* write CDT */
565 for (i = 0; i < lines; i++) {
566 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
567 cx_write(cdt + 16 * i + 4, 0);
568 cx_write(cdt + 16 * i + 8, 0);
569 cx_write(cdt + 16 * i + 12, 0);
570 }
571
572 /* write CMDS */
573 if (ch->jumponly)
574 cx_write(ch->cmds_start + 0, 8);
575 else
576 cx_write(ch->cmds_start + 0, risc);
577
578 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
579 cx_write(ch->cmds_start + 8, cdt);
580 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
581 cx_write(ch->cmds_start + 16, ch->ctrl_start);
582
583 /* IQ size */
584 if (ch->jumponly)
585 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
586 else
587 cx_write(ch->cmds_start + 20, 64 >> 2);
588
589 /* zero out */
590 for (i = 24; i < 80; i += 4)
591 cx_write(ch->cmds_start + i, 0);
592
593 /* fill registers */
594 cx_write(ch->ptr1_reg, ch->fifo_start);
595 cx_write(ch->ptr2_reg, cdt);
596 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
597 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
598
599 return 0;
600}
601EXPORT_SYMBOL(cx25821_sram_channel_setup_audio);
602
603void cx25821_sram_channel_dump(struct cx25821_dev *dev, struct sram_channel *ch)
604{
605 static char *name[] = {
606 "init risc lo",
607 "init risc hi",
608 "cdt base",
609 "cdt size",
610 "iq base",
611 "iq size",
612 "risc pc lo",
613 "risc pc hi",
614 "iq wr ptr",
615 "iq rd ptr",
616 "cdt current",
617 "pci target lo",
618 "pci target hi",
619 "line / byte",
620 };
621 u32 risc;
622 unsigned int i, j, n;
623
624 pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name);
625 for (i = 0; i < ARRAY_SIZE(name); i++)
626 pr_warn("cmds + 0x%2x: %-15s: 0x%08x\n",
627 i * 4, name[i], cx_read(ch->cmds_start + 4 * i));
628
629 j = i * 4;
630 for (i = 0; i < 4;) {
631 risc = cx_read(ch->cmds_start + 4 * (i + 14));
632 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i);
633 i += cx25821_risc_decode(risc);
634 }
635
636 for (i = 0; i < (64 >> 2); i += n) {
637 risc = cx_read(ch->ctrl_start + 4 * i);
638 /* No consideration for bits 63-32 */
639
640 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
641 i * 4, ch->ctrl_start + 4 * i, i);
642 n = cx25821_risc_decode(risc);
643 for (j = 1; j < n; j++) {
644 risc = cx_read(ch->ctrl_start + 4 * (i + j));
645 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
646 4 * (i + j), i + j, risc, j);
647 }
648 }
649
650 pr_warn(" : fifo: 0x%08x -> 0x%x\n",
651 ch->fifo_start, ch->fifo_start + ch->fifo_size);
652 pr_warn(" : ctrl: 0x%08x -> 0x%x\n",
653 ch->ctrl_start, ch->ctrl_start + 6 * 16);
654 pr_warn(" : ptr1_reg: 0x%08x\n",
655 cx_read(ch->ptr1_reg));
656 pr_warn(" : ptr2_reg: 0x%08x\n",
657 cx_read(ch->ptr2_reg));
658 pr_warn(" : cnt1_reg: 0x%08x\n",
659 cx_read(ch->cnt1_reg));
660 pr_warn(" : cnt2_reg: 0x%08x\n",
661 cx_read(ch->cnt2_reg));
662}
663EXPORT_SYMBOL(cx25821_sram_channel_dump);
664
665void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
666 struct sram_channel *ch)
667{
668 static const char * const name[] = {
669 "init risc lo",
670 "init risc hi",
671 "cdt base",
672 "cdt size",
673 "iq base",
674 "iq size",
675 "risc pc lo",
676 "risc pc hi",
677 "iq wr ptr",
678 "iq rd ptr",
679 "cdt current",
680 "pci target lo",
681 "pci target hi",
682 "line / byte",
683 };
684
685 u32 risc, value, tmp;
686 unsigned int i, j, n;
687
688 pr_info("\n%s: %s - dma Audio channel status dump\n",
689 dev->name, ch->name);
690
691 for (i = 0; i < ARRAY_SIZE(name); i++)
692 pr_info("%s: cmds + 0x%2x: %-15s: 0x%08x\n",
693 dev->name, i * 4, name[i],
694 cx_read(ch->cmds_start + 4 * i));
695
696 j = i * 4;
697 for (i = 0; i < 4;) {
698 risc = cx_read(ch->cmds_start + 4 * (i + 14));
699 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i);
700 i += cx25821_risc_decode(risc);
701 }
702
703 for (i = 0; i < (64 >> 2); i += n) {
704 risc = cx_read(ch->ctrl_start + 4 * i);
705 /* No consideration for bits 63-32 */
706
707 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
708 i * 4, ch->ctrl_start + 4 * i, i);
709 n = cx25821_risc_decode(risc);
710
711 for (j = 1; j < n; j++) {
712 risc = cx_read(ch->ctrl_start + 4 * (i + j));
713 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
714 4 * (i + j), i + j, risc, j);
715 }
716 }
717
718 pr_warn(" : fifo: 0x%08x -> 0x%x\n",
719 ch->fifo_start, ch->fifo_start + ch->fifo_size);
720 pr_warn(" : ctrl: 0x%08x -> 0x%x\n",
721 ch->ctrl_start, ch->ctrl_start + 6 * 16);
722 pr_warn(" : ptr1_reg: 0x%08x\n",
723 cx_read(ch->ptr1_reg));
724 pr_warn(" : ptr2_reg: 0x%08x\n",
725 cx_read(ch->ptr2_reg));
726 pr_warn(" : cnt1_reg: 0x%08x\n",
727 cx_read(ch->cnt1_reg));
728 pr_warn(" : cnt2_reg: 0x%08x\n",
729 cx_read(ch->cnt2_reg));
730
731 for (i = 0; i < 4; i++) {
732 risc = cx_read(ch->cmds_start + 56 + (i * 4));
733 pr_warn("instruction %d = 0x%x\n", i, risc);
734 }
735
736 /* read data from the first cdt buffer */
737 risc = cx_read(AUD_A_CDT);
738 pr_warn("\nread cdt loc=0x%x\n", risc);
739 for (i = 0; i < 8; i++) {
740 n = cx_read(risc + i * 4);
741 pr_cont("0x%x ", n);
742 }
743 pr_cont("\n\n");
744
745 value = cx_read(CLK_RST);
746 CX25821_INFO(" CLK_RST = 0x%x\n\n", value);
747
748 value = cx_read(PLL_A_POST_STAT_BIST);
749 CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value);
750 value = cx_read(PLL_A_INT_FRAC);
751 CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value);
752
753 value = cx_read(PLL_B_POST_STAT_BIST);
754 CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value);
755 value = cx_read(PLL_B_INT_FRAC);
756 CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value);
757
758 value = cx_read(PLL_C_POST_STAT_BIST);
759 CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value);
760 value = cx_read(PLL_C_INT_FRAC);
761 CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value);
762
763 value = cx_read(PLL_D_POST_STAT_BIST);
764 CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value);
765 value = cx_read(PLL_D_INT_FRAC);
766 CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value);
767
768 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
769 CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value);
770}
771EXPORT_SYMBOL(cx25821_sram_channel_dump_audio);
772
773static void cx25821_shutdown(struct cx25821_dev *dev)
774{
775 int i;
776
777 /* disable RISC controller */
778 cx_write(DEV_CNTRL2, 0);
779
780 /* Disable Video A/B activity */
781 for (i = 0; i < VID_CHANNEL_NUM; i++) {
782 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
783 cx_write(dev->channels[i].sram_channels->int_msk, 0);
784 }
785
786 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
787 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
788 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
789 cx_write(dev->channels[i].sram_channels->int_msk, 0);
790 }
791
792 /* Disable Audio activity */
793 cx_write(AUD_INT_DMA_CTL, 0);
794
795 /* Disable Serial port */
796 cx_write(UART_CTL, 0);
797
798 /* Disable Interrupts */
799 cx_write(PCI_INT_MSK, 0);
800 cx_write(AUD_A_INT_MSK, 0);
801}
802
803void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
804 u32 format)
805{
806 if (channel_select <= 7 && channel_select >= 0) {
807 cx_write(dev->channels[channel_select].
808 sram_channels->pix_frmt, format);
809 dev->channels[channel_select].pixel_formats = format;
810 }
811}
812
813static void cx25821_set_vip_mode(struct cx25821_dev *dev,
814 struct sram_channel *ch)
815{
816 cx_write(ch->pix_frmt, PIXEL_FRMT_422);
817 cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
818}
819
820static void cx25821_initialize(struct cx25821_dev *dev)
821{
822 int i;
823
824 dprintk(1, "%s()\n", __func__);
825
826 cx25821_shutdown(dev);
827 cx_write(PCI_INT_STAT, 0xffffffff);
828
829 for (i = 0; i < VID_CHANNEL_NUM; i++)
830 cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff);
831
832 cx_write(AUD_A_INT_STAT, 0xffffffff);
833 cx_write(AUD_B_INT_STAT, 0xffffffff);
834 cx_write(AUD_C_INT_STAT, 0xffffffff);
835 cx_write(AUD_D_INT_STAT, 0xffffffff);
836 cx_write(AUD_E_INT_STAT, 0xffffffff);
837
838 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
839 cx_write(PAD_CTRL, 0x12); /* for I2C */
840 cx25821_registers_init(dev); /* init Pecos registers */
841 mdelay(100);
842
843 for (i = 0; i < VID_CHANNEL_NUM; i++) {
844 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
845 cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels,
846 1440, 0);
847 dev->channels[i].pixel_formats = PIXEL_FRMT_422;
848 dev->channels[i].use_cif_resolution = FALSE;
849 }
850
851 /* Probably only affect Downstream */
852 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
853 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
854 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
855 }
856
857 cx25821_sram_channel_setup_audio(dev,
858 dev->channels[SRAM_CH08].sram_channels,
859 128, 0);
860
861 cx25821_gpio_init(dev);
862}
863
864static int cx25821_get_resources(struct cx25821_dev *dev)
865{
866 if (request_mem_region
867 (pci_resource_start(dev->pci, 0), pci_resource_len(dev->pci, 0),
868 dev->name))
869 return 0;
870
871 pr_err("%s: can't get MMIO memory @ 0x%llx\n",
872 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
873
874 return -EBUSY;
875}
876
877static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
878{
879 dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
880
881 pr_info("%s(): Hardware revision = 0x%02x\n",
882 __func__, dev->hwrevision);
883}
884
885static void cx25821_iounmap(struct cx25821_dev *dev)
886{
887 if (dev == NULL)
888 return;
889
890 /* Releasing IO memory */
891 if (dev->lmmio != NULL) {
892 CX25821_INFO("Releasing lmmio.\n");
893 iounmap(dev->lmmio);
894 dev->lmmio = NULL;
895 }
896}
897
898static int cx25821_dev_setup(struct cx25821_dev *dev)
899{
900 int io_size = 0, i;
901
902 pr_info("\n***********************************\n");
903 pr_info("cx25821 set up\n");
904 pr_info("***********************************\n\n");
905
906 mutex_init(&dev->lock);
907
908 atomic_inc(&dev->refcount);
909
910 dev->nr = ++cx25821_devcount;
911 sprintf(dev->name, "cx25821[%d]", dev->nr);
912
913 mutex_lock(&cx25821_devlist_mutex);
914 list_add_tail(&dev->devlist, &cx25821_devlist);
915 mutex_unlock(&cx25821_devlist_mutex);
916
917 strcpy(cx25821_boards[UNKNOWN_BOARD].name, "unknown");
918 strcpy(cx25821_boards[CX25821_BOARD].name, "cx25821");
919
920 if (dev->pci->device != 0x8210) {
921 pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n",
922 __func__, dev->pci->device);
923 return -1;
924 } else {
925 pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device);
926 }
927
928 /* Apply a sensible clock frequency for the PCIe bridge */
929 dev->clk_freq = 28000000;
930 for (i = 0; i < MAX_VID_CHANNEL_NUM; i++)
931 dev->channels[i].sram_channels = &cx25821_sram_channels[i];
932
933 if (dev->nr > 1)
934 CX25821_INFO("dev->nr > 1!");
935
936 /* board config */
937 dev->board = 1; /* card[dev->nr]; */
938 dev->_max_num_decoders = MAX_DECODERS;
939
940 dev->pci_bus = dev->pci->bus->number;
941 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
942 dev->pci_irqmask = 0x001f00;
943
944 /* External Master 1 Bus */
945 dev->i2c_bus[0].nr = 0;
946 dev->i2c_bus[0].dev = dev;
947 dev->i2c_bus[0].reg_stat = I2C1_STAT;
948 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
949 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
950 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
951 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
952 dev->i2c_bus[0].i2c_period = (0x07 << 24); /* 1.95MHz */
953
954 if (cx25821_get_resources(dev) < 0) {
955 pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n",
956 dev->name, dev->pci->subsystem_vendor,
957 dev->pci->subsystem_device);
958
959 cx25821_devcount--;
960 return -EBUSY;
961 }
962
963 /* PCIe stuff */
964 dev->base_io_addr = pci_resource_start(dev->pci, 0);
965 io_size = pci_resource_len(dev->pci, 0);
966
967 if (!dev->base_io_addr) {
968 CX25821_ERR("No PCI Memory resources, exiting!\n");
969 return -ENODEV;
970 }
971
972 dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
973
974 if (!dev->lmmio) {
975 CX25821_ERR
976 ("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
977 cx25821_iounmap(dev);
978 return -ENOMEM;
979 }
980
981 dev->bmmio = (u8 __iomem *) dev->lmmio;
982
983 pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
984 dev->name, dev->pci->subsystem_vendor,
985 dev->pci->subsystem_device, cx25821_boards[dev->board].name,
986 dev->board, card[dev->nr] == dev->board ?
987 "insmod option" : "autodetected");
988
989 /* init hardware */
990 cx25821_initialize(dev);
991
992 cx25821_i2c_register(&dev->i2c_bus[0]);
993/* cx25821_i2c_register(&dev->i2c_bus[1]);
994 * cx25821_i2c_register(&dev->i2c_bus[2]); */
995
996 CX25821_INFO("i2c register! bus->i2c_rc = %d\n",
997 dev->i2c_bus[0].i2c_rc);
998
999 cx25821_card_setup(dev);
1000
1001 if (medusa_video_init(dev) < 0)
1002 CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__);
1003
1004 cx25821_video_register(dev);
1005
1006 /* register IOCTL device */
1007 dev->ioctl_dev =
1008 cx25821_vdev_init(dev, dev->pci, &cx25821_videoioctl_template,
1009 "video");
1010
1011 if (video_register_device
1012 (dev->ioctl_dev, VFL_TYPE_GRABBER, VIDEO_IOCTL_CH) < 0) {
1013 cx25821_videoioctl_unregister(dev);
1014 pr_err("%s(): Failed to register video adapter for IOCTL, so unregistering videoioctl device\n",
1015 __func__);
1016 }
1017
1018 cx25821_dev_checkrevision(dev);
1019 CX25821_INFO("setup done!\n");
1020
1021 return 0;
1022}
1023
1024void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev,
1025 struct upstream_user_struct *up_data)
1026{
1027 dev->_isNTSC = !strcmp(dev->vid_stdname, "NTSC") ? 1 : 0;
1028
1029 dev->tvnorm = !dev->_isNTSC ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1030 medusa_set_videostandard(dev);
1031
1032 cx25821_vidupstream_init_ch1(dev, dev->channel_select,
1033 dev->pixel_format);
1034}
1035
1036void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev,
1037 struct upstream_user_struct *up_data)
1038{
1039 dev->_isNTSC_ch2 = !strcmp(dev->vid_stdname_ch2, "NTSC") ? 1 : 0;
1040
1041 dev->tvnorm = !dev->_isNTSC_ch2 ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1042 medusa_set_videostandard(dev);
1043
1044 cx25821_vidupstream_init_ch2(dev, dev->channel_select_ch2,
1045 dev->pixel_format_ch2);
1046}
1047
1048void cx25821_start_upstream_audio(struct cx25821_dev *dev,
1049 struct upstream_user_struct *up_data)
1050{
1051 cx25821_audio_upstream_init(dev, AUDIO_UPSTREAM_SRAM_CHANNEL_B);
1052}
1053
1054void cx25821_dev_unregister(struct cx25821_dev *dev)
1055{
1056 int i;
1057
1058 if (!dev->base_io_addr)
1059 return;
1060
1061 cx25821_free_mem_upstream_ch1(dev);
1062 cx25821_free_mem_upstream_ch2(dev);
1063 cx25821_free_mem_upstream_audio(dev);
1064
1065 release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
1066
1067 if (!atomic_dec_and_test(&dev->refcount))
1068 return;
1069
1070 for (i = 0; i < VID_CHANNEL_NUM; i++)
1071 cx25821_video_unregister(dev, i);
1072
1073 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
1074 i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) {
1075 cx25821_video_unregister(dev, i);
1076 }
1077
1078 cx25821_videoioctl_unregister(dev);
1079
1080 cx25821_i2c_unregister(&dev->i2c_bus[0]);
1081 cx25821_iounmap(dev);
1082}
1083EXPORT_SYMBOL(cx25821_dev_unregister);
1084
1085static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
1086 unsigned int offset, u32 sync_line,
1087 unsigned int bpl, unsigned int padding,
1088 unsigned int lines)
1089{
1090 struct scatterlist *sg;
1091 unsigned int line, todo;
1092
1093 /* sync instruction */
1094 if (sync_line != NO_SYNC_LINE)
1095 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1096
1097 /* scan lines */
1098 sg = sglist;
1099 for (line = 0; line < lines; line++) {
1100 while (offset && offset >= sg_dma_len(sg)) {
1101 offset -= sg_dma_len(sg);
1102 sg++;
1103 }
1104 if (bpl <= sg_dma_len(sg) - offset) {
1105 /* fits into current chunk */
1106 *(rp++) =
1107 cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL | bpl);
1108 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1109 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1110 offset += bpl;
1111 } else {
1112 /* scanline needs to be split */
1113 todo = bpl;
1114 *(rp++) =
1115 cpu_to_le32(RISC_WRITE | RISC_SOL |
1116 (sg_dma_len(sg) - offset));
1117 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1118 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1119 todo -= (sg_dma_len(sg) - offset);
1120 offset = 0;
1121 sg++;
1122 while (todo > sg_dma_len(sg)) {
1123 *(rp++) =
1124 cpu_to_le32(RISC_WRITE | sg_dma_len(sg));
1125 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1126 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1127 todo -= sg_dma_len(sg);
1128 sg++;
1129 }
1130 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1131 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1132 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1133 offset += todo;
1134 }
1135
1136 offset += padding;
1137 }
1138
1139 return rp;
1140}
1141
1142int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1143 struct scatterlist *sglist, unsigned int top_offset,
1144 unsigned int bottom_offset, unsigned int bpl,
1145 unsigned int padding, unsigned int lines)
1146{
1147 u32 instructions;
1148 u32 fields;
1149 __le32 *rp;
1150 int rc;
1151
1152 fields = 0;
1153 if (UNSET != top_offset)
1154 fields++;
1155 if (UNSET != bottom_offset)
1156 fields++;
1157
1158 /* estimate risc mem: worst case is one write per page border +
1159 one write per scan line + syncs + jump (all 2 dwords). Padding
1160 can cause next bpl to start close to a page border. First DMA
1161 region may be smaller than PAGE_SIZE */
1162 /* write and jump need and extra dword */
1163 instructions =
1164 fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
1165 instructions += 2;
1166 rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1167
1168 if (rc < 0)
1169 return rc;
1170
1171 /* write risc instructions */
1172 rp = risc->cpu;
1173
1174 if (UNSET != top_offset) {
1175 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1176 lines);
1177 }
1178
1179 if (UNSET != bottom_offset) {
1180 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1181 padding, lines);
1182 }
1183
1184 /* save pointer to jmp instruction address */
1185 risc->jmp = rp;
1186 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1187
1188 return 0;
1189}
1190
1191static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
1192 unsigned int offset, u32 sync_line,
1193 unsigned int bpl, unsigned int padding,
1194 unsigned int lines, unsigned int lpi)
1195{
1196 struct scatterlist *sg;
1197 unsigned int line, todo, sol;
1198
1199 /* sync instruction */
1200 if (sync_line != NO_SYNC_LINE)
1201 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1202
1203 /* scan lines */
1204 sg = sglist;
1205 for (line = 0; line < lines; line++) {
1206 while (offset && offset >= sg_dma_len(sg)) {
1207 offset -= sg_dma_len(sg);
1208 sg++;
1209 }
1210
1211 if (lpi && line > 0 && !(line % lpi))
1212 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1213 else
1214 sol = RISC_SOL;
1215
1216 if (bpl <= sg_dma_len(sg) - offset) {
1217 /* fits into current chunk */
1218 *(rp++) =
1219 cpu_to_le32(RISC_WRITE | sol | RISC_EOL | bpl);
1220 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1221 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1222 offset += bpl;
1223 } else {
1224 /* scanline needs to be split */
1225 todo = bpl;
1226 *(rp++) = cpu_to_le32(RISC_WRITE | sol |
1227 (sg_dma_len(sg) - offset));
1228 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1229 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1230 todo -= (sg_dma_len(sg) - offset);
1231 offset = 0;
1232 sg++;
1233 while (todo > sg_dma_len(sg)) {
1234 *(rp++) = cpu_to_le32(RISC_WRITE |
1235 sg_dma_len(sg));
1236 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1237 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1238 todo -= sg_dma_len(sg);
1239 sg++;
1240 }
1241 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1242 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1243 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1244 offset += todo;
1245 }
1246 offset += padding;
1247 }
1248
1249 return rp;
1250}
1251
1252int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1253 struct btcx_riscmem *risc,
1254 struct scatterlist *sglist,
1255 unsigned int bpl,
1256 unsigned int lines, unsigned int lpi)
1257{
1258 u32 instructions;
1259 __le32 *rp;
1260 int rc;
1261
1262 /* estimate risc mem: worst case is one write per page border +
1263 one write per scan line + syncs + jump (all 2 dwords). Here
1264 there is no padding and no sync. First DMA region may be smaller
1265 than PAGE_SIZE */
1266 /* Jump and write need an extra dword */
1267 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1268 instructions += 1;
1269
1270 rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1271 if (rc < 0)
1272 return rc;
1273
1274 /* write risc instructions */
1275 rp = risc->cpu;
1276 rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
1277 lines, lpi);
1278
1279 /* save pointer to jmp instruction address */
1280 risc->jmp = rp;
1281 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1282 return 0;
1283}
1284EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
1285
1286int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1287 u32 reg, u32 mask, u32 value)
1288{
1289 __le32 *rp;
1290 int rc;
1291
1292 rc = btcx_riscmem_alloc(pci, risc, 4 * 16);
1293
1294 if (rc < 0)
1295 return rc;
1296
1297 /* write risc instructions */
1298 rp = risc->cpu;
1299
1300 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1);
1301 *(rp++) = cpu_to_le32(reg);
1302 *(rp++) = cpu_to_le32(value);
1303 *(rp++) = cpu_to_le32(mask);
1304 *(rp++) = cpu_to_le32(RISC_JUMP);
1305 *(rp++) = cpu_to_le32(risc->dma);
1306 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1307 return 0;
1308}
1309
1310void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf)
1311{
1312 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1313
1314 BUG_ON(in_interrupt());
1315 videobuf_waiton(q, &buf->vb, 0, 0);
1316 videobuf_dma_unmap(q->dev, dma);
1317 videobuf_dma_free(dma);
1318 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1319 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1320}
1321
1322static irqreturn_t cx25821_irq(int irq, void *dev_id)
1323{
1324 struct cx25821_dev *dev = dev_id;
1325 u32 pci_status, pci_mask;
1326 u32 vid_status;
1327 int i, handled = 0;
1328 u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1329
1330 pci_status = cx_read(PCI_INT_STAT);
1331 pci_mask = cx_read(PCI_INT_MSK);
1332
1333 if (pci_status == 0)
1334 goto out;
1335
1336 for (i = 0; i < VID_CHANNEL_NUM; i++) {
1337 if (pci_status & mask[i]) {
1338 vid_status = cx_read(dev->channels[i].
1339 sram_channels->int_stat);
1340
1341 if (vid_status)
1342 handled +=
1343 cx25821_video_irq(dev, i, vid_status);
1344
1345 cx_write(PCI_INT_STAT, mask[i]);
1346 }
1347 }
1348
1349out:
1350 return IRQ_RETVAL(handled);
1351}
1352
1353void cx25821_print_irqbits(char *name, char *tag, char **strings,
1354 int len, u32 bits, u32 mask)
1355{
1356 unsigned int i;
1357
1358 printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits);
1359
1360 for (i = 0; i < len; i++) {
1361 if (!(bits & (1 << i)))
1362 continue;
1363 if (strings[i])
1364 pr_cont(" %s", strings[i]);
1365 else
1366 pr_cont(" %d", i);
1367 if (!(mask & (1 << i)))
1368 continue;
1369 pr_cont("*");
1370 }
1371 pr_cont("\n");
1372}
1373EXPORT_SYMBOL(cx25821_print_irqbits);
1374
1375struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1376{
1377 struct cx25821_dev *dev = pci_get_drvdata(pci);
1378 return dev;
1379}
1380EXPORT_SYMBOL(cx25821_dev_get);
1381
1382static int __devinit cx25821_initdev(struct pci_dev *pci_dev,
1383 const struct pci_device_id *pci_id)
1384{
1385 struct cx25821_dev *dev;
1386 int err = 0;
1387
1388 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1389 if (NULL == dev)
1390 return -ENOMEM;
1391
1392 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1393 if (err < 0)
1394 goto fail_free;
1395
1396 /* pci init */
1397 dev->pci = pci_dev;
1398 if (pci_enable_device(pci_dev)) {
1399 err = -EIO;
1400
1401 pr_info("pci enable failed!\n");
1402
1403 goto fail_unregister_device;
1404 }
1405
1406 pr_info("Athena pci enable !\n");
1407
1408 err = cx25821_dev_setup(dev);
1409 if (err) {
1410 if (err == -EBUSY)
1411 goto fail_unregister_device;
1412 else
1413 goto fail_unregister_pci;
1414 }
1415
1416 /* print pci info */
1417 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1418 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1419 pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1420 dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1421 dev->pci_lat, (unsigned long long)dev->base_io_addr);
1422
1423 pci_set_master(pci_dev);
1424 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1425 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1426 err = -EIO;
1427 goto fail_irq;
1428 }
1429
1430 err =
1431 request_irq(pci_dev->irq, cx25821_irq, IRQF_SHARED | IRQF_DISABLED,
1432 dev->name, dev);
1433
1434 if (err < 0) {
1435 pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq);
1436 goto fail_irq;
1437 }
1438
1439 return 0;
1440
1441fail_irq:
1442 pr_info("cx25821_initdev() can't get IRQ !\n");
1443 cx25821_dev_unregister(dev);
1444
1445fail_unregister_pci:
1446 pci_disable_device(pci_dev);
1447fail_unregister_device:
1448 v4l2_device_unregister(&dev->v4l2_dev);
1449
1450fail_free:
1451 kfree(dev);
1452 return err;
1453}
1454
1455static void __devexit cx25821_finidev(struct pci_dev *pci_dev)
1456{
1457 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1458 struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1459
1460 cx25821_shutdown(dev);
1461 pci_disable_device(pci_dev);
1462
1463 /* unregister stuff */
1464 if (pci_dev->irq)
1465 free_irq(pci_dev->irq, dev);
1466
1467 mutex_lock(&cx25821_devlist_mutex);
1468 list_del(&dev->devlist);
1469 mutex_unlock(&cx25821_devlist_mutex);
1470
1471 cx25821_dev_unregister(dev);
1472 v4l2_device_unregister(v4l2_dev);
1473 kfree(dev);
1474}
1475
1476static struct pci_device_id cx25821_pci_tbl[] = {
1477 {
1478 /* CX25821 Athena */
1479 .vendor = 0x14f1,
1480 .device = 0x8210,
1481 .subvendor = 0x14f1,
1482 .subdevice = 0x0920,
1483 },
1484 {
1485 /* --- end of list --- */
1486 }
1487};
1488
1489MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
1490
1491static struct pci_driver cx25821_pci_driver = {
1492 .name = "cx25821",
1493 .id_table = cx25821_pci_tbl,
1494 .probe = cx25821_initdev,
1495 .remove = __devexit_p(cx25821_finidev),
1496 /* TODO */
1497 .suspend = NULL,
1498 .resume = NULL,
1499};
1500
1501static int __init cx25821_init(void)
1502{
1503 pr_info("driver version %d.%d.%d loaded\n",
1504 (CX25821_VERSION_CODE >> 16) & 0xff,
1505 (CX25821_VERSION_CODE >> 8) & 0xff,
1506 CX25821_VERSION_CODE & 0xff);
1507 return pci_register_driver(&cx25821_pci_driver);
1508}
1509
1510static void __exit cx25821_fini(void)
1511{
1512 pci_unregister_driver(&cx25821_pci_driver);
1513}
1514
1515EXPORT_SYMBOL(cx25821_set_gpiopin_direction);
1516
1517module_init(cx25821_init);
1518module_exit(cx25821_fini);
diff --git a/drivers/staging/cx25821/cx25821-gpio.c b/drivers/staging/cx25821/cx25821-gpio.c
new file mode 100644
index 00000000000..2f154b3658a
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-gpio.c
@@ -0,0 +1,97 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include "cx25821.h"
24
25/********************* GPIO stuffs *********************/
26void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
27 int pin_number, int pin_logic_value)
28{
29 int bit = pin_number;
30 u32 gpio_oe_reg = GPIO_LO_OE;
31 u32 gpio_register = 0;
32 u32 value = 0;
33
34 /* Check for valid pinNumber */
35 if (pin_number >= 47)
36 return;
37
38 if (pin_number > 31) {
39 bit = pin_number - 31;
40 gpio_oe_reg = GPIO_HI_OE;
41 }
42 /* Here we will make sure that the GPIOs 0 and 1 are output. keep the
43 * rest as is */
44 gpio_register = cx_read(gpio_oe_reg);
45
46 if (pin_logic_value == 1)
47 value = gpio_register | Set_GPIO_Bit(bit);
48 else
49 value = gpio_register & Clear_GPIO_Bit(bit);
50
51 cx_write(gpio_oe_reg, value);
52}
53
54static void cx25821_set_gpiopin_logicvalue(struct cx25821_dev *dev,
55 int pin_number, int pin_logic_value)
56{
57 int bit = pin_number;
58 u32 gpio_reg = GPIO_LO;
59 u32 value = 0;
60
61 /* Check for valid pinNumber */
62 if (pin_number >= 47)
63 return;
64
65 /* change to output direction */
66 cx25821_set_gpiopin_direction(dev, pin_number, 0);
67
68 if (pin_number > 31) {
69 bit = pin_number - 31;
70 gpio_reg = GPIO_HI;
71 }
72
73 value = cx_read(gpio_reg);
74
75 if (pin_logic_value == 0)
76 value &= Clear_GPIO_Bit(bit);
77 else
78 value |= Set_GPIO_Bit(bit);
79
80 cx_write(gpio_reg, value);
81}
82
83void cx25821_gpio_init(struct cx25821_dev *dev)
84{
85 if (dev == NULL)
86 return;
87
88 switch (dev->board) {
89 case CX25821_BOARD_CONEXANT_ATHENA10:
90 default:
91 /* set GPIO 5 to select the path for Medusa/Athena */
92 cx25821_set_gpiopin_logicvalue(dev, 5, 1);
93 mdelay(20);
94 break;
95 }
96
97}
diff --git a/drivers/staging/cx25821/cx25821-gpio.h b/drivers/staging/cx25821/cx25821-gpio.h
new file mode 100644
index 00000000000..ca07644154a
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-gpio.h
@@ -0,0 +1,2 @@
1
2void cx25821_gpio_init(struct athena_dev *dev);
diff --git a/drivers/staging/cx25821/cx25821-i2c.c b/drivers/staging/cx25821/cx25821-i2c.c
new file mode 100644
index 00000000000..130dfebebe2
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-i2c.c
@@ -0,0 +1,425 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 *
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include "cx25821.h"
27#include <linux/i2c.h>
28
29static unsigned int i2c_debug;
30module_param(i2c_debug, int, 0644);
31MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]");
32
33static unsigned int i2c_scan;
34module_param(i2c_scan, int, 0444);
35MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time");
36
37#define dprintk(level, fmt, arg...) \
38do { \
39 if (i2c_debug >= level) \
40 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ##arg); \
41} while (0)
42
43#define I2C_WAIT_DELAY 32
44#define I2C_WAIT_RETRY 64
45
46#define I2C_EXTEND (1 << 3)
47#define I2C_NOSTOP (1 << 4)
48
49static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
50{
51 struct cx25821_i2c *bus = i2c_adap->algo_data;
52 struct cx25821_dev *dev = bus->dev;
53 return cx_read(bus->reg_stat) & 0x01;
54}
55
56static inline int i2c_is_busy(struct i2c_adapter *i2c_adap)
57{
58 struct cx25821_i2c *bus = i2c_adap->algo_data;
59 struct cx25821_dev *dev = bus->dev;
60 return cx_read(bus->reg_stat) & 0x02 ? 1 : 0;
61}
62
63static int i2c_wait_done(struct i2c_adapter *i2c_adap)
64{
65 int count;
66
67 for (count = 0; count < I2C_WAIT_RETRY; count++) {
68 if (!i2c_is_busy(i2c_adap))
69 break;
70 udelay(I2C_WAIT_DELAY);
71 }
72
73 if (I2C_WAIT_RETRY == count)
74 return 0;
75
76 return 1;
77}
78
79static int i2c_sendbytes(struct i2c_adapter *i2c_adap,
80 const struct i2c_msg *msg, int joined_rlen)
81{
82 struct cx25821_i2c *bus = i2c_adap->algo_data;
83 struct cx25821_dev *dev = bus->dev;
84 u32 wdata, addr, ctrl;
85 int retval, cnt;
86
87 if (joined_rlen)
88 dprintk(1, "%s(msg->wlen=%d, nextmsg->rlen=%d)\n", __func__,
89 msg->len, joined_rlen);
90 else
91 dprintk(1, "%s(msg->len=%d)\n", __func__, msg->len);
92
93 /* Deal with i2c probe functions with zero payload */
94 if (msg->len == 0) {
95 cx_write(bus->reg_addr, msg->addr << 25);
96 cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2));
97
98 if (!i2c_wait_done(i2c_adap))
99 return -EIO;
100
101 if (!i2c_slave_did_ack(i2c_adap))
102 return -EIO;
103
104 dprintk(1, "%s(): returns 0\n", __func__);
105 return 0;
106 }
107
108 /* dev, reg + first byte */
109 addr = (msg->addr << 25) | msg->buf[0];
110 wdata = msg->buf[0];
111
112 ctrl = bus->i2c_period | (1 << 12) | (1 << 2);
113
114 if (msg->len > 1)
115 ctrl |= I2C_NOSTOP | I2C_EXTEND;
116 else if (joined_rlen)
117 ctrl |= I2C_NOSTOP;
118
119 cx_write(bus->reg_addr, addr);
120 cx_write(bus->reg_wdata, wdata);
121 cx_write(bus->reg_ctrl, ctrl);
122
123 retval = i2c_wait_done(i2c_adap);
124 if (retval < 0)
125 goto err;
126
127 if (retval == 0)
128 goto eio;
129
130 if (i2c_debug) {
131 if (!(ctrl & I2C_NOSTOP))
132 printk(" >\n");
133 }
134
135 for (cnt = 1; cnt < msg->len; cnt++) {
136 /* following bytes */
137 wdata = msg->buf[cnt];
138 ctrl = bus->i2c_period | (1 << 12) | (1 << 2);
139
140 if (cnt < msg->len - 1)
141 ctrl |= I2C_NOSTOP | I2C_EXTEND;
142 else if (joined_rlen)
143 ctrl |= I2C_NOSTOP;
144
145 cx_write(bus->reg_addr, addr);
146 cx_write(bus->reg_wdata, wdata);
147 cx_write(bus->reg_ctrl, ctrl);
148
149 retval = i2c_wait_done(i2c_adap);
150 if (retval < 0)
151 goto err;
152
153 if (retval == 0)
154 goto eio;
155
156 if (i2c_debug) {
157 dprintk(1, " %02x", msg->buf[cnt]);
158 if (!(ctrl & I2C_NOSTOP))
159 dprintk(1, " >\n");
160 }
161 }
162
163 return msg->len;
164
165eio:
166 retval = -EIO;
167err:
168 if (i2c_debug)
169 pr_err(" ERR: %d\n", retval);
170 return retval;
171}
172
173static int i2c_readbytes(struct i2c_adapter *i2c_adap,
174 const struct i2c_msg *msg, int joined)
175{
176 struct cx25821_i2c *bus = i2c_adap->algo_data;
177 struct cx25821_dev *dev = bus->dev;
178 u32 ctrl, cnt;
179 int retval;
180
181 if (i2c_debug && !joined)
182 dprintk(1, "6-%s(msg->len=%d)\n", __func__, msg->len);
183
184 /* Deal with i2c probe functions with zero payload */
185 if (msg->len == 0) {
186 cx_write(bus->reg_addr, msg->addr << 25);
187 cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2) | 1);
188 if (!i2c_wait_done(i2c_adap))
189 return -EIO;
190 if (!i2c_slave_did_ack(i2c_adap))
191 return -EIO;
192
193 dprintk(1, "%s(): returns 0\n", __func__);
194 return 0;
195 }
196
197 if (i2c_debug) {
198 if (joined)
199 dprintk(1, " R");
200 else
201 dprintk(1, " <R %02x", (msg->addr << 1) + 1);
202 }
203
204 for (cnt = 0; cnt < msg->len; cnt++) {
205
206 ctrl = bus->i2c_period | (1 << 12) | (1 << 2) | 1;
207
208 if (cnt < msg->len - 1)
209 ctrl |= I2C_NOSTOP | I2C_EXTEND;
210
211 cx_write(bus->reg_addr, msg->addr << 25);
212 cx_write(bus->reg_ctrl, ctrl);
213
214 retval = i2c_wait_done(i2c_adap);
215 if (retval < 0)
216 goto err;
217 if (retval == 0)
218 goto eio;
219 msg->buf[cnt] = cx_read(bus->reg_rdata) & 0xff;
220
221 if (i2c_debug) {
222 dprintk(1, " %02x", msg->buf[cnt]);
223 if (!(ctrl & I2C_NOSTOP))
224 dprintk(1, " >\n");
225 }
226 }
227
228 return msg->len;
229eio:
230 retval = -EIO;
231err:
232 if (i2c_debug)
233 pr_err(" ERR: %d\n", retval);
234 return retval;
235}
236
237static int i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
238{
239 struct cx25821_i2c *bus = i2c_adap->algo_data;
240 struct cx25821_dev *dev = bus->dev;
241 int i, retval = 0;
242
243 dprintk(1, "%s(num = %d)\n", __func__, num);
244
245 for (i = 0; i < num; i++) {
246 dprintk(1, "%s(num = %d) addr = 0x%02x len = 0x%x\n",
247 __func__, num, msgs[i].addr, msgs[i].len);
248
249 if (msgs[i].flags & I2C_M_RD) {
250 /* read */
251 retval = i2c_readbytes(i2c_adap, &msgs[i], 0);
252 } else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) &&
253 msgs[i].addr == msgs[i + 1].addr) {
254 /* write then read from same address */
255 retval =
256 i2c_sendbytes(i2c_adap, &msgs[i], msgs[i + 1].len);
257
258 if (retval < 0)
259 goto err;
260 i++;
261 retval = i2c_readbytes(i2c_adap, &msgs[i], 1);
262 } else {
263 /* write */
264 retval = i2c_sendbytes(i2c_adap, &msgs[i], 0);
265 }
266
267 if (retval < 0)
268 goto err;
269 }
270 return num;
271
272err:
273 return retval;
274}
275
276
277static u32 cx25821_functionality(struct i2c_adapter *adap)
278{
279 return I2C_FUNC_SMBUS_EMUL |
280 I2C_FUNC_I2C |
281 I2C_FUNC_SMBUS_WORD_DATA |
282 I2C_FUNC_SMBUS_READ_WORD_DATA | I2C_FUNC_SMBUS_WRITE_WORD_DATA;
283}
284
285static struct i2c_algorithm cx25821_i2c_algo_template = {
286 .master_xfer = i2c_xfer,
287 .functionality = cx25821_functionality,
288#ifdef NEED_ALGO_CONTROL
289 .algo_control = dummy_algo_control,
290#endif
291};
292
293static struct i2c_adapter cx25821_i2c_adap_template = {
294 .name = "cx25821",
295 .owner = THIS_MODULE,
296 .algo = &cx25821_i2c_algo_template,
297};
298
299static struct i2c_client cx25821_i2c_client_template = {
300 .name = "cx25821 internal",
301};
302
303/* init + register i2c algo-bit adapter */
304int cx25821_i2c_register(struct cx25821_i2c *bus)
305{
306 struct cx25821_dev *dev = bus->dev;
307
308 dprintk(1, "%s(bus = %d)\n", __func__, bus->nr);
309
310 memcpy(&bus->i2c_adap, &cx25821_i2c_adap_template,
311 sizeof(bus->i2c_adap));
312 memcpy(&bus->i2c_algo, &cx25821_i2c_algo_template,
313 sizeof(bus->i2c_algo));
314 memcpy(&bus->i2c_client, &cx25821_i2c_client_template,
315 sizeof(bus->i2c_client));
316
317 bus->i2c_adap.dev.parent = &dev->pci->dev;
318
319 strlcpy(bus->i2c_adap.name, bus->dev->name, sizeof(bus->i2c_adap.name));
320
321 bus->i2c_algo.data = bus;
322 bus->i2c_adap.algo_data = bus;
323 i2c_set_adapdata(&bus->i2c_adap, &dev->v4l2_dev);
324 i2c_add_adapter(&bus->i2c_adap);
325
326 bus->i2c_client.adapter = &bus->i2c_adap;
327
328 /* set up the I2c */
329 bus->i2c_client.addr = (0x88 >> 1);
330
331 return bus->i2c_rc;
332}
333
334int cx25821_i2c_unregister(struct cx25821_i2c *bus)
335{
336 i2c_del_adapter(&bus->i2c_adap);
337 return 0;
338}
339
340void cx25821_av_clk(struct cx25821_dev *dev, int enable)
341{
342 /* write 0 to bus 2 addr 0x144 via i2x_xfer() */
343 char buffer[3];
344 struct i2c_msg msg;
345 dprintk(1, "%s(enabled = %d)\n", __func__, enable);
346
347 /* Register 0x144 */
348 buffer[0] = 0x01;
349 buffer[1] = 0x44;
350 if (enable == 1)
351 buffer[2] = 0x05;
352 else
353 buffer[2] = 0x00;
354
355 msg.addr = 0x44;
356 msg.flags = I2C_M_TEN;
357 msg.len = 3;
358 msg.buf = buffer;
359
360 i2c_xfer(&dev->i2c_bus[0].i2c_adap, &msg, 1);
361}
362
363int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value)
364{
365 struct i2c_client *client = &bus->i2c_client;
366 int retval = 0;
367 int v = 0;
368 u8 addr[2] = { 0, 0 };
369 u8 buf[4] = { 0, 0, 0, 0 };
370
371 struct i2c_msg msgs[2] = {
372 {
373 .addr = client->addr,
374 .flags = 0,
375 .len = 2,
376 .buf = addr,
377 }, {
378 .addr = client->addr,
379 .flags = I2C_M_RD,
380 .len = 4,
381 .buf = buf,
382 }
383 };
384
385 addr[0] = (reg_addr >> 8);
386 addr[1] = (reg_addr & 0xff);
387 msgs[0].addr = 0x44;
388 msgs[1].addr = 0x44;
389
390 retval = i2c_xfer(client->adapter, msgs, 2);
391
392 v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
393 *value = v;
394
395 return v;
396}
397
398int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value)
399{
400 struct i2c_client *client = &bus->i2c_client;
401 int retval = 0;
402 u8 buf[6] = { 0, 0, 0, 0, 0, 0 };
403
404 struct i2c_msg msgs[1] = {
405 {
406 .addr = client->addr,
407 .flags = 0,
408 .len = 6,
409 .buf = buf,
410 }
411 };
412
413 buf[0] = reg_addr >> 8;
414 buf[1] = reg_addr & 0xff;
415 buf[5] = (value >> 24) & 0xff;
416 buf[4] = (value >> 16) & 0xff;
417 buf[3] = (value >> 8) & 0xff;
418 buf[2] = value & 0xff;
419 client->flags = 0;
420 msgs[0].addr = 0x44;
421
422 retval = i2c_xfer(client->adapter, msgs, 1);
423
424 return retval;
425}
diff --git a/drivers/staging/cx25821/cx25821-medusa-defines.h b/drivers/staging/cx25821/cx25821-medusa-defines.h
new file mode 100644
index 00000000000..60d197f5755
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-medusa-defines.h
@@ -0,0 +1,42 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _MEDUSA_DEF_H_
24#define _MEDUSA_DEF_H_
25
26/* Video deocder that we supported */
27#define VDEC_A 0
28#define VDEC_B 1
29#define VDEC_C 2
30#define VDEC_D 3
31#define VDEC_E 4
32#define VDEC_F 5
33#define VDEC_G 6
34#define VDEC_H 7
35
36/* end of display sequence */
37#define END_OF_SEQ 0xF;
38
39/* registry string size */
40#define MAX_REGISTRY_SZ 40;
41
42#endif
diff --git a/drivers/staging/cx25821/cx25821-medusa-reg.h b/drivers/staging/cx25821/cx25821-medusa-reg.h
new file mode 100644
index 00000000000..1c1c228352d
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-medusa-reg.h
@@ -0,0 +1,455 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __MEDUSA_REGISTERS__
24#define __MEDUSA_REGISTERS__
25
26/* Serial Slave Registers */
27#define HOST_REGISTER1 0x0000
28#define HOST_REGISTER2 0x0001
29
30/* Chip Configuration Registers */
31#define CHIP_CTRL 0x0100
32#define AFE_AB_CTRL 0x0104
33#define AFE_CD_CTRL 0x0108
34#define AFE_EF_CTRL 0x010C
35#define AFE_GH_CTRL 0x0110
36#define DENC_AB_CTRL 0x0114
37#define BYP_AB_CTRL 0x0118
38#define MON_A_CTRL 0x011C
39#define DISP_SEQ_A 0x0120
40#define DISP_SEQ_B 0x0124
41#define DISP_AB_CNT 0x0128
42#define DISP_CD_CNT 0x012C
43#define DISP_EF_CNT 0x0130
44#define DISP_GH_CNT 0x0134
45#define DISP_IJ_CNT 0x0138
46#define PIN_OE_CTRL 0x013C
47#define PIN_SPD_CTRL 0x0140
48#define PIN_SPD_CTRL2 0x0144
49#define IRQ_STAT_CTRL 0x0148
50#define POWER_CTRL_AB 0x014C
51#define POWER_CTRL_CD 0x0150
52#define POWER_CTRL_EF 0x0154
53#define POWER_CTRL_GH 0x0158
54#define TUNE_CTRL 0x015C
55#define BIAS_CTRL 0x0160
56#define AFE_AB_DIAG_CTRL 0x0164
57#define AFE_CD_DIAG_CTRL 0x0168
58#define AFE_EF_DIAG_CTRL 0x016C
59#define AFE_GH_DIAG_CTRL 0x0170
60#define PLL_AB_DIAG_CTRL 0x0174
61#define PLL_CD_DIAG_CTRL 0x0178
62#define PLL_EF_DIAG_CTRL 0x017C
63#define PLL_GH_DIAG_CTRL 0x0180
64#define TEST_CTRL 0x0184
65#define BIST_STAT 0x0188
66#define BIST_STAT2 0x018C
67#define BIST_VID_PLL_AB_STAT 0x0190
68#define BIST_VID_PLL_CD_STAT 0x0194
69#define BIST_VID_PLL_EF_STAT 0x0198
70#define BIST_VID_PLL_GH_STAT 0x019C
71#define DLL_DIAG_CTRL 0x01A0
72#define DEV_CH_ID_CTRL 0x01A4
73#define ABIST_CTRL_STATUS 0x01A8
74#define ABIST_FREQ 0x01AC
75#define ABIST_GOERT_SHIFT 0x01B0
76#define ABIST_COEF12 0x01B4
77#define ABIST_COEF34 0x01B8
78#define ABIST_COEF56 0x01BC
79#define ABIST_COEF7_SNR 0x01C0
80#define ABIST_ADC_CAL 0x01C4
81#define ABIST_BIN1_VGA0 0x01C8
82#define ABIST_BIN2_VGA1 0x01CC
83#define ABIST_BIN3_VGA2 0x01D0
84#define ABIST_BIN4_VGA3 0x01D4
85#define ABIST_BIN5_VGA4 0x01D8
86#define ABIST_BIN6_VGA5 0x01DC
87#define ABIST_BIN7_VGA6 0x0x1E0
88#define ABIST_CLAMP_A 0x0x1E4
89#define ABIST_CLAMP_B 0x0x1E8
90#define ABIST_CLAMP_C 0x01EC
91#define ABIST_CLAMP_D 0x01F0
92#define ABIST_CLAMP_E 0x01F4
93#define ABIST_CLAMP_F 0x01F8
94
95/* Digital Video Encoder A Registers */
96#define DENC_A_REG_1 0x0200
97#define DENC_A_REG_2 0x0204
98#define DENC_A_REG_3 0x0208
99#define DENC_A_REG_4 0x020C
100#define DENC_A_REG_5 0x0210
101#define DENC_A_REG_6 0x0214
102#define DENC_A_REG_7 0x0218
103#define DENC_A_REG_8 0x021C
104
105/* Digital Video Encoder B Registers */
106#define DENC_B_REG_1 0x0300
107#define DENC_B_REG_2 0x0304
108#define DENC_B_REG_3 0x0308
109#define DENC_B_REG_4 0x030C
110#define DENC_B_REG_5 0x0310
111#define DENC_B_REG_6 0x0314
112#define DENC_B_REG_7 0x0318
113#define DENC_B_REG_8 0x031C
114
115/* Video Decoder A Registers */
116#define MODE_CTRL 0x1000
117#define OUT_CTRL1 0x1004
118#define OUT_CTRL_NS 0x1008
119#define GEN_STAT 0x100C
120#define INT_STAT_MASK 0x1010
121#define LUMA_CTRL 0x1014
122#define CHROMA_CTRL 0x1018
123#define CRUSH_CTRL 0x101C
124#define HORIZ_TIM_CTRL 0x1020
125#define VERT_TIM_CTRL 0x1024
126#define MISC_TIM_CTRL 0x1028
127#define FIELD_COUNT 0x102C
128#define HSCALE_CTRL 0x1030
129#define VSCALE_CTRL 0x1034
130#define MAN_VGA_CTRL 0x1038
131#define MAN_AGC_CTRL 0x103C
132#define DFE_CTRL1 0x1040
133#define DFE_CTRL2 0x1044
134#define DFE_CTRL3 0x1048
135#define PLL_CTRL 0x104C
136#define PLL_CTRL_FAST 0x1050
137#define HTL_CTRL 0x1054
138#define SRC_CFG 0x1058
139#define SC_STEP_SIZE 0x105C
140#define SC_CONVERGE_CTRL 0x1060
141#define SC_LOOP_CTRL 0x1064
142#define COMB_2D_HFS_CFG 0x1068
143#define COMB_2D_HFD_CFG 0x106C
144#define COMB_2D_LF_CFG 0x1070
145#define COMB_2D_BLEND 0x1074
146#define COMB_MISC_CTRL 0x1078
147#define COMB_FLAT_THRESH_CTRL 0x107C
148#define COMB_TEST 0x1080
149#define BP_MISC_CTRL 0x1084
150#define VCR_DET_CTRL 0x1088
151#define NOISE_DET_CTRL 0x108C
152#define COMB_FLAT_NOISE_CTRL 0x1090
153#define VERSION 0x11F8
154#define SOFT_RST_CTRL 0x11FC
155
156/* Video Decoder B Registers */
157#define VDEC_B_MODE_CTRL 0x1200
158#define VDEC_B_OUT_CTRL1 0x1204
159#define VDEC_B_OUT_CTRL_NS 0x1208
160#define VDEC_B_GEN_STAT 0x120C
161#define VDEC_B_INT_STAT_MASK 0x1210
162#define VDEC_B_LUMA_CTRL 0x1214
163#define VDEC_B_CHROMA_CTRL 0x1218
164#define VDEC_B_CRUSH_CTRL 0x121C
165#define VDEC_B_HORIZ_TIM_CTRL 0x1220
166#define VDEC_B_VERT_TIM_CTRL 0x1224
167#define VDEC_B_MISC_TIM_CTRL 0x1228
168#define VDEC_B_FIELD_COUNT 0x122C
169#define VDEC_B_HSCALE_CTRL 0x1230
170#define VDEC_B_VSCALE_CTRL 0x1234
171#define VDEC_B_MAN_VGA_CTRL 0x1238
172#define VDEC_B_MAN_AGC_CTRL 0x123C
173#define VDEC_B_DFE_CTRL1 0x1240
174#define VDEC_B_DFE_CTRL2 0x1244
175#define VDEC_B_DFE_CTRL3 0x1248
176#define VDEC_B_PLL_CTRL 0x124C
177#define VDEC_B_PLL_CTRL_FAST 0x1250
178#define VDEC_B_HTL_CTRL 0x1254
179#define VDEC_B_SRC_CFG 0x1258
180#define VDEC_B_SC_STEP_SIZE 0x125C
181#define VDEC_B_SC_CONVERGE_CTRL 0x1260
182#define VDEC_B_SC_LOOP_CTRL 0x1264
183#define VDEC_B_COMB_2D_HFS_CFG 0x1268
184#define VDEC_B_COMB_2D_HFD_CFG 0x126C
185#define VDEC_B_COMB_2D_LF_CFG 0x1270
186#define VDEC_B_COMB_2D_BLEND 0x1274
187#define VDEC_B_COMB_MISC_CTRL 0x1278
188#define VDEC_B_COMB_FLAT_THRESH_CTRL 0x127C
189#define VDEC_B_COMB_TEST 0x1280
190#define VDEC_B_BP_MISC_CTRL 0x1284
191#define VDEC_B_VCR_DET_CTRL 0x1288
192#define VDEC_B_NOISE_DET_CTRL 0x128C
193#define VDEC_B_COMB_FLAT_NOISE_CTRL 0x1290
194#define VDEC_B_VERSION 0x13F8
195#define VDEC_B_SOFT_RST_CTRL 0x13FC
196
197/* Video Decoder C Registers */
198#define VDEC_C_MODE_CTRL 0x1400
199#define VDEC_C_OUT_CTRL1 0x1404
200#define VDEC_C_OUT_CTRL_NS 0x1408
201#define VDEC_C_GEN_STAT 0x140C
202#define VDEC_C_INT_STAT_MASK 0x1410
203#define VDEC_C_LUMA_CTRL 0x1414
204#define VDEC_C_CHROMA_CTRL 0x1418
205#define VDEC_C_CRUSH_CTRL 0x141C
206#define VDEC_C_HORIZ_TIM_CTRL 0x1420
207#define VDEC_C_VERT_TIM_CTRL 0x1424
208#define VDEC_C_MISC_TIM_CTRL 0x1428
209#define VDEC_C_FIELD_COUNT 0x142C
210#define VDEC_C_HSCALE_CTRL 0x1430
211#define VDEC_C_VSCALE_CTRL 0x1434
212#define VDEC_C_MAN_VGA_CTRL 0x1438
213#define VDEC_C_MAN_AGC_CTRL 0x143C
214#define VDEC_C_DFE_CTRL1 0x1440
215#define VDEC_C_DFE_CTRL2 0x1444
216#define VDEC_C_DFE_CTRL3 0x1448
217#define VDEC_C_PLL_CTRL 0x144C
218#define VDEC_C_PLL_CTRL_FAST 0x1450
219#define VDEC_C_HTL_CTRL 0x1454
220#define VDEC_C_SRC_CFG 0x1458
221#define VDEC_C_SC_STEP_SIZE 0x145C
222#define VDEC_C_SC_CONVERGE_CTRL 0x1460
223#define VDEC_C_SC_LOOP_CTRL 0x1464
224#define VDEC_C_COMB_2D_HFS_CFG 0x1468
225#define VDEC_C_COMB_2D_HFD_CFG 0x146C
226#define VDEC_C_COMB_2D_LF_CFG 0x1470
227#define VDEC_C_COMB_2D_BLEND 0x1474
228#define VDEC_C_COMB_MISC_CTRL 0x1478
229#define VDEC_C_COMB_FLAT_THRESH_CTRL 0x147C
230#define VDEC_C_COMB_TEST 0x1480
231#define VDEC_C_BP_MISC_CTRL 0x1484
232#define VDEC_C_VCR_DET_CTRL 0x1488
233#define VDEC_C_NOISE_DET_CTRL 0x148C
234#define VDEC_C_COMB_FLAT_NOISE_CTRL 0x1490
235#define VDEC_C_VERSION 0x15F8
236#define VDEC_C_SOFT_RST_CTRL 0x15FC
237
238/* Video Decoder D Registers */
239#define VDEC_D_MODE_CTRL 0x1600
240#define VDEC_D_OUT_CTRL1 0x1604
241#define VDEC_D_OUT_CTRL_NS 0x1608
242#define VDEC_D_GEN_STAT 0x160C
243#define VDEC_D_INT_STAT_MASK 0x1610
244#define VDEC_D_LUMA_CTRL 0x1614
245#define VDEC_D_CHROMA_CTRL 0x1618
246#define VDEC_D_CRUSH_CTRL 0x161C
247#define VDEC_D_HORIZ_TIM_CTRL 0x1620
248#define VDEC_D_VERT_TIM_CTRL 0x1624
249#define VDEC_D_MISC_TIM_CTRL 0x1628
250#define VDEC_D_FIELD_COUNT 0x162C
251#define VDEC_D_HSCALE_CTRL 0x1630
252#define VDEC_D_VSCALE_CTRL 0x1634
253#define VDEC_D_MAN_VGA_CTRL 0x1638
254#define VDEC_D_MAN_AGC_CTRL 0x163C
255#define VDEC_D_DFE_CTRL1 0x1640
256#define VDEC_D_DFE_CTRL2 0x1644
257#define VDEC_D_DFE_CTRL3 0x1648
258#define VDEC_D_PLL_CTRL 0x164C
259#define VDEC_D_PLL_CTRL_FAST 0x1650
260#define VDEC_D_HTL_CTRL 0x1654
261#define VDEC_D_SRC_CFG 0x1658
262#define VDEC_D_SC_STEP_SIZE 0x165C
263#define VDEC_D_SC_CONVERGE_CTRL 0x1660
264#define VDEC_D_SC_LOOP_CTRL 0x1664
265#define VDEC_D_COMB_2D_HFS_CFG 0x1668
266#define VDEC_D_COMB_2D_HFD_CFG 0x166C
267#define VDEC_D_COMB_2D_LF_CFG 0x1670
268#define VDEC_D_COMB_2D_BLEND 0x1674
269#define VDEC_D_COMB_MISC_CTRL 0x1678
270#define VDEC_D_COMB_FLAT_THRESH_CTRL 0x167C
271#define VDEC_D_COMB_TEST 0x1680
272#define VDEC_D_BP_MISC_CTRL 0x1684
273#define VDEC_D_VCR_DET_CTRL 0x1688
274#define VDEC_D_NOISE_DET_CTRL 0x168C
275#define VDEC_D_COMB_FLAT_NOISE_CTRL 0x1690
276#define VDEC_D_VERSION 0x17F8
277#define VDEC_D_SOFT_RST_CTRL 0x17FC
278
279/* Video Decoder E Registers */
280#define VDEC_E_MODE_CTRL 0x1800
281#define VDEC_E_OUT_CTRL1 0x1804
282#define VDEC_E_OUT_CTRL_NS 0x1808
283#define VDEC_E_GEN_STAT 0x180C
284#define VDEC_E_INT_STAT_MASK 0x1810
285#define VDEC_E_LUMA_CTRL 0x1814
286#define VDEC_E_CHROMA_CTRL 0x1818
287#define VDEC_E_CRUSH_CTRL 0x181C
288#define VDEC_E_HORIZ_TIM_CTRL 0x1820
289#define VDEC_E_VERT_TIM_CTRL 0x1824
290#define VDEC_E_MISC_TIM_CTRL 0x1828
291#define VDEC_E_FIELD_COUNT 0x182C
292#define VDEC_E_HSCALE_CTRL 0x1830
293#define VDEC_E_VSCALE_CTRL 0x1834
294#define VDEC_E_MAN_VGA_CTRL 0x1838
295#define VDEC_E_MAN_AGC_CTRL 0x183C
296#define VDEC_E_DFE_CTRL1 0x1840
297#define VDEC_E_DFE_CTRL2 0x1844
298#define VDEC_E_DFE_CTRL3 0x1848
299#define VDEC_E_PLL_CTRL 0x184C
300#define VDEC_E_PLL_CTRL_FAST 0x1850
301#define VDEC_E_HTL_CTRL 0x1854
302#define VDEC_E_SRC_CFG 0x1858
303#define VDEC_E_SC_STEP_SIZE 0x185C
304#define VDEC_E_SC_CONVERGE_CTRL 0x1860
305#define VDEC_E_SC_LOOP_CTRL 0x1864
306#define VDEC_E_COMB_2D_HFS_CFG 0x1868
307#define VDEC_E_COMB_2D_HFD_CFG 0x186C
308#define VDEC_E_COMB_2D_LF_CFG 0x1870
309#define VDEC_E_COMB_2D_BLEND 0x1874
310#define VDEC_E_COMB_MISC_CTRL 0x1878
311#define VDEC_E_COMB_FLAT_THRESH_CTRL 0x187C
312#define VDEC_E_COMB_TEST 0x1880
313#define VDEC_E_BP_MISC_CTRL 0x1884
314#define VDEC_E_VCR_DET_CTRL 0x1888
315#define VDEC_E_NOISE_DET_CTRL 0x188C
316#define VDEC_E_COMB_FLAT_NOISE_CTRL 0x1890
317#define VDEC_E_VERSION 0x19F8
318#define VDEC_E_SOFT_RST_CTRL 0x19FC
319
320/* Video Decoder F Registers */
321#define VDEC_F_MODE_CTRL 0x1A00
322#define VDEC_F_OUT_CTRL1 0x1A04
323#define VDEC_F_OUT_CTRL_NS 0x1A08
324#define VDEC_F_GEN_STAT 0x1A0C
325#define VDEC_F_INT_STAT_MASK 0x1A10
326#define VDEC_F_LUMA_CTRL 0x1A14
327#define VDEC_F_CHROMA_CTRL 0x1A18
328#define VDEC_F_CRUSH_CTRL 0x1A1C
329#define VDEC_F_HORIZ_TIM_CTRL 0x1A20
330#define VDEC_F_VERT_TIM_CTRL 0x1A24
331#define VDEC_F_MISC_TIM_CTRL 0x1A28
332#define VDEC_F_FIELD_COUNT 0x1A2C
333#define VDEC_F_HSCALE_CTRL 0x1A30
334#define VDEC_F_VSCALE_CTRL 0x1A34
335#define VDEC_F_MAN_VGA_CTRL 0x1A38
336#define VDEC_F_MAN_AGC_CTRL 0x1A3C
337#define VDEC_F_DFE_CTRL1 0x1A40
338#define VDEC_F_DFE_CTRL2 0x1A44
339#define VDEC_F_DFE_CTRL3 0x1A48
340#define VDEC_F_PLL_CTRL 0x1A4C
341#define VDEC_F_PLL_CTRL_FAST 0x1A50
342#define VDEC_F_HTL_CTRL 0x1A54
343#define VDEC_F_SRC_CFG 0x1A58
344#define VDEC_F_SC_STEP_SIZE 0x1A5C
345#define VDEC_F_SC_CONVERGE_CTRL 0x1A60
346#define VDEC_F_SC_LOOP_CTRL 0x1A64
347#define VDEC_F_COMB_2D_HFS_CFG 0x1A68
348#define VDEC_F_COMB_2D_HFD_CFG 0x1A6C
349#define VDEC_F_COMB_2D_LF_CFG 0x1A70
350#define VDEC_F_COMB_2D_BLEND 0x1A74
351#define VDEC_F_COMB_MISC_CTRL 0x1A78
352#define VDEC_F_COMB_FLAT_THRESH_CTRL 0x1A7C
353#define VDEC_F_COMB_TEST 0x1A80
354#define VDEC_F_BP_MISC_CTRL 0x1A84
355#define VDEC_F_VCR_DET_CTRL 0x1A88
356#define VDEC_F_NOISE_DET_CTRL 0x1A8C
357#define VDEC_F_COMB_FLAT_NOISE_CTRL 0x1A90
358#define VDEC_F_VERSION 0x1BF8
359#define VDEC_F_SOFT_RST_CTRL 0x1BFC
360
361/* Video Decoder G Registers */
362#define VDEC_G_MODE_CTRL 0x1C00
363#define VDEC_G_OUT_CTRL1 0x1C04
364#define VDEC_G_OUT_CTRL_NS 0x1C08
365#define VDEC_G_GEN_STAT 0x1C0C
366#define VDEC_G_INT_STAT_MASK 0x1C10
367#define VDEC_G_LUMA_CTRL 0x1C14
368#define VDEC_G_CHROMA_CTRL 0x1C18
369#define VDEC_G_CRUSH_CTRL 0x1C1C
370#define VDEC_G_HORIZ_TIM_CTRL 0x1C20
371#define VDEC_G_VERT_TIM_CTRL 0x1C24
372#define VDEC_G_MISC_TIM_CTRL 0x1C28
373#define VDEC_G_FIELD_COUNT 0x1C2C
374#define VDEC_G_HSCALE_CTRL 0x1C30
375#define VDEC_G_VSCALE_CTRL 0x1C34
376#define VDEC_G_MAN_VGA_CTRL 0x1C38
377#define VDEC_G_MAN_AGC_CTRL 0x1C3C
378#define VDEC_G_DFE_CTRL1 0x1C40
379#define VDEC_G_DFE_CTRL2 0x1C44
380#define VDEC_G_DFE_CTRL3 0x1C48
381#define VDEC_G_PLL_CTRL 0x1C4C
382#define VDEC_G_PLL_CTRL_FAST 0x1C50
383#define VDEC_G_HTL_CTRL 0x1C54
384#define VDEC_G_SRC_CFG 0x1C58
385#define VDEC_G_SC_STEP_SIZE 0x1C5C
386#define VDEC_G_SC_CONVERGE_CTRL 0x1C60
387#define VDEC_G_SC_LOOP_CTRL 0x1C64
388#define VDEC_G_COMB_2D_HFS_CFG 0x1C68
389#define VDEC_G_COMB_2D_HFD_CFG 0x1C6C
390#define VDEC_G_COMB_2D_LF_CFG 0x1C70
391#define VDEC_G_COMB_2D_BLEND 0x1C74
392#define VDEC_G_COMB_MISC_CTRL 0x1C78
393#define VDEC_G_COMB_FLAT_THRESH_CTRL 0x1C7C
394#define VDEC_G_COMB_TEST 0x1C80
395#define VDEC_G_BP_MISC_CTRL 0x1C84
396#define VDEC_G_VCR_DET_CTRL 0x1C88
397#define VDEC_G_NOISE_DET_CTRL 0x1C8C
398#define VDEC_G_COMB_FLAT_NOISE_CTRL 0x1C90
399#define VDEC_G_VERSION 0x1DF8
400#define VDEC_G_SOFT_RST_CTRL 0x1DFC
401
402/* Video Decoder H Registers */
403#define VDEC_H_MODE_CTRL 0x1E00
404#define VDEC_H_OUT_CTRL1 0x1E04
405#define VDEC_H_OUT_CTRL_NS 0x1E08
406#define VDEC_H_GEN_STAT 0x1E0C
407#define VDEC_H_INT_STAT_MASK 0x1E1E
408#define VDEC_H_LUMA_CTRL 0x1E14
409#define VDEC_H_CHROMA_CTRL 0x1E18
410#define VDEC_H_CRUSH_CTRL 0x1E1C
411#define VDEC_H_HORIZ_TIM_CTRL 0x1E20
412#define VDEC_H_VERT_TIM_CTRL 0x1E24
413#define VDEC_H_MISC_TIM_CTRL 0x1E28
414#define VDEC_H_FIELD_COUNT 0x1E2C
415#define VDEC_H_HSCALE_CTRL 0x1E30
416#define VDEC_H_VSCALE_CTRL 0x1E34
417#define VDEC_H_MAN_VGA_CTRL 0x1E38
418#define VDEC_H_MAN_AGC_CTRL 0x1E3C
419#define VDEC_H_DFE_CTRL1 0x1E40
420#define VDEC_H_DFE_CTRL2 0x1E44
421#define VDEC_H_DFE_CTRL3 0x1E48
422#define VDEC_H_PLL_CTRL 0x1E4C
423#define VDEC_H_PLL_CTRL_FAST 0x1E50
424#define VDEC_H_HTL_CTRL 0x1E54
425#define VDEC_H_SRC_CFG 0x1E58
426#define VDEC_H_SC_STEP_SIZE 0x1E5C
427#define VDEC_H_SC_CONVERGE_CTRL 0x1E60
428#define VDEC_H_SC_LOOP_CTRL 0x1E64
429#define VDEC_H_COMB_2D_HFS_CFG 0x1E68
430#define VDEC_H_COMB_2D_HFD_CFG 0x1E6C
431#define VDEC_H_COMB_2D_LF_CFG 0x1E70
432#define VDEC_H_COMB_2D_BLEND 0x1E74
433#define VDEC_H_COMB_MISC_CTRL 0x1E78
434#define VDEC_H_COMB_FLAT_THRESH_CTRL 0x1E7C
435#define VDEC_H_COMB_TEST 0x1E80
436#define VDEC_H_BP_MISC_CTRL 0x1E84
437#define VDEC_H_VCR_DET_CTRL 0x1E88
438#define VDEC_H_NOISE_DET_CTRL 0x1E8C
439#define VDEC_H_COMB_FLAT_NOISE_CTRL 0x1E90
440#define VDEC_H_VERSION 0x1FF8
441#define VDEC_H_SOFT_RST_CTRL 0x1FFC
442
443/*****************************************************************************/
444/* LUMA_CTRL register fields */
445#define VDEC_A_BRITE_CTRL 0x1014
446#define VDEC_A_CNTRST_CTRL 0x1015
447#define VDEC_A_PEAK_SEL 0x1016
448
449/*****************************************************************************/
450/* CHROMA_CTRL register fields */
451#define VDEC_A_USAT_CTRL 0x1018
452#define VDEC_A_VSAT_CTRL 0x1019
453#define VDEC_A_HUE_CTRL 0x101A
454
455#endif
diff --git a/drivers/staging/cx25821/cx25821-medusa-video.c b/drivers/staging/cx25821/cx25821-medusa-video.c
new file mode 100644
index 00000000000..fc780d0908d
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-medusa-video.c
@@ -0,0 +1,872 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24
25#include "cx25821.h"
26#include "cx25821-medusa-video.h"
27#include "cx25821-biffuncs.h"
28
29/*
30 * medusa_enable_bluefield_output()
31 *
32 * Enable the generation of blue filed output if no video
33 *
34 */
35static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
36 int enable)
37{
38 int ret_val = 1;
39 u32 value = 0;
40 u32 tmp = 0;
41 int out_ctrl = OUT_CTRL1;
42 int out_ctrl_ns = OUT_CTRL_NS;
43
44 switch (channel) {
45 default:
46 case VDEC_A:
47 break;
48 case VDEC_B:
49 out_ctrl = VDEC_B_OUT_CTRL1;
50 out_ctrl_ns = VDEC_B_OUT_CTRL_NS;
51 break;
52 case VDEC_C:
53 out_ctrl = VDEC_C_OUT_CTRL1;
54 out_ctrl_ns = VDEC_C_OUT_CTRL_NS;
55 break;
56 case VDEC_D:
57 out_ctrl = VDEC_D_OUT_CTRL1;
58 out_ctrl_ns = VDEC_D_OUT_CTRL_NS;
59 break;
60 case VDEC_E:
61 out_ctrl = VDEC_E_OUT_CTRL1;
62 out_ctrl_ns = VDEC_E_OUT_CTRL_NS;
63 return;
64 case VDEC_F:
65 out_ctrl = VDEC_F_OUT_CTRL1;
66 out_ctrl_ns = VDEC_F_OUT_CTRL_NS;
67 return;
68 case VDEC_G:
69 out_ctrl = VDEC_G_OUT_CTRL1;
70 out_ctrl_ns = VDEC_G_OUT_CTRL_NS;
71 return;
72 case VDEC_H:
73 out_ctrl = VDEC_H_OUT_CTRL1;
74 out_ctrl_ns = VDEC_H_OUT_CTRL_NS;
75 return;
76 }
77
78 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp);
79 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */
80 if (enable)
81 value |= 0x00000080; /* set BLUE_FIELD_EN */
82 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value);
83
84 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp);
85 value &= 0xFFFFFF7F;
86 if (enable)
87 value |= 0x00000080; /* set BLUE_FIELD_EN */
88 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value);
89}
90
91static int medusa_initialize_ntsc(struct cx25821_dev *dev)
92{
93 int ret_val = 0;
94 int i = 0;
95 u32 value = 0;
96 u32 tmp = 0;
97
98 mutex_lock(&dev->lock);
99
100 for (i = 0; i < MAX_DECODERS; i++) {
101 /* set video format NTSC-M */
102 value =
103 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
104 &tmp);
105 value &= 0xFFFFFFF0;
106 /* enable the fast locking mode bit[16] */
107 value |= 0x10001;
108 ret_val =
109 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
110 value);
111
112 /* resolution NTSC 720x480 */
113 value =
114 cx25821_i2c_read(&dev->i2c_bus[0],
115 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
116 value &= 0x00C00C00;
117 value |= 0x612D0074;
118 ret_val =
119 cx25821_i2c_write(&dev->i2c_bus[0],
120 HORIZ_TIM_CTRL + (0x200 * i), value);
121
122 value =
123 cx25821_i2c_read(&dev->i2c_bus[0],
124 VERT_TIM_CTRL + (0x200 * i), &tmp);
125 value &= 0x00C00C00;
126 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */
127 ret_val =
128 cx25821_i2c_write(&dev->i2c_bus[0],
129 VERT_TIM_CTRL + (0x200 * i), value);
130
131 /* chroma subcarrier step size */
132 ret_val =
133 cx25821_i2c_write(&dev->i2c_bus[0],
134 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
135
136 /* enable VIP optional active */
137 value =
138 cx25821_i2c_read(&dev->i2c_bus[0],
139 OUT_CTRL_NS + (0x200 * i), &tmp);
140 value &= 0xFFFBFFFF;
141 value |= 0x00040000;
142 ret_val =
143 cx25821_i2c_write(&dev->i2c_bus[0],
144 OUT_CTRL_NS + (0x200 * i), value);
145
146 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
147 value =
148 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
149 &tmp);
150 value &= 0xFFFBFFFF;
151 value |= 0x00040000;
152 ret_val =
153 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
154 value);
155
156 /*
157 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
158 * when the input switching rate < 16 fields
159 */
160 value =
161 cx25821_i2c_read(&dev->i2c_bus[0],
162 MISC_TIM_CTRL + (0x200 * i), &tmp);
163 /* disable special play detection */
164 value = setBitAtPos(value, 14);
165 value = clearBitAtPos(value, 15);
166 ret_val =
167 cx25821_i2c_write(&dev->i2c_bus[0],
168 MISC_TIM_CTRL + (0x200 * i), value);
169
170 /* set vbi_gate_en to 0 */
171 value =
172 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
173 &tmp);
174 value = clearBitAtPos(value, 29);
175 ret_val =
176 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
177 value);
178
179 /* Enable the generation of blue field output if no video */
180 medusa_enable_bluefield_output(dev, i, 1);
181 }
182
183 for (i = 0; i < MAX_ENCODERS; i++) {
184 /* NTSC hclock */
185 value =
186 cx25821_i2c_read(&dev->i2c_bus[0],
187 DENC_A_REG_1 + (0x100 * i), &tmp);
188 value &= 0xF000FC00;
189 value |= 0x06B402D0;
190 ret_val =
191 cx25821_i2c_write(&dev->i2c_bus[0],
192 DENC_A_REG_1 + (0x100 * i), value);
193
194 /* burst begin and burst end */
195 value =
196 cx25821_i2c_read(&dev->i2c_bus[0],
197 DENC_A_REG_2 + (0x100 * i), &tmp);
198 value &= 0xFF000000;
199 value |= 0x007E9054;
200 ret_val =
201 cx25821_i2c_write(&dev->i2c_bus[0],
202 DENC_A_REG_2 + (0x100 * i), value);
203
204 value =
205 cx25821_i2c_read(&dev->i2c_bus[0],
206 DENC_A_REG_3 + (0x100 * i), &tmp);
207 value &= 0xFC00FE00;
208 value |= 0x00EC00F0;
209 ret_val =
210 cx25821_i2c_write(&dev->i2c_bus[0],
211 DENC_A_REG_3 + (0x100 * i), value);
212
213 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */
214 value =
215 cx25821_i2c_read(&dev->i2c_bus[0],
216 DENC_A_REG_4 + (0x100 * i), &tmp);
217 value &= 0x00FCFFFF;
218 value |= 0x13020000;
219 ret_val =
220 cx25821_i2c_write(&dev->i2c_bus[0],
221 DENC_A_REG_4 + (0x100 * i), value);
222
223 value =
224 cx25821_i2c_read(&dev->i2c_bus[0],
225 DENC_A_REG_5 + (0x100 * i), &tmp);
226 value &= 0xFFFF0000;
227 value |= 0x0000E575;
228 ret_val =
229 cx25821_i2c_write(&dev->i2c_bus[0],
230 DENC_A_REG_5 + (0x100 * i), value);
231
232 ret_val =
233 cx25821_i2c_write(&dev->i2c_bus[0],
234 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
235
236 /* Subcarrier Increment */
237 ret_val =
238 cx25821_i2c_write(&dev->i2c_bus[0],
239 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
240 }
241
242 /* set picture resolutions */
243 /* 0 - 720 */
244 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
245 /* 0 - 480 */
246 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
247
248 /* set Bypass input format to NTSC 525 lines */
249 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
250 value |= 0x00080200;
251 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
252
253 mutex_unlock(&dev->lock);
254
255 return ret_val;
256}
257
258static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
259{
260 int ret_val = -1;
261 u32 value = 0, tmp = 0;
262
263 /* Setup for 2D threshold */
264 ret_val =
265 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFS_CFG + (0x200 * dec),
266 0x20002861);
267 ret_val =
268 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_HFD_CFG + (0x200 * dec),
269 0x20002861);
270 ret_val =
271 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_LF_CFG + (0x200 * dec),
272 0x200A1023);
273
274 /* Setup flat chroma and luma thresholds */
275 value =
276 cx25821_i2c_read(&dev->i2c_bus[0],
277 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
278 value &= 0x06230000;
279 ret_val =
280 cx25821_i2c_write(&dev->i2c_bus[0],
281 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
282
283 /* set comb 2D blend */
284 ret_val =
285 cx25821_i2c_write(&dev->i2c_bus[0], COMB_2D_BLEND + (0x200 * dec),
286 0x210F0F0F);
287
288 /* COMB MISC CONTROL */
289 ret_val =
290 cx25821_i2c_write(&dev->i2c_bus[0], COMB_MISC_CTRL + (0x200 * dec),
291 0x41120A7F);
292
293 return ret_val;
294}
295
296static int medusa_initialize_pal(struct cx25821_dev *dev)
297{
298 int ret_val = 0;
299 int i = 0;
300 u32 value = 0;
301 u32 tmp = 0;
302
303 mutex_lock(&dev->lock);
304
305 for (i = 0; i < MAX_DECODERS; i++) {
306 /* set video format PAL-BDGHI */
307 value =
308 cx25821_i2c_read(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
309 &tmp);
310 value &= 0xFFFFFFF0;
311 /* enable the fast locking mode bit[16] */
312 value |= 0x10004;
313 ret_val =
314 cx25821_i2c_write(&dev->i2c_bus[0], MODE_CTRL + (0x200 * i),
315 value);
316
317 /* resolution PAL 720x576 */
318 value =
319 cx25821_i2c_read(&dev->i2c_bus[0],
320 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
321 value &= 0x00C00C00;
322 value |= 0x632D007D;
323 ret_val =
324 cx25821_i2c_write(&dev->i2c_bus[0],
325 HORIZ_TIM_CTRL + (0x200 * i), value);
326
327 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */
328 value =
329 cx25821_i2c_read(&dev->i2c_bus[0],
330 VERT_TIM_CTRL + (0x200 * i), &tmp);
331 value &= 0x00C00C00;
332 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */
333 ret_val =
334 cx25821_i2c_write(&dev->i2c_bus[0],
335 VERT_TIM_CTRL + (0x200 * i), value);
336
337 /* chroma subcarrier step size */
338 ret_val =
339 cx25821_i2c_write(&dev->i2c_bus[0],
340 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
341
342 /* enable VIP optional active */
343 value =
344 cx25821_i2c_read(&dev->i2c_bus[0],
345 OUT_CTRL_NS + (0x200 * i), &tmp);
346 value &= 0xFFFBFFFF;
347 value |= 0x00040000;
348 ret_val =
349 cx25821_i2c_write(&dev->i2c_bus[0],
350 OUT_CTRL_NS + (0x200 * i), value);
351
352 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
353 value =
354 cx25821_i2c_read(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
355 &tmp);
356 value &= 0xFFFBFFFF;
357 value |= 0x00040000;
358 ret_val =
359 cx25821_i2c_write(&dev->i2c_bus[0], OUT_CTRL1 + (0x200 * i),
360 value);
361
362 /*
363 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
364 * when the input switching rate < 16 fields
365 */
366 value =
367 cx25821_i2c_read(&dev->i2c_bus[0],
368 MISC_TIM_CTRL + (0x200 * i), &tmp);
369 /* disable special play detection */
370 value = setBitAtPos(value, 14);
371 value = clearBitAtPos(value, 15);
372 ret_val =
373 cx25821_i2c_write(&dev->i2c_bus[0],
374 MISC_TIM_CTRL + (0x200 * i), value);
375
376 /* set vbi_gate_en to 0 */
377 value =
378 cx25821_i2c_read(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
379 &tmp);
380 value = clearBitAtPos(value, 29);
381 ret_val =
382 cx25821_i2c_write(&dev->i2c_bus[0], DFE_CTRL1 + (0x200 * i),
383 value);
384
385 medusa_PALCombInit(dev, i);
386
387 /* Enable the generation of blue field output if no video */
388 medusa_enable_bluefield_output(dev, i, 1);
389 }
390
391 for (i = 0; i < MAX_ENCODERS; i++) {
392 /* PAL hclock */
393 value =
394 cx25821_i2c_read(&dev->i2c_bus[0],
395 DENC_A_REG_1 + (0x100 * i), &tmp);
396 value &= 0xF000FC00;
397 value |= 0x06C002D0;
398 ret_val =
399 cx25821_i2c_write(&dev->i2c_bus[0],
400 DENC_A_REG_1 + (0x100 * i), value);
401
402 /* burst begin and burst end */
403 value =
404 cx25821_i2c_read(&dev->i2c_bus[0],
405 DENC_A_REG_2 + (0x100 * i), &tmp);
406 value &= 0xFF000000;
407 value |= 0x007E9754;
408 ret_val =
409 cx25821_i2c_write(&dev->i2c_bus[0],
410 DENC_A_REG_2 + (0x100 * i), value);
411
412 /* hblank and vactive */
413 value =
414 cx25821_i2c_read(&dev->i2c_bus[0],
415 DENC_A_REG_3 + (0x100 * i), &tmp);
416 value &= 0xFC00FE00;
417 value |= 0x00FC0120;
418 ret_val =
419 cx25821_i2c_write(&dev->i2c_bus[0],
420 DENC_A_REG_3 + (0x100 * i), value);
421
422 /* set PAL vblank, phase alternation, 0 IRE pedestal */
423 value =
424 cx25821_i2c_read(&dev->i2c_bus[0],
425 DENC_A_REG_4 + (0x100 * i), &tmp);
426 value &= 0x00FCFFFF;
427 value |= 0x14010000;
428 ret_val =
429 cx25821_i2c_write(&dev->i2c_bus[0],
430 DENC_A_REG_4 + (0x100 * i), value);
431
432 value =
433 cx25821_i2c_read(&dev->i2c_bus[0],
434 DENC_A_REG_5 + (0x100 * i), &tmp);
435 value &= 0xFFFF0000;
436 value |= 0x0000F078;
437 ret_val =
438 cx25821_i2c_write(&dev->i2c_bus[0],
439 DENC_A_REG_5 + (0x100 * i), value);
440
441 ret_val =
442 cx25821_i2c_write(&dev->i2c_bus[0],
443 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
444
445 /* Subcarrier Increment */
446 ret_val =
447 cx25821_i2c_write(&dev->i2c_bus[0],
448 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
449 }
450
451 /* set picture resolutions */
452 /* 0 - 720 */
453 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
454 /* 0 - 576 */
455 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
456
457 /* set Bypass input format to PAL 625 lines */
458 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
459 value &= 0xFFF7FDFF;
460 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
461
462 mutex_unlock(&dev->lock);
463
464 return ret_val;
465}
466
467int medusa_set_videostandard(struct cx25821_dev *dev)
468{
469 int status = STATUS_SUCCESS;
470 u32 value = 0, tmp = 0;
471
472 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
473 status = medusa_initialize_pal(dev);
474 else
475 status = medusa_initialize_ntsc(dev);
476
477 /* Enable DENC_A output */
478 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp);
479 value = setBitAtPos(value, 4);
480 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value);
481
482 /* Enable DENC_B output */
483 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp);
484 value = setBitAtPos(value, 4);
485 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
486
487 return status;
488}
489
490void medusa_set_resolution(struct cx25821_dev *dev, int width,
491 int decoder_select)
492{
493 int decoder = 0;
494 int decoder_count = 0;
495 int ret_val = 0;
496 u32 hscale = 0x0;
497 u32 vscale = 0x0;
498 const int MAX_WIDTH = 720;
499
500 mutex_lock(&dev->lock);
501
502 /* validate the width - cannot be negative */
503 if (width > MAX_WIDTH) {
504 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n",
505 __func__, width, MAX_WIDTH);
506 width = MAX_WIDTH;
507 }
508
509 if (decoder_select <= 7 && decoder_select >= 0) {
510 decoder = decoder_select;
511 decoder_count = decoder_select + 1;
512 } else {
513 decoder = 0;
514 decoder_count = _num_decoders;
515 }
516
517 switch (width) {
518 case 320:
519 hscale = 0x13E34B;
520 vscale = 0x0;
521 break;
522
523 case 352:
524 hscale = 0x10A273;
525 vscale = 0x0;
526 break;
527
528 case 176:
529 hscale = 0x3115B2;
530 vscale = 0x1E00;
531 break;
532
533 case 160:
534 hscale = 0x378D84;
535 vscale = 0x1E00;
536 break;
537
538 default: /* 720 */
539 hscale = 0x0;
540 vscale = 0x0;
541 break;
542 }
543
544 for (; decoder < decoder_count; decoder++) {
545 /* write scaling values for each decoder */
546 ret_val =
547 cx25821_i2c_write(&dev->i2c_bus[0],
548 HSCALE_CTRL + (0x200 * decoder), hscale);
549 ret_val =
550 cx25821_i2c_write(&dev->i2c_bus[0],
551 VSCALE_CTRL + (0x200 * decoder), vscale);
552 }
553
554 mutex_unlock(&dev->lock);
555}
556
557static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
558 int duration)
559{
560 int ret_val = 0;
561 u32 fld_cnt = 0;
562 u32 tmp = 0;
563 u32 disp_cnt_reg = DISP_AB_CNT;
564
565 mutex_lock(&dev->lock);
566
567 /* no support */
568 if (decoder < VDEC_A && decoder > VDEC_H) {
569 mutex_unlock(&dev->lock);
570 return;
571 }
572
573 switch (decoder) {
574 default:
575 break;
576 case VDEC_C:
577 case VDEC_D:
578 disp_cnt_reg = DISP_CD_CNT;
579 break;
580 case VDEC_E:
581 case VDEC_F:
582 disp_cnt_reg = DISP_EF_CNT;
583 break;
584 case VDEC_G:
585 case VDEC_H:
586 disp_cnt_reg = DISP_GH_CNT;
587 break;
588 }
589
590 _display_field_cnt[decoder] = duration;
591
592 /* update hardware */
593 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
594
595 if (!(decoder % 2)) { /* EVEN decoder */
596 fld_cnt &= 0xFFFF0000;
597 fld_cnt |= duration;
598 } else {
599 fld_cnt &= 0x0000FFFF;
600 fld_cnt |= ((u32) duration) << 16;
601 }
602
603 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt);
604
605 mutex_unlock(&dev->lock);
606}
607
608/* Map to Medusa register setting */
609static int mapM(int srcMin,
610 int srcMax, int srcVal, int dstMin, int dstMax, int *dstVal)
611{
612 int numerator;
613 int denominator;
614 int quotient;
615
616 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax))
617 return -1;
618 /*
619 * This is the overall expression used:
620 * *dstVal =
621 * (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin;
622 * but we need to account for rounding so below we use the modulus
623 * operator to find the remainder and increment if necessary.
624 */
625 numerator = (srcVal - srcMin) * (dstMax - dstMin);
626 denominator = srcMax - srcMin;
627 quotient = numerator / denominator;
628
629 if (2 * (numerator % denominator) >= denominator)
630 quotient++;
631
632 *dstVal = quotient + dstMin;
633
634 return 0;
635}
636
637static unsigned long convert_to_twos(long numeric, unsigned long bits_len)
638{
639 unsigned char temp;
640
641 if (numeric >= 0)
642 return numeric;
643 else {
644 temp = ~(abs(numeric) & 0xFF);
645 temp += 1;
646 return temp;
647 }
648}
649
650int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
651{
652 int ret_val = 0;
653 int value = 0;
654 u32 val = 0, tmp = 0;
655
656 mutex_lock(&dev->lock);
657 if ((brightness > VIDEO_PROCAMP_MAX)
658 || (brightness < VIDEO_PROCAMP_MIN)) {
659 mutex_unlock(&dev->lock);
660 return -1;
661 }
662 ret_val =
663 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness,
664 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
665 value = convert_to_twos(value, 8);
666 val =
667 cx25821_i2c_read(&dev->i2c_bus[0],
668 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
669 val &= 0xFFFFFF00;
670 ret_val |=
671 cx25821_i2c_write(&dev->i2c_bus[0],
672 VDEC_A_BRITE_CTRL + (0x200 * decoder),
673 val | value);
674 mutex_unlock(&dev->lock);
675 return ret_val;
676}
677
678int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
679{
680 int ret_val = 0;
681 int value = 0;
682 u32 val = 0, tmp = 0;
683
684 mutex_lock(&dev->lock);
685
686 if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) {
687 mutex_unlock(&dev->lock);
688 return -1;
689 }
690
691 ret_val =
692 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast,
693 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
694 val =
695 cx25821_i2c_read(&dev->i2c_bus[0],
696 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
697 val &= 0xFFFFFF00;
698 ret_val |=
699 cx25821_i2c_write(&dev->i2c_bus[0],
700 VDEC_A_CNTRST_CTRL + (0x200 * decoder),
701 val | value);
702
703 mutex_unlock(&dev->lock);
704 return ret_val;
705}
706
707int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
708{
709 int ret_val = 0;
710 int value = 0;
711 u32 val = 0, tmp = 0;
712
713 mutex_lock(&dev->lock);
714
715 if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) {
716 mutex_unlock(&dev->lock);
717 return -1;
718 }
719
720 ret_val =
721 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue, SIGNED_BYTE_MIN,
722 SIGNED_BYTE_MAX, &value);
723
724 value = convert_to_twos(value, 8);
725 val =
726 cx25821_i2c_read(&dev->i2c_bus[0],
727 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
728 val &= 0xFFFFFF00;
729
730 ret_val |=
731 cx25821_i2c_write(&dev->i2c_bus[0],
732 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
733
734 mutex_unlock(&dev->lock);
735 return ret_val;
736}
737
738int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
739{
740 int ret_val = 0;
741 int value = 0;
742 u32 val = 0, tmp = 0;
743
744 mutex_lock(&dev->lock);
745
746 if ((saturation > VIDEO_PROCAMP_MAX)
747 || (saturation < VIDEO_PROCAMP_MIN)) {
748 mutex_unlock(&dev->lock);
749 return -1;
750 }
751
752 ret_val =
753 mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation,
754 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
755
756 val =
757 cx25821_i2c_read(&dev->i2c_bus[0],
758 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
759 val &= 0xFFFFFF00;
760 ret_val |=
761 cx25821_i2c_write(&dev->i2c_bus[0],
762 VDEC_A_USAT_CTRL + (0x200 * decoder),
763 val | value);
764
765 val =
766 cx25821_i2c_read(&dev->i2c_bus[0],
767 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
768 val &= 0xFFFFFF00;
769 ret_val |=
770 cx25821_i2c_write(&dev->i2c_bus[0],
771 VDEC_A_VSAT_CTRL + (0x200 * decoder),
772 val | value);
773
774 mutex_unlock(&dev->lock);
775 return ret_val;
776}
777
778/* Program the display sequence and monitor output. */
779
780int medusa_video_init(struct cx25821_dev *dev)
781{
782 u32 value = 0, tmp = 0;
783 int ret_val = 0;
784 int i = 0;
785
786 mutex_lock(&dev->lock);
787
788 _num_decoders = dev->_max_num_decoders;
789
790 /* disable Auto source selection on all video decoders */
791 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
792 value &= 0xFFFFF0FF;
793 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
794
795 if (ret_val < 0)
796 goto error;
797
798 /* Turn off Master source switch enable */
799 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
800 value &= 0xFFFFFFDF;
801 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
802
803 if (ret_val < 0)
804 goto error;
805
806 mutex_unlock(&dev->lock);
807
808 for (i = 0; i < _num_decoders; i++)
809 medusa_set_decoderduration(dev, i, _display_field_cnt[i]);
810
811 mutex_lock(&dev->lock);
812
813 /* Select monitor as DENC A input, power up the DAC */
814 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
815 value &= 0xFF70FF70;
816 value |= 0x00090008; /* set en_active */
817 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
818
819 if (ret_val < 0)
820 goto error;
821
822 /* enable input is VIP/656 */
823 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
824 value |= 0x00040100; /* enable VIP */
825 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
826
827 if (ret_val < 0)
828 goto error;
829
830 /* select AFE clock to output mode */
831 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
832 value &= 0x83FFFFFF;
833 ret_val =
834 cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL,
835 value | 0x10000000);
836
837 if (ret_val < 0)
838 goto error;
839
840 /* Turn on all of the data out and control output pins. */
841 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
842 value &= 0xFEF0FE00;
843 if (_num_decoders == MAX_DECODERS) {
844 /*
845 * Note: The octal board does not support control pins(bit16-19)
846 * These bits are ignored in the octal board.
847 *
848 * disable VDEC A-C port, default to Mobilygen Interface
849 */
850 value |= 0x010001F8;
851 } else {
852 /* disable VDEC A-C port, default to Mobilygen Interface */
853 value |= 0x010F0108;
854 }
855
856 value |= 7;
857 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value);
858
859 if (ret_val < 0)
860 goto error;
861
862
863 mutex_unlock(&dev->lock);
864
865 ret_val = medusa_set_videostandard(dev);
866
867 return ret_val;
868
869error:
870 mutex_unlock(&dev->lock);
871 return ret_val;
872}
diff --git a/drivers/staging/cx25821/cx25821-medusa-video.h b/drivers/staging/cx25821/cx25821-medusa-video.h
new file mode 100644
index 00000000000..6175e096185
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-medusa-video.h
@@ -0,0 +1,49 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _MEDUSA_VIDEO_H
24#define _MEDUSA_VIDEO_H
25
26#include "cx25821-medusa-defines.h"
27
28/* Color control constants */
29#define VIDEO_PROCAMP_MIN 0
30#define VIDEO_PROCAMP_MAX 10000
31#define UNSIGNED_BYTE_MIN 0
32#define UNSIGNED_BYTE_MAX 0xFF
33#define SIGNED_BYTE_MIN -128
34#define SIGNED_BYTE_MAX 127
35
36/* Default video color settings */
37#define SHARPNESS_DEFAULT 50
38#define SATURATION_DEFAULT 5000
39#define BRIGHTNESS_DEFAULT 6200
40#define CONTRAST_DEFAULT 5000
41#define HUE_DEFAULT 5000
42
43unsigned short _num_decoders;
44unsigned short _num_cameras;
45
46unsigned int _video_standard;
47int _display_field_cnt[MAX_DECODERS];
48
49#endif
diff --git a/drivers/staging/cx25821/cx25821-reg.h b/drivers/staging/cx25821/cx25821-reg.h
new file mode 100644
index 00000000000..a3fc25a4dc0
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-reg.h
@@ -0,0 +1,1592 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __CX25821_REGISTERS__
24#define __CX25821_REGISTERS__
25
26/* Risc Instructions */
27#define RISC_CNT_INC 0x00010000
28#define RISC_CNT_RESET 0x00030000
29#define RISC_IRQ1 0x01000000
30#define RISC_IRQ2 0x02000000
31#define RISC_EOL 0x04000000
32#define RISC_SOL 0x08000000
33#define RISC_WRITE 0x10000000
34#define RISC_SKIP 0x20000000
35#define RISC_JUMP 0x70000000
36#define RISC_SYNC 0x80000000
37#define RISC_RESYNC 0x80008000
38#define RISC_READ 0x90000000
39#define RISC_WRITERM 0xB0000000
40#define RISC_WRITECM 0xC0000000
41#define RISC_WRITECR 0xD0000000
42#define RISC_WRITEC 0x50000000
43#define RISC_READC 0xA0000000
44
45#define RISC_SYNC_ODD 0x00000000
46#define RISC_SYNC_EVEN 0x00000200
47#define RISC_SYNC_ODD_VBI 0x00000006
48#define RISC_SYNC_EVEN_VBI 0x00000207
49#define RISC_NOOP 0xF0000000
50
51/*****************************************************************************
52* ASB SRAM
53 *****************************************************************************/
54#define TX_SRAM 0x000000 /* Transmit SRAM */
55
56/*****************************************************************************/
57#define RX_RAM 0x010000 /* Receive SRAM */
58
59/*****************************************************************************
60* Application Layer (AL)
61 *****************************************************************************/
62#define DEV_CNTRL2 0x040000 /* Device control */
63#define FLD_RUN_RISC 0x00000020
64
65/* ***************************************************************************** */
66#define PCI_INT_MSK 0x040010 /* PCI interrupt mask */
67#define PCI_INT_STAT 0x040014 /* PCI interrupt status */
68#define PCI_INT_MSTAT 0x040018 /* PCI interrupt masked status */
69#define FLD_HAMMERHEAD_INT (1 << 27)
70#define FLD_UART_INT (1 << 26)
71#define FLD_IRQN_INT (1 << 25)
72#define FLD_TM_INT (1 << 28)
73#define FLD_I2C_3_RACK (1 << 27)
74#define FLD_I2C_3_INT (1 << 26)
75#define FLD_I2C_2_RACK (1 << 25)
76#define FLD_I2C_2_INT (1 << 24)
77#define FLD_I2C_1_RACK (1 << 23)
78#define FLD_I2C_1_INT (1 << 22)
79
80#define FLD_APB_DMA_BERR_INT (1 << 21)
81#define FLD_AL_WR_BERR_INT (1 << 20)
82#define FLD_AL_RD_BERR_INT (1 << 19)
83#define FLD_RISC_WR_BERR_INT (1 << 18)
84#define FLD_RISC_RD_BERR_INT (1 << 17)
85
86#define FLD_VID_I_INT (1 << 8)
87#define FLD_VID_H_INT (1 << 7)
88#define FLD_VID_G_INT (1 << 6)
89#define FLD_VID_F_INT (1 << 5)
90#define FLD_VID_E_INT (1 << 4)
91#define FLD_VID_D_INT (1 << 3)
92#define FLD_VID_C_INT (1 << 2)
93#define FLD_VID_B_INT (1 << 1)
94#define FLD_VID_A_INT (1 << 0)
95
96/* ***************************************************************************** */
97#define VID_A_INT_MSK 0x040020 /* Video A interrupt mask */
98#define VID_A_INT_STAT 0x040024 /* Video A interrupt status */
99#define VID_A_INT_MSTAT 0x040028 /* Video A interrupt masked status */
100#define VID_A_INT_SSTAT 0x04002C /* Video A interrupt set status */
101
102/* ***************************************************************************** */
103#define VID_B_INT_MSK 0x040030 /* Video B interrupt mask */
104#define VID_B_INT_STAT 0x040034 /* Video B interrupt status */
105#define VID_B_INT_MSTAT 0x040038 /* Video B interrupt masked status */
106#define VID_B_INT_SSTAT 0x04003C /* Video B interrupt set status */
107
108/* ***************************************************************************** */
109#define VID_C_INT_MSK 0x040040 /* Video C interrupt mask */
110#define VID_C_INT_STAT 0x040044 /* Video C interrupt status */
111#define VID_C_INT_MSTAT 0x040048 /* Video C interrupt masked status */
112#define VID_C_INT_SSTAT 0x04004C /* Video C interrupt set status */
113
114/* ***************************************************************************** */
115#define VID_D_INT_MSK 0x040050 /* Video D interrupt mask */
116#define VID_D_INT_STAT 0x040054 /* Video D interrupt status */
117#define VID_D_INT_MSTAT 0x040058 /* Video D interrupt masked status */
118#define VID_D_INT_SSTAT 0x04005C /* Video D interrupt set status */
119
120/* ***************************************************************************** */
121#define VID_E_INT_MSK 0x040060 /* Video E interrupt mask */
122#define VID_E_INT_STAT 0x040064 /* Video E interrupt status */
123#define VID_E_INT_MSTAT 0x040068 /* Video E interrupt masked status */
124#define VID_E_INT_SSTAT 0x04006C /* Video E interrupt set status */
125
126/* ***************************************************************************** */
127#define VID_F_INT_MSK 0x040070 /* Video F interrupt mask */
128#define VID_F_INT_STAT 0x040074 /* Video F interrupt status */
129#define VID_F_INT_MSTAT 0x040078 /* Video F interrupt masked status */
130#define VID_F_INT_SSTAT 0x04007C /* Video F interrupt set status */
131
132/* ***************************************************************************** */
133#define VID_G_INT_MSK 0x040080 /* Video G interrupt mask */
134#define VID_G_INT_STAT 0x040084 /* Video G interrupt status */
135#define VID_G_INT_MSTAT 0x040088 /* Video G interrupt masked status */
136#define VID_G_INT_SSTAT 0x04008C /* Video G interrupt set status */
137
138/* ***************************************************************************** */
139#define VID_H_INT_MSK 0x040090 /* Video H interrupt mask */
140#define VID_H_INT_STAT 0x040094 /* Video H interrupt status */
141#define VID_H_INT_MSTAT 0x040098 /* Video H interrupt masked status */
142#define VID_H_INT_SSTAT 0x04009C /* Video H interrupt set status */
143
144/* ***************************************************************************** */
145#define VID_I_INT_MSK 0x0400A0 /* Video I interrupt mask */
146#define VID_I_INT_STAT 0x0400A4 /* Video I interrupt status */
147#define VID_I_INT_MSTAT 0x0400A8 /* Video I interrupt masked status */
148#define VID_I_INT_SSTAT 0x0400AC /* Video I interrupt set status */
149
150/* ***************************************************************************** */
151#define VID_J_INT_MSK 0x0400B0 /* Video J interrupt mask */
152#define VID_J_INT_STAT 0x0400B4 /* Video J interrupt status */
153#define VID_J_INT_MSTAT 0x0400B8 /* Video J interrupt masked status */
154#define VID_J_INT_SSTAT 0x0400BC /* Video J interrupt set status */
155
156#define FLD_VID_SRC_OPC_ERR 0x00020000
157#define FLD_VID_DST_OPC_ERR 0x00010000
158#define FLD_VID_SRC_SYNC 0x00002000
159#define FLD_VID_DST_SYNC 0x00001000
160#define FLD_VID_SRC_UF 0x00000200
161#define FLD_VID_DST_OF 0x00000100
162#define FLD_VID_SRC_RISC2 0x00000020
163#define FLD_VID_DST_RISC2 0x00000010
164#define FLD_VID_SRC_RISC1 0x00000002
165#define FLD_VID_DST_RISC1 0x00000001
166#define FLD_VID_SRC_ERRORS (FLD_VID_SRC_OPC_ERR | FLD_VID_SRC_SYNC | FLD_VID_SRC_UF)
167#define FLD_VID_DST_ERRORS (FLD_VID_DST_OPC_ERR | FLD_VID_DST_SYNC | FLD_VID_DST_OF)
168
169/* ***************************************************************************** */
170#define AUD_A_INT_MSK 0x0400C0 /* Audio Int interrupt mask */
171#define AUD_A_INT_STAT 0x0400C4 /* Audio Int interrupt status */
172#define AUD_A_INT_MSTAT 0x0400C8 /* Audio Int interrupt masked status */
173#define AUD_A_INT_SSTAT 0x0400CC /* Audio Int interrupt set status */
174
175/* ***************************************************************************** */
176#define AUD_B_INT_MSK 0x0400D0 /* Audio Int interrupt mask */
177#define AUD_B_INT_STAT 0x0400D4 /* Audio Int interrupt status */
178#define AUD_B_INT_MSTAT 0x0400D8 /* Audio Int interrupt masked status */
179#define AUD_B_INT_SSTAT 0x0400DC /* Audio Int interrupt set status */
180
181/* ***************************************************************************** */
182#define AUD_C_INT_MSK 0x0400E0 /* Audio Int interrupt mask */
183#define AUD_C_INT_STAT 0x0400E4 /* Audio Int interrupt status */
184#define AUD_C_INT_MSTAT 0x0400E8 /* Audio Int interrupt masked status */
185#define AUD_C_INT_SSTAT 0x0400EC /* Audio Int interrupt set status */
186
187/* ***************************************************************************** */
188#define AUD_D_INT_MSK 0x0400F0 /* Audio Int interrupt mask */
189#define AUD_D_INT_STAT 0x0400F4 /* Audio Int interrupt status */
190#define AUD_D_INT_MSTAT 0x0400F8 /* Audio Int interrupt masked status */
191#define AUD_D_INT_SSTAT 0x0400FC /* Audio Int interrupt set status */
192
193/* ***************************************************************************** */
194#define AUD_E_INT_MSK 0x040100 /* Audio Int interrupt mask */
195#define AUD_E_INT_STAT 0x040104 /* Audio Int interrupt status */
196#define AUD_E_INT_MSTAT 0x040108 /* Audio Int interrupt masked status */
197#define AUD_E_INT_SSTAT 0x04010C /* Audio Int interrupt set status */
198
199#define FLD_AUD_SRC_OPC_ERR 0x00020000
200#define FLD_AUD_DST_OPC_ERR 0x00010000
201#define FLD_AUD_SRC_SYNC 0x00002000
202#define FLD_AUD_DST_SYNC 0x00001000
203#define FLD_AUD_SRC_OF 0x00000200
204#define FLD_AUD_DST_OF 0x00000100
205#define FLD_AUD_SRC_RISCI2 0x00000020
206#define FLD_AUD_DST_RISCI2 0x00000010
207#define FLD_AUD_SRC_RISCI1 0x00000002
208#define FLD_AUD_DST_RISCI1 0x00000001
209
210/* ***************************************************************************** */
211#define MBIF_A_INT_MSK 0x040110 /* MBIF Int interrupt mask */
212#define MBIF_A_INT_STAT 0x040114 /* MBIF Int interrupt status */
213#define MBIF_A_INT_MSTAT 0x040118 /* MBIF Int interrupt masked status */
214#define MBIF_A_INT_SSTAT 0x04011C /* MBIF Int interrupt set status */
215
216/* ***************************************************************************** */
217#define MBIF_B_INT_MSK 0x040120 /* MBIF Int interrupt mask */
218#define MBIF_B_INT_STAT 0x040124 /* MBIF Int interrupt status */
219#define MBIF_B_INT_MSTAT 0x040128 /* MBIF Int interrupt masked status */
220#define MBIF_B_INT_SSTAT 0x04012C /* MBIF Int interrupt set status */
221
222#define FLD_MBIF_DST_OPC_ERR 0x00010000
223#define FLD_MBIF_DST_SYNC 0x00001000
224#define FLD_MBIF_DST_OF 0x00000100
225#define FLD_MBIF_DST_RISCI2 0x00000010
226#define FLD_MBIF_DST_RISCI1 0x00000001
227
228/* ***************************************************************************** */
229#define AUD_EXT_INT_MSK 0x040060 /* Audio Ext interrupt mask */
230#define AUD_EXT_INT_STAT 0x040064 /* Audio Ext interrupt status */
231#define AUD_EXT_INT_MSTAT 0x040068 /* Audio Ext interrupt masked status */
232#define AUD_EXT_INT_SSTAT 0x04006C /* Audio Ext interrupt set status */
233#define FLD_AUD_EXT_OPC_ERR 0x00010000
234#define FLD_AUD_EXT_SYNC 0x00001000
235#define FLD_AUD_EXT_OF 0x00000100
236#define FLD_AUD_EXT_RISCI2 0x00000010
237#define FLD_AUD_EXT_RISCI1 0x00000001
238
239/* ***************************************************************************** */
240#define GPIO_LO 0x110010 /* Lower of GPIO pins [31:0] */
241#define GPIO_HI 0x110014 /* Upper WORD of GPIO pins [47:31] */
242
243#define GPIO_LO_OE 0x110018 /* Lower of GPIO output enable [31:0] */
244#define GPIO_HI_OE 0x11001C /* Upper word of GPIO output enable [47:32] */
245
246#define GPIO_LO_INT_MSK 0x11003C /* GPIO interrupt mask */
247#define GPIO_LO_INT_STAT 0x110044 /* GPIO interrupt status */
248#define GPIO_LO_INT_MSTAT 0x11004C /* GPIO interrupt masked status */
249#define GPIO_LO_ISM_SNS 0x110054 /* GPIO interrupt sensitivity */
250#define GPIO_LO_ISM_POL 0x11005C /* GPIO interrupt polarity */
251
252#define GPIO_HI_INT_MSK 0x110040 /* GPIO interrupt mask */
253#define GPIO_HI_INT_STAT 0x110048 /* GPIO interrupt status */
254#define GPIO_HI_INT_MSTAT 0x110050 /* GPIO interrupt masked status */
255#define GPIO_HI_ISM_SNS 0x110058 /* GPIO interrupt sensitivity */
256#define GPIO_HI_ISM_POL 0x110060 /* GPIO interrupt polarity */
257
258#define FLD_GPIO43_INT (1 << 11)
259#define FLD_GPIO42_INT (1 << 10)
260#define FLD_GPIO41_INT (1 << 9)
261#define FLD_GPIO40_INT (1 << 8)
262
263#define FLD_GPIO9_INT (1 << 9)
264#define FLD_GPIO8_INT (1 << 8)
265#define FLD_GPIO7_INT (1 << 7)
266#define FLD_GPIO6_INT (1 << 6)
267#define FLD_GPIO5_INT (1 << 5)
268#define FLD_GPIO4_INT (1 << 4)
269#define FLD_GPIO3_INT (1 << 3)
270#define FLD_GPIO2_INT (1 << 2)
271#define FLD_GPIO1_INT (1 << 1)
272#define FLD_GPIO0_INT (1 << 0)
273
274/* ***************************************************************************** */
275#define TC_REQ 0x040090 /* Rider PCI Express traFFic class request */
276
277/* ***************************************************************************** */
278#define TC_REQ_SET 0x040094 /* Rider PCI Express traFFic class request set */
279
280/* ***************************************************************************** */
281/* Rider */
282/* ***************************************************************************** */
283
284/* PCI Compatible Header */
285/* ***************************************************************************** */
286#define RDR_CFG0 0x050000
287#define RDR_VENDOR_DEVICE_ID_CFG 0x050000
288
289/* ***************************************************************************** */
290#define RDR_CFG1 0x050004
291
292/* ***************************************************************************** */
293#define RDR_CFG2 0x050008
294
295/* ***************************************************************************** */
296#define RDR_CFG3 0x05000C
297
298/* ***************************************************************************** */
299#define RDR_CFG4 0x050010
300
301/* ***************************************************************************** */
302#define RDR_CFG5 0x050014
303
304/* ***************************************************************************** */
305#define RDR_CFG6 0x050018
306
307/* ***************************************************************************** */
308#define RDR_CFG7 0x05001C
309
310/* ***************************************************************************** */
311#define RDR_CFG8 0x050020
312
313/* ***************************************************************************** */
314#define RDR_CFG9 0x050024
315
316/* ***************************************************************************** */
317#define RDR_CFGA 0x050028
318
319/* ***************************************************************************** */
320#define RDR_CFGB 0x05002C
321#define RDR_SUSSYSTEM_ID_CFG 0x05002C
322
323/* ***************************************************************************** */
324#define RDR_CFGC 0x050030
325
326/* ***************************************************************************** */
327#define RDR_CFGD 0x050034
328
329/* ***************************************************************************** */
330#define RDR_CFGE 0x050038
331
332/* ***************************************************************************** */
333#define RDR_CFGF 0x05003C
334
335/* ***************************************************************************** */
336/* PCI-Express Capabilities */
337/* ***************************************************************************** */
338#define RDR_PECAP 0x050040
339
340/* ***************************************************************************** */
341#define RDR_PEDEVCAP 0x050044
342
343/* ***************************************************************************** */
344#define RDR_PEDEVSC 0x050048
345
346/* ***************************************************************************** */
347#define RDR_PELINKCAP 0x05004C
348
349/* ***************************************************************************** */
350#define RDR_PELINKSC 0x050050
351
352/* ***************************************************************************** */
353#define RDR_PMICAP 0x050080
354
355/* ***************************************************************************** */
356#define RDR_PMCSR 0x050084
357
358/* ***************************************************************************** */
359#define RDR_VPDCAP 0x050090
360
361/* ***************************************************************************** */
362#define RDR_VPDDATA 0x050094
363
364/* ***************************************************************************** */
365#define RDR_MSICAP 0x0500A0
366
367/* ***************************************************************************** */
368#define RDR_MSIARL 0x0500A4
369
370/* ***************************************************************************** */
371#define RDR_MSIARU 0x0500A8
372
373/* ***************************************************************************** */
374#define RDR_MSIDATA 0x0500AC
375
376/* ***************************************************************************** */
377/* PCI Express Extended Capabilities */
378/* ***************************************************************************** */
379#define RDR_AERXCAP 0x050100
380
381/* ***************************************************************************** */
382#define RDR_AERUESTA 0x050104
383
384/* ***************************************************************************** */
385#define RDR_AERUEMSK 0x050108
386
387/* ***************************************************************************** */
388#define RDR_AERUESEV 0x05010C
389
390/* ***************************************************************************** */
391#define RDR_AERCESTA 0x050110
392
393/* ***************************************************************************** */
394#define RDR_AERCEMSK 0x050114
395
396/* ***************************************************************************** */
397#define RDR_AERCC 0x050118
398
399/* ***************************************************************************** */
400#define RDR_AERHL0 0x05011C
401
402/* ***************************************************************************** */
403#define RDR_AERHL1 0x050120
404
405/* ***************************************************************************** */
406#define RDR_AERHL2 0x050124
407
408/* ***************************************************************************** */
409#define RDR_AERHL3 0x050128
410
411/* ***************************************************************************** */
412#define RDR_VCXCAP 0x050200
413
414/* ***************************************************************************** */
415#define RDR_VCCAP1 0x050204
416
417/* ***************************************************************************** */
418#define RDR_VCCAP2 0x050208
419
420/* ***************************************************************************** */
421#define RDR_VCSC 0x05020C
422
423/* ***************************************************************************** */
424#define RDR_VCR0_CAP 0x050210
425
426/* ***************************************************************************** */
427#define RDR_VCR0_CTRL 0x050214
428
429/* ***************************************************************************** */
430#define RDR_VCR0_STAT 0x050218
431
432/* ***************************************************************************** */
433#define RDR_VCR1_CAP 0x05021C
434
435/* ***************************************************************************** */
436#define RDR_VCR1_CTRL 0x050220
437
438/* ***************************************************************************** */
439#define RDR_VCR1_STAT 0x050224
440
441/* ***************************************************************************** */
442#define RDR_VCR2_CAP 0x050228
443
444/* ***************************************************************************** */
445#define RDR_VCR2_CTRL 0x05022C
446
447/* ***************************************************************************** */
448#define RDR_VCR2_STAT 0x050230
449
450/* ***************************************************************************** */
451#define RDR_VCR3_CAP 0x050234
452
453/* ***************************************************************************** */
454#define RDR_VCR3_CTRL 0x050238
455
456/* ***************************************************************************** */
457#define RDR_VCR3_STAT 0x05023C
458
459/* ***************************************************************************** */
460#define RDR_VCARB0 0x050240
461
462/* ***************************************************************************** */
463#define RDR_VCARB1 0x050244
464
465/* ***************************************************************************** */
466#define RDR_VCARB2 0x050248
467
468/* ***************************************************************************** */
469#define RDR_VCARB3 0x05024C
470
471/* ***************************************************************************** */
472#define RDR_VCARB4 0x050250
473
474/* ***************************************************************************** */
475#define RDR_VCARB5 0x050254
476
477/* ***************************************************************************** */
478#define RDR_VCARB6 0x050258
479
480/* ***************************************************************************** */
481#define RDR_VCARB7 0x05025C
482
483/* ***************************************************************************** */
484#define RDR_RDRSTAT0 0x050300
485
486/* ***************************************************************************** */
487#define RDR_RDRSTAT1 0x050304
488
489/* ***************************************************************************** */
490#define RDR_RDRCTL0 0x050308
491
492/* ***************************************************************************** */
493#define RDR_RDRCTL1 0x05030C
494
495/* ***************************************************************************** */
496/* Transaction Layer Registers */
497/* ***************************************************************************** */
498#define RDR_TLSTAT0 0x050310
499
500/* ***************************************************************************** */
501#define RDR_TLSTAT1 0x050314
502
503/* ***************************************************************************** */
504#define RDR_TLCTL0 0x050318
505#define FLD_CFG_UR_CPL_MODE 0x00000040
506#define FLD_CFG_CORR_ERR_QUITE 0x00000020
507#define FLD_CFG_RCB_CK_EN 0x00000010
508#define FLD_CFG_BNDRY_CK_EN 0x00000008
509#define FLD_CFG_BYTE_EN_CK_EN 0x00000004
510#define FLD_CFG_RELAX_ORDER_MSK 0x00000002
511#define FLD_CFG_TAG_ORDER_EN 0x00000001
512
513/* ***************************************************************************** */
514#define RDR_TLCTL1 0x05031C
515
516/* ***************************************************************************** */
517#define RDR_REQRCAL 0x050320
518
519/* ***************************************************************************** */
520#define RDR_REQRCAU 0x050324
521
522/* ***************************************************************************** */
523#define RDR_REQEPA 0x050328
524
525/* ***************************************************************************** */
526#define RDR_REQCTRL 0x05032C
527
528/* ***************************************************************************** */
529#define RDR_REQSTAT 0x050330
530
531/* ***************************************************************************** */
532#define RDR_TL_TEST 0x050334
533
534/* ***************************************************************************** */
535#define RDR_VCR01_CTL 0x050348
536
537/* ***************************************************************************** */
538#define RDR_VCR23_CTL 0x05034C
539
540/* ***************************************************************************** */
541#define RDR_RX_VCR0_FC 0x050350
542
543/* ***************************************************************************** */
544#define RDR_RX_VCR1_FC 0x050354
545
546/* ***************************************************************************** */
547#define RDR_RX_VCR2_FC 0x050358
548
549/* ***************************************************************************** */
550#define RDR_RX_VCR3_FC 0x05035C
551
552/* ***************************************************************************** */
553/* Data Link Layer Registers */
554/* ***************************************************************************** */
555#define RDR_DLLSTAT 0x050360
556
557/* ***************************************************************************** */
558#define RDR_DLLCTRL 0x050364
559
560/* ***************************************************************************** */
561#define RDR_REPLAYTO 0x050368
562
563/* ***************************************************************************** */
564#define RDR_ACKLATTO 0x05036C
565
566/* ***************************************************************************** */
567/* MAC Layer Registers */
568/* ***************************************************************************** */
569#define RDR_MACSTAT0 0x050380
570
571/* ***************************************************************************** */
572#define RDR_MACSTAT1 0x050384
573
574/* ***************************************************************************** */
575#define RDR_MACCTRL0 0x050388
576
577/* ***************************************************************************** */
578#define RDR_MACCTRL1 0x05038C
579
580/* ***************************************************************************** */
581#define RDR_MACCTRL2 0x050390
582
583/* ***************************************************************************** */
584#define RDR_MAC_LB_DATA 0x050394
585
586/* ***************************************************************************** */
587#define RDR_L0S_EXIT_LAT 0x050398
588
589/* ***************************************************************************** */
590/* DMAC */
591/* ***************************************************************************** */
592#define DMA1_PTR1 0x100000 /* DMA Current Ptr : Ch#1 */
593
594/* ***************************************************************************** */
595#define DMA2_PTR1 0x100004 /* DMA Current Ptr : Ch#2 */
596
597/* ***************************************************************************** */
598#define DMA3_PTR1 0x100008 /* DMA Current Ptr : Ch#3 */
599
600/* ***************************************************************************** */
601#define DMA4_PTR1 0x10000C /* DMA Current Ptr : Ch#4 */
602
603/* ***************************************************************************** */
604#define DMA5_PTR1 0x100010 /* DMA Current Ptr : Ch#5 */
605
606/* ***************************************************************************** */
607#define DMA6_PTR1 0x100014 /* DMA Current Ptr : Ch#6 */
608
609/* ***************************************************************************** */
610#define DMA7_PTR1 0x100018 /* DMA Current Ptr : Ch#7 */
611
612/* ***************************************************************************** */
613#define DMA8_PTR1 0x10001C /* DMA Current Ptr : Ch#8 */
614
615/* ***************************************************************************** */
616#define DMA9_PTR1 0x100020 /* DMA Current Ptr : Ch#9 */
617
618/* ***************************************************************************** */
619#define DMA10_PTR1 0x100024 /* DMA Current Ptr : Ch#10 */
620
621/* ***************************************************************************** */
622#define DMA11_PTR1 0x100028 /* DMA Current Ptr : Ch#11 */
623
624/* ***************************************************************************** */
625#define DMA12_PTR1 0x10002C /* DMA Current Ptr : Ch#12 */
626
627/* ***************************************************************************** */
628#define DMA13_PTR1 0x100030 /* DMA Current Ptr : Ch#13 */
629
630/* ***************************************************************************** */
631#define DMA14_PTR1 0x100034 /* DMA Current Ptr : Ch#14 */
632
633/* ***************************************************************************** */
634#define DMA15_PTR1 0x100038 /* DMA Current Ptr : Ch#15 */
635
636/* ***************************************************************************** */
637#define DMA16_PTR1 0x10003C /* DMA Current Ptr : Ch#16 */
638
639/* ***************************************************************************** */
640#define DMA17_PTR1 0x100040 /* DMA Current Ptr : Ch#17 */
641
642/* ***************************************************************************** */
643#define DMA18_PTR1 0x100044 /* DMA Current Ptr : Ch#18 */
644
645/* ***************************************************************************** */
646#define DMA19_PTR1 0x100048 /* DMA Current Ptr : Ch#19 */
647
648/* ***************************************************************************** */
649#define DMA20_PTR1 0x10004C /* DMA Current Ptr : Ch#20 */
650
651/* ***************************************************************************** */
652#define DMA21_PTR1 0x100050 /* DMA Current Ptr : Ch#21 */
653
654/* ***************************************************************************** */
655#define DMA22_PTR1 0x100054 /* DMA Current Ptr : Ch#22 */
656
657/* ***************************************************************************** */
658#define DMA23_PTR1 0x100058 /* DMA Current Ptr : Ch#23 */
659
660/* ***************************************************************************** */
661#define DMA24_PTR1 0x10005C /* DMA Current Ptr : Ch#24 */
662
663/* ***************************************************************************** */
664#define DMA25_PTR1 0x100060 /* DMA Current Ptr : Ch#25 */
665
666/* ***************************************************************************** */
667#define DMA26_PTR1 0x100064 /* DMA Current Ptr : Ch#26 */
668
669/* ***************************************************************************** */
670#define DMA1_PTR2 0x100080 /* DMA Tab Ptr : Ch#1 */
671
672/* ***************************************************************************** */
673#define DMA2_PTR2 0x100084 /* DMA Tab Ptr : Ch#2 */
674
675/* ***************************************************************************** */
676#define DMA3_PTR2 0x100088 /* DMA Tab Ptr : Ch#3 */
677
678/* ***************************************************************************** */
679#define DMA4_PTR2 0x10008C /* DMA Tab Ptr : Ch#4 */
680
681/* ***************************************************************************** */
682#define DMA5_PTR2 0x100090 /* DMA Tab Ptr : Ch#5 */
683
684/* ***************************************************************************** */
685#define DMA6_PTR2 0x100094 /* DMA Tab Ptr : Ch#6 */
686
687/* ***************************************************************************** */
688#define DMA7_PTR2 0x100098 /* DMA Tab Ptr : Ch#7 */
689
690/* ***************************************************************************** */
691#define DMA8_PTR2 0x10009C /* DMA Tab Ptr : Ch#8 */
692
693/* ***************************************************************************** */
694#define DMA9_PTR2 0x1000A0 /* DMA Tab Ptr : Ch#9 */
695
696/* ***************************************************************************** */
697#define DMA10_PTR2 0x1000A4 /* DMA Tab Ptr : Ch#10 */
698
699/* ***************************************************************************** */
700#define DMA11_PTR2 0x1000A8 /* DMA Tab Ptr : Ch#11 */
701
702/* ***************************************************************************** */
703#define DMA12_PTR2 0x1000AC /* DMA Tab Ptr : Ch#12 */
704
705/* ***************************************************************************** */
706#define DMA13_PTR2 0x1000B0 /* DMA Tab Ptr : Ch#13 */
707
708/* ***************************************************************************** */
709#define DMA14_PTR2 0x1000B4 /* DMA Tab Ptr : Ch#14 */
710
711/* ***************************************************************************** */
712#define DMA15_PTR2 0x1000B8 /* DMA Tab Ptr : Ch#15 */
713
714/* ***************************************************************************** */
715#define DMA16_PTR2 0x1000BC /* DMA Tab Ptr : Ch#16 */
716
717/* ***************************************************************************** */
718#define DMA17_PTR2 0x1000C0 /* DMA Tab Ptr : Ch#17 */
719
720/* ***************************************************************************** */
721#define DMA18_PTR2 0x1000C4 /* DMA Tab Ptr : Ch#18 */
722
723/* ***************************************************************************** */
724#define DMA19_PTR2 0x1000C8 /* DMA Tab Ptr : Ch#19 */
725
726/* ***************************************************************************** */
727#define DMA20_PTR2 0x1000CC /* DMA Tab Ptr : Ch#20 */
728
729/* ***************************************************************************** */
730#define DMA21_PTR2 0x1000D0 /* DMA Tab Ptr : Ch#21 */
731
732/* ***************************************************************************** */
733#define DMA22_PTR2 0x1000D4 /* DMA Tab Ptr : Ch#22 */
734
735/* ***************************************************************************** */
736#define DMA23_PTR2 0x1000D8 /* DMA Tab Ptr : Ch#23 */
737
738/* ***************************************************************************** */
739#define DMA24_PTR2 0x1000DC /* DMA Tab Ptr : Ch#24 */
740
741/* ***************************************************************************** */
742#define DMA25_PTR2 0x1000E0 /* DMA Tab Ptr : Ch#25 */
743
744/* ***************************************************************************** */
745#define DMA26_PTR2 0x1000E4 /* DMA Tab Ptr : Ch#26 */
746
747/* ***************************************************************************** */
748#define DMA1_CNT1 0x100100 /* DMA BuFFer Size : Ch#1 */
749
750/* ***************************************************************************** */
751#define DMA2_CNT1 0x100104 /* DMA BuFFer Size : Ch#2 */
752
753/* ***************************************************************************** */
754#define DMA3_CNT1 0x100108 /* DMA BuFFer Size : Ch#3 */
755
756/* ***************************************************************************** */
757#define DMA4_CNT1 0x10010C /* DMA BuFFer Size : Ch#4 */
758
759/* ***************************************************************************** */
760#define DMA5_CNT1 0x100110 /* DMA BuFFer Size : Ch#5 */
761
762/* ***************************************************************************** */
763#define DMA6_CNT1 0x100114 /* DMA BuFFer Size : Ch#6 */
764
765/* ***************************************************************************** */
766#define DMA7_CNT1 0x100118 /* DMA BuFFer Size : Ch#7 */
767
768/* ***************************************************************************** */
769#define DMA8_CNT1 0x10011C /* DMA BuFFer Size : Ch#8 */
770
771/* ***************************************************************************** */
772#define DMA9_CNT1 0x100120 /* DMA BuFFer Size : Ch#9 */
773
774/* ***************************************************************************** */
775#define DMA10_CNT1 0x100124 /* DMA BuFFer Size : Ch#10 */
776
777/* ***************************************************************************** */
778#define DMA11_CNT1 0x100128 /* DMA BuFFer Size : Ch#11 */
779
780/* ***************************************************************************** */
781#define DMA12_CNT1 0x10012C /* DMA BuFFer Size : Ch#12 */
782
783/* ***************************************************************************** */
784#define DMA13_CNT1 0x100130 /* DMA BuFFer Size : Ch#13 */
785
786/* ***************************************************************************** */
787#define DMA14_CNT1 0x100134 /* DMA BuFFer Size : Ch#14 */
788
789/* ***************************************************************************** */
790#define DMA15_CNT1 0x100138 /* DMA BuFFer Size : Ch#15 */
791
792/* ***************************************************************************** */
793#define DMA16_CNT1 0x10013C /* DMA BuFFer Size : Ch#16 */
794
795/* ***************************************************************************** */
796#define DMA17_CNT1 0x100140 /* DMA BuFFer Size : Ch#17 */
797
798/* ***************************************************************************** */
799#define DMA18_CNT1 0x100144 /* DMA BuFFer Size : Ch#18 */
800
801/* ***************************************************************************** */
802#define DMA19_CNT1 0x100148 /* DMA BuFFer Size : Ch#19 */
803
804/* ***************************************************************************** */
805#define DMA20_CNT1 0x10014C /* DMA BuFFer Size : Ch#20 */
806
807/* ***************************************************************************** */
808#define DMA21_CNT1 0x100150 /* DMA BuFFer Size : Ch#21 */
809
810/* ***************************************************************************** */
811#define DMA22_CNT1 0x100154 /* DMA BuFFer Size : Ch#22 */
812
813/* ***************************************************************************** */
814#define DMA23_CNT1 0x100158 /* DMA BuFFer Size : Ch#23 */
815
816/* ***************************************************************************** */
817#define DMA24_CNT1 0x10015C /* DMA BuFFer Size : Ch#24 */
818
819/* ***************************************************************************** */
820#define DMA25_CNT1 0x100160 /* DMA BuFFer Size : Ch#25 */
821
822/* ***************************************************************************** */
823#define DMA26_CNT1 0x100164 /* DMA BuFFer Size : Ch#26 */
824
825/* ***************************************************************************** */
826#define DMA1_CNT2 0x100180 /* DMA Table Size : Ch#1 */
827
828/* ***************************************************************************** */
829#define DMA2_CNT2 0x100184 /* DMA Table Size : Ch#2 */
830
831/* ***************************************************************************** */
832#define DMA3_CNT2 0x100188 /* DMA Table Size : Ch#3 */
833
834/* ***************************************************************************** */
835#define DMA4_CNT2 0x10018C /* DMA Table Size : Ch#4 */
836
837/* ***************************************************************************** */
838#define DMA5_CNT2 0x100190 /* DMA Table Size : Ch#5 */
839
840/* ***************************************************************************** */
841#define DMA6_CNT2 0x100194 /* DMA Table Size : Ch#6 */
842
843/* ***************************************************************************** */
844#define DMA7_CNT2 0x100198 /* DMA Table Size : Ch#7 */
845
846/* ***************************************************************************** */
847#define DMA8_CNT2 0x10019C /* DMA Table Size : Ch#8 */
848
849/* ***************************************************************************** */
850#define DMA9_CNT2 0x1001A0 /* DMA Table Size : Ch#9 */
851
852/* ***************************************************************************** */
853#define DMA10_CNT2 0x1001A4 /* DMA Table Size : Ch#10 */
854
855/* ***************************************************************************** */
856#define DMA11_CNT2 0x1001A8 /* DMA Table Size : Ch#11 */
857
858/* ***************************************************************************** */
859#define DMA12_CNT2 0x1001AC /* DMA Table Size : Ch#12 */
860
861/* ***************************************************************************** */
862#define DMA13_CNT2 0x1001B0 /* DMA Table Size : Ch#13 */
863
864/* ***************************************************************************** */
865#define DMA14_CNT2 0x1001B4 /* DMA Table Size : Ch#14 */
866
867/* ***************************************************************************** */
868#define DMA15_CNT2 0x1001B8 /* DMA Table Size : Ch#15 */
869
870/* ***************************************************************************** */
871#define DMA16_CNT2 0x1001BC /* DMA Table Size : Ch#16 */
872
873/* ***************************************************************************** */
874#define DMA17_CNT2 0x1001C0 /* DMA Table Size : Ch#17 */
875
876/* ***************************************************************************** */
877#define DMA18_CNT2 0x1001C4 /* DMA Table Size : Ch#18 */
878
879/* ***************************************************************************** */
880#define DMA19_CNT2 0x1001C8 /* DMA Table Size : Ch#19 */
881
882/* ***************************************************************************** */
883#define DMA20_CNT2 0x1001CC /* DMA Table Size : Ch#20 */
884
885/* ***************************************************************************** */
886#define DMA21_CNT2 0x1001D0 /* DMA Table Size : Ch#21 */
887
888/* ***************************************************************************** */
889#define DMA22_CNT2 0x1001D4 /* DMA Table Size : Ch#22 */
890
891/* ***************************************************************************** */
892#define DMA23_CNT2 0x1001D8 /* DMA Table Size : Ch#23 */
893
894/* ***************************************************************************** */
895#define DMA24_CNT2 0x1001DC /* DMA Table Size : Ch#24 */
896
897/* ***************************************************************************** */
898#define DMA25_CNT2 0x1001E0 /* DMA Table Size : Ch#25 */
899
900/* ***************************************************************************** */
901#define DMA26_CNT2 0x1001E4 /* DMA Table Size : Ch#26 */
902
903/* ***************************************************************************** */
904 /* ITG */
905/* ***************************************************************************** */
906#define TM_CNT_LDW 0x110000 /* Timer : Counter low */
907
908/* ***************************************************************************** */
909#define TM_CNT_UW 0x110004 /* Timer : Counter high word */
910
911/* ***************************************************************************** */
912#define TM_LMT_LDW 0x110008 /* Timer : Limit low */
913
914/* ***************************************************************************** */
915#define TM_LMT_UW 0x11000C /* Timer : Limit high word */
916
917/* ***************************************************************************** */
918#define GP0_IO 0x110010 /* GPIO output enables data I/O */
919#define FLD_GP_OE 0x00FF0000 /* GPIO: GP_OE output enable */
920#define FLD_GP_IN 0x0000FF00 /* GPIO: GP_IN status */
921#define FLD_GP_OUT 0x000000FF /* GPIO: GP_OUT control */
922
923/* ***************************************************************************** */
924#define GPIO_ISM 0x110014 /* GPIO interrupt sensitivity mode */
925#define FLD_GP_ISM_SNS 0x00000070
926#define FLD_GP_ISM_POL 0x00000007
927
928/* ***************************************************************************** */
929#define SOFT_RESET 0x11001C /* Output system reset reg */
930#define FLD_PECOS_SOFT_RESET 0x00000001
931
932/* ***************************************************************************** */
933#define MC416_RWD 0x110020 /* MC416 GPIO[18:3] pin */
934#define MC416_OEN 0x110024 /* Output enable of GPIO[18:3] */
935#define MC416_CTL 0x110028
936
937/* ***************************************************************************** */
938#define ALT_PIN_OUT_SEL 0x11002C /* Alternate GPIO output select */
939
940#define FLD_ALT_GPIO_OUT_SEL 0xF0000000
941/* 0 Disabled <-- default */
942/* 1 GPIO[0] */
943/* 2 GPIO[10] */
944/* 3 VIP_656_DATA_VAL */
945/* 4 VIP_656_DATA[0] */
946/* 5 VIP_656_CLK */
947/* 6 VIP_656_DATA_EXT[1] */
948/* 7 VIP_656_DATA_EXT[0] */
949/* 8 ATT_IF */
950
951#define FLD_AUX_PLL_CLK_ALT_SEL 0x0F000000
952/* 0 AUX_PLL_CLK<-- default */
953/* 1 GPIO[2] */
954/* 2 GPIO[10] */
955/* 3 VIP_656_DATA_VAL */
956/* 4 VIP_656_DATA[0] */
957/* 5 VIP_656_CLK */
958/* 6 VIP_656_DATA_EXT[1] */
959/* 7 VIP_656_DATA_EXT[0] */
960
961#define FLD_IR_TX_ALT_SEL 0x00F00000
962/* 0 IR_TX <-- default */
963/* 1 GPIO[1] */
964/* 2 GPIO[10] */
965/* 3 VIP_656_DATA_VAL */
966/* 4 VIP_656_DATA[0] */
967/* 5 VIP_656_CLK */
968/* 6 VIP_656_DATA_EXT[1] */
969/* 7 VIP_656_DATA_EXT[0] */
970
971#define FLD_IR_RX_ALT_SEL 0x000F0000
972/* 0 IR_RX <-- default */
973/* 1 GPIO[0] */
974/* 2 GPIO[10] */
975/* 3 VIP_656_DATA_VAL */
976/* 4 VIP_656_DATA[0] */
977/* 5 VIP_656_CLK */
978/* 6 VIP_656_DATA_EXT[1] */
979/* 7 VIP_656_DATA_EXT[0] */
980
981#define FLD_GPIO10_ALT_SEL 0x0000F000
982/* 0 GPIO[10] <-- default */
983/* 1 GPIO[0] */
984/* 2 GPIO[10] */
985/* 3 VIP_656_DATA_VAL */
986/* 4 VIP_656_DATA[0] */
987/* 5 VIP_656_CLK */
988/* 6 VIP_656_DATA_EXT[1] */
989/* 7 VIP_656_DATA_EXT[0] */
990
991#define FLD_GPIO2_ALT_SEL 0x00000F00
992/* 0 GPIO[2] <-- default */
993/* 1 GPIO[1] */
994/* 2 GPIO[10] */
995/* 3 VIP_656_DATA_VAL */
996/* 4 VIP_656_DATA[0] */
997/* 5 VIP_656_CLK */
998/* 6 VIP_656_DATA_EXT[1] */
999/* 7 VIP_656_DATA_EXT[0] */
1000
1001#define FLD_GPIO1_ALT_SEL 0x000000F0
1002/* 0 GPIO[1] <-- default */
1003/* 1 GPIO[0] */
1004/* 2 GPIO[10] */
1005/* 3 VIP_656_DATA_VAL */
1006/* 4 VIP_656_DATA[0] */
1007/* 5 VIP_656_CLK */
1008/* 6 VIP_656_DATA_EXT[1] */
1009/* 7 VIP_656_DATA_EXT[0] */
1010
1011#define FLD_GPIO0_ALT_SEL 0x0000000F
1012/* 0 GPIO[0] <-- default */
1013/* 1 GPIO[1] */
1014/* 2 GPIO[10] */
1015/* 3 VIP_656_DATA_VAL */
1016/* 4 VIP_656_DATA[0] */
1017/* 5 VIP_656_CLK */
1018/* 6 VIP_656_DATA_EXT[1] */
1019/* 7 VIP_656_DATA_EXT[0] */
1020
1021#define ALT_PIN_IN_SEL 0x110030 /* Alternate GPIO input select */
1022
1023#define FLD_GPIO10_ALT_IN_SEL 0x0000F000
1024/* 0 GPIO[10] <-- default */
1025/* 1 IR_RX */
1026/* 2 IR_TX */
1027/* 3 AUX_PLL_CLK */
1028/* 4 IF_ATT_SEL */
1029/* 5 GPIO[0] */
1030/* 6 GPIO[1] */
1031/* 7 GPIO[2] */
1032
1033#define FLD_GPIO2_ALT_IN_SEL 0x00000F00
1034/* 0 GPIO[2] <-- default */
1035/* 1 IR_RX */
1036/* 2 IR_TX */
1037/* 3 AUX_PLL_CLK */
1038/* 4 IF_ATT_SEL */
1039
1040#define FLD_GPIO1_ALT_IN_SEL 0x000000F0
1041/* 0 GPIO[1] <-- default */
1042/* 1 IR_RX */
1043/* 2 IR_TX */
1044/* 3 AUX_PLL_CLK */
1045/* 4 IF_ATT_SEL */
1046
1047#define FLD_GPIO0_ALT_IN_SEL 0x0000000F
1048/* 0 GPIO[0] <-- default */
1049/* 1 IR_RX */
1050/* 2 IR_TX */
1051/* 3 AUX_PLL_CLK */
1052/* 4 IF_ATT_SEL */
1053
1054/* ***************************************************************************** */
1055#define TEST_BUS_CTL1 0x110040 /* Test bus control register #1 */
1056
1057/* ***************************************************************************** */
1058#define TEST_BUS_CTL2 0x110044 /* Test bus control register #2 */
1059
1060/* ***************************************************************************** */
1061#define CLK_DELAY 0x110048 /* Clock delay */
1062#define FLD_MOE_CLK_DIS 0x80000000 /* Disable MoE clock */
1063
1064/* ***************************************************************************** */
1065#define PAD_CTRL 0x110068 /* Pad drive strength control */
1066
1067/* ***************************************************************************** */
1068#define MBIST_CTRL 0x110050 /* SRAM memory built-in self test control */
1069
1070/* ***************************************************************************** */
1071#define MBIST_STAT 0x110054 /* SRAM memory built-in self test status */
1072
1073/* ***************************************************************************** */
1074/* PLL registers */
1075/* ***************************************************************************** */
1076#define PLL_A_INT_FRAC 0x110088
1077#define PLL_A_POST_STAT_BIST 0x11008C
1078#define PLL_B_INT_FRAC 0x110090
1079#define PLL_B_POST_STAT_BIST 0x110094
1080#define PLL_C_INT_FRAC 0x110098
1081#define PLL_C_POST_STAT_BIST 0x11009C
1082#define PLL_D_INT_FRAC 0x1100A0
1083#define PLL_D_POST_STAT_BIST 0x1100A4
1084
1085#define CLK_RST 0x11002C
1086#define FLD_VID_I_CLK_NOE 0x00001000
1087#define FLD_VID_J_CLK_NOE 0x00002000
1088#define FLD_USE_ALT_PLL_REF 0x00004000
1089
1090#define VID_CH_MODE_SEL 0x110078
1091#define VID_CH_CLK_SEL 0x11007C
1092
1093/* ***************************************************************************** */
1094#define VBI_A_DMA 0x130008 /* VBI A DMA data port */
1095
1096/* ***************************************************************************** */
1097#define VID_A_VIP_CTL 0x130080 /* Video A VIP format control */
1098#define FLD_VIP_MODE 0x00000001
1099
1100/* ***************************************************************************** */
1101#define VID_A_PIXEL_FRMT 0x130084 /* Video A pixel format */
1102#define FLD_VID_A_GAMMA_DIS 0x00000008
1103#define FLD_VID_A_FORMAT 0x00000007
1104#define FLD_VID_A_GAMMA_FACTOR 0x00000010
1105
1106/* ***************************************************************************** */
1107#define VID_A_VBI_CTL 0x130088 /* Video A VBI miscellaneous control */
1108#define FLD_VID_A_VIP_EXT 0x00000003
1109
1110/* ***************************************************************************** */
1111#define VID_B_DMA 0x130100 /* Video B DMA data port */
1112
1113/* ***************************************************************************** */
1114#define VBI_B_DMA 0x130108 /* VBI B DMA data port */
1115
1116/* ***************************************************************************** */
1117#define VID_B_SRC_SEL 0x130144 /* Video B source select */
1118#define FLD_VID_B_SRC_SEL 0x00000000
1119
1120/* ***************************************************************************** */
1121#define VID_B_LNGTH 0x130150 /* Video B line length */
1122#define FLD_VID_B_LN_LNGTH 0x00000FFF
1123
1124/* ***************************************************************************** */
1125#define VID_B_VIP_CTL 0x130180 /* Video B VIP format control */
1126
1127/* ***************************************************************************** */
1128#define VID_B_PIXEL_FRMT 0x130184 /* Video B pixel format */
1129#define FLD_VID_B_GAMMA_DIS 0x00000008
1130#define FLD_VID_B_FORMAT 0x00000007
1131#define FLD_VID_B_GAMMA_FACTOR 0x00000010
1132
1133/* ***************************************************************************** */
1134#define VID_C_DMA 0x130200 /* Video C DMA data port */
1135
1136/* ***************************************************************************** */
1137#define VID_C_LNGTH 0x130250 /* Video C line length */
1138#define FLD_VID_C_LN_LNGTH 0x00000FFF
1139
1140/* ***************************************************************************** */
1141/* Video Destination Channels */
1142/* ***************************************************************************** */
1143
1144#define VID_DST_A_GPCNT 0x130020 /* Video A general purpose counter */
1145#define VID_DST_B_GPCNT 0x130120 /* Video B general purpose counter */
1146#define VID_DST_C_GPCNT 0x130220 /* Video C general purpose counter */
1147#define VID_DST_D_GPCNT 0x130320 /* Video D general purpose counter */
1148#define VID_DST_E_GPCNT 0x130420 /* Video E general purpose counter */
1149#define VID_DST_F_GPCNT 0x130520 /* Video F general purpose counter */
1150#define VID_DST_G_GPCNT 0x130620 /* Video G general purpose counter */
1151#define VID_DST_H_GPCNT 0x130720 /* Video H general purpose counter */
1152
1153/* ***************************************************************************** */
1154
1155#define VID_DST_A_GPCNT_CTL 0x130030 /* Video A general purpose control */
1156#define VID_DST_B_GPCNT_CTL 0x130130 /* Video B general purpose control */
1157#define VID_DST_C_GPCNT_CTL 0x130230 /* Video C general purpose control */
1158#define VID_DST_D_GPCNT_CTL 0x130330 /* Video D general purpose control */
1159#define VID_DST_E_GPCNT_CTL 0x130430 /* Video E general purpose control */
1160#define VID_DST_F_GPCNT_CTL 0x130530 /* Video F general purpose control */
1161#define VID_DST_G_GPCNT_CTL 0x130630 /* Video G general purpose control */
1162#define VID_DST_H_GPCNT_CTL 0x130730 /* Video H general purpose control */
1163
1164/* ***************************************************************************** */
1165
1166#define VID_DST_A_DMA_CTL 0x130040 /* Video A DMA control */
1167#define VID_DST_B_DMA_CTL 0x130140 /* Video B DMA control */
1168#define VID_DST_C_DMA_CTL 0x130240 /* Video C DMA control */
1169#define VID_DST_D_DMA_CTL 0x130340 /* Video D DMA control */
1170#define VID_DST_E_DMA_CTL 0x130440 /* Video E DMA control */
1171#define VID_DST_F_DMA_CTL 0x130540 /* Video F DMA control */
1172#define VID_DST_G_DMA_CTL 0x130640 /* Video G DMA control */
1173#define VID_DST_H_DMA_CTL 0x130740 /* Video H DMA control */
1174
1175#define FLD_VID_RISC_EN 0x00000010
1176#define FLD_VID_FIFO_EN 0x00000001
1177
1178/* ***************************************************************************** */
1179
1180#define VID_DST_A_VIP_CTL 0x130080 /* Video A VIP control */
1181#define VID_DST_B_VIP_CTL 0x130180 /* Video B VIP control */
1182#define VID_DST_C_VIP_CTL 0x130280 /* Video C VIP control */
1183#define VID_DST_D_VIP_CTL 0x130380 /* Video D VIP control */
1184#define VID_DST_E_VIP_CTL 0x130480 /* Video E VIP control */
1185#define VID_DST_F_VIP_CTL 0x130580 /* Video F VIP control */
1186#define VID_DST_G_VIP_CTL 0x130680 /* Video G VIP control */
1187#define VID_DST_H_VIP_CTL 0x130780 /* Video H VIP control */
1188
1189/* ***************************************************************************** */
1190
1191#define VID_DST_A_PIX_FRMT 0x130084 /* Video A Pixel format */
1192#define VID_DST_B_PIX_FRMT 0x130184 /* Video B Pixel format */
1193#define VID_DST_C_PIX_FRMT 0x130284 /* Video C Pixel format */
1194#define VID_DST_D_PIX_FRMT 0x130384 /* Video D Pixel format */
1195#define VID_DST_E_PIX_FRMT 0x130484 /* Video E Pixel format */
1196#define VID_DST_F_PIX_FRMT 0x130584 /* Video F Pixel format */
1197#define VID_DST_G_PIX_FRMT 0x130684 /* Video G Pixel format */
1198#define VID_DST_H_PIX_FRMT 0x130784 /* Video H Pixel format */
1199
1200/* ***************************************************************************** */
1201/* Video Source Channels */
1202/* ***************************************************************************** */
1203
1204#define VID_SRC_A_GPCNT_CTL 0x130804 /* Video A general purpose control */
1205#define VID_SRC_B_GPCNT_CTL 0x130904 /* Video B general purpose control */
1206#define VID_SRC_C_GPCNT_CTL 0x130A04 /* Video C general purpose control */
1207#define VID_SRC_D_GPCNT_CTL 0x130B04 /* Video D general purpose control */
1208#define VID_SRC_E_GPCNT_CTL 0x130C04 /* Video E general purpose control */
1209#define VID_SRC_F_GPCNT_CTL 0x130D04 /* Video F general purpose control */
1210#define VID_SRC_I_GPCNT_CTL 0x130E04 /* Video I general purpose control */
1211#define VID_SRC_J_GPCNT_CTL 0x130F04 /* Video J general purpose control */
1212
1213/* ***************************************************************************** */
1214
1215#define VID_SRC_A_GPCNT 0x130808 /* Video A general purpose counter */
1216#define VID_SRC_B_GPCNT 0x130908 /* Video B general purpose counter */
1217#define VID_SRC_C_GPCNT 0x130A08 /* Video C general purpose counter */
1218#define VID_SRC_D_GPCNT 0x130B08 /* Video D general purpose counter */
1219#define VID_SRC_E_GPCNT 0x130C08 /* Video E general purpose counter */
1220#define VID_SRC_F_GPCNT 0x130D08 /* Video F general purpose counter */
1221#define VID_SRC_I_GPCNT 0x130E08 /* Video I general purpose counter */
1222#define VID_SRC_J_GPCNT 0x130F08 /* Video J general purpose counter */
1223
1224/* ***************************************************************************** */
1225
1226#define VID_SRC_A_DMA_CTL 0x13080C /* Video A DMA control */
1227#define VID_SRC_B_DMA_CTL 0x13090C /* Video B DMA control */
1228#define VID_SRC_C_DMA_CTL 0x130A0C /* Video C DMA control */
1229#define VID_SRC_D_DMA_CTL 0x130B0C /* Video D DMA control */
1230#define VID_SRC_E_DMA_CTL 0x130C0C /* Video E DMA control */
1231#define VID_SRC_F_DMA_CTL 0x130D0C /* Video F DMA control */
1232#define VID_SRC_I_DMA_CTL 0x130E0C /* Video I DMA control */
1233#define VID_SRC_J_DMA_CTL 0x130F0C /* Video J DMA control */
1234
1235#define FLD_APB_RISC_EN 0x00000010
1236#define FLD_APB_FIFO_EN 0x00000001
1237
1238/* ***************************************************************************** */
1239
1240#define VID_SRC_A_FMT_CTL 0x130810 /* Video A format control */
1241#define VID_SRC_B_FMT_CTL 0x130910 /* Video B format control */
1242#define VID_SRC_C_FMT_CTL 0x130A10 /* Video C format control */
1243#define VID_SRC_D_FMT_CTL 0x130B10 /* Video D format control */
1244#define VID_SRC_E_FMT_CTL 0x130C10 /* Video E format control */
1245#define VID_SRC_F_FMT_CTL 0x130D10 /* Video F format control */
1246#define VID_SRC_I_FMT_CTL 0x130E10 /* Video I format control */
1247#define VID_SRC_J_FMT_CTL 0x130F10 /* Video J format control */
1248
1249/* ***************************************************************************** */
1250
1251#define VID_SRC_A_ACTIVE_CTL1 0x130814 /* Video A active control 1 */
1252#define VID_SRC_B_ACTIVE_CTL1 0x130914 /* Video B active control 1 */
1253#define VID_SRC_C_ACTIVE_CTL1 0x130A14 /* Video C active control 1 */
1254#define VID_SRC_D_ACTIVE_CTL1 0x130B14 /* Video D active control 1 */
1255#define VID_SRC_E_ACTIVE_CTL1 0x130C14 /* Video E active control 1 */
1256#define VID_SRC_F_ACTIVE_CTL1 0x130D14 /* Video F active control 1 */
1257#define VID_SRC_I_ACTIVE_CTL1 0x130E14 /* Video I active control 1 */
1258#define VID_SRC_J_ACTIVE_CTL1 0x130F14 /* Video J active control 1 */
1259
1260/* ***************************************************************************** */
1261
1262#define VID_SRC_A_ACTIVE_CTL2 0x130818 /* Video A active control 2 */
1263#define VID_SRC_B_ACTIVE_CTL2 0x130918 /* Video B active control 2 */
1264#define VID_SRC_C_ACTIVE_CTL2 0x130A18 /* Video C active control 2 */
1265#define VID_SRC_D_ACTIVE_CTL2 0x130B18 /* Video D active control 2 */
1266#define VID_SRC_E_ACTIVE_CTL2 0x130C18 /* Video E active control 2 */
1267#define VID_SRC_F_ACTIVE_CTL2 0x130D18 /* Video F active control 2 */
1268#define VID_SRC_I_ACTIVE_CTL2 0x130E18 /* Video I active control 2 */
1269#define VID_SRC_J_ACTIVE_CTL2 0x130F18 /* Video J active control 2 */
1270
1271/* ***************************************************************************** */
1272
1273#define VID_SRC_A_CDT_SZ 0x13081C /* Video A CDT size */
1274#define VID_SRC_B_CDT_SZ 0x13091C /* Video B CDT size */
1275#define VID_SRC_C_CDT_SZ 0x130A1C /* Video C CDT size */
1276#define VID_SRC_D_CDT_SZ 0x130B1C /* Video D CDT size */
1277#define VID_SRC_E_CDT_SZ 0x130C1C /* Video E CDT size */
1278#define VID_SRC_F_CDT_SZ 0x130D1C /* Video F CDT size */
1279#define VID_SRC_I_CDT_SZ 0x130E1C /* Video I CDT size */
1280#define VID_SRC_J_CDT_SZ 0x130F1C /* Video J CDT size */
1281
1282/* ***************************************************************************** */
1283/* Audio I/F */
1284/* ***************************************************************************** */
1285#define AUD_DST_A_DMA 0x140000 /* Audio Int A DMA data port */
1286#define AUD_SRC_A_DMA 0x140008 /* Audio Int A DMA data port */
1287
1288#define AUD_A_GPCNT 0x140010 /* Audio Int A gp counter */
1289#define FLD_AUD_A_GP_CNT 0x0000FFFF
1290
1291#define AUD_A_GPCNT_CTL 0x140014 /* Audio Int A gp control */
1292
1293#define AUD_A_LNGTH 0x140018 /* Audio Int A line length */
1294
1295#define AUD_A_CFG 0x14001C /* Audio Int A configuration */
1296
1297/* ***************************************************************************** */
1298#define AUD_DST_B_DMA 0x140100 /* Audio Int B DMA data port */
1299#define AUD_SRC_B_DMA 0x140108 /* Audio Int B DMA data port */
1300
1301#define AUD_B_GPCNT 0x140110 /* Audio Int B gp counter */
1302#define FLD_AUD_B_GP_CNT 0x0000FFFF
1303
1304#define AUD_B_GPCNT_CTL 0x140114 /* Audio Int B gp control */
1305
1306#define AUD_B_LNGTH 0x140118 /* Audio Int B line length */
1307
1308#define AUD_B_CFG 0x14011C /* Audio Int B configuration */
1309
1310/* ***************************************************************************** */
1311#define AUD_DST_C_DMA 0x140200 /* Audio Int C DMA data port */
1312#define AUD_SRC_C_DMA 0x140208 /* Audio Int C DMA data port */
1313
1314#define AUD_C_GPCNT 0x140210 /* Audio Int C gp counter */
1315#define FLD_AUD_C_GP_CNT 0x0000FFFF
1316
1317#define AUD_C_GPCNT_CTL 0x140214 /* Audio Int C gp control */
1318
1319#define AUD_C_LNGTH 0x140218 /* Audio Int C line length */
1320
1321#define AUD_C_CFG 0x14021C /* Audio Int C configuration */
1322
1323/* ***************************************************************************** */
1324#define AUD_DST_D_DMA 0x140300 /* Audio Int D DMA data port */
1325#define AUD_SRC_D_DMA 0x140308 /* Audio Int D DMA data port */
1326
1327#define AUD_D_GPCNT 0x140310 /* Audio Int D gp counter */
1328#define FLD_AUD_D_GP_CNT 0x0000FFFF
1329
1330#define AUD_D_GPCNT_CTL 0x140314 /* Audio Int D gp control */
1331
1332#define AUD_D_LNGTH 0x140318 /* Audio Int D line length */
1333
1334#define AUD_D_CFG 0x14031C /* Audio Int D configuration */
1335
1336/* ***************************************************************************** */
1337#define AUD_SRC_E_DMA 0x140400 /* Audio Int E DMA data port */
1338
1339#define AUD_E_GPCNT 0x140410 /* Audio Int E gp counter */
1340#define FLD_AUD_E_GP_CNT 0x0000FFFF
1341
1342#define AUD_E_GPCNT_CTL 0x140414 /* Audio Int E gp control */
1343
1344#define AUD_E_CFG 0x14041C /* Audio Int E configuration */
1345
1346/* ***************************************************************************** */
1347
1348#define FLD_AUD_DST_LN_LNGTH 0x00000FFF
1349
1350#define FLD_AUD_DST_PK_MODE 0x00004000
1351
1352#define FLD_AUD_CLK_ENABLE 0x00000200
1353
1354#define FLD_AUD_MASTER_MODE 0x00000002
1355
1356#define FLD_AUD_SONY_MODE 0x00000001
1357
1358#define FLD_AUD_CLK_SELECT_PLL_D 0x00001800
1359
1360#define FLD_AUD_DST_ENABLE 0x00020000
1361
1362#define FLD_AUD_SRC_ENABLE 0x00010000
1363
1364/* ***************************************************************************** */
1365#define AUD_INT_DMA_CTL 0x140500 /* Audio Int DMA control */
1366
1367#define FLD_AUD_SRC_E_RISC_EN 0x00008000
1368#define FLD_AUD_SRC_C_RISC_EN 0x00004000
1369#define FLD_AUD_SRC_B_RISC_EN 0x00002000
1370#define FLD_AUD_SRC_A_RISC_EN 0x00001000
1371
1372#define FLD_AUD_DST_D_RISC_EN 0x00000800
1373#define FLD_AUD_DST_C_RISC_EN 0x00000400
1374#define FLD_AUD_DST_B_RISC_EN 0x00000200
1375#define FLD_AUD_DST_A_RISC_EN 0x00000100
1376
1377#define FLD_AUD_SRC_E_FIFO_EN 0x00000080
1378#define FLD_AUD_SRC_C_FIFO_EN 0x00000040
1379#define FLD_AUD_SRC_B_FIFO_EN 0x00000020
1380#define FLD_AUD_SRC_A_FIFO_EN 0x00000010
1381
1382#define FLD_AUD_DST_D_FIFO_EN 0x00000008
1383#define FLD_AUD_DST_C_FIFO_EN 0x00000004
1384#define FLD_AUD_DST_B_FIFO_EN 0x00000002
1385#define FLD_AUD_DST_A_FIFO_EN 0x00000001
1386
1387/* ***************************************************************************** */
1388/* */
1389/* Mobilygen Interface Registers */
1390/* */
1391/* ***************************************************************************** */
1392/* Mobilygen Interface A */
1393/* ***************************************************************************** */
1394#define MB_IF_A_DMA 0x150000 /* MBIF A DMA data port */
1395#define MB_IF_A_GPCN 0x150008 /* MBIF A GP counter */
1396#define MB_IF_A_GPCN_CTRL 0x15000C
1397#define MB_IF_A_DMA_CTRL 0x150010
1398#define MB_IF_A_LENGTH 0x150014
1399#define MB_IF_A_HDMA_XFER_SZ 0x150018
1400#define MB_IF_A_HCMD 0x15001C
1401#define MB_IF_A_HCONFIG 0x150020
1402#define MB_IF_A_DATA_STRUCT_0 0x150024
1403#define MB_IF_A_DATA_STRUCT_1 0x150028
1404#define MB_IF_A_DATA_STRUCT_2 0x15002C
1405#define MB_IF_A_DATA_STRUCT_3 0x150030
1406#define MB_IF_A_DATA_STRUCT_4 0x150034
1407#define MB_IF_A_DATA_STRUCT_5 0x150038
1408#define MB_IF_A_DATA_STRUCT_6 0x15003C
1409#define MB_IF_A_DATA_STRUCT_7 0x150040
1410#define MB_IF_A_DATA_STRUCT_8 0x150044
1411#define MB_IF_A_DATA_STRUCT_9 0x150048
1412#define MB_IF_A_DATA_STRUCT_A 0x15004C
1413#define MB_IF_A_DATA_STRUCT_B 0x150050
1414#define MB_IF_A_DATA_STRUCT_C 0x150054
1415#define MB_IF_A_DATA_STRUCT_D 0x150058
1416#define MB_IF_A_DATA_STRUCT_E 0x15005C
1417#define MB_IF_A_DATA_STRUCT_F 0x150060
1418/* ***************************************************************************** */
1419/* Mobilygen Interface B */
1420/* ***************************************************************************** */
1421#define MB_IF_B_DMA 0x160000 /* MBIF A DMA data port */
1422#define MB_IF_B_GPCN 0x160008 /* MBIF A GP counter */
1423#define MB_IF_B_GPCN_CTRL 0x16000C
1424#define MB_IF_B_DMA_CTRL 0x160010
1425#define MB_IF_B_LENGTH 0x160014
1426#define MB_IF_B_HDMA_XFER_SZ 0x160018
1427#define MB_IF_B_HCMD 0x16001C
1428#define MB_IF_B_HCONFIG 0x160020
1429#define MB_IF_B_DATA_STRUCT_0 0x160024
1430#define MB_IF_B_DATA_STRUCT_1 0x160028
1431#define MB_IF_B_DATA_STRUCT_2 0x16002C
1432#define MB_IF_B_DATA_STRUCT_3 0x160030
1433#define MB_IF_B_DATA_STRUCT_4 0x160034
1434#define MB_IF_B_DATA_STRUCT_5 0x160038
1435#define MB_IF_B_DATA_STRUCT_6 0x16003C
1436#define MB_IF_B_DATA_STRUCT_7 0x160040
1437#define MB_IF_B_DATA_STRUCT_8 0x160044
1438#define MB_IF_B_DATA_STRUCT_9 0x160048
1439#define MB_IF_B_DATA_STRUCT_A 0x16004C
1440#define MB_IF_B_DATA_STRUCT_B 0x160050
1441#define MB_IF_B_DATA_STRUCT_C 0x160054
1442#define MB_IF_B_DATA_STRUCT_D 0x160058
1443#define MB_IF_B_DATA_STRUCT_E 0x16005C
1444#define MB_IF_B_DATA_STRUCT_F 0x160060
1445
1446/* MB_DMA_CTRL */
1447#define FLD_MB_IF_RISC_EN 0x00000010
1448#define FLD_MB_IF_FIFO_EN 0x00000001
1449
1450/* MB_LENGTH */
1451#define FLD_MB_IF_LN_LNGTH 0x00000FFF
1452
1453/* MB_HCMD register */
1454#define FLD_MB_HCMD_H_GO 0x80000000
1455#define FLD_MB_HCMD_H_BUSY 0x40000000
1456#define FLD_MB_HCMD_H_DMA_HOLD 0x10000000
1457#define FLD_MB_HCMD_H_DMA_BUSY 0x08000000
1458#define FLD_MB_HCMD_H_DMA_TYPE 0x04000000
1459#define FLD_MB_HCMD_H_DMA_XACT 0x02000000
1460#define FLD_MB_HCMD_H_RW_N 0x01000000
1461#define FLD_MB_HCMD_H_ADDR 0x00FF0000
1462#define FLD_MB_HCMD_H_DATA 0x0000FFFF
1463
1464/* ***************************************************************************** */
1465/* I2C #1 */
1466/* ***************************************************************************** */
1467#define I2C1_ADDR 0x180000 /* I2C #1 address */
1468#define FLD_I2C_DADDR 0xfe000000 /* RW [31:25] I2C Device Address */
1469 /* RO [24] reserved */
1470/* ***************************************************************************** */
1471#define FLD_I2C_SADDR 0x00FFFFFF /* RW [23:0] I2C Sub-address */
1472
1473/* ***************************************************************************** */
1474#define I2C1_WDATA 0x180004 /* I2C #1 write data */
1475#define FLD_I2C_WDATA 0xFFFFFFFF /* RW [31:0] */
1476
1477/* ***************************************************************************** */
1478#define I2C1_CTRL 0x180008 /* I2C #1 control */
1479#define FLD_I2C_PERIOD 0xFF000000 /* RW [31:24] */
1480#define FLD_I2C_SCL_IN 0x00200000 /* RW [21] */
1481#define FLD_I2C_SDA_IN 0x00100000 /* RW [20] */
1482 /* RO [19:18] reserved */
1483#define FLD_I2C_SCL_OUT 0x00020000 /* RW [17] */
1484#define FLD_I2C_SDA_OUT 0x00010000 /* RW [16] */
1485 /* RO [15] reserved */
1486#define FLD_I2C_DATA_LEN 0x00007000 /* RW [14:12] */
1487#define FLD_I2C_SADDR_INC 0x00000800 /* RW [11] */
1488 /* RO [10:9] reserved */
1489#define FLD_I2C_SADDR_LEN 0x00000300 /* RW [9:8] */
1490 /* RO [7:6] reserved */
1491#define FLD_I2C_SOFT 0x00000020 /* RW [5] */
1492#define FLD_I2C_NOSTOP 0x00000010 /* RW [4] */
1493#define FLD_I2C_EXTEND 0x00000008 /* RW [3] */
1494#define FLD_I2C_SYNC 0x00000004 /* RW [2] */
1495#define FLD_I2C_READ_SA 0x00000002 /* RW [1] */
1496#define FLD_I2C_READ_WRN 0x00000001 /* RW [0] */
1497
1498/* ***************************************************************************** */
1499#define I2C1_RDATA 0x18000C /* I2C #1 read data */
1500#define FLD_I2C_RDATA 0xFFFFFFFF /* RO [31:0] */
1501
1502/* ***************************************************************************** */
1503#define I2C1_STAT 0x180010 /* I2C #1 status */
1504#define FLD_I2C_XFER_IN_PROG 0x00000002 /* RO [1] */
1505#define FLD_I2C_RACK 0x00000001 /* RO [0] */
1506
1507/* ***************************************************************************** */
1508/* I2C #2 */
1509/* ***************************************************************************** */
1510#define I2C2_ADDR 0x190000 /* I2C #2 address */
1511
1512/* ***************************************************************************** */
1513#define I2C2_WDATA 0x190004 /* I2C #2 write data */
1514
1515/* ***************************************************************************** */
1516#define I2C2_CTRL 0x190008 /* I2C #2 control */
1517
1518/* ***************************************************************************** */
1519#define I2C2_RDATA 0x19000C /* I2C #2 read data */
1520
1521/* ***************************************************************************** */
1522#define I2C2_STAT 0x190010 /* I2C #2 status */
1523
1524/* ***************************************************************************** */
1525/* I2C #3 */
1526/* ***************************************************************************** */
1527#define I2C3_ADDR 0x1A0000 /* I2C #3 address */
1528
1529/* ***************************************************************************** */
1530#define I2C3_WDATA 0x1A0004 /* I2C #3 write data */
1531
1532/* ***************************************************************************** */
1533#define I2C3_CTRL 0x1A0008 /* I2C #3 control */
1534
1535/* ***************************************************************************** */
1536#define I2C3_RDATA 0x1A000C /* I2C #3 read data */
1537
1538/* ***************************************************************************** */
1539#define I2C3_STAT 0x1A0010 /* I2C #3 status */
1540
1541/* ***************************************************************************** */
1542/* UART */
1543/* ***************************************************************************** */
1544#define UART_CTL 0x1B0000 /* UART Control Register */
1545#define FLD_LOOP_BACK_EN (1 << 7) /* RW field - default 0 */
1546#define FLD_RX_TRG_SZ (3 << 2) /* RW field - default 0 */
1547#define FLD_RX_EN (1 << 1) /* RW field - default 0 */
1548#define FLD_TX_EN (1 << 0) /* RW field - default 0 */
1549
1550/* ***************************************************************************** */
1551#define UART_BRD 0x1B0004 /* UART Baud Rate Divisor */
1552#define FLD_BRD 0x0000FFFF /* RW field - default 0x197 */
1553
1554/* ***************************************************************************** */
1555#define UART_DBUF 0x1B0008 /* UART Tx/Rx Data BuFFer */
1556#define FLD_DB 0xFFFFFFFF /* RW field - default 0 */
1557
1558/* ***************************************************************************** */
1559#define UART_ISR 0x1B000C /* UART Interrupt Status */
1560#define FLD_RXD_TIMEOUT_EN (1 << 7) /* RW field - default 0 */
1561#define FLD_FRM_ERR_EN (1 << 6) /* RW field - default 0 */
1562#define FLD_RXD_RDY_EN (1 << 5) /* RW field - default 0 */
1563#define FLD_TXD_EMPTY_EN (1 << 4) /* RW field - default 0 */
1564#define FLD_RXD_OVERFLOW (1 << 3) /* RW field - default 0 */
1565#define FLD_FRM_ERR (1 << 2) /* RW field - default 0 */
1566#define FLD_RXD_RDY (1 << 1) /* RW field - default 0 */
1567#define FLD_TXD_EMPTY (1 << 0) /* RW field - default 0 */
1568
1569/* ***************************************************************************** */
1570#define UART_CNT 0x1B0010 /* UART Tx/Rx FIFO Byte Count */
1571#define FLD_TXD_CNT (0x1F << 8) /* RW field - default 0 */
1572#define FLD_RXD_CNT (0x1F << 0) /* RW field - default 0 */
1573
1574/* ***************************************************************************** */
1575/* Motion Detection */
1576#define MD_CH0_GRID_BLOCK_YCNT 0x170014
1577#define MD_CH1_GRID_BLOCK_YCNT 0x170094
1578#define MD_CH2_GRID_BLOCK_YCNT 0x170114
1579#define MD_CH3_GRID_BLOCK_YCNT 0x170194
1580#define MD_CH4_GRID_BLOCK_YCNT 0x170214
1581#define MD_CH5_GRID_BLOCK_YCNT 0x170294
1582#define MD_CH6_GRID_BLOCK_YCNT 0x170314
1583#define MD_CH7_GRID_BLOCK_YCNT 0x170394
1584
1585#define PIXEL_FRMT_422 4
1586#define PIXEL_FRMT_411 5
1587#define PIXEL_FRMT_Y8 6
1588
1589#define PIXEL_ENGINE_VIP1 0
1590#define PIXEL_ENGINE_VIP2 1
1591
1592#endif /* Athena_REGISTERS */
diff --git a/drivers/staging/cx25821/cx25821-sram.h b/drivers/staging/cx25821/cx25821-sram.h
new file mode 100644
index 00000000000..5f05d153bc4
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-sram.h
@@ -0,0 +1,261 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __ATHENA_SRAM_H__
24#define __ATHENA_SRAM_H__
25
26/* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */
27#define VID_CMDS_SIZE 80 /* Video CMDS size in bytes */
28#define AUDIO_CMDS_SIZE 80 /* AUDIO CMDS size in bytes */
29#define MBIF_CMDS_SIZE 80 /* MBIF CMDS size in bytes */
30
31/* #define RX_SRAM_POOL_START_SIZE = 0; // Start of useable RX SRAM for buffers */
32#define VID_IQ_SIZE 64 /* VID instruction queue size in bytes */
33#define MBIF_IQ_SIZE 64
34#define AUDIO_IQ_SIZE 64 /* AUD instruction queue size in bytes */
35
36#define VID_CDT_SIZE 64 /* VID cluster descriptor table size in bytes */
37#define MBIF_CDT_SIZE 64 /* MBIF/HBI cluster descriptor table size in bytes */
38#define AUDIO_CDT_SIZE 48 /* AUD cluster descriptor table size in bytes */
39
40/* #define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM */
41/* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */
42
43/* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */
44/* #define MSI_DATA_SIZE = 64; // Reserved (MSI Data, RISC working stora */
45
46#define VID_CLUSTER_SIZE 1440 /* VID cluster data line */
47#define AUDIO_CLUSTER_SIZE 128 /* AUDIO cluster data line */
48#define MBIF_CLUSTER_SIZE 1440 /* MBIF/HBI cluster data line */
49
50/* #define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM */
51/* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */
52
53/* Receive SRAM */
54#define RX_SRAM_START 0x10000
55#define VID_A_DOWN_CMDS 0x10000
56#define VID_B_DOWN_CMDS 0x10050
57#define VID_C_DOWN_CMDS 0x100A0
58#define VID_D_DOWN_CMDS 0x100F0
59#define VID_E_DOWN_CMDS 0x10140
60#define VID_F_DOWN_CMDS 0x10190
61#define VID_G_DOWN_CMDS 0x101E0
62#define VID_H_DOWN_CMDS 0x10230
63#define VID_A_UP_CMDS 0x10280
64#define VID_B_UP_CMDS 0x102D0
65#define VID_C_UP_CMDS 0x10320
66#define VID_D_UP_CMDS 0x10370
67#define VID_E_UP_CMDS 0x103C0
68#define VID_F_UP_CMDS 0x10410
69#define VID_I_UP_CMDS 0x10460
70#define VID_J_UP_CMDS 0x104B0
71#define AUD_A_DOWN_CMDS 0x10500
72#define AUD_B_DOWN_CMDS 0x10550
73#define AUD_C_DOWN_CMDS 0x105A0
74#define AUD_D_DOWN_CMDS 0x105F0
75#define AUD_A_UP_CMDS 0x10640
76#define AUD_B_UP_CMDS 0x10690
77#define AUD_C_UP_CMDS 0x106E0
78#define AUD_E_UP_CMDS 0x10730
79#define MBIF_A_DOWN_CMDS 0x10780
80#define MBIF_B_DOWN_CMDS 0x107D0
81#define DMA_SCRATCH_PAD 0x10820 /* Scratch pad area from 0x10820 to 0x10B40 */
82
83/* #define RX_SRAM_POOL_START = 0x105B0; */
84
85#define VID_A_IQ 0x11000
86#define VID_B_IQ 0x11040
87#define VID_C_IQ 0x11080
88#define VID_D_IQ 0x110C0
89#define VID_E_IQ 0x11100
90#define VID_F_IQ 0x11140
91#define VID_G_IQ 0x11180
92#define VID_H_IQ 0x111C0
93#define VID_I_IQ 0x11200
94#define VID_J_IQ 0x11240
95#define AUD_A_IQ 0x11280
96#define AUD_B_IQ 0x112C0
97#define AUD_C_IQ 0x11300
98#define AUD_D_IQ 0x11340
99#define AUD_E_IQ 0x11380
100#define MBIF_A_IQ 0x11000
101#define MBIF_B_IQ 0x110C0
102
103#define VID_A_CDT 0x10C00
104#define VID_B_CDT 0x10C40
105#define VID_C_CDT 0x10C80
106#define VID_D_CDT 0x10CC0
107#define VID_E_CDT 0x10D00
108#define VID_F_CDT 0x10D40
109#define VID_G_CDT 0x10D80
110#define VID_H_CDT 0x10DC0
111#define VID_I_CDT 0x10E00
112#define VID_J_CDT 0x10E40
113#define AUD_A_CDT 0x10E80
114#define AUD_B_CDT 0x10EB0
115#define AUD_C_CDT 0x10EE0
116#define AUD_D_CDT 0x10F10
117#define AUD_E_CDT 0x10F40
118#define MBIF_A_CDT 0x10C00
119#define MBIF_B_CDT 0x10CC0
120
121/* Cluster Buffer for RX */
122#define VID_A_UP_CLUSTER_1 0x11400
123#define VID_A_UP_CLUSTER_2 0x119A0
124#define VID_A_UP_CLUSTER_3 0x11F40
125#define VID_A_UP_CLUSTER_4 0x124E0
126
127#define VID_B_UP_CLUSTER_1 0x12A80
128#define VID_B_UP_CLUSTER_2 0x13020
129#define VID_B_UP_CLUSTER_3 0x135C0
130#define VID_B_UP_CLUSTER_4 0x13B60
131
132#define VID_C_UP_CLUSTER_1 0x14100
133#define VID_C_UP_CLUSTER_2 0x146A0
134#define VID_C_UP_CLUSTER_3 0x14C40
135#define VID_C_UP_CLUSTER_4 0x151E0
136
137#define VID_D_UP_CLUSTER_1 0x15780
138#define VID_D_UP_CLUSTER_2 0x15D20
139#define VID_D_UP_CLUSTER_3 0x162C0
140#define VID_D_UP_CLUSTER_4 0x16860
141
142#define VID_E_UP_CLUSTER_1 0x16E00
143#define VID_E_UP_CLUSTER_2 0x173A0
144#define VID_E_UP_CLUSTER_3 0x17940
145#define VID_E_UP_CLUSTER_4 0x17EE0
146
147#define VID_F_UP_CLUSTER_1 0x18480
148#define VID_F_UP_CLUSTER_2 0x18A20
149#define VID_F_UP_CLUSTER_3 0x18FC0
150#define VID_F_UP_CLUSTER_4 0x19560
151
152#define VID_I_UP_CLUSTER_1 0x19B00
153#define VID_I_UP_CLUSTER_2 0x1A0A0
154#define VID_I_UP_CLUSTER_3 0x1A640
155#define VID_I_UP_CLUSTER_4 0x1ABE0
156
157#define VID_J_UP_CLUSTER_1 0x1B180
158#define VID_J_UP_CLUSTER_2 0x1B720
159#define VID_J_UP_CLUSTER_3 0x1BCC0
160#define VID_J_UP_CLUSTER_4 0x1C260
161
162#define AUD_A_UP_CLUSTER_1 0x1C800
163#define AUD_A_UP_CLUSTER_2 0x1C880
164#define AUD_A_UP_CLUSTER_3 0x1C900
165
166#define AUD_B_UP_CLUSTER_1 0x1C980
167#define AUD_B_UP_CLUSTER_2 0x1CA00
168#define AUD_B_UP_CLUSTER_3 0x1CA80
169
170#define AUD_C_UP_CLUSTER_1 0x1CB00
171#define AUD_C_UP_CLUSTER_2 0x1CB80
172#define AUD_C_UP_CLUSTER_3 0x1CC00
173
174#define AUD_E_UP_CLUSTER_1 0x1CC80
175#define AUD_E_UP_CLUSTER_2 0x1CD00
176#define AUD_E_UP_CLUSTER_3 0x1CD80
177
178#define RX_SRAM_POOL_FREE 0x1CE00
179#define RX_SRAM_END 0x1D000
180
181/* Free Receive SRAM 144 Bytes */
182
183/* Transmit SRAM */
184#define TX_SRAM_POOL_START 0x00000
185
186#define VID_A_DOWN_CLUSTER_1 0x00040
187#define VID_A_DOWN_CLUSTER_2 0x005E0
188#define VID_A_DOWN_CLUSTER_3 0x00B80
189#define VID_A_DOWN_CLUSTER_4 0x01120
190
191#define VID_B_DOWN_CLUSTER_1 0x016C0
192#define VID_B_DOWN_CLUSTER_2 0x01C60
193#define VID_B_DOWN_CLUSTER_3 0x02200
194#define VID_B_DOWN_CLUSTER_4 0x027A0
195
196#define VID_C_DOWN_CLUSTER_1 0x02D40
197#define VID_C_DOWN_CLUSTER_2 0x032E0
198#define VID_C_DOWN_CLUSTER_3 0x03880
199#define VID_C_DOWN_CLUSTER_4 0x03E20
200
201#define VID_D_DOWN_CLUSTER_1 0x043C0
202#define VID_D_DOWN_CLUSTER_2 0x04960
203#define VID_D_DOWN_CLUSTER_3 0x04F00
204#define VID_D_DOWN_CLUSTER_4 0x054A0
205
206#define VID_E_DOWN_CLUSTER_1 0x05a40
207#define VID_E_DOWN_CLUSTER_2 0x05FE0
208#define VID_E_DOWN_CLUSTER_3 0x06580
209#define VID_E_DOWN_CLUSTER_4 0x06B20
210
211#define VID_F_DOWN_CLUSTER_1 0x070C0
212#define VID_F_DOWN_CLUSTER_2 0x07660
213#define VID_F_DOWN_CLUSTER_3 0x07C00
214#define VID_F_DOWN_CLUSTER_4 0x081A0
215
216#define VID_G_DOWN_CLUSTER_1 0x08740
217#define VID_G_DOWN_CLUSTER_2 0x08CE0
218#define VID_G_DOWN_CLUSTER_3 0x09280
219#define VID_G_DOWN_CLUSTER_4 0x09820
220
221#define VID_H_DOWN_CLUSTER_1 0x09DC0
222#define VID_H_DOWN_CLUSTER_2 0x0A360
223#define VID_H_DOWN_CLUSTER_3 0x0A900
224#define VID_H_DOWN_CLUSTER_4 0x0AEA0
225
226#define AUD_A_DOWN_CLUSTER_1 0x0B500
227#define AUD_A_DOWN_CLUSTER_2 0x0B580
228#define AUD_A_DOWN_CLUSTER_3 0x0B600
229
230#define AUD_B_DOWN_CLUSTER_1 0x0B680
231#define AUD_B_DOWN_CLUSTER_2 0x0B700
232#define AUD_B_DOWN_CLUSTER_3 0x0B780
233
234#define AUD_C_DOWN_CLUSTER_1 0x0B800
235#define AUD_C_DOWN_CLUSTER_2 0x0B880
236#define AUD_C_DOWN_CLUSTER_3 0x0B900
237
238#define AUD_D_DOWN_CLUSTER_1 0x0B980
239#define AUD_D_DOWN_CLUSTER_2 0x0BA00
240#define AUD_D_DOWN_CLUSTER_3 0x0BA80
241
242#define TX_SRAM_POOL_FREE 0x0BB00
243#define TX_SRAM_END 0x0C000
244
245#define BYTES_TO_DWORDS(bcount) ((bcount) >> 2)
246#define BYTES_TO_QWORDS(bcount) ((bcount) >> 3)
247#define BYTES_TO_OWORDS(bcount) ((bcount) >> 4)
248
249#define VID_IQ_SIZE_DW BYTES_TO_DWORDS(VID_IQ_SIZE)
250#define VID_CDT_SIZE_QW BYTES_TO_QWORDS(VID_CDT_SIZE)
251#define VID_CLUSTER_SIZE_OW BYTES_TO_OWORDS(VID_CLUSTER_SIZE)
252
253#define AUDIO_IQ_SIZE_DW BYTES_TO_DWORDS(AUDIO_IQ_SIZE)
254#define AUDIO_CDT_SIZE_QW BYTES_TO_QWORDS(AUDIO_CDT_SIZE)
255#define AUDIO_CLUSTER_SIZE_QW BYTES_TO_QWORDS(AUDIO_CLUSTER_SIZE)
256
257#define MBIF_IQ_SIZE_DW BYTES_TO_DWORDS(MBIF_IQ_SIZE)
258#define MBIF_CDT_SIZE_QW BYTES_TO_QWORDS(MBIF_CDT_SIZE)
259#define MBIF_CLUSTER_SIZE_OW BYTES_TO_OWORDS(MBIF_CLUSTER_SIZE)
260
261#endif
diff --git a/drivers/staging/cx25821/cx25821-video-upstream-ch2.c b/drivers/staging/cx25821/cx25821-video-upstream-ch2.c
new file mode 100644
index 00000000000..655357da3d6
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-video-upstream-ch2.c
@@ -0,0 +1,836 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24
25#include "cx25821-video.h"
26#include "cx25821-video-upstream-ch2.h"
27
28#include <linux/fs.h>
29#include <linux/errno.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <linux/module.h>
33#include <linux/syscalls.h>
34#include <linux/file.h>
35#include <linux/fcntl.h>
36#include <linux/slab.h>
37#include <linux/uaccess.h>
38
39MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
40MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
41MODULE_LICENSE("GPL");
42
43static int _intr_msk =
44 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
45
46static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
47 __le32 *rp, unsigned int offset,
48 unsigned int bpl, u32 sync_line,
49 unsigned int lines,
50 int fifo_enable, int field_type)
51{
52 unsigned int line, i;
53 int dist_betwn_starts = bpl * 2;
54
55 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
56
57 if (USE_RISC_NOOP_VIDEO) {
58 for (i = 0; i < NUM_NO_OPS; i++)
59 *(rp++) = cpu_to_le32(RISC_NOOP);
60 }
61
62 /* scan lines */
63 for (line = 0; line < lines; line++) {
64 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
65 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
66 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
67
68 if ((lines <= NTSC_FIELD_HEIGHT)
69 || (line < (NTSC_FIELD_HEIGHT - 1))
70 || !(dev->_isNTSC_ch2)) {
71 offset += dist_betwn_starts;
72 }
73 }
74
75 return rp;
76}
77
78static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
79 __le32 *rp,
80 dma_addr_t databuf_phys_addr,
81 unsigned int offset,
82 u32 sync_line, unsigned int bpl,
83 unsigned int lines,
84 int fifo_enable, int field_type)
85{
86 unsigned int line, i;
87 struct sram_channel *sram_ch =
88 dev->channels[dev->_channel2_upstream_select].sram_channels;
89 int dist_betwn_starts = bpl * 2;
90
91 /* sync instruction */
92 if (sync_line != NO_SYNC_LINE)
93 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
94
95 if (USE_RISC_NOOP_VIDEO) {
96 for (i = 0; i < NUM_NO_OPS; i++)
97 *(rp++) = cpu_to_le32(RISC_NOOP);
98 }
99
100 /* scan lines */
101 for (line = 0; line < lines; line++) {
102 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
103 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
104 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
105
106 if ((lines <= NTSC_FIELD_HEIGHT)
107 || (line < (NTSC_FIELD_HEIGHT - 1))
108 || !(dev->_isNTSC_ch2)) {
109 offset += dist_betwn_starts;
110 }
111
112 /*
113 check if we need to enable the FIFO after the first 4 lines
114 For the upstream video channel, the risc engine will enable
115 the FIFO.
116 */
117 if (fifo_enable && line == 3) {
118 *(rp++) = RISC_WRITECR;
119 *(rp++) = sram_ch->dma_ctl;
120 *(rp++) = FLD_VID_FIFO_EN;
121 *(rp++) = 0x00000001;
122 }
123 }
124
125 return rp;
126}
127
128int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
129 struct pci_dev *pci,
130 unsigned int top_offset, unsigned int bpl,
131 unsigned int lines)
132{
133 __le32 *rp;
134 int fifo_enable = 0;
135 int singlefield_lines = lines >> 1; /*get line count for single field */
136 int odd_num_lines = singlefield_lines;
137 int frame = 0;
138 int frame_size = 0;
139 int databuf_offset = 0;
140 int risc_program_size = 0;
141 int risc_flag = RISC_CNT_RESET;
142 unsigned int bottom_offset = bpl;
143 dma_addr_t risc_phys_jump_addr;
144
145 if (dev->_isNTSC_ch2) {
146 odd_num_lines = singlefield_lines + 1;
147 risc_program_size = FRAME1_VID_PROG_SIZE;
148 frame_size =
149 (bpl ==
150 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
151 FRAME_SIZE_NTSC_Y422;
152 } else {
153 risc_program_size = PAL_VID_PROG_SIZE;
154 frame_size =
155 (bpl ==
156 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
157 }
158
159 /* Virtual address of Risc buffer program */
160 rp = dev->_dma_virt_addr_ch2;
161
162 for (frame = 0; frame < NUM_FRAMES; frame++) {
163 databuf_offset = frame_size * frame;
164
165 if (UNSET != top_offset) {
166 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
167 rp = cx25821_risc_field_upstream_ch2(dev, rp,
168 dev->
169 _data_buf_phys_addr_ch2
170 + databuf_offset,
171 top_offset, 0, bpl,
172 odd_num_lines,
173 fifo_enable,
174 ODD_FIELD);
175 }
176
177 fifo_enable = FIFO_DISABLE;
178
179 /* Even field */
180 rp = cx25821_risc_field_upstream_ch2(dev, rp,
181 dev->
182 _data_buf_phys_addr_ch2 +
183 databuf_offset,
184 bottom_offset, 0x200, bpl,
185 singlefield_lines,
186 fifo_enable, EVEN_FIELD);
187
188 if (frame == 0) {
189 risc_flag = RISC_CNT_RESET;
190 risc_phys_jump_addr =
191 dev->_dma_phys_start_addr_ch2 + risc_program_size;
192 } else {
193 risc_flag = RISC_CNT_INC;
194 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
195 }
196
197 /*
198 Loop to 2ndFrameRISC or to Start of
199 Risc program & generate IRQ
200 */
201 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
202 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
203 *(rp++) = cpu_to_le32(0);
204 }
205
206 return 0;
207}
208
209void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
210{
211 struct sram_channel *sram_ch =
212 dev->channels[VID_UPSTREAM_SRAM_CHANNEL_J].sram_channels;
213 u32 tmp = 0;
214
215 if (!dev->_is_running_ch2) {
216 pr_info("No video file is currently running so return!\n");
217 return;
218 }
219 /* Disable RISC interrupts */
220 tmp = cx_read(sram_ch->int_msk);
221 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
222
223 /* Turn OFF risc and fifo */
224 tmp = cx_read(sram_ch->dma_ctl);
225 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
226
227 /* Clear data buffer memory */
228 if (dev->_data_buf_virt_addr_ch2)
229 memset(dev->_data_buf_virt_addr_ch2, 0,
230 dev->_data_buf_size_ch2);
231
232 dev->_is_running_ch2 = 0;
233 dev->_is_first_frame_ch2 = 0;
234 dev->_frame_count_ch2 = 0;
235 dev->_file_status_ch2 = END_OF_FILE;
236
237 kfree(dev->_irq_queues_ch2);
238 dev->_irq_queues_ch2 = NULL;
239
240 kfree(dev->_filename_ch2);
241
242 tmp = cx_read(VID_CH_MODE_SEL);
243 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
244}
245
246void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
247{
248 if (dev->_is_running_ch2)
249 cx25821_stop_upstream_video_ch2(dev);
250
251 if (dev->_dma_virt_addr_ch2) {
252 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
253 dev->_dma_virt_addr_ch2,
254 dev->_dma_phys_addr_ch2);
255 dev->_dma_virt_addr_ch2 = NULL;
256 }
257
258 if (dev->_data_buf_virt_addr_ch2) {
259 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
260 dev->_data_buf_virt_addr_ch2,
261 dev->_data_buf_phys_addr_ch2);
262 dev->_data_buf_virt_addr_ch2 = NULL;
263 }
264}
265
266int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
267{
268 struct file *myfile;
269 int frame_index_temp = dev->_frame_index_ch2;
270 int i = 0;
271 int line_size =
272 (dev->_pixel_format_ch2 ==
273 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
274 int frame_size = 0;
275 int frame_offset = 0;
276 ssize_t vfs_read_retval = 0;
277 char mybuf[line_size];
278 loff_t file_offset;
279 loff_t pos;
280 mm_segment_t old_fs;
281
282 if (dev->_file_status_ch2 == END_OF_FILE)
283 return 0;
284
285 if (dev->_isNTSC_ch2) {
286 frame_size =
287 (line_size ==
288 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
289 FRAME_SIZE_NTSC_Y422;
290 } else {
291 frame_size =
292 (line_size ==
293 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
294 }
295
296 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
297 file_offset = dev->_frame_count_ch2 * frame_size;
298
299 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
300 if (IS_ERR(myfile)) {
301 const int open_errno = -PTR_ERR(myfile);
302 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
303 __func__, dev->_filename_ch2, open_errno);
304 return PTR_ERR(myfile);
305 } else {
306 if (!(myfile->f_op)) {
307 pr_err("%s(): File has no file operations registered!\n",
308 __func__);
309 filp_close(myfile, NULL);
310 return -EIO;
311 }
312
313 if (!myfile->f_op->read) {
314 pr_err("%s(): File has no READ operations registered!\n",
315 __func__);
316 filp_close(myfile, NULL);
317 return -EIO;
318 }
319
320 pos = myfile->f_pos;
321 old_fs = get_fs();
322 set_fs(KERNEL_DS);
323
324 for (i = 0; i < dev->_lines_count_ch2; i++) {
325 pos = file_offset;
326
327 vfs_read_retval =
328 vfs_read(myfile, mybuf, line_size, &pos);
329
330 if (vfs_read_retval > 0 && vfs_read_retval == line_size
331 && dev->_data_buf_virt_addr_ch2 != NULL) {
332 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
333 frame_offset / 4), mybuf,
334 vfs_read_retval);
335 }
336
337 file_offset += vfs_read_retval;
338 frame_offset += vfs_read_retval;
339
340 if (vfs_read_retval < line_size) {
341 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
342 __func__);
343 break;
344 }
345 }
346
347 if (i > 0)
348 dev->_frame_count_ch2++;
349
350 dev->_file_status_ch2 =
351 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
352
353 set_fs(old_fs);
354 filp_close(myfile, NULL);
355 }
356
357 return 0;
358}
359
360static void cx25821_vidups_handler_ch2(struct work_struct *work)
361{
362 struct cx25821_dev *dev =
363 container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
364
365 if (!dev) {
366 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
367 __func__);
368 return;
369 }
370
371 cx25821_get_frame_ch2(dev,
372 dev->channels[dev->
373 _channel2_upstream_select].sram_channels);
374}
375
376int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
377{
378 struct file *myfile;
379 int i = 0, j = 0;
380 int line_size =
381 (dev->_pixel_format_ch2 ==
382 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
383 ssize_t vfs_read_retval = 0;
384 char mybuf[line_size];
385 loff_t pos;
386 loff_t offset = (unsigned long)0;
387 mm_segment_t old_fs;
388
389 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
390
391 if (IS_ERR(myfile)) {
392 const int open_errno = -PTR_ERR(myfile);
393 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
394 __func__, dev->_filename_ch2, open_errno);
395 return PTR_ERR(myfile);
396 } else {
397 if (!(myfile->f_op)) {
398 pr_err("%s(): File has no file operations registered!\n",
399 __func__);
400 filp_close(myfile, NULL);
401 return -EIO;
402 }
403
404 if (!myfile->f_op->read) {
405 pr_err("%s(): File has no READ operations registered! Returning\n",
406 __func__);
407 filp_close(myfile, NULL);
408 return -EIO;
409 }
410
411 pos = myfile->f_pos;
412 old_fs = get_fs();
413 set_fs(KERNEL_DS);
414
415 for (j = 0; j < NUM_FRAMES; j++) {
416 for (i = 0; i < dev->_lines_count_ch2; i++) {
417 pos = offset;
418
419 vfs_read_retval =
420 vfs_read(myfile, mybuf, line_size, &pos);
421
422 if (vfs_read_retval > 0
423 && vfs_read_retval == line_size
424 && dev->_data_buf_virt_addr_ch2 != NULL) {
425 memcpy((void *)(dev->
426 _data_buf_virt_addr_ch2
427 + offset / 4), mybuf,
428 vfs_read_retval);
429 }
430
431 offset += vfs_read_retval;
432
433 if (vfs_read_retval < line_size) {
434 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
435 __func__);
436 break;
437 }
438 }
439
440 if (i > 0)
441 dev->_frame_count_ch2++;
442
443 if (vfs_read_retval < line_size)
444 break;
445 }
446
447 dev->_file_status_ch2 =
448 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
449
450 set_fs(old_fs);
451 myfile->f_pos = 0;
452 filp_close(myfile, NULL);
453 }
454
455 return 0;
456}
457
458static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
459 struct sram_channel *sram_ch,
460 int bpl)
461{
462 int ret = 0;
463 dma_addr_t dma_addr;
464 dma_addr_t data_dma_addr;
465
466 if (dev->_dma_virt_addr_ch2 != NULL) {
467 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
468 dev->_dma_virt_addr_ch2,
469 dev->_dma_phys_addr_ch2);
470 }
471
472 dev->_dma_virt_addr_ch2 =
473 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
474 &dma_addr);
475 dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
476 dev->_dma_phys_start_addr_ch2 = dma_addr;
477 dev->_dma_phys_addr_ch2 = dma_addr;
478 dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
479
480 if (!dev->_dma_virt_addr_ch2) {
481 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
482 return -ENOMEM;
483 }
484
485 /* Iniitize at this address until n bytes to 0 */
486 memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
487
488 if (dev->_data_buf_virt_addr_ch2 != NULL) {
489 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
490 dev->_data_buf_virt_addr_ch2,
491 dev->_data_buf_phys_addr_ch2);
492 }
493 /* For Video Data buffer allocation */
494 dev->_data_buf_virt_addr_ch2 =
495 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
496 &data_dma_addr);
497 dev->_data_buf_phys_addr_ch2 = data_dma_addr;
498 dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
499
500 if (!dev->_data_buf_virt_addr_ch2) {
501 pr_err("FAILED to allocate memory for data buffer! Returning\n");
502 return -ENOMEM;
503 }
504
505 /* Initialize at this address until n bytes to 0 */
506 memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
507
508 ret = cx25821_openfile_ch2(dev, sram_ch);
509 if (ret < 0)
510 return ret;
511
512 /* Creating RISC programs */
513 ret =
514 cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
515 dev->_lines_count_ch2);
516 if (ret < 0) {
517 pr_info("Failed creating Video Upstream Risc programs!\n");
518 goto error;
519 }
520
521 return 0;
522
523 error:
524 return ret;
525}
526
527int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
528 u32 status)
529{
530 u32 int_msk_tmp;
531 struct sram_channel *channel = dev->channels[chan_num].sram_channels;
532 int singlefield_lines = NTSC_FIELD_HEIGHT;
533 int line_size_in_bytes = Y422_LINE_SZ;
534 int odd_risc_prog_size = 0;
535 dma_addr_t risc_phys_jump_addr;
536 __le32 *rp;
537
538 if (status & FLD_VID_SRC_RISC1) {
539 /* We should only process one program per call */
540 u32 prog_cnt = cx_read(channel->gpcnt);
541
542 /*
543 * Since we've identified our IRQ, clear our bits from the
544 * interrupt mask and interrupt status registers
545 */
546 int_msk_tmp = cx_read(channel->int_msk);
547 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
548 cx_write(channel->int_stat, _intr_msk);
549
550 spin_lock(&dev->slock);
551
552 dev->_frame_index_ch2 = prog_cnt;
553
554 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
555
556 if (dev->_is_first_frame_ch2) {
557 dev->_is_first_frame_ch2 = 0;
558
559 if (dev->_isNTSC_ch2) {
560 singlefield_lines += 1;
561 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
562 } else {
563 singlefield_lines = PAL_FIELD_HEIGHT;
564 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
565 }
566
567 if (dev->_dma_virt_start_addr_ch2 != NULL) {
568 line_size_in_bytes =
569 (dev->_pixel_format_ch2 ==
570 PIXEL_FRMT_411) ? Y411_LINE_SZ :
571 Y422_LINE_SZ;
572 risc_phys_jump_addr =
573 dev->_dma_phys_start_addr_ch2 +
574 odd_risc_prog_size;
575
576 rp = cx25821_update_riscprogram_ch2(dev,
577 dev->
578 _dma_virt_start_addr_ch2,
579 TOP_OFFSET,
580 line_size_in_bytes,
581 0x0,
582 singlefield_lines,
583 FIFO_DISABLE,
584 ODD_FIELD);
585
586 /* Jump to Even Risc program of 1st Frame */
587 *(rp++) = cpu_to_le32(RISC_JUMP);
588 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
589 *(rp++) = cpu_to_le32(0);
590 }
591 }
592
593 spin_unlock(&dev->slock);
594 }
595
596 if (dev->_file_status_ch2 == END_OF_FILE) {
597 pr_info("EOF Channel 2 Framecount = %d\n",
598 dev->_frame_count_ch2);
599 return -1;
600 }
601 /* ElSE, set the interrupt mask register, re-enable irq. */
602 int_msk_tmp = cx_read(channel->int_msk);
603 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
604
605 return 0;
606}
607
608static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
609{
610 struct cx25821_dev *dev = dev_id;
611 u32 msk_stat, vid_status;
612 int handled = 0;
613 int channel_num = 0;
614 struct sram_channel *sram_ch;
615
616 if (!dev)
617 return -1;
618
619 channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
620 sram_ch = dev->channels[channel_num].sram_channels;
621
622 msk_stat = cx_read(sram_ch->int_mstat);
623 vid_status = cx_read(sram_ch->int_stat);
624
625 /* Only deal with our interrupt */
626 if (vid_status) {
627 handled =
628 cx25821_video_upstream_irq_ch2(dev, channel_num,
629 vid_status);
630 }
631
632 if (handled < 0)
633 cx25821_stop_upstream_video_ch2(dev);
634 else
635 handled += handled;
636
637 return IRQ_RETVAL(handled);
638}
639
640static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
641 struct sram_channel *ch, int pix_format)
642{
643 int width = WIDTH_D1;
644 int height = dev->_lines_count_ch2;
645 int num_lines, odd_num_lines;
646 u32 value;
647 int vip_mode = PIXEL_ENGINE_VIP1;
648
649 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
650 value &= 0xFFFFFFEF;
651 value |= dev->_isNTSC_ch2 ? 0 : 0x10;
652 cx_write(ch->vid_fmt_ctl, value);
653
654 /*
655 * set number of active pixels in each line. Default is 720
656 * pixels in both NTSC and PAL format
657 */
658 cx_write(ch->vid_active_ctl1, width);
659
660 num_lines = (height / 2) & 0x3FF;
661 odd_num_lines = num_lines;
662
663 if (dev->_isNTSC_ch2)
664 odd_num_lines += 1;
665
666 value = (num_lines << 16) | odd_num_lines;
667
668 /* set number of active lines in field 0 (top) and field 1 (bottom) */
669 cx_write(ch->vid_active_ctl2, value);
670
671 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
672}
673
674int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
675 struct sram_channel *sram_ch)
676{
677 u32 tmp = 0;
678 int err = 0;
679
680 /*
681 * 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface
682 * for channel A-C
683 */
684 tmp = cx_read(VID_CH_MODE_SEL);
685 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
686
687 /*
688 * Set the physical start address of the RISC program in the initial
689 * program counter(IPC) member of the cmds.
690 */
691 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
692 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
693
694 /* reset counter */
695 cx_write(sram_ch->gpcnt_ctl, 3);
696
697 /* Clear our bits from the interrupt status register. */
698 cx_write(sram_ch->int_stat, _intr_msk);
699
700 /* Set the interrupt mask register, enable irq. */
701 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
702 tmp = cx_read(sram_ch->int_msk);
703 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
704
705 err =
706 request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
707 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
708 if (err < 0) {
709 pr_err("%s: can't get upstream IRQ %d\n",
710 dev->name, dev->pci->irq);
711 goto fail_irq;
712 }
713 /* Start the DMA engine */
714 tmp = cx_read(sram_ch->dma_ctl);
715 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
716
717 dev->_is_running_ch2 = 1;
718 dev->_is_first_frame_ch2 = 1;
719
720 return 0;
721
722 fail_irq:
723 cx25821_dev_unregister(dev);
724 return err;
725}
726
727int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
728 int pixel_format)
729{
730 struct sram_channel *sram_ch;
731 u32 tmp;
732 int retval = 0;
733 int err = 0;
734 int data_frame_size = 0;
735 int risc_buffer_size = 0;
736 int str_length = 0;
737
738 if (dev->_is_running_ch2) {
739 pr_info("Video Channel is still running so return!\n");
740 return 0;
741 }
742
743 dev->_channel2_upstream_select = channel_select;
744 sram_ch = dev->channels[channel_select].sram_channels;
745
746 INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
747 dev->_irq_queues_ch2 =
748 create_singlethread_workqueue("cx25821_workqueue2");
749
750 if (!dev->_irq_queues_ch2) {
751 pr_err("create_singlethread_workqueue() for Video FAILED!\n");
752 return -ENOMEM;
753 }
754 /*
755 * 656/VIP SRC Upstream Channel I & J and 7 -
756 * Host Bus Interface for channel A-C
757 */
758 tmp = cx_read(VID_CH_MODE_SEL);
759 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
760
761 dev->_is_running_ch2 = 0;
762 dev->_frame_count_ch2 = 0;
763 dev->_file_status_ch2 = RESET_STATUS;
764 dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
765 dev->_pixel_format_ch2 = pixel_format;
766 dev->_line_size_ch2 =
767 (dev->_pixel_format_ch2 ==
768 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
769 data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
770 risc_buffer_size =
771 dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
772
773 if (dev->input_filename_ch2) {
774 str_length = strlen(dev->input_filename_ch2);
775 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
776
777 if (!dev->_filename_ch2)
778 goto error;
779
780 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
781 str_length + 1);
782 } else {
783 str_length = strlen(dev->_defaultname_ch2);
784 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
785
786 if (!dev->_filename_ch2)
787 goto error;
788
789 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
790 str_length + 1);
791 }
792
793 /* Default if filename is empty string */
794 if (strcmp(dev->input_filename_ch2, "") == 0) {
795 if (dev->_isNTSC_ch2) {
796 dev->_filename_ch2 =
797 (dev->_pixel_format_ch2 ==
798 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
799 "/root/vidtest.yuv";
800 } else {
801 dev->_filename_ch2 =
802 (dev->_pixel_format_ch2 ==
803 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
804 "/root/pal422.yuv";
805 }
806 }
807
808 retval =
809 cx25821_sram_channel_setup_upstream(dev, sram_ch,
810 dev->_line_size_ch2, 0);
811
812 /* setup fifo + format */
813 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
814
815 dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
816 dev->upstream_databuf_size_ch2 = data_frame_size * 2;
817
818 /* Allocating buffers and prepare RISC program */
819 retval =
820 cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
821 dev->_line_size_ch2);
822 if (retval < 0) {
823 pr_err("%s: Failed to set up Video upstream buffers!\n",
824 dev->name);
825 goto error;
826 }
827
828 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
829
830 return 0;
831
832 error:
833 cx25821_dev_unregister(dev);
834
835 return err;
836}
diff --git a/drivers/staging/cx25821/cx25821-video-upstream-ch2.h b/drivers/staging/cx25821/cx25821-video-upstream-ch2.h
new file mode 100644
index 00000000000..029e8305724
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-video-upstream-ch2.h
@@ -0,0 +1,101 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/mutex.h>
24#include <linux/workqueue.h>
25
26#define OPEN_FILE_1 0
27#define NUM_PROGS 8
28#define NUM_FRAMES 2
29#define ODD_FIELD 0
30#define EVEN_FIELD 1
31#define TOP_OFFSET 0
32#define FIFO_DISABLE 0
33#define FIFO_ENABLE 1
34#define TEST_FRAMES 5
35#define END_OF_FILE 0
36#define IN_PROGRESS 1
37#define RESET_STATUS -1
38#define NUM_NO_OPS 5
39
40/* PAL and NTSC line sizes and number of lines. */
41#define WIDTH_D1 720
42#define NTSC_LINES_PER_FRAME 480
43#define PAL_LINES_PER_FRAME 576
44#define PAL_LINE_SZ 1440
45#define Y422_LINE_SZ 1440
46#define Y411_LINE_SZ 1080
47#define NTSC_FIELD_HEIGHT 240
48#define NTSC_ODD_FLD_LINES 241
49#define PAL_FIELD_HEIGHT 288
50
51#define FRAME_SIZE_NTSC_Y422 (NTSC_LINES_PER_FRAME * Y422_LINE_SZ)
52#define FRAME_SIZE_NTSC_Y411 (NTSC_LINES_PER_FRAME * Y411_LINE_SZ)
53#define FRAME_SIZE_PAL_Y422 (PAL_LINES_PER_FRAME * Y422_LINE_SZ)
54#define FRAME_SIZE_PAL_Y411 (PAL_LINES_PER_FRAME * Y411_LINE_SZ)
55
56#define NTSC_DATA_BUF_SZ (Y422_LINE_SZ * NTSC_LINES_PER_FRAME)
57#define PAL_DATA_BUF_SZ (Y422_LINE_SZ * PAL_LINES_PER_FRAME)
58
59#define RISC_WRITECR_INSTRUCTION_SIZE 16
60#define RISC_SYNC_INSTRUCTION_SIZE 4
61#define JUMP_INSTRUCTION_SIZE 12
62#define MAXSIZE_NO_OPS 36
63#define DWORD_SIZE 4
64
65#define USE_RISC_NOOP_VIDEO 1
66
67#ifdef USE_RISC_NOOP_VIDEO
68#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \
69 RISC_SYNC_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
70
71#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE)
72
73#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
74 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE)
75
76#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \
77 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
78
79#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \
80 JUMP_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
81
82#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE))
83
84#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
85 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE)
86#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \
87 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
88#endif
89
90#ifndef USE_RISC_NOOP_VIDEO
91#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE)
92#define PAL_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + PAL_US_VID_PROG_SIZE))
93#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
94 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
95#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE)
96#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE)
97#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
98#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE))
99#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
100 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
101#endif
diff --git a/drivers/staging/cx25821/cx25821-video-upstream.c b/drivers/staging/cx25821/cx25821-video-upstream.c
new file mode 100644
index 00000000000..eb0172bf39d
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-video-upstream.c
@@ -0,0 +1,889 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24
25#include "cx25821-video.h"
26#include "cx25821-video-upstream.h"
27
28#include <linux/fs.h>
29#include <linux/errno.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <linux/module.h>
33#include <linux/syscalls.h>
34#include <linux/file.h>
35#include <linux/fcntl.h>
36#include <linux/slab.h>
37#include <linux/uaccess.h>
38
39MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
40MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
41MODULE_LICENSE("GPL");
42
43static int _intr_msk =
44 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
45
46int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
47 struct sram_channel *ch,
48 unsigned int bpl, u32 risc)
49{
50 unsigned int i, lines;
51 u32 cdt;
52
53 if (ch->cmds_start == 0) {
54 cx_write(ch->ptr1_reg, 0);
55 cx_write(ch->ptr2_reg, 0);
56 cx_write(ch->cnt2_reg, 0);
57 cx_write(ch->cnt1_reg, 0);
58 return 0;
59 }
60
61 bpl = (bpl + 7) & ~7; /* alignment */
62 cdt = ch->cdt;
63 lines = ch->fifo_size / bpl;
64
65 if (lines > 4)
66 lines = 4;
67
68 BUG_ON(lines < 2);
69
70 /* write CDT */
71 for (i = 0; i < lines; i++) {
72 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
73 cx_write(cdt + 16 * i + 4, 0);
74 cx_write(cdt + 16 * i + 8, 0);
75 cx_write(cdt + 16 * i + 12, 0);
76 }
77
78 /* write CMDS */
79 cx_write(ch->cmds_start + 0, risc);
80
81 cx_write(ch->cmds_start + 4, 0);
82 cx_write(ch->cmds_start + 8, cdt);
83 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
84 cx_write(ch->cmds_start + 16, ch->ctrl_start);
85
86 cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
87
88 for (i = 24; i < 80; i += 4)
89 cx_write(ch->cmds_start + i, 0);
90
91 /* fill registers */
92 cx_write(ch->ptr1_reg, ch->fifo_start);
93 cx_write(ch->ptr2_reg, cdt);
94 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
95 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
96
97 return 0;
98}
99
100static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev,
101 __le32 *rp, unsigned int offset,
102 unsigned int bpl, u32 sync_line,
103 unsigned int lines, int fifo_enable,
104 int field_type)
105{
106 unsigned int line, i;
107 int dist_betwn_starts = bpl * 2;
108
109 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
110
111 if (USE_RISC_NOOP_VIDEO) {
112 for (i = 0; i < NUM_NO_OPS; i++)
113 *(rp++) = cpu_to_le32(RISC_NOOP);
114 }
115
116 /* scan lines */
117 for (line = 0; line < lines; line++) {
118 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
119 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset);
120 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
121
122 if ((lines <= NTSC_FIELD_HEIGHT)
123 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
124 offset += dist_betwn_starts;
125 }
126 }
127
128 return rp;
129}
130
131static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp,
132 dma_addr_t databuf_phys_addr,
133 unsigned int offset, u32 sync_line,
134 unsigned int bpl, unsigned int lines,
135 int fifo_enable, int field_type)
136{
137 unsigned int line, i;
138 struct sram_channel *sram_ch =
139 dev->channels[dev->_channel_upstream_select].sram_channels;
140 int dist_betwn_starts = bpl * 2;
141
142 /* sync instruction */
143 if (sync_line != NO_SYNC_LINE)
144 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
145
146 if (USE_RISC_NOOP_VIDEO) {
147 for (i = 0; i < NUM_NO_OPS; i++)
148 *(rp++) = cpu_to_le32(RISC_NOOP);
149 }
150
151 /* scan lines */
152 for (line = 0; line < lines; line++) {
153 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
154 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
155 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
156
157 if ((lines <= NTSC_FIELD_HEIGHT)
158 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC))
159 /* to skip the other field line */
160 offset += dist_betwn_starts;
161
162 /* check if we need to enable the FIFO after the first 4 lines
163 * For the upstream video channel, the risc engine will enable
164 * the FIFO. */
165 if (fifo_enable && line == 3) {
166 *(rp++) = RISC_WRITECR;
167 *(rp++) = sram_ch->dma_ctl;
168 *(rp++) = FLD_VID_FIFO_EN;
169 *(rp++) = 0x00000001;
170 }
171 }
172
173 return rp;
174}
175
176int cx25821_risc_buffer_upstream(struct cx25821_dev *dev,
177 struct pci_dev *pci,
178 unsigned int top_offset,
179 unsigned int bpl, unsigned int lines)
180{
181 __le32 *rp;
182 int fifo_enable = 0;
183 /* get line count for single field */
184 int singlefield_lines = lines >> 1;
185 int odd_num_lines = singlefield_lines;
186 int frame = 0;
187 int frame_size = 0;
188 int databuf_offset = 0;
189 int risc_program_size = 0;
190 int risc_flag = RISC_CNT_RESET;
191 unsigned int bottom_offset = bpl;
192 dma_addr_t risc_phys_jump_addr;
193
194 if (dev->_isNTSC) {
195 odd_num_lines = singlefield_lines + 1;
196 risc_program_size = FRAME1_VID_PROG_SIZE;
197 frame_size =
198 (bpl ==
199 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
200 FRAME_SIZE_NTSC_Y422;
201 } else {
202 risc_program_size = PAL_VID_PROG_SIZE;
203 frame_size =
204 (bpl ==
205 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
206 }
207
208 /* Virtual address of Risc buffer program */
209 rp = dev->_dma_virt_addr;
210
211 for (frame = 0; frame < NUM_FRAMES; frame++) {
212 databuf_offset = frame_size * frame;
213
214 if (UNSET != top_offset) {
215 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
216 rp = cx25821_risc_field_upstream(dev, rp,
217 dev->
218 _data_buf_phys_addr +
219 databuf_offset,
220 top_offset, 0, bpl,
221 odd_num_lines,
222 fifo_enable,
223 ODD_FIELD);
224 }
225
226 fifo_enable = FIFO_DISABLE;
227
228 /* Even Field */
229 rp = cx25821_risc_field_upstream(dev, rp,
230 dev->_data_buf_phys_addr +
231 databuf_offset, bottom_offset,
232 0x200, bpl, singlefield_lines,
233 fifo_enable, EVEN_FIELD);
234
235 if (frame == 0) {
236 risc_flag = RISC_CNT_RESET;
237 risc_phys_jump_addr =
238 dev->_dma_phys_start_addr + risc_program_size;
239 } else {
240 risc_phys_jump_addr = dev->_dma_phys_start_addr;
241 risc_flag = RISC_CNT_INC;
242 }
243
244 /* Loop to 2ndFrameRISC or to Start of Risc
245 * program & generate IRQ
246 */
247 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
248 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
249 *(rp++) = cpu_to_le32(0);
250 }
251
252 return 0;
253}
254
255void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
256{
257 struct sram_channel *sram_ch =
258 dev->channels[VID_UPSTREAM_SRAM_CHANNEL_I].sram_channels;
259 u32 tmp = 0;
260
261 if (!dev->_is_running) {
262 pr_info("No video file is currently running so return!\n");
263 return;
264 }
265 /* Disable RISC interrupts */
266 tmp = cx_read(sram_ch->int_msk);
267 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
268
269 /* Turn OFF risc and fifo enable */
270 tmp = cx_read(sram_ch->dma_ctl);
271 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
272
273 /* Clear data buffer memory */
274 if (dev->_data_buf_virt_addr)
275 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
276
277 dev->_is_running = 0;
278 dev->_is_first_frame = 0;
279 dev->_frame_count = 0;
280 dev->_file_status = END_OF_FILE;
281
282 kfree(dev->_irq_queues);
283 dev->_irq_queues = NULL;
284
285 kfree(dev->_filename);
286
287 tmp = cx_read(VID_CH_MODE_SEL);
288 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
289}
290
291void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
292{
293 if (dev->_is_running)
294 cx25821_stop_upstream_video_ch1(dev);
295
296 if (dev->_dma_virt_addr) {
297 pci_free_consistent(dev->pci, dev->_risc_size,
298 dev->_dma_virt_addr, dev->_dma_phys_addr);
299 dev->_dma_virt_addr = NULL;
300 }
301
302 if (dev->_data_buf_virt_addr) {
303 pci_free_consistent(dev->pci, dev->_data_buf_size,
304 dev->_data_buf_virt_addr,
305 dev->_data_buf_phys_addr);
306 dev->_data_buf_virt_addr = NULL;
307 }
308}
309
310int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch)
311{
312 struct file *myfile;
313 int frame_index_temp = dev->_frame_index;
314 int i = 0;
315 int line_size =
316 (dev->_pixel_format ==
317 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
318 int frame_size = 0;
319 int frame_offset = 0;
320 ssize_t vfs_read_retval = 0;
321 char mybuf[line_size];
322 loff_t file_offset;
323 loff_t pos;
324 mm_segment_t old_fs;
325
326 if (dev->_file_status == END_OF_FILE)
327 return 0;
328
329 if (dev->_isNTSC) {
330 frame_size =
331 (line_size ==
332 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
333 FRAME_SIZE_NTSC_Y422;
334 } else {
335 frame_size =
336 (line_size ==
337 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
338 }
339
340 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
341 file_offset = dev->_frame_count * frame_size;
342
343 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
344
345 if (IS_ERR(myfile)) {
346 const int open_errno = -PTR_ERR(myfile);
347 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
348 __func__, dev->_filename, open_errno);
349 return PTR_ERR(myfile);
350 } else {
351 if (!(myfile->f_op)) {
352 pr_err("%s(): File has no file operations registered!\n",
353 __func__);
354 filp_close(myfile, NULL);
355 return -EIO;
356 }
357
358 if (!myfile->f_op->read) {
359 pr_err("%s(): File has no READ operations registered!\n",
360 __func__);
361 filp_close(myfile, NULL);
362 return -EIO;
363 }
364
365 pos = myfile->f_pos;
366 old_fs = get_fs();
367 set_fs(KERNEL_DS);
368
369 for (i = 0; i < dev->_lines_count; i++) {
370 pos = file_offset;
371
372 vfs_read_retval =
373 vfs_read(myfile, mybuf, line_size, &pos);
374
375 if (vfs_read_retval > 0 && vfs_read_retval == line_size
376 && dev->_data_buf_virt_addr != NULL) {
377 memcpy((void *)(dev->_data_buf_virt_addr +
378 frame_offset / 4), mybuf,
379 vfs_read_retval);
380 }
381
382 file_offset += vfs_read_retval;
383 frame_offset += vfs_read_retval;
384
385 if (vfs_read_retval < line_size) {
386 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
387 __func__);
388 break;
389 }
390 }
391
392 if (i > 0)
393 dev->_frame_count++;
394
395 dev->_file_status =
396 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
397
398 set_fs(old_fs);
399 filp_close(myfile, NULL);
400 }
401
402 return 0;
403}
404
405static void cx25821_vidups_handler(struct work_struct *work)
406{
407 struct cx25821_dev *dev =
408 container_of(work, struct cx25821_dev, _irq_work_entry);
409
410 if (!dev) {
411 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
412 __func__);
413 return;
414 }
415
416 cx25821_get_frame(dev,
417 dev->channels[dev->_channel_upstream_select].
418 sram_channels);
419}
420
421int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch)
422{
423 struct file *myfile;
424 int i = 0, j = 0;
425 int line_size =
426 (dev->_pixel_format ==
427 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
428 ssize_t vfs_read_retval = 0;
429 char mybuf[line_size];
430 loff_t pos;
431 loff_t offset = (unsigned long)0;
432 mm_segment_t old_fs;
433
434 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
435
436 if (IS_ERR(myfile)) {
437 const int open_errno = -PTR_ERR(myfile);
438 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
439 __func__, dev->_filename, open_errno);
440 return PTR_ERR(myfile);
441 } else {
442 if (!(myfile->f_op)) {
443 pr_err("%s(): File has no file operations registered!\n",
444 __func__);
445 filp_close(myfile, NULL);
446 return -EIO;
447 }
448
449 if (!myfile->f_op->read) {
450 pr_err("%s(): File has no READ operations registered! Returning\n",
451 __func__);
452 filp_close(myfile, NULL);
453 return -EIO;
454 }
455
456 pos = myfile->f_pos;
457 old_fs = get_fs();
458 set_fs(KERNEL_DS);
459
460 for (j = 0; j < NUM_FRAMES; j++) {
461 for (i = 0; i < dev->_lines_count; i++) {
462 pos = offset;
463
464 vfs_read_retval =
465 vfs_read(myfile, mybuf, line_size, &pos);
466
467 if (vfs_read_retval > 0
468 && vfs_read_retval == line_size
469 && dev->_data_buf_virt_addr != NULL) {
470 memcpy((void *)(dev->
471 _data_buf_virt_addr +
472 offset / 4), mybuf,
473 vfs_read_retval);
474 }
475
476 offset += vfs_read_retval;
477
478 if (vfs_read_retval < line_size) {
479 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
480 __func__);
481 break;
482 }
483 }
484
485 if (i > 0)
486 dev->_frame_count++;
487
488 if (vfs_read_retval < line_size)
489 break;
490 }
491
492 dev->_file_status =
493 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
494
495 set_fs(old_fs);
496 myfile->f_pos = 0;
497 filp_close(myfile, NULL);
498 }
499
500 return 0;
501}
502
503int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
504 struct sram_channel *sram_ch, int bpl)
505{
506 int ret = 0;
507 dma_addr_t dma_addr;
508 dma_addr_t data_dma_addr;
509
510 if (dev->_dma_virt_addr != NULL) {
511 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size,
512 dev->_dma_virt_addr, dev->_dma_phys_addr);
513 }
514
515 dev->_dma_virt_addr =
516 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size,
517 &dma_addr);
518 dev->_dma_virt_start_addr = dev->_dma_virt_addr;
519 dev->_dma_phys_start_addr = dma_addr;
520 dev->_dma_phys_addr = dma_addr;
521 dev->_risc_size = dev->upstream_riscbuf_size;
522
523 if (!dev->_dma_virt_addr) {
524 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
525 return -ENOMEM;
526 }
527
528 /* Clear memory at address */
529 memset(dev->_dma_virt_addr, 0, dev->_risc_size);
530
531 if (dev->_data_buf_virt_addr != NULL) {
532 pci_free_consistent(dev->pci, dev->upstream_databuf_size,
533 dev->_data_buf_virt_addr,
534 dev->_data_buf_phys_addr);
535 }
536 /* For Video Data buffer allocation */
537 dev->_data_buf_virt_addr =
538 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size,
539 &data_dma_addr);
540 dev->_data_buf_phys_addr = data_dma_addr;
541 dev->_data_buf_size = dev->upstream_databuf_size;
542
543 if (!dev->_data_buf_virt_addr) {
544 pr_err("FAILED to allocate memory for data buffer! Returning\n");
545 return -ENOMEM;
546 }
547
548 /* Clear memory at address */
549 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
550
551 ret = cx25821_openfile(dev, sram_ch);
552 if (ret < 0)
553 return ret;
554
555 /* Create RISC programs */
556 ret =
557 cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl,
558 dev->_lines_count);
559 if (ret < 0) {
560 pr_info("Failed creating Video Upstream Risc programs!\n");
561 goto error;
562 }
563
564 return 0;
565
566error:
567 return ret;
568}
569
570int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num,
571 u32 status)
572{
573 u32 int_msk_tmp;
574 struct sram_channel *channel = dev->channels[chan_num].sram_channels;
575 int singlefield_lines = NTSC_FIELD_HEIGHT;
576 int line_size_in_bytes = Y422_LINE_SZ;
577 int odd_risc_prog_size = 0;
578 dma_addr_t risc_phys_jump_addr;
579 __le32 *rp;
580
581 if (status & FLD_VID_SRC_RISC1) {
582 /* We should only process one program per call */
583 u32 prog_cnt = cx_read(channel->gpcnt);
584
585 /* Since we've identified our IRQ, clear our bits from the
586 * interrupt mask and interrupt status registers */
587 int_msk_tmp = cx_read(channel->int_msk);
588 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
589 cx_write(channel->int_stat, _intr_msk);
590
591 spin_lock(&dev->slock);
592
593 dev->_frame_index = prog_cnt;
594
595 queue_work(dev->_irq_queues, &dev->_irq_work_entry);
596
597 if (dev->_is_first_frame) {
598 dev->_is_first_frame = 0;
599
600 if (dev->_isNTSC) {
601 singlefield_lines += 1;
602 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
603 } else {
604 singlefield_lines = PAL_FIELD_HEIGHT;
605 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
606 }
607
608 if (dev->_dma_virt_start_addr != NULL) {
609 line_size_in_bytes =
610 (dev->_pixel_format ==
611 PIXEL_FRMT_411) ? Y411_LINE_SZ :
612 Y422_LINE_SZ;
613 risc_phys_jump_addr =
614 dev->_dma_phys_start_addr +
615 odd_risc_prog_size;
616
617 rp = cx25821_update_riscprogram(dev,
618 dev->
619 _dma_virt_start_addr,
620 TOP_OFFSET,
621 line_size_in_bytes,
622 0x0,
623 singlefield_lines,
624 FIFO_DISABLE,
625 ODD_FIELD);
626
627 /* Jump to Even Risc program of 1st Frame */
628 *(rp++) = cpu_to_le32(RISC_JUMP);
629 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
630 *(rp++) = cpu_to_le32(0);
631 }
632 }
633
634 spin_unlock(&dev->slock);
635 } else {
636 if (status & FLD_VID_SRC_UF)
637 pr_err("%s(): Video Received Underflow Error Interrupt!\n",
638 __func__);
639
640 if (status & FLD_VID_SRC_SYNC)
641 pr_err("%s(): Video Received Sync Error Interrupt!\n",
642 __func__);
643
644 if (status & FLD_VID_SRC_OPC_ERR)
645 pr_err("%s(): Video Received OpCode Error Interrupt!\n",
646 __func__);
647 }
648
649 if (dev->_file_status == END_OF_FILE) {
650 pr_err("EOF Channel 1 Framecount = %d\n", dev->_frame_count);
651 return -1;
652 }
653 /* ElSE, set the interrupt mask register, re-enable irq. */
654 int_msk_tmp = cx_read(channel->int_msk);
655 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
656
657 return 0;
658}
659
660static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
661{
662 struct cx25821_dev *dev = dev_id;
663 u32 msk_stat, vid_status;
664 int handled = 0;
665 int channel_num = 0;
666 struct sram_channel *sram_ch;
667
668 if (!dev)
669 return -1;
670
671 channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
672
673 sram_ch = dev->channels[channel_num].sram_channels;
674
675 msk_stat = cx_read(sram_ch->int_mstat);
676 vid_status = cx_read(sram_ch->int_stat);
677
678 /* Only deal with our interrupt */
679 if (vid_status) {
680 handled =
681 cx25821_video_upstream_irq(dev, channel_num, vid_status);
682 }
683
684 if (handled < 0)
685 cx25821_stop_upstream_video_ch1(dev);
686 else
687 handled += handled;
688
689 return IRQ_RETVAL(handled);
690}
691
692void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch,
693 int pix_format)
694{
695 int width = WIDTH_D1;
696 int height = dev->_lines_count;
697 int num_lines, odd_num_lines;
698 u32 value;
699 int vip_mode = OUTPUT_FRMT_656;
700
701 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
702 value &= 0xFFFFFFEF;
703 value |= dev->_isNTSC ? 0 : 0x10;
704 cx_write(ch->vid_fmt_ctl, value);
705
706 /* set number of active pixels in each line.
707 * Default is 720 pixels in both NTSC and PAL format */
708 cx_write(ch->vid_active_ctl1, width);
709
710 num_lines = (height / 2) & 0x3FF;
711 odd_num_lines = num_lines;
712
713 if (dev->_isNTSC)
714 odd_num_lines += 1;
715
716 value = (num_lines << 16) | odd_num_lines;
717
718 /* set number of active lines in field 0 (top) and field 1 (bottom) */
719 cx_write(ch->vid_active_ctl2, value);
720
721 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
722}
723
724int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
725 struct sram_channel *sram_ch)
726{
727 u32 tmp = 0;
728 int err = 0;
729
730 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
731 * channel A-C
732 */
733 tmp = cx_read(VID_CH_MODE_SEL);
734 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
735
736 /* Set the physical start address of the RISC program in the initial
737 * program counter(IPC) member of the cmds.
738 */
739 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
740 /* Risc IPC High 64 bits 63-32 */
741 cx_write(sram_ch->cmds_start + 4, 0);
742
743 /* reset counter */
744 cx_write(sram_ch->gpcnt_ctl, 3);
745
746 /* Clear our bits from the interrupt status register. */
747 cx_write(sram_ch->int_stat, _intr_msk);
748
749 /* Set the interrupt mask register, enable irq. */
750 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
751 tmp = cx_read(sram_ch->int_msk);
752 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
753
754 err =
755 request_irq(dev->pci->irq, cx25821_upstream_irq,
756 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
757 if (err < 0) {
758 pr_err("%s: can't get upstream IRQ %d\n",
759 dev->name, dev->pci->irq);
760 goto fail_irq;
761 }
762
763 /* Start the DMA engine */
764 tmp = cx_read(sram_ch->dma_ctl);
765 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
766
767 dev->_is_running = 1;
768 dev->_is_first_frame = 1;
769
770 return 0;
771
772fail_irq:
773 cx25821_dev_unregister(dev);
774 return err;
775}
776
777int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
778 int pixel_format)
779{
780 struct sram_channel *sram_ch;
781 u32 tmp;
782 int retval = 0;
783 int err = 0;
784 int data_frame_size = 0;
785 int risc_buffer_size = 0;
786 int str_length = 0;
787
788 if (dev->_is_running) {
789 pr_info("Video Channel is still running so return!\n");
790 return 0;
791 }
792
793 dev->_channel_upstream_select = channel_select;
794 sram_ch = dev->channels[channel_select].sram_channels;
795
796 INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
797 dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
798
799 if (!dev->_irq_queues) {
800 pr_err("create_singlethread_workqueue() for Video FAILED!\n");
801 return -ENOMEM;
802 }
803 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
804 * channel A-C
805 */
806 tmp = cx_read(VID_CH_MODE_SEL);
807 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
808
809 dev->_is_running = 0;
810 dev->_frame_count = 0;
811 dev->_file_status = RESET_STATUS;
812 dev->_lines_count = dev->_isNTSC ? 480 : 576;
813 dev->_pixel_format = pixel_format;
814 dev->_line_size =
815 (dev->_pixel_format ==
816 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
817 data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
818 risc_buffer_size =
819 dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
820
821 if (dev->input_filename) {
822 str_length = strlen(dev->input_filename);
823 dev->_filename = kmalloc(str_length + 1, GFP_KERNEL);
824
825 if (!dev->_filename)
826 goto error;
827
828 memcpy(dev->_filename, dev->input_filename, str_length + 1);
829 } else {
830 str_length = strlen(dev->_defaultname);
831 dev->_filename = kmalloc(str_length + 1, GFP_KERNEL);
832
833 if (!dev->_filename)
834 goto error;
835
836 memcpy(dev->_filename, dev->_defaultname, str_length + 1);
837 }
838
839 /* Default if filename is empty string */
840 if (strcmp(dev->input_filename, "") == 0) {
841 if (dev->_isNTSC) {
842 dev->_filename =
843 (dev->_pixel_format ==
844 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
845 "/root/vidtest.yuv";
846 } else {
847 dev->_filename =
848 (dev->_pixel_format ==
849 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
850 "/root/pal422.yuv";
851 }
852 }
853
854 dev->_is_running = 0;
855 dev->_frame_count = 0;
856 dev->_file_status = RESET_STATUS;
857 dev->_lines_count = dev->_isNTSC ? 480 : 576;
858 dev->_pixel_format = pixel_format;
859 dev->_line_size =
860 (dev->_pixel_format ==
861 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
862
863 retval =
864 cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size,
865 0);
866
867 /* setup fifo + format */
868 cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
869
870 dev->upstream_riscbuf_size = risc_buffer_size * 2;
871 dev->upstream_databuf_size = data_frame_size * 2;
872
873 /* Allocating buffers and prepare RISC program */
874 retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
875 if (retval < 0) {
876 pr_err("%s: Failed to set up Video upstream buffers!\n",
877 dev->name);
878 goto error;
879 }
880
881 cx25821_start_video_dma_upstream(dev, sram_ch);
882
883 return 0;
884
885error:
886 cx25821_dev_unregister(dev);
887
888 return err;
889}
diff --git a/drivers/staging/cx25821/cx25821-video-upstream.h b/drivers/staging/cx25821/cx25821-video-upstream.h
new file mode 100644
index 00000000000..f0b3ac0880a
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-video-upstream.h
@@ -0,0 +1,109 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/mutex.h>
24#include <linux/workqueue.h>
25
26#define OUTPUT_FRMT_656 0
27#define OPEN_FILE_1 0
28#define NUM_PROGS 8
29#define NUM_FRAMES 2
30#define ODD_FIELD 0
31#define EVEN_FIELD 1
32#define TOP_OFFSET 0
33#define FIFO_DISABLE 0
34#define FIFO_ENABLE 1
35#define TEST_FRAMES 5
36#define END_OF_FILE 0
37#define IN_PROGRESS 1
38#define RESET_STATUS -1
39#define NUM_NO_OPS 5
40
41/* PAL and NTSC line sizes and number of lines. */
42#define WIDTH_D1 720
43#define NTSC_LINES_PER_FRAME 480
44#define PAL_LINES_PER_FRAME 576
45#define PAL_LINE_SZ 1440
46#define Y422_LINE_SZ 1440
47#define Y411_LINE_SZ 1080
48#define NTSC_FIELD_HEIGHT 240
49#define NTSC_ODD_FLD_LINES 241
50#define PAL_FIELD_HEIGHT 288
51
52#define FRAME_SIZE_NTSC_Y422 (NTSC_LINES_PER_FRAME * Y422_LINE_SZ)
53#define FRAME_SIZE_NTSC_Y411 (NTSC_LINES_PER_FRAME * Y411_LINE_SZ)
54#define FRAME_SIZE_PAL_Y422 (PAL_LINES_PER_FRAME * Y422_LINE_SZ)
55#define FRAME_SIZE_PAL_Y411 (PAL_LINES_PER_FRAME * Y411_LINE_SZ)
56
57#define NTSC_DATA_BUF_SZ (Y422_LINE_SZ * NTSC_LINES_PER_FRAME)
58#define PAL_DATA_BUF_SZ (Y422_LINE_SZ * PAL_LINES_PER_FRAME)
59
60#define RISC_WRITECR_INSTRUCTION_SIZE 16
61#define RISC_SYNC_INSTRUCTION_SIZE 4
62#define JUMP_INSTRUCTION_SIZE 12
63#define MAXSIZE_NO_OPS 36
64#define DWORD_SIZE 4
65
66#define USE_RISC_NOOP_VIDEO 1
67
68#ifdef USE_RISC_NOOP_VIDEO
69#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \
70 RISC_SYNC_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
71
72#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE)
73
74#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
75 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE)
76
77#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \
78 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
79
80#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + \
81 RISC_WRITECR_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
82
83#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \
84 JUMP_INSTRUCTION_SIZE + NUM_NO_OPS*DWORD_SIZE)
85
86#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE))
87
88#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
89 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE + 2*NUM_NO_OPS*DWORD_SIZE)
90
91#endif
92
93#ifndef USE_RISC_NOOP_VIDEO
94#define PAL_US_VID_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + \
95 RISC_SYNC_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
96
97#define PAL_RISC_BUF_SIZE (2 * PAL_US_VID_PROG_SIZE)
98
99#define PAL_VID_PROG_SIZE ((PAL_FIELD_HEIGHT*2) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
100 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
101
102#define ODD_FLD_PAL_PROG_SIZE ((PAL_FIELD_HEIGHT) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE)
103#define ODD_FLD_NTSC_PROG_SIZE ((NTSC_ODD_FLD_LINES) * 3 * DWORD_SIZE + RISC_SYNC_INSTRUCTION_SIZE + RISC_WRITECR_INSTRUCTION_SIZE)
104
105#define NTSC_US_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + 1) * 3 * DWORD_SIZE + RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
106#define NTSC_RISC_BUF_SIZE (2 * (RISC_SYNC_INSTRUCTION_SIZE + NTSC_US_VID_PROG_SIZE))
107#define FRAME1_VID_PROG_SIZE ((NTSC_ODD_FLD_LINES + NTSC_FIELD_HEIGHT) * 3 * DWORD_SIZE + 2*RISC_SYNC_INSTRUCTION_SIZE + \
108 RISC_WRITECR_INSTRUCTION_SIZE + JUMP_INSTRUCTION_SIZE)
109#endif
diff --git a/drivers/staging/cx25821/cx25821-video.c b/drivers/staging/cx25821/cx25821-video.c
new file mode 100644
index 00000000000..7a0304a8573
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-video.c
@@ -0,0 +1,2008 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7 * Parts adapted/taken from Eduardo Moscoso Rubino
8 * Copyright (C) 2009 Eduardo Moscoso Rubino <moscoso@TopoLogica.com>
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 *
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28
29#include "cx25821-video.h"
30
31MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
32MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
33MODULE_LICENSE("GPL");
34
35static unsigned int video_nr[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
36static unsigned int radio_nr[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
37
38module_param_array(video_nr, int, NULL, 0444);
39module_param_array(radio_nr, int, NULL, 0444);
40
41MODULE_PARM_DESC(video_nr, "video device numbers");
42MODULE_PARM_DESC(radio_nr, "radio device numbers");
43
44static unsigned int video_debug = VIDEO_DEBUG;
45module_param(video_debug, int, 0644);
46MODULE_PARM_DESC(video_debug, "enable debug messages [video]");
47
48static unsigned int irq_debug;
49module_param(irq_debug, int, 0644);
50MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]");
51
52unsigned int vid_limit = 16;
53module_param(vid_limit, int, 0644);
54MODULE_PARM_DESC(vid_limit, "capture memory limit in megabytes");
55
56static void cx25821_init_controls(struct cx25821_dev *dev, int chan_num);
57
58static const struct v4l2_file_operations video_fops;
59static const struct v4l2_ioctl_ops video_ioctl_ops;
60
61#define FORMAT_FLAGS_PACKED 0x01
62
63struct cx25821_fmt formats[] = {
64 {
65 .name = "8 bpp, gray",
66 .fourcc = V4L2_PIX_FMT_GREY,
67 .depth = 8,
68 .flags = FORMAT_FLAGS_PACKED,
69 }, {
70 .name = "4:1:1, packed, Y41P",
71 .fourcc = V4L2_PIX_FMT_Y41P,
72 .depth = 12,
73 .flags = FORMAT_FLAGS_PACKED,
74 }, {
75 .name = "4:2:2, packed, YUYV",
76 .fourcc = V4L2_PIX_FMT_YUYV,
77 .depth = 16,
78 .flags = FORMAT_FLAGS_PACKED,
79 }, {
80 .name = "4:2:2, packed, UYVY",
81 .fourcc = V4L2_PIX_FMT_UYVY,
82 .depth = 16,
83 .flags = FORMAT_FLAGS_PACKED,
84 }, {
85 .name = "4:2:0, YUV",
86 .fourcc = V4L2_PIX_FMT_YUV420,
87 .depth = 12,
88 .flags = FORMAT_FLAGS_PACKED,
89 },
90};
91
92int cx25821_get_format_size(void)
93{
94 return ARRAY_SIZE(formats);
95}
96
97struct cx25821_fmt *cx25821_format_by_fourcc(unsigned int fourcc)
98{
99 unsigned int i;
100
101 if (fourcc == V4L2_PIX_FMT_Y41P || fourcc == V4L2_PIX_FMT_YUV411P) {
102 return formats + 1;
103 }
104
105 for (i = 0; i < ARRAY_SIZE(formats); i++)
106 if (formats[i].fourcc == fourcc)
107 return formats + i;
108
109 pr_err("%s(0x%08x) NOT FOUND\n", __func__, fourcc);
110 return NULL;
111}
112
113void cx25821_dump_video_queue(struct cx25821_dev *dev, struct cx25821_dmaqueue *q)
114{
115 struct cx25821_buffer *buf;
116 struct list_head *item;
117 dprintk(1, "%s()\n", __func__);
118
119 if (!list_empty(&q->active)) {
120 list_for_each(item, &q->active)
121 buf = list_entry(item, struct cx25821_buffer, vb.queue);
122 }
123
124 if (!list_empty(&q->queued)) {
125 list_for_each(item, &q->queued)
126 buf = list_entry(item, struct cx25821_buffer, vb.queue);
127 }
128
129}
130
131void cx25821_video_wakeup(struct cx25821_dev *dev, struct cx25821_dmaqueue *q,
132 u32 count)
133{
134 struct cx25821_buffer *buf;
135 int bc;
136
137 for (bc = 0;; bc++) {
138 if (list_empty(&q->active)) {
139 dprintk(1, "bc=%d (=0: active empty)\n", bc);
140 break;
141 }
142
143 buf =
144 list_entry(q->active.next, struct cx25821_buffer, vb.queue);
145
146 /* count comes from the hw and it is 16bit wide --
147 * this trick handles wrap-arounds correctly for
148 * up to 32767 buffers in flight... */
149 if ((s16) (count - buf->count) < 0) {
150 break;
151 }
152
153 do_gettimeofday(&buf->vb.ts);
154 buf->vb.state = VIDEOBUF_DONE;
155 list_del(&buf->vb.queue);
156 wake_up(&buf->vb.done);
157 }
158
159 if (list_empty(&q->active))
160 del_timer(&q->timeout);
161 else
162 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
163 if (bc != 1)
164 pr_err("%s: %d buffers handled (should be 1)\n",
165 __func__, bc);
166}
167
168#ifdef TUNER_FLAG
169int cx25821_set_tvnorm(struct cx25821_dev *dev, v4l2_std_id norm)
170{
171 dprintk(1, "%s(norm = 0x%08x) name: [%s]\n",
172 __func__, (unsigned int)norm, v4l2_norm_to_name(norm));
173
174 dev->tvnorm = norm;
175
176 /* Tell the internal A/V decoder */
177 cx25821_call_all(dev, core, s_std, norm);
178
179 return 0;
180}
181#endif
182
183struct video_device *cx25821_vdev_init(struct cx25821_dev *dev,
184 struct pci_dev *pci,
185 struct video_device *template,
186 char *type)
187{
188 struct video_device *vfd;
189 dprintk(1, "%s()\n", __func__);
190
191 vfd = video_device_alloc();
192 if (NULL == vfd)
193 return NULL;
194 *vfd = *template;
195 vfd->v4l2_dev = &dev->v4l2_dev;
196 vfd->release = video_device_release;
197 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name, type,
198 cx25821_boards[dev->board].name);
199 video_set_drvdata(vfd, dev);
200 return vfd;
201}
202
203/*
204static int cx25821_ctrl_query(struct v4l2_queryctrl *qctrl)
205{
206 int i;
207
208 if (qctrl->id < V4L2_CID_BASE || qctrl->id >= V4L2_CID_LASTP1)
209 return -EINVAL;
210 for (i = 0; i < CX25821_CTLS; i++)
211 if (cx25821_ctls[i].v.id == qctrl->id)
212 break;
213 if (i == CX25821_CTLS) {
214 *qctrl = no_ctl;
215 return 0;
216 }
217 *qctrl = cx25821_ctls[i].v;
218 return 0;
219}
220*/
221
222/* resource management */
223int cx25821_res_get(struct cx25821_dev *dev, struct cx25821_fh *fh, unsigned int bit)
224{
225 dprintk(1, "%s()\n", __func__);
226 if (fh->resources & bit)
227 /* have it already allocated */
228 return 1;
229
230 /* is it free? */
231 mutex_lock(&dev->lock);
232 if (dev->channels[fh->channel_id].resources & bit) {
233 /* no, someone else uses it */
234 mutex_unlock(&dev->lock);
235 return 0;
236 }
237 /* it's free, grab it */
238 fh->resources |= bit;
239 dev->channels[fh->channel_id].resources |= bit;
240 dprintk(1, "res: get %d\n", bit);
241 mutex_unlock(&dev->lock);
242 return 1;
243}
244
245int cx25821_res_check(struct cx25821_fh *fh, unsigned int bit)
246{
247 return fh->resources & bit;
248}
249
250int cx25821_res_locked(struct cx25821_fh *fh, unsigned int bit)
251{
252 return fh->dev->channels[fh->channel_id].resources & bit;
253}
254
255void cx25821_res_free(struct cx25821_dev *dev, struct cx25821_fh *fh, unsigned int bits)
256{
257 BUG_ON((fh->resources & bits) != bits);
258 dprintk(1, "%s()\n", __func__);
259
260 mutex_lock(&dev->lock);
261 fh->resources &= ~bits;
262 dev->channels[fh->channel_id].resources &= ~bits;
263 dprintk(1, "res: put %d\n", bits);
264 mutex_unlock(&dev->lock);
265}
266
267int cx25821_video_mux(struct cx25821_dev *dev, unsigned int input)
268{
269 struct v4l2_routing route;
270 memset(&route, 0, sizeof(route));
271
272 dprintk(1, "%s(): video_mux: %d [vmux=%d, gpio=0x%x,0x%x,0x%x,0x%x]\n",
273 __func__, input, INPUT(input)->vmux, INPUT(input)->gpio0,
274 INPUT(input)->gpio1, INPUT(input)->gpio2, INPUT(input)->gpio3);
275 dev->input = input;
276
277 route.input = INPUT(input)->vmux;
278
279 /* Tell the internal A/V decoder */
280 cx25821_call_all(dev, video, s_routing, INPUT(input)->vmux, 0, 0);
281
282 return 0;
283}
284
285int cx25821_start_video_dma(struct cx25821_dev *dev,
286 struct cx25821_dmaqueue *q,
287 struct cx25821_buffer *buf,
288 struct sram_channel *channel)
289{
290 int tmp = 0;
291
292 /* setup fifo + format */
293 cx25821_sram_channel_setup(dev, channel, buf->bpl, buf->risc.dma);
294
295 /* reset counter */
296 cx_write(channel->gpcnt_ctl, 3);
297 q->count = 1;
298
299 /* enable irq */
300 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << channel->i));
301 cx_set(channel->int_msk, 0x11);
302
303 /* start dma */
304 cx_write(channel->dma_ctl, 0x11); /* FIFO and RISC enable */
305
306 /* make sure upstream setting if any is reversed */
307 tmp = cx_read(VID_CH_MODE_SEL);
308 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
309
310 return 0;
311}
312
313int cx25821_restart_video_queue(struct cx25821_dev *dev,
314 struct cx25821_dmaqueue *q,
315 struct sram_channel *channel)
316{
317 struct cx25821_buffer *buf, *prev;
318 struct list_head *item;
319
320 if (!list_empty(&q->active)) {
321 buf =
322 list_entry(q->active.next, struct cx25821_buffer, vb.queue);
323
324 cx25821_start_video_dma(dev, q, buf, channel);
325
326 list_for_each(item, &q->active) {
327 buf = list_entry(item, struct cx25821_buffer, vb.queue);
328 buf->count = q->count++;
329 }
330
331 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
332 return 0;
333 }
334
335 prev = NULL;
336 for (;;) {
337 if (list_empty(&q->queued))
338 return 0;
339
340 buf =
341 list_entry(q->queued.next, struct cx25821_buffer, vb.queue);
342
343 if (NULL == prev) {
344 list_move_tail(&buf->vb.queue, &q->active);
345 cx25821_start_video_dma(dev, q, buf, channel);
346 buf->vb.state = VIDEOBUF_ACTIVE;
347 buf->count = q->count++;
348 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
349 } else if (prev->vb.width == buf->vb.width &&
350 prev->vb.height == buf->vb.height &&
351 prev->fmt == buf->fmt) {
352 list_move_tail(&buf->vb.queue, &q->active);
353 buf->vb.state = VIDEOBUF_ACTIVE;
354 buf->count = q->count++;
355 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
356 prev->risc.jmp[2] = cpu_to_le32(0); /* Bits 63 - 32 */
357 } else {
358 return 0;
359 }
360 prev = buf;
361 }
362}
363
364void cx25821_vid_timeout(unsigned long data)
365{
366 struct cx25821_data *timeout_data = (struct cx25821_data *)data;
367 struct cx25821_dev *dev = timeout_data->dev;
368 struct sram_channel *channel = timeout_data->channel;
369 struct cx25821_dmaqueue *q = &dev->channels[channel->i].vidq;
370 struct cx25821_buffer *buf;
371 unsigned long flags;
372
373 /* cx25821_sram_channel_dump(dev, channel); */
374 cx_clear(channel->dma_ctl, 0x11);
375
376 spin_lock_irqsave(&dev->slock, flags);
377 while (!list_empty(&q->active)) {
378 buf =
379 list_entry(q->active.next, struct cx25821_buffer, vb.queue);
380 list_del(&buf->vb.queue);
381
382 buf->vb.state = VIDEOBUF_ERROR;
383 wake_up(&buf->vb.done);
384 }
385
386 cx25821_restart_video_queue(dev, q, channel);
387 spin_unlock_irqrestore(&dev->slock, flags);
388}
389
390int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status)
391{
392 u32 count = 0;
393 int handled = 0;
394 u32 mask;
395 struct sram_channel *channel = dev->channels[chan_num].sram_channels;
396
397 mask = cx_read(channel->int_msk);
398 if (0 == (status & mask))
399 return handled;
400
401 cx_write(channel->int_stat, status);
402
403 /* risc op code error */
404 if (status & (1 << 16)) {
405 pr_warn("%s, %s: video risc op code error\n",
406 dev->name, channel->name);
407 cx_clear(channel->dma_ctl, 0x11);
408 cx25821_sram_channel_dump(dev, channel);
409 }
410
411 /* risc1 y */
412 if (status & FLD_VID_DST_RISC1) {
413 spin_lock(&dev->slock);
414 count = cx_read(channel->gpcnt);
415 cx25821_video_wakeup(dev,
416 &dev->channels[channel->i].vidq, count);
417 spin_unlock(&dev->slock);
418 handled++;
419 }
420
421 /* risc2 y */
422 if (status & 0x10) {
423 dprintk(2, "stopper video\n");
424 spin_lock(&dev->slock);
425 cx25821_restart_video_queue(dev,
426 &dev->channels[channel->i].vidq,
427 channel);
428 spin_unlock(&dev->slock);
429 handled++;
430 }
431 return handled;
432}
433
434void cx25821_videoioctl_unregister(struct cx25821_dev *dev)
435{
436 if (dev->ioctl_dev) {
437 if (video_is_registered(dev->ioctl_dev))
438 video_unregister_device(dev->ioctl_dev);
439 else
440 video_device_release(dev->ioctl_dev);
441
442 dev->ioctl_dev = NULL;
443 }
444}
445
446void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num)
447{
448 cx_clear(PCI_INT_MSK, 1);
449
450 if (dev->channels[chan_num].video_dev) {
451 if (video_is_registered(dev->channels[chan_num].video_dev))
452 video_unregister_device(
453 dev->channels[chan_num].video_dev);
454 else
455 video_device_release(
456 dev->channels[chan_num].video_dev);
457
458 dev->channels[chan_num].video_dev = NULL;
459
460 btcx_riscmem_free(dev->pci,
461 &dev->channels[chan_num].vidq.stopper);
462
463 pr_warn("device %d released!\n", chan_num);
464 }
465
466}
467
468int cx25821_video_register(struct cx25821_dev *dev)
469{
470 int err;
471 int i;
472
473 struct video_device cx25821_video_device = {
474 .name = "cx25821-video",
475 .fops = &video_fops,
476 .minor = -1,
477 .ioctl_ops = &video_ioctl_ops,
478 .tvnorms = CX25821_NORMS,
479 .current_norm = V4L2_STD_NTSC_M,
480 };
481
482 spin_lock_init(&dev->slock);
483
484 for (i = 0; i < MAX_VID_CHANNEL_NUM - 1; ++i) {
485 cx25821_init_controls(dev, i);
486
487 cx25821_risc_stopper(dev->pci,
488 &dev->channels[i].vidq.stopper,
489 dev->channels[i].sram_channels->dma_ctl,
490 0x11, 0);
491
492 dev->channels[i].sram_channels = &cx25821_sram_channels[i];
493 dev->channels[i].video_dev = NULL;
494 dev->channels[i].resources = 0;
495
496 cx_write(dev->channels[i].sram_channels->int_stat,
497 0xffffffff);
498
499 INIT_LIST_HEAD(&dev->channels[i].vidq.active);
500 INIT_LIST_HEAD(&dev->channels[i].vidq.queued);
501
502 dev->channels[i].timeout_data.dev = dev;
503 dev->channels[i].timeout_data.channel =
504 &cx25821_sram_channels[i];
505 dev->channels[i].vidq.timeout.function =
506 cx25821_vid_timeout;
507 dev->channels[i].vidq.timeout.data =
508 (unsigned long)&dev->channels[i].timeout_data;
509 init_timer(&dev->channels[i].vidq.timeout);
510
511 /* register v4l devices */
512 dev->channels[i].video_dev = cx25821_vdev_init(dev,
513 dev->pci, &cx25821_video_device, "video");
514
515 err = video_register_device(dev->channels[i].video_dev,
516 VFL_TYPE_GRABBER, video_nr[dev->nr]);
517
518 if (err < 0)
519 goto fail_unreg;
520
521 }
522
523 /* set PCI interrupt */
524 cx_set(PCI_INT_MSK, 0xff);
525
526 /* initial device configuration */
527 mutex_lock(&dev->lock);
528#ifdef TUNER_FLAG
529 dev->tvnorm = cx25821_video_device.current_norm;
530 cx25821_set_tvnorm(dev, dev->tvnorm);
531#endif
532 mutex_unlock(&dev->lock);
533
534
535 return 0;
536
537fail_unreg:
538 cx25821_video_unregister(dev, i);
539 return err;
540}
541
542int cx25821_buffer_setup(struct videobuf_queue *q, unsigned int *count,
543 unsigned int *size)
544{
545 struct cx25821_fh *fh = q->priv_data;
546
547 *size = fh->fmt->depth * fh->width * fh->height >> 3;
548
549 if (0 == *count)
550 *count = 32;
551
552 if (*size * *count > vid_limit * 1024 * 1024)
553 *count = (vid_limit * 1024 * 1024) / *size;
554
555 return 0;
556}
557
558int cx25821_buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
559 enum v4l2_field field)
560{
561 struct cx25821_fh *fh = q->priv_data;
562 struct cx25821_dev *dev = fh->dev;
563 struct cx25821_buffer *buf =
564 container_of(vb, struct cx25821_buffer, vb);
565 int rc, init_buffer = 0;
566 u32 line0_offset, line1_offset;
567 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
568 int bpl_local = LINE_SIZE_D1;
569 int channel_opened = fh->channel_id;
570
571 BUG_ON(NULL == fh->fmt);
572 if (fh->width < 48 || fh->width > 720 ||
573 fh->height < 32 || fh->height > 576)
574 return -EINVAL;
575
576 buf->vb.size = (fh->width * fh->height * fh->fmt->depth) >> 3;
577
578 if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size)
579 return -EINVAL;
580
581 if (buf->fmt != fh->fmt ||
582 buf->vb.width != fh->width ||
583 buf->vb.height != fh->height || buf->vb.field != field) {
584 buf->fmt = fh->fmt;
585 buf->vb.width = fh->width;
586 buf->vb.height = fh->height;
587 buf->vb.field = field;
588 init_buffer = 1;
589 }
590
591 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
592 init_buffer = 1;
593 rc = videobuf_iolock(q, &buf->vb, NULL);
594 if (0 != rc) {
595 printk(KERN_DEBUG pr_fmt("videobuf_iolock failed!\n"));
596 goto fail;
597 }
598 }
599
600 dprintk(1, "init_buffer=%d\n", init_buffer);
601
602 if (init_buffer) {
603
604 channel_opened = dev->channel_opened;
605 channel_opened = (channel_opened < 0
606 || channel_opened > 7) ? 7 : channel_opened;
607
608 if (dev->channels[channel_opened]
609 .pixel_formats == PIXEL_FRMT_411)
610 buf->bpl = (buf->fmt->depth * buf->vb.width) >> 3;
611 else
612 buf->bpl = (buf->fmt->depth >> 3) * (buf->vb.width);
613
614 if (dev->channels[channel_opened]
615 .pixel_formats == PIXEL_FRMT_411) {
616 bpl_local = buf->bpl;
617 } else {
618 bpl_local = buf->bpl; /* Default */
619
620 if (channel_opened >= 0 && channel_opened <= 7) {
621 if (dev->channels[channel_opened]
622 .use_cif_resolution) {
623 if (dev->tvnorm & V4L2_STD_PAL_BG
624 || dev->tvnorm & V4L2_STD_PAL_DK)
625 bpl_local = 352 << 1;
626 else
627 bpl_local =
628 dev->channels[channel_opened].
629 cif_width <<
630 1;
631 }
632 }
633 }
634
635 switch (buf->vb.field) {
636 case V4L2_FIELD_TOP:
637 cx25821_risc_buffer(dev->pci, &buf->risc,
638 dma->sglist, 0, UNSET,
639 buf->bpl, 0, buf->vb.height);
640 break;
641 case V4L2_FIELD_BOTTOM:
642 cx25821_risc_buffer(dev->pci, &buf->risc,
643 dma->sglist, UNSET, 0,
644 buf->bpl, 0, buf->vb.height);
645 break;
646 case V4L2_FIELD_INTERLACED:
647 /* All other formats are top field first */
648 line0_offset = 0;
649 line1_offset = buf->bpl;
650 dprintk(1, "top field first\n");
651
652 cx25821_risc_buffer(dev->pci, &buf->risc,
653 dma->sglist, line0_offset,
654 bpl_local, bpl_local, bpl_local,
655 buf->vb.height >> 1);
656 break;
657 case V4L2_FIELD_SEQ_TB:
658 cx25821_risc_buffer(dev->pci, &buf->risc,
659 dma->sglist,
660 0, buf->bpl * (buf->vb.height >> 1),
661 buf->bpl, 0, buf->vb.height >> 1);
662 break;
663 case V4L2_FIELD_SEQ_BT:
664 cx25821_risc_buffer(dev->pci, &buf->risc,
665 dma->sglist,
666 buf->bpl * (buf->vb.height >> 1), 0,
667 buf->bpl, 0, buf->vb.height >> 1);
668 break;
669 default:
670 BUG();
671 }
672 }
673
674 dprintk(2, "[%p/%d] buffer_prep - %dx%d %dbpp \"%s\" - dma=0x%08lx\n",
675 buf, buf->vb.i, fh->width, fh->height, fh->fmt->depth,
676 fh->fmt->name, (unsigned long)buf->risc.dma);
677
678 buf->vb.state = VIDEOBUF_PREPARED;
679
680 return 0;
681
682 fail:
683 cx25821_free_buffer(q, buf);
684 return rc;
685}
686
687void cx25821_buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb)
688{
689 struct cx25821_buffer *buf =
690 container_of(vb, struct cx25821_buffer, vb);
691
692 cx25821_free_buffer(q, buf);
693}
694
695struct videobuf_queue *get_queue(struct cx25821_fh *fh)
696{
697 switch (fh->type) {
698 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
699 return &fh->vidq;
700 default:
701 BUG();
702 return NULL;
703 }
704}
705
706int cx25821_get_resource(struct cx25821_fh *fh, int resource)
707{
708 switch (fh->type) {
709 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
710 return resource;
711 default:
712 BUG();
713 return 0;
714 }
715}
716
717int cx25821_video_mmap(struct file *file, struct vm_area_struct *vma)
718{
719 struct cx25821_fh *fh = file->private_data;
720
721 return videobuf_mmap_mapper(get_queue(fh), vma);
722}
723
724
725static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
726{
727 struct cx25821_buffer *buf =
728 container_of(vb, struct cx25821_buffer, vb);
729 struct cx25821_buffer *prev;
730 struct cx25821_fh *fh = vq->priv_data;
731 struct cx25821_dev *dev = fh->dev;
732 struct cx25821_dmaqueue *q = &dev->channels[fh->channel_id].vidq;
733
734 /* add jump to stopper */
735 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
736 buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
737 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
738
739 dprintk(2, "jmp to stopper (0x%x)\n", buf->risc.jmp[1]);
740
741 if (!list_empty(&q->queued)) {
742 list_add_tail(&buf->vb.queue, &q->queued);
743 buf->vb.state = VIDEOBUF_QUEUED;
744 dprintk(2, "[%p/%d] buffer_queue - append to queued\n", buf,
745 buf->vb.i);
746
747 } else if (list_empty(&q->active)) {
748 list_add_tail(&buf->vb.queue, &q->active);
749 cx25821_start_video_dma(dev, q, buf,
750 dev->channels[fh->channel_id].
751 sram_channels);
752 buf->vb.state = VIDEOBUF_ACTIVE;
753 buf->count = q->count++;
754 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
755 dprintk(2,
756 "[%p/%d] buffer_queue - first active, buf cnt = %d, \
757 q->count = %d\n",
758 buf, buf->vb.i, buf->count, q->count);
759 } else {
760 prev =
761 list_entry(q->active.prev, struct cx25821_buffer, vb.queue);
762 if (prev->vb.width == buf->vb.width
763 && prev->vb.height == buf->vb.height
764 && prev->fmt == buf->fmt) {
765 list_add_tail(&buf->vb.queue, &q->active);
766 buf->vb.state = VIDEOBUF_ACTIVE;
767 buf->count = q->count++;
768 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
769
770 /* 64 bit bits 63-32 */
771 prev->risc.jmp[2] = cpu_to_le32(0);
772 dprintk(2,
773 "[%p/%d] buffer_queue - append to active, \
774 buf->count=%d\n",
775 buf, buf->vb.i, buf->count);
776
777 } else {
778 list_add_tail(&buf->vb.queue, &q->queued);
779 buf->vb.state = VIDEOBUF_QUEUED;
780 dprintk(2, "[%p/%d] buffer_queue - first queued\n", buf,
781 buf->vb.i);
782 }
783 }
784
785 if (list_empty(&q->active))
786 dprintk(2, "active queue empty!\n");
787}
788
789static struct videobuf_queue_ops cx25821_video_qops = {
790 .buf_setup = cx25821_buffer_setup,
791 .buf_prepare = cx25821_buffer_prepare,
792 .buf_queue = buffer_queue,
793 .buf_release = cx25821_buffer_release,
794};
795
796static int video_open(struct file *file)
797{
798 struct video_device *vdev = video_devdata(file);
799 struct cx25821_dev *h, *dev = video_drvdata(file);
800 struct cx25821_fh *fh;
801 struct list_head *list;
802 int minor = video_devdata(file)->minor;
803 enum v4l2_buf_type type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
804 u32 pix_format;
805 int ch_id = 0;
806 int i;
807
808 dprintk(1, "open dev=%s type=%s\n",
809 video_device_node_name(vdev),
810 v4l2_type_names[type]);
811
812 /* allocate + initialize per filehandle data */
813 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
814 if (NULL == fh)
815 return -ENOMEM;
816
817 mutex_lock(&cx25821_devlist_mutex);
818
819 list_for_each(list, &cx25821_devlist)
820 {
821 h = list_entry(list, struct cx25821_dev, devlist);
822
823 for (i = 0; i < MAX_VID_CHANNEL_NUM; i++) {
824 if (h->channels[i].video_dev &&
825 h->channels[i].video_dev->minor == minor) {
826 dev = h;
827 ch_id = i;
828 type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
829 }
830 }
831 }
832
833 if (NULL == dev) {
834 mutex_unlock(&cx25821_devlist_mutex);
835 kfree(fh);
836 return -ENODEV;
837 }
838
839 file->private_data = fh;
840 fh->dev = dev;
841 fh->type = type;
842 fh->width = 720;
843 fh->channel_id = ch_id;
844
845 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
846 fh->height = 576;
847 else
848 fh->height = 480;
849
850 dev->channel_opened = fh->channel_id;
851 pix_format =
852 (dev->channels[ch_id].pixel_formats ==
853 PIXEL_FRMT_411) ? V4L2_PIX_FMT_Y41P : V4L2_PIX_FMT_YUYV;
854 fh->fmt = cx25821_format_by_fourcc(pix_format);
855
856 v4l2_prio_open(&dev->channels[ch_id].prio, &fh->prio);
857
858 videobuf_queue_sg_init(&fh->vidq, &cx25821_video_qops,
859 &dev->pci->dev, &dev->slock,
860 V4L2_BUF_TYPE_VIDEO_CAPTURE,
861 V4L2_FIELD_INTERLACED,
862 sizeof(struct cx25821_buffer), fh, NULL);
863
864 dprintk(1, "post videobuf_queue_init()\n");
865 mutex_unlock(&cx25821_devlist_mutex);
866
867 return 0;
868}
869
870static ssize_t video_read(struct file *file, char __user * data, size_t count,
871 loff_t *ppos)
872{
873 struct cx25821_fh *fh = file->private_data;
874
875 switch (fh->type) {
876 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
877 if (cx25821_res_locked(fh, RESOURCE_VIDEO0))
878 return -EBUSY;
879
880 return videobuf_read_one(&fh->vidq, data, count, ppos,
881 file->f_flags & O_NONBLOCK);
882
883 default:
884 BUG();
885 return 0;
886 }
887}
888
889static unsigned int video_poll(struct file *file,
890 struct poll_table_struct *wait)
891{
892 struct cx25821_fh *fh = file->private_data;
893 struct cx25821_buffer *buf;
894
895 if (cx25821_res_check(fh, RESOURCE_VIDEO0)) {
896 /* streaming capture */
897 if (list_empty(&fh->vidq.stream))
898 return POLLERR;
899 buf = list_entry(fh->vidq.stream.next,
900 struct cx25821_buffer, vb.stream);
901 } else {
902 /* read() capture */
903 buf = (struct cx25821_buffer *)fh->vidq.read_buf;
904 if (NULL == buf)
905 return POLLERR;
906 }
907
908 poll_wait(file, &buf->vb.done, wait);
909 if (buf->vb.state == VIDEOBUF_DONE || buf->vb.state == VIDEOBUF_ERROR) {
910 if (buf->vb.state == VIDEOBUF_DONE) {
911 struct cx25821_dev *dev = fh->dev;
912
913 if (dev && dev->channels[fh->channel_id]
914 .use_cif_resolution) {
915 u8 cam_id = *((char *)buf->vb.baddr + 3);
916 memcpy((char *)buf->vb.baddr,
917 (char *)buf->vb.baddr + (fh->width * 2),
918 (fh->width * 2));
919 *((char *)buf->vb.baddr + 3) = cam_id;
920 }
921 }
922
923 return POLLIN | POLLRDNORM;
924 }
925
926 return 0;
927}
928
929static int video_release(struct file *file)
930{
931 struct cx25821_fh *fh = file->private_data;
932 struct cx25821_dev *dev = fh->dev;
933
934 /* stop the risc engine and fifo */
935 cx_write(channel0->dma_ctl, 0); /* FIFO and RISC disable */
936
937 /* stop video capture */
938 if (cx25821_res_check(fh, RESOURCE_VIDEO0)) {
939 videobuf_queue_cancel(&fh->vidq);
940 cx25821_res_free(dev, fh, RESOURCE_VIDEO0);
941 }
942
943 if (fh->vidq.read_buf) {
944 cx25821_buffer_release(&fh->vidq, fh->vidq.read_buf);
945 kfree(fh->vidq.read_buf);
946 }
947
948 videobuf_mmap_free(&fh->vidq);
949
950 v4l2_prio_close(&dev->channels[fh->channel_id].prio, fh->prio);
951 file->private_data = NULL;
952 kfree(fh);
953
954 return 0;
955}
956
957static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
958{
959 struct cx25821_fh *fh = priv;
960 struct cx25821_dev *dev = fh->dev;
961
962 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE))
963 return -EINVAL;
964
965 if (unlikely(i != fh->type))
966 return -EINVAL;
967
968 if (unlikely(!cx25821_res_get(dev, fh,
969 cx25821_get_resource(fh, RESOURCE_VIDEO0))))
970 return -EBUSY;
971
972 return videobuf_streamon(get_queue(fh));
973}
974
975static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
976{
977 struct cx25821_fh *fh = priv;
978 struct cx25821_dev *dev = fh->dev;
979 int err, res;
980
981 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
982 return -EINVAL;
983 if (i != fh->type)
984 return -EINVAL;
985
986 res = cx25821_get_resource(fh, RESOURCE_VIDEO0);
987 err = videobuf_streamoff(get_queue(fh));
988 if (err < 0)
989 return err;
990 cx25821_res_free(dev, fh, res);
991 return 0;
992}
993
994static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
995 struct v4l2_format *f)
996{
997 struct cx25821_fh *fh = priv;
998 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
999 struct v4l2_mbus_framefmt mbus_fmt;
1000 int err;
1001 int pix_format = PIXEL_FRMT_422;
1002
1003 if (fh) {
1004 err = v4l2_prio_check(&dev->channels[fh->channel_id]
1005 .prio, fh->prio);
1006 if (0 != err)
1007 return err;
1008 }
1009
1010 dprintk(2, "%s()\n", __func__);
1011 err = cx25821_vidioc_try_fmt_vid_cap(file, priv, f);
1012
1013 if (0 != err)
1014 return err;
1015
1016 fh->fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat);
1017 fh->vidq.field = f->fmt.pix.field;
1018
1019 /* check if width and height is valid based on set standard */
1020 if (cx25821_is_valid_width(f->fmt.pix.width, dev->tvnorm))
1021 fh->width = f->fmt.pix.width;
1022
1023 if (cx25821_is_valid_height(f->fmt.pix.height, dev->tvnorm))
1024 fh->height = f->fmt.pix.height;
1025
1026 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P)
1027 pix_format = PIXEL_FRMT_411;
1028 else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
1029 pix_format = PIXEL_FRMT_422;
1030 else
1031 return -EINVAL;
1032
1033 cx25821_set_pixel_format(dev, SRAM_CH00, pix_format);
1034
1035 /* check if cif resolution */
1036 if (fh->width == 320 || fh->width == 352)
1037 dev->channels[fh->channel_id].use_cif_resolution = 1;
1038 else
1039 dev->channels[fh->channel_id].use_cif_resolution = 0;
1040
1041 dev->channels[fh->channel_id].cif_width = fh->width;
1042 medusa_set_resolution(dev, fh->width, SRAM_CH00);
1043
1044 dprintk(2, "%s(): width=%d height=%d field=%d\n", __func__, fh->width,
1045 fh->height, fh->vidq.field);
1046 v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, V4L2_MBUS_FMT_FIXED);
1047 cx25821_call_all(dev, video, s_mbus_fmt, &mbus_fmt);
1048
1049 return 0;
1050}
1051
1052static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p)
1053{
1054 int ret_val = 0;
1055 struct cx25821_fh *fh = priv;
1056 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1057
1058 ret_val = videobuf_dqbuf(get_queue(fh), p, file->f_flags & O_NONBLOCK);
1059
1060 p->sequence = dev->channels[fh->channel_id].vidq.count;
1061
1062 return ret_val;
1063}
1064
1065static int vidioc_log_status(struct file *file, void *priv)
1066{
1067 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1068 struct cx25821_fh *fh = priv;
1069 char name[32 + 2];
1070
1071 struct sram_channel *sram_ch = dev->channels[fh->channel_id]
1072 .sram_channels;
1073 u32 tmp = 0;
1074
1075 snprintf(name, sizeof(name), "%s/2", dev->name);
1076 pr_info("%s/2: ============ START LOG STATUS ============\n",
1077 dev->name);
1078 cx25821_call_all(dev, core, log_status);
1079 tmp = cx_read(sram_ch->dma_ctl);
1080 pr_info("Video input 0 is %s\n",
1081 (tmp & 0x11) ? "streaming" : "stopped");
1082 pr_info("%s/2: ============= END LOG STATUS =============\n",
1083 dev->name);
1084 return 0;
1085}
1086
1087static int vidioc_s_ctrl(struct file *file, void *priv,
1088 struct v4l2_control *ctl)
1089{
1090 struct cx25821_fh *fh = priv;
1091 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1092 int err;
1093
1094 if (fh) {
1095 err = v4l2_prio_check(&dev->channels[fh->channel_id]
1096 .prio, fh->prio);
1097 if (0 != err)
1098 return err;
1099 }
1100
1101 return cx25821_set_control(dev, ctl, fh->channel_id);
1102}
1103
1104/* VIDEO IOCTLS */
1105int cx25821_vidioc_g_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
1106{
1107 struct cx25821_fh *fh = priv;
1108
1109 f->fmt.pix.width = fh->width;
1110 f->fmt.pix.height = fh->height;
1111 f->fmt.pix.field = fh->vidq.field;
1112 f->fmt.pix.pixelformat = fh->fmt->fourcc;
1113 f->fmt.pix.bytesperline = (f->fmt.pix.width * fh->fmt->depth) >> 3;
1114 f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
1115
1116 return 0;
1117}
1118
1119int cx25821_vidioc_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f)
1120{
1121 struct cx25821_fmt *fmt;
1122 enum v4l2_field field;
1123 unsigned int maxw, maxh;
1124
1125 fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat);
1126 if (NULL == fmt)
1127 return -EINVAL;
1128
1129 field = f->fmt.pix.field;
1130 maxw = 720;
1131 maxh = 576;
1132
1133 if (V4L2_FIELD_ANY == field) {
1134 field = (f->fmt.pix.height > maxh / 2)
1135 ? V4L2_FIELD_INTERLACED : V4L2_FIELD_TOP;
1136 }
1137
1138 switch (field) {
1139 case V4L2_FIELD_TOP:
1140 case V4L2_FIELD_BOTTOM:
1141 maxh = maxh / 2;
1142 break;
1143 case V4L2_FIELD_INTERLACED:
1144 break;
1145 default:
1146 return -EINVAL;
1147 }
1148
1149 f->fmt.pix.field = field;
1150 if (f->fmt.pix.height < 32)
1151 f->fmt.pix.height = 32;
1152 if (f->fmt.pix.height > maxh)
1153 f->fmt.pix.height = maxh;
1154 if (f->fmt.pix.width < 48)
1155 f->fmt.pix.width = 48;
1156 if (f->fmt.pix.width > maxw)
1157 f->fmt.pix.width = maxw;
1158 f->fmt.pix.width &= ~0x03;
1159 f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
1160 f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
1161
1162 return 0;
1163}
1164
1165int cx25821_vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
1166{
1167 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1168
1169 strcpy(cap->driver, "cx25821");
1170 strlcpy(cap->card, cx25821_boards[dev->board].name, sizeof(cap->card));
1171 sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci));
1172 cap->version = CX25821_VERSION_CODE;
1173 cap->capabilities =
1174 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
1175 if (UNSET != dev->tuner_type)
1176 cap->capabilities |= V4L2_CAP_TUNER;
1177 return 0;
1178}
1179
1180int cx25821_vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
1181 struct v4l2_fmtdesc *f)
1182{
1183 if (unlikely(f->index >= ARRAY_SIZE(formats)))
1184 return -EINVAL;
1185
1186 strlcpy(f->description, formats[f->index].name, sizeof(f->description));
1187 f->pixelformat = formats[f->index].fourcc;
1188
1189 return 0;
1190}
1191
1192int cx25821_vidioc_reqbufs(struct file *file, void *priv, struct v4l2_requestbuffers *p)
1193{
1194 struct cx25821_fh *fh = priv;
1195 return videobuf_reqbufs(get_queue(fh), p);
1196}
1197
1198int cx25821_vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *p)
1199{
1200 struct cx25821_fh *fh = priv;
1201 return videobuf_querybuf(get_queue(fh), p);
1202}
1203
1204int cx25821_vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p)
1205{
1206 struct cx25821_fh *fh = priv;
1207 return videobuf_qbuf(get_queue(fh), p);
1208}
1209
1210int cx25821_vidioc_g_priority(struct file *file, void *f, enum v4l2_priority *p)
1211{
1212 struct cx25821_dev *dev = ((struct cx25821_fh *)f)->dev;
1213 struct cx25821_fh *fh = f;
1214
1215 *p = v4l2_prio_max(&dev->channels[fh->channel_id].prio);
1216
1217 return 0;
1218}
1219
1220int cx25821_vidioc_s_priority(struct file *file, void *f, enum v4l2_priority prio)
1221{
1222 struct cx25821_fh *fh = f;
1223 struct cx25821_dev *dev = ((struct cx25821_fh *)f)->dev;
1224
1225 return v4l2_prio_change(&dev->channels[fh->channel_id]
1226 .prio, &fh->prio, prio);
1227}
1228
1229#ifdef TUNER_FLAG
1230int cx25821_vidioc_s_std(struct file *file, void *priv, v4l2_std_id * tvnorms)
1231{
1232 struct cx25821_fh *fh = priv;
1233 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1234 int err;
1235
1236 dprintk(1, "%s()\n", __func__);
1237
1238 if (fh) {
1239 err = v4l2_prio_check(&dev->channels[fh->channel_id]
1240 .prio, fh->prio);
1241 if (0 != err)
1242 return err;
1243 }
1244
1245 if (dev->tvnorm == *tvnorms) {
1246 return 0;
1247 }
1248
1249 mutex_lock(&dev->lock);
1250 cx25821_set_tvnorm(dev, *tvnorms);
1251 mutex_unlock(&dev->lock);
1252
1253 medusa_set_videostandard(dev);
1254
1255 return 0;
1256}
1257#endif
1258
1259int cx25821_enum_input(struct cx25821_dev *dev, struct v4l2_input *i)
1260{
1261 static const char *iname[] = {
1262 [CX25821_VMUX_COMPOSITE] = "Composite",
1263 [CX25821_VMUX_SVIDEO] = "S-Video",
1264 [CX25821_VMUX_DEBUG] = "for debug only",
1265 };
1266 unsigned int n;
1267 dprintk(1, "%s()\n", __func__);
1268
1269 n = i->index;
1270 if (n >= 2)
1271 return -EINVAL;
1272
1273 if (0 == INPUT(n)->type)
1274 return -EINVAL;
1275
1276 i->type = V4L2_INPUT_TYPE_CAMERA;
1277 strcpy(i->name, iname[INPUT(n)->type]);
1278
1279 i->std = CX25821_NORMS;
1280 return 0;
1281}
1282
1283int cx25821_vidioc_enum_input(struct file *file, void *priv, struct v4l2_input *i)
1284{
1285 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1286 dprintk(1, "%s()\n", __func__);
1287 return cx25821_enum_input(dev, i);
1288}
1289
1290int cx25821_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1291{
1292 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1293
1294 *i = dev->input;
1295 dprintk(1, "%s(): returns %d\n", __func__, *i);
1296 return 0;
1297}
1298
1299int cx25821_vidioc_s_input(struct file *file, void *priv, unsigned int i)
1300{
1301 struct cx25821_fh *fh = priv;
1302 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1303 int err;
1304
1305 dprintk(1, "%s(%d)\n", __func__, i);
1306
1307 if (fh) {
1308 err = v4l2_prio_check(&dev->channels[fh->channel_id]
1309 .prio, fh->prio);
1310 if (0 != err)
1311 return err;
1312 }
1313
1314 if (i > 2) {
1315 dprintk(1, "%s(): -EINVAL\n", __func__);
1316 return -EINVAL;
1317 }
1318
1319 mutex_lock(&dev->lock);
1320 cx25821_video_mux(dev, i);
1321 mutex_unlock(&dev->lock);
1322 return 0;
1323}
1324
1325#ifdef TUNER_FLAG
1326int cx25821_vidioc_g_frequency(struct file *file, void *priv, struct v4l2_frequency *f)
1327{
1328 struct cx25821_fh *fh = priv;
1329 struct cx25821_dev *dev = fh->dev;
1330
1331 f->frequency = dev->freq;
1332
1333 cx25821_call_all(dev, tuner, g_frequency, f);
1334
1335 return 0;
1336}
1337
1338int cx25821_set_freq(struct cx25821_dev *dev, struct v4l2_frequency *f)
1339{
1340 mutex_lock(&dev->lock);
1341 dev->freq = f->frequency;
1342
1343 cx25821_call_all(dev, tuner, s_frequency, f);
1344
1345 /* When changing channels it is required to reset TVAUDIO */
1346 msleep(10);
1347
1348 mutex_unlock(&dev->lock);
1349
1350 return 0;
1351}
1352
1353int cx25821_vidioc_s_frequency(struct file *file, void *priv, struct v4l2_frequency *f)
1354{
1355 struct cx25821_fh *fh = priv;
1356 struct cx25821_dev *dev;
1357 int err;
1358
1359 if (fh) {
1360 dev = fh->dev;
1361 err = v4l2_prio_check(&dev->channels[fh->channel_id]
1362 .prio, fh->prio);
1363 if (0 != err)
1364 return err;
1365 } else {
1366 pr_err("Invalid fh pointer!\n");
1367 return -EINVAL;
1368 }
1369
1370 return cx25821_set_freq(dev, f);
1371}
1372#endif
1373
1374#ifdef CONFIG_VIDEO_ADV_DEBUG
1375int cx25821_vidioc_g_register(struct file *file, void *fh,
1376 struct v4l2_dbg_register *reg)
1377{
1378 struct cx25821_dev *dev = ((struct cx25821_fh *)fh)->dev;
1379
1380 if (!v4l2_chip_match_host(&reg->match))
1381 return -EINVAL;
1382
1383 cx25821_call_all(dev, core, g_register, reg);
1384
1385 return 0;
1386}
1387
1388int cx25821_vidioc_s_register(struct file *file, void *fh,
1389 struct v4l2_dbg_register *reg)
1390{
1391 struct cx25821_dev *dev = ((struct cx25821_fh *)fh)->dev;
1392
1393 if (!v4l2_chip_match_host(&reg->match))
1394 return -EINVAL;
1395
1396 cx25821_call_all(dev, core, s_register, reg);
1397
1398 return 0;
1399}
1400
1401#endif
1402
1403#ifdef TUNER_FLAG
1404int cx25821_vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
1405{
1406 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1407
1408 if (unlikely(UNSET == dev->tuner_type))
1409 return -EINVAL;
1410 if (0 != t->index)
1411 return -EINVAL;
1412
1413 strcpy(t->name, "Television");
1414 t->type = V4L2_TUNER_ANALOG_TV;
1415 t->capability = V4L2_TUNER_CAP_NORM;
1416 t->rangehigh = 0xffffffffUL;
1417
1418 t->signal = 0xffff; /* LOCKED */
1419 return 0;
1420}
1421
1422int cx25821_vidioc_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
1423{
1424 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1425 struct cx25821_fh *fh = priv;
1426 int err;
1427
1428 if (fh) {
1429 err = v4l2_prio_check(&dev->channels[fh->channel_id]
1430 .prio, fh->prio);
1431 if (0 != err)
1432 return err;
1433 }
1434
1435 dprintk(1, "%s()\n", __func__);
1436 if (UNSET == dev->tuner_type)
1437 return -EINVAL;
1438 if (0 != t->index)
1439 return -EINVAL;
1440
1441 return 0;
1442}
1443
1444#endif
1445/*****************************************************************************/
1446static const struct v4l2_queryctrl no_ctl = {
1447 .name = "42",
1448 .flags = V4L2_CTRL_FLAG_DISABLED,
1449};
1450
1451static struct v4l2_queryctrl cx25821_ctls[] = {
1452 /* --- video --- */
1453 {
1454 .id = V4L2_CID_BRIGHTNESS,
1455 .name = "Brightness",
1456 .minimum = 0,
1457 .maximum = 10000,
1458 .step = 1,
1459 .default_value = 6200,
1460 .type = V4L2_CTRL_TYPE_INTEGER,
1461 }, {
1462 .id = V4L2_CID_CONTRAST,
1463 .name = "Contrast",
1464 .minimum = 0,
1465 .maximum = 10000,
1466 .step = 1,
1467 .default_value = 5000,
1468 .type = V4L2_CTRL_TYPE_INTEGER,
1469 }, {
1470 .id = V4L2_CID_SATURATION,
1471 .name = "Saturation",
1472 .minimum = 0,
1473 .maximum = 10000,
1474 .step = 1,
1475 .default_value = 5000,
1476 .type = V4L2_CTRL_TYPE_INTEGER,
1477 }, {
1478 .id = V4L2_CID_HUE,
1479 .name = "Hue",
1480 .minimum = 0,
1481 .maximum = 10000,
1482 .step = 1,
1483 .default_value = 5000,
1484 .type = V4L2_CTRL_TYPE_INTEGER,
1485 }
1486};
1487static const int CX25821_CTLS = ARRAY_SIZE(cx25821_ctls);
1488
1489static int cx25821_ctrl_query(struct v4l2_queryctrl *qctrl)
1490{
1491 int i;
1492
1493 if (qctrl->id < V4L2_CID_BASE || qctrl->id >= V4L2_CID_LASTP1)
1494 return -EINVAL;
1495 for (i = 0; i < CX25821_CTLS; i++)
1496 if (cx25821_ctls[i].id == qctrl->id)
1497 break;
1498 if (i == CX25821_CTLS) {
1499 *qctrl = no_ctl;
1500 return 0;
1501 }
1502 *qctrl = cx25821_ctls[i];
1503 return 0;
1504}
1505
1506int cx25821_vidioc_queryctrl(struct file *file, void *priv,
1507 struct v4l2_queryctrl *qctrl)
1508{
1509 return cx25821_ctrl_query(qctrl);
1510}
1511
1512/* ------------------------------------------------------------------ */
1513/* VIDEO CTRL IOCTLS */
1514
1515static const struct v4l2_queryctrl *ctrl_by_id(unsigned int id)
1516{
1517 unsigned int i;
1518
1519 for (i = 0; i < CX25821_CTLS; i++)
1520 if (cx25821_ctls[i].id == id)
1521 return cx25821_ctls + i;
1522 return NULL;
1523}
1524
1525int cx25821_vidioc_g_ctrl(struct file *file, void *priv, struct v4l2_control *ctl)
1526{
1527 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1528 struct cx25821_fh *fh = priv;
1529
1530 const struct v4l2_queryctrl *ctrl;
1531
1532 ctrl = ctrl_by_id(ctl->id);
1533
1534 if (NULL == ctrl)
1535 return -EINVAL;
1536 switch (ctl->id) {
1537 case V4L2_CID_BRIGHTNESS:
1538 ctl->value = dev->channels[fh->channel_id].ctl_bright;
1539 break;
1540 case V4L2_CID_HUE:
1541 ctl->value = dev->channels[fh->channel_id].ctl_hue;
1542 break;
1543 case V4L2_CID_CONTRAST:
1544 ctl->value = dev->channels[fh->channel_id].ctl_contrast;
1545 break;
1546 case V4L2_CID_SATURATION:
1547 ctl->value = dev->channels[fh->channel_id].ctl_saturation;
1548 break;
1549 }
1550 return 0;
1551}
1552
1553int cx25821_set_control(struct cx25821_dev *dev,
1554 struct v4l2_control *ctl, int chan_num)
1555{
1556 int err;
1557 const struct v4l2_queryctrl *ctrl;
1558
1559 err = -EINVAL;
1560
1561 ctrl = ctrl_by_id(ctl->id);
1562
1563 if (NULL == ctrl)
1564 return err;
1565
1566 switch (ctrl->type) {
1567 case V4L2_CTRL_TYPE_BOOLEAN:
1568 case V4L2_CTRL_TYPE_MENU:
1569 case V4L2_CTRL_TYPE_INTEGER:
1570 if (ctl->value < ctrl->minimum)
1571 ctl->value = ctrl->minimum;
1572 if (ctl->value > ctrl->maximum)
1573 ctl->value = ctrl->maximum;
1574 break;
1575 default:
1576 /* nothing */ ;
1577 }
1578
1579 switch (ctl->id) {
1580 case V4L2_CID_BRIGHTNESS:
1581 dev->channels[chan_num].ctl_bright = ctl->value;
1582 medusa_set_brightness(dev, ctl->value, chan_num);
1583 break;
1584 case V4L2_CID_HUE:
1585 dev->channels[chan_num].ctl_hue = ctl->value;
1586 medusa_set_hue(dev, ctl->value, chan_num);
1587 break;
1588 case V4L2_CID_CONTRAST:
1589 dev->channels[chan_num].ctl_contrast = ctl->value;
1590 medusa_set_contrast(dev, ctl->value, chan_num);
1591 break;
1592 case V4L2_CID_SATURATION:
1593 dev->channels[chan_num].ctl_saturation = ctl->value;
1594 medusa_set_saturation(dev, ctl->value, chan_num);
1595 break;
1596 }
1597
1598 err = 0;
1599
1600 return err;
1601}
1602
1603static void cx25821_init_controls(struct cx25821_dev *dev, int chan_num)
1604{
1605 struct v4l2_control ctrl;
1606 int i;
1607 for (i = 0; i < CX25821_CTLS; i++) {
1608 ctrl.id = cx25821_ctls[i].id;
1609 ctrl.value = cx25821_ctls[i].default_value;
1610
1611 cx25821_set_control(dev, &ctrl, chan_num);
1612 }
1613}
1614
1615int cx25821_vidioc_cropcap(struct file *file, void *priv, struct v4l2_cropcap *cropcap)
1616{
1617 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1618
1619 if (cropcap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1620 return -EINVAL;
1621 cropcap->bounds.top = cropcap->bounds.left = 0;
1622 cropcap->bounds.width = 720;
1623 cropcap->bounds.height = dev->tvnorm == V4L2_STD_PAL_BG ? 576 : 480;
1624 cropcap->pixelaspect.numerator =
1625 dev->tvnorm == V4L2_STD_PAL_BG ? 59 : 10;
1626 cropcap->pixelaspect.denominator =
1627 dev->tvnorm == V4L2_STD_PAL_BG ? 54 : 11;
1628 cropcap->defrect = cropcap->bounds;
1629 return 0;
1630}
1631
1632int cx25821_vidioc_s_crop(struct file *file, void *priv, struct v4l2_crop *crop)
1633{
1634 struct cx25821_dev *dev = ((struct cx25821_fh *)priv)->dev;
1635 struct cx25821_fh *fh = priv;
1636 int err;
1637
1638 if (fh) {
1639 err = v4l2_prio_check(&dev->channels[fh->channel_id].
1640 prio, fh->prio);
1641 if (0 != err)
1642 return err;
1643 }
1644 /* cx25821_vidioc_s_crop not supported */
1645 return -EINVAL;
1646}
1647
1648int cx25821_vidioc_g_crop(struct file *file, void *priv, struct v4l2_crop *crop)
1649{
1650 /* cx25821_vidioc_g_crop not supported */
1651 return -EINVAL;
1652}
1653
1654int cx25821_vidioc_querystd(struct file *file, void *priv, v4l2_std_id * norm)
1655{
1656 /* medusa does not support video standard sensing of current input */
1657 *norm = CX25821_NORMS;
1658
1659 return 0;
1660}
1661
1662int cx25821_is_valid_width(u32 width, v4l2_std_id tvnorm)
1663{
1664 if (tvnorm == V4L2_STD_PAL_BG) {
1665 if (width == 352 || width == 720)
1666 return 1;
1667 else
1668 return 0;
1669 }
1670
1671 if (tvnorm == V4L2_STD_NTSC_M) {
1672 if (width == 320 || width == 352 || width == 720)
1673 return 1;
1674 else
1675 return 0;
1676 }
1677 return 0;
1678}
1679
1680int cx25821_is_valid_height(u32 height, v4l2_std_id tvnorm)
1681{
1682 if (tvnorm == V4L2_STD_PAL_BG) {
1683 if (height == 576 || height == 288)
1684 return 1;
1685 else
1686 return 0;
1687 }
1688
1689 if (tvnorm == V4L2_STD_NTSC_M) {
1690 if (height == 480 || height == 240)
1691 return 1;
1692 else
1693 return 0;
1694 }
1695
1696 return 0;
1697}
1698
1699static long video_ioctl_upstream9(struct file *file, unsigned int cmd,
1700 unsigned long arg)
1701{
1702 struct cx25821_fh *fh = file->private_data;
1703 struct cx25821_dev *dev = fh->dev;
1704 int command = 0;
1705 struct upstream_user_struct *data_from_user;
1706
1707 data_from_user = (struct upstream_user_struct *)arg;
1708
1709 if (!data_from_user) {
1710 pr_err("%s(): Upstream data is INVALID. Returning\n", __func__);
1711 return 0;
1712 }
1713
1714 command = data_from_user->command;
1715
1716 if (command != UPSTREAM_START_VIDEO &&
1717 command != UPSTREAM_STOP_VIDEO)
1718 return 0;
1719
1720 dev->input_filename = data_from_user->input_filename;
1721 dev->input_audiofilename = data_from_user->input_filename;
1722 dev->vid_stdname = data_from_user->vid_stdname;
1723 dev->pixel_format = data_from_user->pixel_format;
1724 dev->channel_select = data_from_user->channel_select;
1725 dev->command = data_from_user->command;
1726
1727 switch (command) {
1728 case UPSTREAM_START_VIDEO:
1729 cx25821_start_upstream_video_ch1(dev, data_from_user);
1730 break;
1731
1732 case UPSTREAM_STOP_VIDEO:
1733 cx25821_stop_upstream_video_ch1(dev);
1734 break;
1735 }
1736
1737 return 0;
1738}
1739
1740static long video_ioctl_upstream10(struct file *file, unsigned int cmd,
1741 unsigned long arg)
1742{
1743 struct cx25821_fh *fh = file->private_data;
1744 struct cx25821_dev *dev = fh->dev;
1745 int command = 0;
1746 struct upstream_user_struct *data_from_user;
1747
1748 data_from_user = (struct upstream_user_struct *)arg;
1749
1750 if (!data_from_user) {
1751 pr_err("%s(): Upstream data is INVALID. Returning\n", __func__);
1752 return 0;
1753 }
1754
1755 command = data_from_user->command;
1756
1757 if (command != UPSTREAM_START_VIDEO &&
1758 command != UPSTREAM_STOP_VIDEO)
1759 return 0;
1760
1761 dev->input_filename_ch2 = data_from_user->input_filename;
1762 dev->input_audiofilename = data_from_user->input_filename;
1763 dev->vid_stdname_ch2 = data_from_user->vid_stdname;
1764 dev->pixel_format_ch2 = data_from_user->pixel_format;
1765 dev->channel_select_ch2 = data_from_user->channel_select;
1766 dev->command_ch2 = data_from_user->command;
1767
1768 switch (command) {
1769 case UPSTREAM_START_VIDEO:
1770 cx25821_start_upstream_video_ch2(dev, data_from_user);
1771 break;
1772
1773 case UPSTREAM_STOP_VIDEO:
1774 cx25821_stop_upstream_video_ch2(dev);
1775 break;
1776 }
1777
1778 return 0;
1779}
1780
1781static long video_ioctl_upstream11(struct file *file, unsigned int cmd,
1782 unsigned long arg)
1783{
1784 struct cx25821_fh *fh = file->private_data;
1785 struct cx25821_dev *dev = fh->dev;
1786 int command = 0;
1787 struct upstream_user_struct *data_from_user;
1788
1789 data_from_user = (struct upstream_user_struct *)arg;
1790
1791 if (!data_from_user) {
1792 pr_err("%s(): Upstream data is INVALID. Returning\n", __func__);
1793 return 0;
1794 }
1795
1796 command = data_from_user->command;
1797
1798 if (command != UPSTREAM_START_AUDIO &&
1799 command != UPSTREAM_STOP_AUDIO)
1800 return 0;
1801
1802 dev->input_filename = data_from_user->input_filename;
1803 dev->input_audiofilename = data_from_user->input_filename;
1804 dev->vid_stdname = data_from_user->vid_stdname;
1805 dev->pixel_format = data_from_user->pixel_format;
1806 dev->channel_select = data_from_user->channel_select;
1807 dev->command = data_from_user->command;
1808
1809 switch (command) {
1810 case UPSTREAM_START_AUDIO:
1811 cx25821_start_upstream_audio(dev, data_from_user);
1812 break;
1813
1814 case UPSTREAM_STOP_AUDIO:
1815 cx25821_stop_upstream_audio(dev);
1816 break;
1817 }
1818
1819 return 0;
1820}
1821
1822static long video_ioctl_set(struct file *file, unsigned int cmd,
1823 unsigned long arg)
1824{
1825 struct cx25821_fh *fh = file->private_data;
1826 struct cx25821_dev *dev = fh->dev;
1827 struct downstream_user_struct *data_from_user;
1828 int command;
1829 int width = 720;
1830 int selected_channel = 0, pix_format = 0, i = 0;
1831 int cif_enable = 0, cif_width = 0;
1832 u32 value = 0;
1833
1834 data_from_user = (struct downstream_user_struct *)arg;
1835
1836 if (!data_from_user) {
1837 pr_err("%s(): User data is INVALID. Returning\n", __func__);
1838 return 0;
1839 }
1840
1841 command = data_from_user->command;
1842
1843 if (command != SET_VIDEO_STD && command != SET_PIXEL_FORMAT
1844 && command != ENABLE_CIF_RESOLUTION && command != REG_READ
1845 && command != REG_WRITE && command != MEDUSA_READ
1846 && command != MEDUSA_WRITE) {
1847 return 0;
1848 }
1849
1850 switch (command) {
1851 case SET_VIDEO_STD:
1852 dev->tvnorm =
1853 !strcmp(data_from_user->vid_stdname,
1854 "PAL") ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1855 medusa_set_videostandard(dev);
1856 break;
1857
1858 case SET_PIXEL_FORMAT:
1859 selected_channel = data_from_user->decoder_select;
1860 pix_format = data_from_user->pixel_format;
1861
1862 if (!(selected_channel <= 7 && selected_channel >= 0)) {
1863 selected_channel -= 4;
1864 selected_channel = selected_channel % 8;
1865 }
1866
1867 if (selected_channel >= 0)
1868 cx25821_set_pixel_format(dev, selected_channel,
1869 pix_format);
1870
1871 break;
1872
1873 case ENABLE_CIF_RESOLUTION:
1874 selected_channel = data_from_user->decoder_select;
1875 cif_enable = data_from_user->cif_resolution_enable;
1876 cif_width = data_from_user->cif_width;
1877
1878 if (cif_enable) {
1879 if (dev->tvnorm & V4L2_STD_PAL_BG
1880 || dev->tvnorm & V4L2_STD_PAL_DK)
1881 width = 352;
1882 else
1883 width = (cif_width == 320
1884 || cif_width == 352) ? cif_width : 320;
1885 }
1886
1887 if (!(selected_channel <= 7 && selected_channel >= 0)) {
1888 selected_channel -= 4;
1889 selected_channel = selected_channel % 8;
1890 }
1891
1892 if (selected_channel <= 7 && selected_channel >= 0) {
1893 dev->channels[selected_channel].
1894 use_cif_resolution = cif_enable;
1895 dev->channels[selected_channel].cif_width = width;
1896 } else {
1897 for (i = 0; i < VID_CHANNEL_NUM; i++) {
1898 dev->channels[i].use_cif_resolution =
1899 cif_enable;
1900 dev->channels[i].cif_width = width;
1901 }
1902 }
1903
1904 medusa_set_resolution(dev, width, selected_channel);
1905 break;
1906 case REG_READ:
1907 data_from_user->reg_data = cx_read(data_from_user->reg_address);
1908 break;
1909 case REG_WRITE:
1910 cx_write(data_from_user->reg_address, data_from_user->reg_data);
1911 break;
1912 case MEDUSA_READ:
1913 value =
1914 cx25821_i2c_read(&dev->i2c_bus[0],
1915 (u16) data_from_user->reg_address,
1916 &data_from_user->reg_data);
1917 break;
1918 case MEDUSA_WRITE:
1919 cx25821_i2c_write(&dev->i2c_bus[0],
1920 (u16) data_from_user->reg_address,
1921 data_from_user->reg_data);
1922 break;
1923 }
1924
1925 return 0;
1926}
1927
1928static long cx25821_video_ioctl(struct file *file,
1929 unsigned int cmd, unsigned long arg)
1930{
1931 int ret = 0;
1932
1933 struct cx25821_fh *fh = file->private_data;
1934
1935 /* check to see if it's the video upstream */
1936 if (fh->channel_id == SRAM_CH09) {
1937 ret = video_ioctl_upstream9(file, cmd, arg);
1938 return ret;
1939 } else if (fh->channel_id == SRAM_CH10) {
1940 ret = video_ioctl_upstream10(file, cmd, arg);
1941 return ret;
1942 } else if (fh->channel_id == SRAM_CH11) {
1943 ret = video_ioctl_upstream11(file, cmd, arg);
1944 ret = video_ioctl_set(file, cmd, arg);
1945 return ret;
1946 }
1947
1948 return video_ioctl2(file, cmd, arg);
1949}
1950
1951/* exported stuff */
1952static const struct v4l2_file_operations video_fops = {
1953 .owner = THIS_MODULE,
1954 .open = video_open,
1955 .release = video_release,
1956 .read = video_read,
1957 .poll = video_poll,
1958 .mmap = cx25821_video_mmap,
1959 .ioctl = cx25821_video_ioctl,
1960};
1961
1962static const struct v4l2_ioctl_ops video_ioctl_ops = {
1963 .vidioc_querycap = cx25821_vidioc_querycap,
1964 .vidioc_enum_fmt_vid_cap = cx25821_vidioc_enum_fmt_vid_cap,
1965 .vidioc_g_fmt_vid_cap = cx25821_vidioc_g_fmt_vid_cap,
1966 .vidioc_try_fmt_vid_cap = cx25821_vidioc_try_fmt_vid_cap,
1967 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
1968 .vidioc_reqbufs = cx25821_vidioc_reqbufs,
1969 .vidioc_querybuf = cx25821_vidioc_querybuf,
1970 .vidioc_qbuf = cx25821_vidioc_qbuf,
1971 .vidioc_dqbuf = vidioc_dqbuf,
1972#ifdef TUNER_FLAG
1973 .vidioc_s_std = cx25821_vidioc_s_std,
1974 .vidioc_querystd = cx25821_vidioc_querystd,
1975#endif
1976 .vidioc_cropcap = cx25821_vidioc_cropcap,
1977 .vidioc_s_crop = cx25821_vidioc_s_crop,
1978 .vidioc_g_crop = cx25821_vidioc_g_crop,
1979 .vidioc_enum_input = cx25821_vidioc_enum_input,
1980 .vidioc_g_input = cx25821_vidioc_g_input,
1981 .vidioc_s_input = cx25821_vidioc_s_input,
1982 .vidioc_g_ctrl = cx25821_vidioc_g_ctrl,
1983 .vidioc_s_ctrl = vidioc_s_ctrl,
1984 .vidioc_queryctrl = cx25821_vidioc_queryctrl,
1985 .vidioc_streamon = vidioc_streamon,
1986 .vidioc_streamoff = vidioc_streamoff,
1987 .vidioc_log_status = vidioc_log_status,
1988 .vidioc_g_priority = cx25821_vidioc_g_priority,
1989 .vidioc_s_priority = cx25821_vidioc_s_priority,
1990#ifdef TUNER_FLAG
1991 .vidioc_g_tuner = cx25821_vidioc_g_tuner,
1992 .vidioc_s_tuner = cx25821_vidioc_s_tuner,
1993 .vidioc_g_frequency = cx25821_vidioc_g_frequency,
1994 .vidioc_s_frequency = cx25821_vidioc_s_frequency,
1995#endif
1996#ifdef CONFIG_VIDEO_ADV_DEBUG
1997 .vidioc_g_register = cx25821_vidioc_g_register,
1998 .vidioc_s_register = cx25821_vidioc_s_register,
1999#endif
2000};
2001
2002struct video_device cx25821_videoioctl_template = {
2003 .name = "cx25821-videoioctl",
2004 .fops = &video_fops,
2005 .ioctl_ops = &video_ioctl_ops,
2006 .tvnorms = CX25821_NORMS,
2007 .current_norm = V4L2_STD_NTSC_M,
2008};
diff --git a/drivers/staging/cx25821/cx25821-video.h b/drivers/staging/cx25821/cx25821-video.h
new file mode 100644
index 00000000000..f4ee8051b8b
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821-video.h
@@ -0,0 +1,177 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 *
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#ifndef CX25821_VIDEO_H_
25#define CX25821_VIDEO_H_
26
27#include <linux/init.h>
28#include <linux/list.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/kmod.h>
32#include <linux/kernel.h>
33#include <linux/slab.h>
34#include <linux/interrupt.h>
35#include <linux/delay.h>
36#include <linux/kthread.h>
37#include <asm/div64.h>
38
39#include "cx25821.h"
40#include <media/v4l2-common.h>
41#include <media/v4l2-ioctl.h>
42
43#define TUNER_FLAG
44
45#define VIDEO_DEBUG 0
46
47#define dprintk(level, fmt, arg...) \
48do { \
49 if (VIDEO_DEBUG >= level) \
50 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ##arg); \
51} while (0)
52
53/* For IOCTL to identify running upstream */
54#define UPSTREAM_START_VIDEO 700
55#define UPSTREAM_STOP_VIDEO 701
56#define UPSTREAM_START_AUDIO 702
57#define UPSTREAM_STOP_AUDIO 703
58#define UPSTREAM_DUMP_REGISTERS 702
59#define SET_VIDEO_STD 800
60#define SET_PIXEL_FORMAT 1000
61#define ENABLE_CIF_RESOLUTION 1001
62
63#define REG_READ 900
64#define REG_WRITE 901
65#define MEDUSA_READ 910
66#define MEDUSA_WRITE 911
67
68extern struct sram_channel *channel0;
69extern struct sram_channel *channel1;
70extern struct sram_channel *channel2;
71extern struct sram_channel *channel3;
72extern struct sram_channel *channel4;
73extern struct sram_channel *channel5;
74extern struct sram_channel *channel6;
75extern struct sram_channel *channel7;
76extern struct sram_channel *channel9;
77extern struct sram_channel *channel10;
78extern struct sram_channel *channel11;
79extern struct video_device cx25821_videoioctl_template;
80/* extern const u32 *ctrl_classes[]; */
81
82extern unsigned int vid_limit;
83
84#define FORMAT_FLAGS_PACKED 0x01
85extern struct cx25821_fmt formats[];
86extern struct cx25821_fmt *cx25821_format_by_fourcc(unsigned int fourcc);
87extern struct cx25821_data timeout_data[MAX_VID_CHANNEL_NUM];
88
89extern void cx25821_dump_video_queue(struct cx25821_dev *dev,
90 struct cx25821_dmaqueue *q);
91extern void cx25821_video_wakeup(struct cx25821_dev *dev,
92 struct cx25821_dmaqueue *q, u32 count);
93
94#ifdef TUNER_FLAG
95extern int cx25821_set_tvnorm(struct cx25821_dev *dev, v4l2_std_id norm);
96#endif
97
98extern int cx25821_res_get(struct cx25821_dev *dev, struct cx25821_fh *fh,
99 unsigned int bit);
100extern int cx25821_res_check(struct cx25821_fh *fh, unsigned int bit);
101extern int cx25821_res_locked(struct cx25821_fh *fh, unsigned int bit);
102extern void cx25821_res_free(struct cx25821_dev *dev, struct cx25821_fh *fh,
103 unsigned int bits);
104extern int cx25821_video_mux(struct cx25821_dev *dev, unsigned int input);
105extern int cx25821_start_video_dma(struct cx25821_dev *dev,
106 struct cx25821_dmaqueue *q,
107 struct cx25821_buffer *buf,
108 struct sram_channel *channel);
109
110extern int cx25821_set_scale(struct cx25821_dev *dev, unsigned int width,
111 unsigned int height, enum v4l2_field field);
112extern int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status);
113extern void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num);
114extern int cx25821_video_register(struct cx25821_dev *dev);
115extern int cx25821_get_format_size(void);
116
117extern int cx25821_buffer_setup(struct videobuf_queue *q, unsigned int *count,
118 unsigned int *size);
119extern int cx25821_buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
120 enum v4l2_field field);
121extern void cx25821_buffer_release(struct videobuf_queue *q,
122 struct videobuf_buffer *vb);
123extern struct videobuf_queue *get_queue(struct cx25821_fh *fh);
124extern int cx25821_get_resource(struct cx25821_fh *fh, int resource);
125extern int cx25821_video_mmap(struct file *file, struct vm_area_struct *vma);
126extern int cx25821_vidioc_try_fmt_vid_cap(struct file *file, void *priv,
127 struct v4l2_format *f);
128extern int cx25821_vidioc_querycap(struct file *file, void *priv,
129 struct v4l2_capability *cap);
130extern int cx25821_vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
131 struct v4l2_fmtdesc *f);
132extern int cx25821_vidioc_reqbufs(struct file *file, void *priv,
133 struct v4l2_requestbuffers *p);
134extern int cx25821_vidioc_querybuf(struct file *file, void *priv,
135 struct v4l2_buffer *p);
136extern int cx25821_vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *p);
137extern int cx25821_vidioc_s_std(struct file *file, void *priv, v4l2_std_id * tvnorms);
138extern int cx25821_enum_input(struct cx25821_dev *dev, struct v4l2_input *i);
139extern int cx25821_vidioc_enum_input(struct file *file, void *priv,
140 struct v4l2_input *i);
141extern int cx25821_vidioc_g_input(struct file *file, void *priv, unsigned int *i);
142extern int cx25821_vidioc_s_input(struct file *file, void *priv, unsigned int i);
143extern int cx25821_vidioc_g_ctrl(struct file *file, void *priv,
144 struct v4l2_control *ctl);
145extern int cx25821_vidioc_g_fmt_vid_cap(struct file *file, void *priv,
146 struct v4l2_format *f);
147extern int cx25821_vidioc_g_frequency(struct file *file, void *priv,
148 struct v4l2_frequency *f);
149extern int cx25821_set_freq(struct cx25821_dev *dev, struct v4l2_frequency *f);
150extern int cx25821_vidioc_s_frequency(struct file *file, void *priv,
151 struct v4l2_frequency *f);
152extern int cx25821_vidioc_g_register(struct file *file, void *fh,
153 struct v4l2_dbg_register *reg);
154extern int cx25821_vidioc_s_register(struct file *file, void *fh,
155 struct v4l2_dbg_register *reg);
156extern int cx25821_vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t);
157extern int cx25821_vidioc_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t);
158
159extern int cx25821_is_valid_width(u32 width, v4l2_std_id tvnorm);
160extern int cx25821_is_valid_height(u32 height, v4l2_std_id tvnorm);
161
162extern int cx25821_vidioc_g_priority(struct file *file, void *f, enum v4l2_priority *p);
163extern int cx25821_vidioc_s_priority(struct file *file, void *f,
164 enum v4l2_priority prio);
165
166extern int cx25821_vidioc_queryctrl(struct file *file, void *priv,
167 struct v4l2_queryctrl *qctrl);
168extern int cx25821_set_control(struct cx25821_dev *dev,
169 struct v4l2_control *ctrl, int chan_num);
170
171extern int cx25821_vidioc_cropcap(struct file *file, void *fh,
172 struct v4l2_cropcap *cropcap);
173extern int cx25821_vidioc_s_crop(struct file *file, void *priv, struct v4l2_crop *crop);
174extern int cx25821_vidioc_g_crop(struct file *file, void *priv, struct v4l2_crop *crop);
175
176extern int cx25821_vidioc_querystd(struct file *file, void *priv, v4l2_std_id * norm);
177#endif
diff --git a/drivers/staging/cx25821/cx25821.h b/drivers/staging/cx25821/cx25821.h
new file mode 100644
index 00000000000..6230243e2cc
--- /dev/null
+++ b/drivers/staging/cx25821/cx25821.h
@@ -0,0 +1,614 @@
1/*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 *
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#ifndef CX25821_H_
25#define CX25821_H_
26
27#include <linux/pci.h>
28#include <linux/i2c.h>
29#include <linux/i2c-algo-bit.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/sched.h>
33#include <linux/kdev_t.h>
34
35#include <media/v4l2-common.h>
36#include <media/v4l2-device.h>
37#include <media/tuner.h>
38#include <media/tveeprom.h>
39#include <media/videobuf-dma-sg.h>
40#include <media/videobuf-dvb.h>
41
42#include "btcx-risc.h"
43#include "cx25821-reg.h"
44#include "cx25821-medusa-reg.h"
45#include "cx25821-sram.h"
46#include "cx25821-audio.h"
47#include "media/cx2341x.h"
48
49#include <linux/version.h>
50#include <linux/mutex.h>
51
52#define CX25821_VERSION_CODE KERNEL_VERSION(0, 0, 106)
53
54#define UNSET (-1U)
55#define NO_SYNC_LINE (-1U)
56
57#define CX25821_MAXBOARDS 2
58
59#define TRUE 1
60#define FALSE 0
61#define LINE_SIZE_D1 1440
62
63/* Number of decoders and encoders */
64#define MAX_DECODERS 8
65#define MAX_ENCODERS 2
66#define QUAD_DECODERS 4
67#define MAX_CAMERAS 16
68
69/* Max number of inputs by card */
70#define MAX_CX25821_INPUT 8
71#define INPUT(nr) (&cx25821_boards[dev->board].input[nr])
72#define RESOURCE_VIDEO0 1
73#define RESOURCE_VIDEO1 2
74#define RESOURCE_VIDEO2 4
75#define RESOURCE_VIDEO3 8
76#define RESOURCE_VIDEO4 16
77#define RESOURCE_VIDEO5 32
78#define RESOURCE_VIDEO6 64
79#define RESOURCE_VIDEO7 128
80#define RESOURCE_VIDEO8 256
81#define RESOURCE_VIDEO9 512
82#define RESOURCE_VIDEO10 1024
83#define RESOURCE_VIDEO11 2048
84#define RESOURCE_VIDEO_IOCTL 4096
85
86#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
87
88#define UNKNOWN_BOARD 0
89#define CX25821_BOARD 1
90
91/* Currently supported by the driver */
92#define CX25821_NORMS (\
93 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_M_KR | \
94 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
95 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_H | \
96 V4L2_STD_PAL_Nc)
97
98#define CX25821_BOARD_CONEXANT_ATHENA10 1
99#define MAX_VID_CHANNEL_NUM 12
100#define VID_CHANNEL_NUM 8
101
102struct cx25821_fmt {
103 char *name;
104 u32 fourcc; /* v4l2 format id */
105 int depth;
106 int flags;
107 u32 cxformat;
108};
109
110struct cx25821_ctrl {
111 struct v4l2_queryctrl v;
112 u32 off;
113 u32 reg;
114 u32 mask;
115 u32 shift;
116};
117
118struct cx25821_tvnorm {
119 char *name;
120 v4l2_std_id id;
121 u32 cxiformat;
122 u32 cxoformat;
123};
124
125struct cx25821_fh {
126 struct cx25821_dev *dev;
127 enum v4l2_buf_type type;
128 int radio;
129 u32 resources;
130
131 enum v4l2_priority prio;
132
133 /* video overlay */
134 struct v4l2_window win;
135 struct v4l2_clip *clips;
136 unsigned int nclips;
137
138 /* video capture */
139 struct cx25821_fmt *fmt;
140 unsigned int width, height;
141 int channel_id;
142
143 /* vbi capture */
144 struct videobuf_queue vidq;
145 struct videobuf_queue vbiq;
146
147 /* H264 Encoder specifics ONLY */
148 struct videobuf_queue mpegq;
149 atomic_t v4l_reading;
150};
151
152enum cx25821_itype {
153 CX25821_VMUX_COMPOSITE = 1,
154 CX25821_VMUX_SVIDEO,
155 CX25821_VMUX_DEBUG,
156 CX25821_RADIO,
157};
158
159enum cx25821_src_sel_type {
160 CX25821_SRC_SEL_EXT_656_VIDEO = 0,
161 CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO
162};
163
164/* buffer for one video frame */
165struct cx25821_buffer {
166 /* common v4l buffer stuff -- must be first */
167 struct videobuf_buffer vb;
168
169 /* cx25821 specific */
170 unsigned int bpl;
171 struct btcx_riscmem risc;
172 struct cx25821_fmt *fmt;
173 u32 count;
174};
175
176struct cx25821_input {
177 enum cx25821_itype type;
178 unsigned int vmux;
179 u32 gpio0, gpio1, gpio2, gpio3;
180};
181
182typedef enum {
183 CX25821_UNDEFINED = 0,
184 CX25821_RAW,
185 CX25821_264
186} port_t;
187
188struct cx25821_board {
189 char *name;
190 port_t porta, portb, portc;
191 unsigned int tuner_type;
192 unsigned int radio_type;
193 unsigned char tuner_addr;
194 unsigned char radio_addr;
195
196 u32 clk_freq;
197 struct cx25821_input input[2];
198};
199
200struct cx25821_subid {
201 u16 subvendor;
202 u16 subdevice;
203 u32 card;
204};
205
206struct cx25821_i2c {
207 struct cx25821_dev *dev;
208
209 int nr;
210
211 /* i2c i/o */
212 struct i2c_adapter i2c_adap;
213 struct i2c_algo_bit_data i2c_algo;
214 struct i2c_client i2c_client;
215 u32 i2c_rc;
216
217 /* cx25821 registers used for raw addess */
218 u32 i2c_period;
219 u32 reg_ctrl;
220 u32 reg_stat;
221 u32 reg_addr;
222 u32 reg_rdata;
223 u32 reg_wdata;
224};
225
226struct cx25821_dmaqueue {
227 struct list_head active;
228 struct list_head queued;
229 struct timer_list timeout;
230 struct btcx_riscmem stopper;
231 u32 count;
232};
233
234struct cx25821_data {
235 struct cx25821_dev *dev;
236 struct sram_channel *channel;
237};
238
239struct cx25821_channel {
240 struct v4l2_prio_state prio;
241
242 int ctl_bright;
243 int ctl_contrast;
244 int ctl_hue;
245 int ctl_saturation;
246 struct cx25821_data timeout_data;
247
248 struct video_device *video_dev;
249 struct cx25821_dmaqueue vidq;
250
251 struct sram_channel *sram_channels;
252
253 struct mutex lock;
254 int resources;
255
256 int pixel_formats;
257 int use_cif_resolution;
258 int cif_width;
259};
260
261struct cx25821_dev {
262 struct list_head devlist;
263 atomic_t refcount;
264 struct v4l2_device v4l2_dev;
265
266 /* pci stuff */
267 struct pci_dev *pci;
268 unsigned char pci_rev, pci_lat;
269 int pci_bus, pci_slot;
270 u32 base_io_addr;
271 u32 __iomem *lmmio;
272 u8 __iomem *bmmio;
273 int pci_irqmask;
274 int hwrevision;
275
276 u32 clk_freq;
277
278 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
279 struct cx25821_i2c i2c_bus[3];
280
281 int nr;
282 struct mutex lock;
283
284 struct cx25821_channel channels[MAX_VID_CHANNEL_NUM];
285
286 /* board details */
287 unsigned int board;
288 char name[32];
289
290 /* Analog video */
291 u32 resources;
292 unsigned int input;
293 u32 tvaudio;
294 v4l2_std_id tvnorm;
295 unsigned int tuner_type;
296 unsigned char tuner_addr;
297 unsigned int radio_type;
298 unsigned char radio_addr;
299 unsigned int has_radio;
300 unsigned int videc_type;
301 unsigned char videc_addr;
302 unsigned short _max_num_decoders;
303
304 /* Analog Audio Upstream */
305 int _audio_is_running;
306 int _audiopixel_format;
307 int _is_first_audio_frame;
308 int _audiofile_status;
309 int _audio_lines_count;
310 int _audioframe_count;
311 int _audio_upstream_channel_select;
312 int _last_index_irq; /* The last interrupt index processed. */
313
314 __le32 *_risc_audio_jmp_addr;
315 __le32 *_risc_virt_start_addr;
316 __le32 *_risc_virt_addr;
317 dma_addr_t _risc_phys_addr;
318 dma_addr_t _risc_phys_start_addr;
319
320 unsigned int _audiorisc_size;
321 unsigned int _audiodata_buf_size;
322 __le32 *_audiodata_buf_virt_addr;
323 dma_addr_t _audiodata_buf_phys_addr;
324 char *_audiofilename;
325
326 /* V4l */
327 u32 freq;
328 struct video_device *vbi_dev;
329 struct video_device *radio_dev;
330 struct video_device *ioctl_dev;
331
332 spinlock_t slock;
333
334 /* Video Upstream */
335 int _line_size;
336 int _prog_cnt;
337 int _pixel_format;
338 int _is_first_frame;
339 int _is_running;
340 int _file_status;
341 int _lines_count;
342 int _frame_count;
343 int _channel_upstream_select;
344 unsigned int _risc_size;
345
346 __le32 *_dma_virt_start_addr;
347 __le32 *_dma_virt_addr;
348 dma_addr_t _dma_phys_addr;
349 dma_addr_t _dma_phys_start_addr;
350
351 unsigned int _data_buf_size;
352 __le32 *_data_buf_virt_addr;
353 dma_addr_t _data_buf_phys_addr;
354 char *_filename;
355 char *_defaultname;
356
357 int _line_size_ch2;
358 int _prog_cnt_ch2;
359 int _pixel_format_ch2;
360 int _is_first_frame_ch2;
361 int _is_running_ch2;
362 int _file_status_ch2;
363 int _lines_count_ch2;
364 int _frame_count_ch2;
365 int _channel2_upstream_select;
366 unsigned int _risc_size_ch2;
367
368 __le32 *_dma_virt_start_addr_ch2;
369 __le32 *_dma_virt_addr_ch2;
370 dma_addr_t _dma_phys_addr_ch2;
371 dma_addr_t _dma_phys_start_addr_ch2;
372
373 unsigned int _data_buf_size_ch2;
374 __le32 *_data_buf_virt_addr_ch2;
375 dma_addr_t _data_buf_phys_addr_ch2;
376 char *_filename_ch2;
377 char *_defaultname_ch2;
378
379 /* MPEG Encoder ONLY settings */
380 u32 cx23417_mailbox;
381 struct cx2341x_mpeg_params mpeg_params;
382 struct video_device *v4l_device;
383 atomic_t v4l_reader_count;
384 struct cx25821_tvnorm encodernorm;
385
386 u32 upstream_riscbuf_size;
387 u32 upstream_databuf_size;
388 u32 upstream_riscbuf_size_ch2;
389 u32 upstream_databuf_size_ch2;
390 u32 audio_upstream_riscbuf_size;
391 u32 audio_upstream_databuf_size;
392 int _isNTSC;
393 int _frame_index;
394 int _audioframe_index;
395 struct workqueue_struct *_irq_queues;
396 struct work_struct _irq_work_entry;
397 struct workqueue_struct *_irq_queues_ch2;
398 struct work_struct _irq_work_entry_ch2;
399 struct workqueue_struct *_irq_audio_queues;
400 struct work_struct _audio_work_entry;
401 char *input_filename;
402 char *input_filename_ch2;
403 int _frame_index_ch2;
404 int _isNTSC_ch2;
405 char *vid_stdname_ch2;
406 int pixel_format_ch2;
407 int channel_select_ch2;
408 int command_ch2;
409 char *input_audiofilename;
410 char *vid_stdname;
411 int pixel_format;
412 int channel_select;
413 int command;
414 int channel_opened;
415};
416
417struct upstream_user_struct {
418 char *input_filename;
419 char *vid_stdname;
420 int pixel_format;
421 int channel_select;
422 int command;
423};
424
425struct downstream_user_struct {
426 char *vid_stdname;
427 int pixel_format;
428 int cif_resolution_enable;
429 int cif_width;
430 int decoder_select;
431 int command;
432 int reg_address;
433 int reg_data;
434};
435
436extern struct upstream_user_struct *up_data;
437
438static inline struct cx25821_dev *get_cx25821(struct v4l2_device *v4l2_dev)
439{
440 return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev);
441}
442
443#define cx25821_call_all(dev, o, f, args...) \
444 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
445
446extern struct list_head cx25821_devlist;
447extern struct mutex cx25821_devlist_mutex;
448
449extern struct cx25821_board cx25821_boards[];
450extern struct cx25821_subid cx25821_subids[];
451
452#define SRAM_CH00 0 /* Video A */
453#define SRAM_CH01 1 /* Video B */
454#define SRAM_CH02 2 /* Video C */
455#define SRAM_CH03 3 /* Video D */
456#define SRAM_CH04 4 /* Video E */
457#define SRAM_CH05 5 /* Video F */
458#define SRAM_CH06 6 /* Video G */
459#define SRAM_CH07 7 /* Video H */
460
461#define SRAM_CH08 8 /* Audio A */
462#define SRAM_CH09 9 /* Video Upstream I */
463#define SRAM_CH10 10 /* Video Upstream J */
464#define SRAM_CH11 11 /* Audio Upstream AUD_CHANNEL_B */
465
466#define VID_UPSTREAM_SRAM_CHANNEL_I SRAM_CH09
467#define VID_UPSTREAM_SRAM_CHANNEL_J SRAM_CH10
468#define AUDIO_UPSTREAM_SRAM_CHANNEL_B SRAM_CH11
469#define VIDEO_IOCTL_CH 11
470
471struct sram_channel {
472 char *name;
473 u32 i;
474 u32 cmds_start;
475 u32 ctrl_start;
476 u32 cdt;
477 u32 fifo_start;
478 u32 fifo_size;
479 u32 ptr1_reg;
480 u32 ptr2_reg;
481 u32 cnt1_reg;
482 u32 cnt2_reg;
483 u32 int_msk;
484 u32 int_stat;
485 u32 int_mstat;
486 u32 dma_ctl;
487 u32 gpcnt_ctl;
488 u32 gpcnt;
489 u32 aud_length;
490 u32 aud_cfg;
491 u32 fld_aud_fifo_en;
492 u32 fld_aud_risc_en;
493
494 /* For Upstream Video */
495 u32 vid_fmt_ctl;
496 u32 vid_active_ctl1;
497 u32 vid_active_ctl2;
498 u32 vid_cdt_size;
499
500 u32 vip_ctl;
501 u32 pix_frmt;
502 u32 jumponly;
503 u32 irq_bit;
504};
505extern struct sram_channel cx25821_sram_channels[];
506
507#define STATUS_SUCCESS 0
508#define STATUS_UNSUCCESSFUL -1
509
510#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
511#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
512
513#define cx_andor(reg, mask, value) \
514 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
515 ((value) & (mask)), dev->lmmio+((reg)>>2))
516
517#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
518#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
519
520#define Set_GPIO_Bit(Bit) (1 << Bit)
521#define Clear_GPIO_Bit(Bit) (~(1 << Bit))
522
523#define CX25821_ERR(fmt, args...) \
524 pr_err("(%d): " fmt, dev->board, ##args)
525#define CX25821_WARN(fmt, args...) \
526 pr_warn("(%d): " fmt, dev->board, ##args)
527#define CX25821_INFO(fmt, args...) \
528 pr_info("(%d): " fmt, dev->board, ##args)
529
530extern int cx25821_i2c_register(struct cx25821_i2c *bus);
531extern void cx25821_card_setup(struct cx25821_dev *dev);
532extern int cx25821_ir_init(struct cx25821_dev *dev);
533extern int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value);
534extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value);
535extern int cx25821_i2c_unregister(struct cx25821_i2c *bus);
536extern void cx25821_gpio_init(struct cx25821_dev *dev);
537extern void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
538 int pin_number, int pin_logic_value);
539
540extern int medusa_video_init(struct cx25821_dev *dev);
541extern int medusa_set_videostandard(struct cx25821_dev *dev);
542extern void medusa_set_resolution(struct cx25821_dev *dev, int width,
543 int decoder_select);
544extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness,
545 int decoder);
546extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast,
547 int decoder);
548extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder);
549extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation,
550 int decoder);
551
552extern int cx25821_sram_channel_setup(struct cx25821_dev *dev,
553 struct sram_channel *ch, unsigned int bpl,
554 u32 risc);
555
556extern int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
557 struct scatterlist *sglist,
558 unsigned int top_offset,
559 unsigned int bottom_offset,
560 unsigned int bpl,
561 unsigned int padding, unsigned int lines);
562extern int cx25821_risc_databuffer_audio(struct pci_dev *pci,
563 struct btcx_riscmem *risc,
564 struct scatterlist *sglist,
565 unsigned int bpl,
566 unsigned int lines, unsigned int lpi);
567extern void cx25821_free_buffer(struct videobuf_queue *q,
568 struct cx25821_buffer *buf);
569extern int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
570 u32 reg, u32 mask, u32 value);
571extern void cx25821_sram_channel_dump(struct cx25821_dev *dev,
572 struct sram_channel *ch);
573extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
574 struct sram_channel *ch);
575
576extern struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci);
577extern void cx25821_print_irqbits(char *name, char *tag, char **strings,
578 int len, u32 bits, u32 mask);
579extern void cx25821_dev_unregister(struct cx25821_dev *dev);
580extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
581 struct sram_channel *ch,
582 unsigned int bpl, u32 risc);
583
584extern int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev,
585 int channel_select, int pixel_format);
586extern int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev,
587 int channel_select, int pixel_format);
588extern int cx25821_audio_upstream_init(struct cx25821_dev *dev,
589 int channel_select);
590extern void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev);
591extern void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev);
592extern void cx25821_free_mem_upstream_audio(struct cx25821_dev *dev);
593extern void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev,
594 struct upstream_user_struct
595 *up_data);
596extern void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev,
597 struct upstream_user_struct
598 *up_data);
599extern void cx25821_start_upstream_audio(struct cx25821_dev *dev,
600 struct upstream_user_struct *up_data);
601extern void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev);
602extern void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev);
603extern void cx25821_stop_upstream_audio(struct cx25821_dev *dev);
604extern int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
605 struct sram_channel *ch,
606 unsigned int bpl, u32 risc);
607extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel,
608 u32 format);
609extern void cx25821_videoioctl_unregister(struct cx25821_dev *dev);
610extern struct video_device *cx25821_vdev_init(struct cx25821_dev *dev,
611 struct pci_dev *pci,
612 struct video_device *template,
613 char *type);
614#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 12:24:54 -0400