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authorMark <reodge@gmail.com>2010-06-25 08:15:26 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-06-25 14:11:22 -0400
commit3afbe13cbe02ca9911435b274a256f5502bb36de (patch)
treeb03e4d0a93a2be6e6f16342c60a8fc0ee070ca18 /drivers/staging/comedi
parent5e95efecb501fd93c7eed75d405fff1423c56239 (diff)
Staging: comedi: Coding style cleanups in adv_pci_dio.c
This patch fixes up many coding style issues in adv_pci_dio.c found by checkpatch.pl Signed-off-by: Mark Rankilor <reodge@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/comedi')
-rw-r--r--drivers/staging/comedi/drivers/adv_pci_dio.c307
1 files changed, 180 insertions, 127 deletions
diff --git a/drivers/staging/comedi/drivers/adv_pci_dio.c b/drivers/staging/comedi/drivers/adv_pci_dio.c
index d81bbfac695..31a63887ab0 100644
--- a/drivers/staging/comedi/drivers/adv_pci_dio.c
+++ b/drivers/staging/comedi/drivers/adv_pci_dio.c
@@ -8,8 +8,8 @@
8/* 8/*
9Driver: adv_pci_dio 9Driver: adv_pci_dio
10Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U, 10Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1750, PCI-1751, PCI-1752, PCI-1753/E, 11 PCI-1736UP, PCI-1750, PCI-1751, PCI-1752, PCI-1753/E,
12 PCI-1754, PCI-1756, PCI-1762 12 PCI-1754, PCI-1756, PCI-1762
13Author: Michal Dobes <dobes@tesnet.cz> 13Author: Michal Dobes <dobes@tesnet.cz>
14Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733, 14Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1750, 15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1750,
@@ -24,8 +24,8 @@ This driver supports now only insn interface for DI/DO/DIO.
24Configuration options: 24Configuration options:
25 [0] - PCI bus of device (optional) 25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional) 26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI 27 If bus/slot is not specified, the first available PCI
28 device will be used. 28 device will be used.
29 29
30*/ 30*/
31 31
@@ -67,9 +67,12 @@ enum hw_io_access {
67 67
68#define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */ 68#define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
69#define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */ 69#define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
70#define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per card */ 70#define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
71#define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per card */ 71 * card */
72 /* (could be more than one 8254 per subdevice) */ 72#define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
73 * card */
74 /* (could be more than one 8254 per
75 * subdevice) */
73 76
74#define SIZE_8254 4 /* 8254 IO space length */ 77#define SIZE_8254 4 /* 8254 IO space length */
75#define SIZE_8255 4 /* 8255 IO space length */ 78#define SIZE_8255 4 /* 8255 IO space length */
@@ -84,7 +87,8 @@ enum hw_io_access {
84#define PCI1730_DO 2 /* W: Digital output 0-15 */ 87#define PCI1730_DO 2 /* W: Digital output 0-15 */
85#define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */ 88#define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
86#define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */ 89#define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
87#define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for interrupts */ 90#define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
91 * interrupts */
88#define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */ 92#define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
89#define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */ 93#define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
90#define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */ 94#define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
@@ -99,7 +103,8 @@ enum hw_io_access {
99#define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */ 103#define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
100#define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */ 104#define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
101#define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */ 105#define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
102#define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for interrupts */ 106#define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
107 * interrupts */
103#define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */ 108#define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
104#define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */ 109#define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
105#define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */ 110#define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
@@ -161,37 +166,66 @@ enum hw_io_access {
161#define INTCSR3 0x3b 166#define INTCSR3 0x3b
162 167
163/* PCI-1760 mailbox commands */ 168/* PCI-1760 mailbox commands */
164#define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actaul DI status in IMB3 */ 169#define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
170 * DI status in IMB3 */
165#define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */ 171#define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
166#define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */ 172#define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
167#define CMD_ReadCurrentStatus 0x07 /* Read the current status of the register in OMB0, result in IMB0 */ 173#define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
168#define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in IMB1.IMB0 */ 174 * register in OMB0, result in IMB0 */
169#define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in IMB1.IMB0 */ 175#define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
170#define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in OMB0 */ 176 * IMB1.IMB0 */
171#define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on bits in OMB0 */ 177#define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
172#define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on bits in OMB0 */ 178 * IMB1.IMB0 */
173#define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in OMB0 */ 179#define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
174#define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in OMB0 to its reset values */ 180 * OMB0 */
175#define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow interrupts based on bits in OMB0 */ 181#define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
176#define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value interrupts based on bits in OMB0 */ 182 * bits in OMB0 */
177#define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0 - rising, =1 - falling) */ 183#define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
178#define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current value */ 184 * bits in OMB0 */
179#define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value 256*OMB1+OMB0 */ 185#define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
180#define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value 256*OMB1+OMB0 */ 186 * OMB0 */
181#define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value 256*OMB1+OMB0 */ 187#define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
182#define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value 256*OMB1+OMB0 */ 188 * OMB0 to its reset values */
183#define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value 256*OMB1+OMB0 */ 189#define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
184#define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value 256*OMB1+OMB0 */ 190 * interrupts based on bits in OMB0 */
185#define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value 256*OMB1+OMB0 */ 191#define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
186#define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value 256*OMB1+OMB0 */ 192 * interrupts based on bits in OMB0 */
187#define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value 256*OMB1+OMB0 */ 193#define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
188#define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value 256*OMB1+OMB0 */ 194 * - rising, =1 - falling) */
189#define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value 256*OMB1+OMB0 */ 195#define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
190#define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value 256*OMB1+OMB0 */ 196 * value */
191#define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value 256*OMB1+OMB0 */ 197#define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
192#define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value 256*OMB1+OMB0 */ 198 * 256*OMB1+OMB0 */
193#define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value 256*OMB1+OMB0 */ 199#define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
194#define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value 256*OMB1+OMB0 */ 200 * 256*OMB1+OMB0 */
201#define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
202 * 256*OMB1+OMB0 */
203#define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
204 * 256*OMB1+OMB0 */
205#define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
206 * 256*OMB1+OMB0 */
207#define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
208 * 256*OMB1+OMB0 */
209#define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
210 * 256*OMB1+OMB0 */
211#define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
212 * 256*OMB1+OMB0 */
213#define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
214 * 256*OMB1+OMB0 */
215#define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
216 * 256*OMB1+OMB0 */
217#define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
218 * 256*OMB1+OMB0 */
219#define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
220 * 256*OMB1+OMB0 */
221#define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
222 * 256*OMB1+OMB0 */
223#define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
224 * 256*OMB1+OMB0 */
225#define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
226 * 256*OMB1+OMB0 */
227#define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
228 * 256*OMB1+OMB0 */
195 229
196#define OMBCMD_RETRY 0x03 /* 3 times try request before error */ 230#define OMBCMD_RETRY 0x03 /* 3 times try request before error */
197 231
@@ -244,115 +278,115 @@ MODULE_DEVICE_TABLE(pci, pci_dio_pci_table);
244static const struct dio_boardtype boardtypes[] = { 278static const struct dio_boardtype boardtypes[] = {
245 {"pci1730", PCI_VENDOR_ID_ADVANTECH, 0x1730, PCIDIO_MAINREG, 279 {"pci1730", PCI_VENDOR_ID_ADVANTECH, 0x1730, PCIDIO_MAINREG,
246 TYPE_PCI1730, 280 TYPE_PCI1730,
247 {{16, PCI1730_DI, 2, 0}, {16, PCI1730_IDI, 2, 0}}, 281 { {16, PCI1730_DI, 2, 0}, {16, PCI1730_IDI, 2, 0} },
248 {{16, PCI1730_DO, 2, 0}, {16, PCI1730_IDO, 2, 0}}, 282 { {16, PCI1730_DO, 2, 0}, {16, PCI1730_IDO, 2, 0} },
249 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 283 { {0, 0, 0, 0}, {0, 0, 0, 0} },
250 {4, PCI173x_BOARDID, 1, SDF_INTERNAL}, 284 {4, PCI173x_BOARDID, 1, SDF_INTERNAL},
251 {{0, 0, 0, 0}}, 285 { {0, 0, 0, 0} },
252 IO_8b}, 286 IO_8b},
253 {"pci1733", PCI_VENDOR_ID_ADVANTECH, 0x1733, PCIDIO_MAINREG, 287 {"pci1733", PCI_VENDOR_ID_ADVANTECH, 0x1733, PCIDIO_MAINREG,
254 TYPE_PCI1733, 288 TYPE_PCI1733,
255 {{0, 0, 0, 0}, {32, PCI1733_IDI, 4, 0}}, 289 { {0, 0, 0, 0}, {32, PCI1733_IDI, 4, 0} },
256 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 290 { {0, 0, 0, 0}, {0, 0, 0, 0} },
257 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 291 { {0, 0, 0, 0}, {0, 0, 0, 0} },
258 {4, PCI173x_BOARDID, 1, SDF_INTERNAL}, 292 {4, PCI173x_BOARDID, 1, SDF_INTERNAL},
259 {{0, 0, 0, 0}}, 293 { {0, 0, 0, 0} },
260 IO_8b}, 294 IO_8b},
261 {"pci1734", PCI_VENDOR_ID_ADVANTECH, 0x1734, PCIDIO_MAINREG, 295 {"pci1734", PCI_VENDOR_ID_ADVANTECH, 0x1734, PCIDIO_MAINREG,
262 TYPE_PCI1734, 296 TYPE_PCI1734,
263 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 297 { {0, 0, 0, 0}, {0, 0, 0, 0} },
264 {{0, 0, 0, 0}, {32, PCI1734_IDO, 4, 0}}, 298 { {0, 0, 0, 0}, {32, PCI1734_IDO, 4, 0} },
265 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 299 { {0, 0, 0, 0}, {0, 0, 0, 0} },
266 {4, PCI173x_BOARDID, 1, SDF_INTERNAL}, 300 {4, PCI173x_BOARDID, 1, SDF_INTERNAL},
267 {{0, 0, 0, 0}}, 301 { {0, 0, 0, 0} },
268 IO_8b}, 302 IO_8b},
269 {"pci1735", PCI_VENDOR_ID_ADVANTECH, 0x1735, PCIDIO_MAINREG, 303 {"pci1735", PCI_VENDOR_ID_ADVANTECH, 0x1735, PCIDIO_MAINREG,
270 TYPE_PCI1735, 304 TYPE_PCI1735,
271 {{32, PCI1735_DI, 4, 0}, {0, 0, 0, 0}}, 305 { {32, PCI1735_DI, 4, 0}, {0, 0, 0, 0} },
272 {{32, PCI1735_DO, 4, 0}, {0, 0, 0, 0}}, 306 { {32, PCI1735_DO, 4, 0}, {0, 0, 0, 0} },
273 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 307 { {0, 0, 0, 0}, {0, 0, 0, 0} },
274 { 4, PCI1735_BOARDID, 1, SDF_INTERNAL}, 308 { 4, PCI1735_BOARDID, 1, SDF_INTERNAL},
275 {{3, PCI1735_C8254, 1, 0}}, 309 { {3, PCI1735_C8254, 1, 0} },
276 IO_8b}, 310 IO_8b},
277 {"pci1736", PCI_VENDOR_ID_ADVANTECH, 0x1736, PCI1736_MAINREG, 311 {"pci1736", PCI_VENDOR_ID_ADVANTECH, 0x1736, PCI1736_MAINREG,
278 TYPE_PCI1736, 312 TYPE_PCI1736,
279 {{0, 0, 0, 0}, {16, PCI1736_IDI, 2, 0}}, 313 { {0, 0, 0, 0}, {16, PCI1736_IDI, 2, 0} },
280 {{0, 0, 0, 0}, {16, PCI1736_IDO, 2, 0}}, 314 { {0, 0, 0, 0}, {16, PCI1736_IDO, 2, 0} },
281 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 315 { {0, 0, 0, 0}, {0, 0, 0, 0} },
282 {4, PCI1736_BOARDID, 1, SDF_INTERNAL}, 316 {4, PCI1736_BOARDID, 1, SDF_INTERNAL},
283 {{0, 0, 0, 0}}, 317 { {0, 0, 0, 0} },
284 IO_8b}, 318 IO_8b},
285 {"pci1750", PCI_VENDOR_ID_ADVANTECH, 0x1750, PCIDIO_MAINREG, 319 {"pci1750", PCI_VENDOR_ID_ADVANTECH, 0x1750, PCIDIO_MAINREG,
286 TYPE_PCI1750, 320 TYPE_PCI1750,
287 {{0, 0, 0, 0}, {16, PCI1750_IDI, 2, 0}}, 321 { {0, 0, 0, 0}, {16, PCI1750_IDI, 2, 0} },
288 {{0, 0, 0, 0}, {16, PCI1750_IDO, 2, 0}}, 322 { {0, 0, 0, 0}, {16, PCI1750_IDO, 2, 0} },
289 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 323 { {0, 0, 0, 0}, {0, 0, 0, 0} },
290 {0, 0, 0, 0}, 324 {0, 0, 0, 0},
291 {{0, 0, 0, 0}}, 325 { {0, 0, 0, 0} },
292 IO_8b}, 326 IO_8b},
293 {"pci1751", PCI_VENDOR_ID_ADVANTECH, 0x1751, PCIDIO_MAINREG, 327 {"pci1751", PCI_VENDOR_ID_ADVANTECH, 0x1751, PCIDIO_MAINREG,
294 TYPE_PCI1751, 328 TYPE_PCI1751,
295 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 329 { {0, 0, 0, 0}, {0, 0, 0, 0} },
296 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 330 { {0, 0, 0, 0}, {0, 0, 0, 0} },
297 {{48, PCI1751_DIO, 2, 0}, {0, 0, 0, 0}}, 331 { {48, PCI1751_DIO, 2, 0}, {0, 0, 0, 0} },
298 {0, 0, 0, 0}, 332 {0, 0, 0, 0},
299 {{0, 0, 0, 0}}, 333 { {0, 0, 0, 0} },
300 IO_8b}, 334 IO_8b},
301 {"pci1752", PCI_VENDOR_ID_ADVANTECH, 0x1752, PCIDIO_MAINREG, 335 {"pci1752", PCI_VENDOR_ID_ADVANTECH, 0x1752, PCIDIO_MAINREG,
302 TYPE_PCI1752, 336 TYPE_PCI1752,
303 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 337 { {0, 0, 0, 0}, {0, 0, 0, 0} },
304 {{32, PCI1752_IDO, 2, 0}, {32, PCI1752_IDO2, 2, 0}}, 338 { {32, PCI1752_IDO, 2, 0}, {32, PCI1752_IDO2, 2, 0} },
305 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 339 { {0, 0, 0, 0}, {0, 0, 0, 0} },
306 {4, PCI175x_BOARDID, 1, SDF_INTERNAL}, 340 {4, PCI175x_BOARDID, 1, SDF_INTERNAL},
307 {{0, 0, 0, 0}}, 341 { {0, 0, 0, 0} },
308 IO_16b}, 342 IO_16b},
309 {"pci1753", PCI_VENDOR_ID_ADVANTECH, 0x1753, PCIDIO_MAINREG, 343 {"pci1753", PCI_VENDOR_ID_ADVANTECH, 0x1753, PCIDIO_MAINREG,
310 TYPE_PCI1753, 344 TYPE_PCI1753,
311 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 345 { {0, 0, 0, 0}, {0, 0, 0, 0} },
312 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 346 { {0, 0, 0, 0}, {0, 0, 0, 0} },
313 {{96, PCI1753_DIO, 4, 0}, {0, 0, 0, 0}}, 347 { {96, PCI1753_DIO, 4, 0}, {0, 0, 0, 0} },
314 {0, 0, 0, 0}, 348 {0, 0, 0, 0},
315 {{0, 0, 0, 0}}, 349 { {0, 0, 0, 0} },
316 IO_8b}, 350 IO_8b},
317 {"pci1753e", PCI_VENDOR_ID_ADVANTECH, 0x1753, PCIDIO_MAINREG, 351 {"pci1753e", PCI_VENDOR_ID_ADVANTECH, 0x1753, PCIDIO_MAINREG,
318 TYPE_PCI1753E, 352 TYPE_PCI1753E,
319 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 353 { {0, 0, 0, 0}, {0, 0, 0, 0} },
320 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 354 { {0, 0, 0, 0}, {0, 0, 0, 0} },
321 {{96, PCI1753_DIO, 4, 0}, {96, PCI1753E_DIO, 4, 0}}, 355 { {96, PCI1753_DIO, 4, 0}, {96, PCI1753E_DIO, 4, 0} },
322 {0, 0, 0, 0}, 356 {0, 0, 0, 0},
323 {{0, 0, 0, 0}}, 357 { {0, 0, 0, 0} },
324 IO_8b}, 358 IO_8b},
325 {"pci1754", PCI_VENDOR_ID_ADVANTECH, 0x1754, PCIDIO_MAINREG, 359 {"pci1754", PCI_VENDOR_ID_ADVANTECH, 0x1754, PCIDIO_MAINREG,
326 TYPE_PCI1754, 360 TYPE_PCI1754,
327 {{32, PCI1754_IDI, 2, 0}, {32, PCI1754_IDI2, 2, 0}}, 361 { {32, PCI1754_IDI, 2, 0}, {32, PCI1754_IDI2, 2, 0} },
328 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 362 { {0, 0, 0, 0}, {0, 0, 0, 0} },
329 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 363 { {0, 0, 0, 0}, {0, 0, 0, 0} },
330 {4, PCI175x_BOARDID, 1, SDF_INTERNAL}, 364 {4, PCI175x_BOARDID, 1, SDF_INTERNAL},
331 {{0, 0, 0, 0}}, 365 { {0, 0, 0, 0} },
332 IO_16b}, 366 IO_16b},
333 {"pci1756", PCI_VENDOR_ID_ADVANTECH, 0x1756, PCIDIO_MAINREG, 367 {"pci1756", PCI_VENDOR_ID_ADVANTECH, 0x1756, PCIDIO_MAINREG,
334 TYPE_PCI1756, 368 TYPE_PCI1756,
335 {{0, 0, 0, 0}, {32, PCI1756_IDI, 2, 0}}, 369 { {0, 0, 0, 0}, {32, PCI1756_IDI, 2, 0} },
336 {{0, 0, 0, 0}, {32, PCI1756_IDO, 2, 0}}, 370 { {0, 0, 0, 0}, {32, PCI1756_IDO, 2, 0} },
337 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 371 { {0, 0, 0, 0}, {0, 0, 0, 0} },
338 {4, PCI175x_BOARDID, 1, SDF_INTERNAL}, 372 {4, PCI175x_BOARDID, 1, SDF_INTERNAL},
339 {{0, 0, 0, 0}}, 373 { {0, 0, 0, 0} },
340 IO_16b}, 374 IO_16b},
341 {"pci1760", PCI_VENDOR_ID_ADVANTECH, 0x1760, 0, 375 {"pci1760", PCI_VENDOR_ID_ADVANTECH, 0x1760, 0,
342 TYPE_PCI1760, 376 TYPE_PCI1760,
343 {{0, 0, 0, 0}, {0, 0, 0, 0}}, /* This card have own setup work */ 377 { {0, 0, 0, 0}, {0, 0, 0, 0} }, /* This card have own setup work */
344 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 378 { {0, 0, 0, 0}, {0, 0, 0, 0} },
345 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 379 { {0, 0, 0, 0}, {0, 0, 0, 0} },
346 {0, 0, 0, 0}, 380 {0, 0, 0, 0},
347 {{0, 0, 0, 0}}, 381 { {0, 0, 0, 0} },
348 IO_8b}, 382 IO_8b},
349 {"pci1762", PCI_VENDOR_ID_ADVANTECH, 0x1762, PCIDIO_MAINREG, 383 {"pci1762", PCI_VENDOR_ID_ADVANTECH, 0x1762, PCIDIO_MAINREG,
350 TYPE_PCI1762, 384 TYPE_PCI1762,
351 {{0, 0, 0, 0}, {16, PCI1762_IDI, 1, 0}}, 385 { {0, 0, 0, 0}, {16, PCI1762_IDI, 1, 0} },
352 {{0, 0, 0, 0}, {16, PCI1762_RO, 1, 0}}, 386 { {0, 0, 0, 0}, {16, PCI1762_RO, 1, 0} },
353 {{0, 0, 0, 0}, {0, 0, 0, 0}}, 387 { {0, 0, 0, 0}, {0, 0, 0, 0} },
354 {4, PCI1762_BOARDID, 1, SDF_INTERNAL}, 388 {4, PCI1762_BOARDID, 1, SDF_INTERNAL},
355 {{0, 0, 0, 0}}, 389 { {0, 0, 0, 0} },
356 IO_16b} 390 IO_16b}
357}; 391};
358 392
@@ -372,13 +406,16 @@ struct pci_dio_private {
372 char valid; /* card is usable */ 406 char valid; /* card is usable */
373 char GlobalIrqEnabled; /* 1= any IRQ source is enabled */ 407 char GlobalIrqEnabled; /* 1= any IRQ source is enabled */
374 /* PCI-1760 specific data */ 408 /* PCI-1760 specific data */
375 unsigned char IDICntEnable; /* counter's counting enable status */ 409 unsigned char IDICntEnable; /* counter's counting enable status */
376 unsigned char IDICntOverEnable; /* counter's overflow interrupts enable status */ 410 unsigned char IDICntOverEnable; /* counter's overflow interrupts enable
377 unsigned char IDICntMatchEnable; /* counter's match interrupts enable status */ 411 * status */
378 unsigned char IDICntEdge; /* counter's count edge value (bit=0 - rising, =1 - falling) */ 412 unsigned char IDICntMatchEnable; /* counter's match interrupts
413 * enable status */
414 unsigned char IDICntEdge; /* counter's count edge value
415 * (bit=0 - rising, =1 - falling) */
379 unsigned short CntResValue[8]; /* counters' reset value */ 416 unsigned short CntResValue[8]; /* counters' reset value */
380 unsigned short CntMatchValue[8]; /* counters' match interrupt value */ 417 unsigned short CntMatchValue[8]; /* counters' match interrupt value */
381 unsigned char IDIFiltersEn; /* IDI's digital filters enable status */ 418 unsigned char IDIFiltersEn; /* IDI's digital filters enable status */
382 unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */ 419 unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */
383 unsigned char IDIPatMatchValue; /* IDI's pattern match value */ 420 unsigned char IDIPatMatchValue; /* IDI's pattern match value */
384 unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */ 421 unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */
@@ -691,7 +728,8 @@ static int pci1760_insn_cnt_write(struct comedi_device *dev,
691 }; 728 };
692 unsigned char imb[4]; 729 unsigned char imb[4];
693 730
694 if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) { /* Set reset value if different */ 731 /* Set reset value if different */
732 if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {
695 ret = pci1760_mbxrequest(dev, omb, imb); 733 ret = pci1760_mbxrequest(dev, omb, imb);
696 if (!ret) 734 if (!ret)
697 return ret; 735 return ret;
@@ -704,7 +742,8 @@ static int pci1760_insn_cnt_write(struct comedi_device *dev,
704 if (!ret) 742 if (!ret)
705 return ret; 743 return ret;
706 744
707 if (!(bitmask & devpriv->IDICntEnable)) { /* start counter if it don't run */ 745 /* start counter if it don't run */
746 if (!(bitmask & devpriv->IDICntEnable)) {
708 omb[0] = bitmask; 747 omb[0] = bitmask;
709 omb[2] = CMD_EnableIDICounters; 748 omb[2] = CMD_EnableIDICounters;
710 ret = pci1760_mbxrequest(dev, omb, imb); 749 ret = pci1760_mbxrequest(dev, omb, imb);
@@ -740,12 +779,14 @@ static int pci1760_reset(struct comedi_device *dev)
740 devpriv->IDICntEnable = 0; 779 devpriv->IDICntEnable = 0;
741 780
742 omb[0] = 0x00; 781 omb[0] = 0x00;
743 omb[2] = CMD_OverflowIDICounters; /* disable counters overflow interrupts */ 782 omb[2] = CMD_OverflowIDICounters; /* disable counters overflow
783 * interrupts */
744 pci1760_mbxrequest(dev, omb, imb); 784 pci1760_mbxrequest(dev, omb, imb);
745 devpriv->IDICntOverEnable = 0; 785 devpriv->IDICntOverEnable = 0;
746 786
747 omb[0] = 0x00; 787 omb[0] = 0x00;
748 omb[2] = CMD_MatchIntIDICounters; /* disable counters match value interrupts */ 788 omb[2] = CMD_MatchIntIDICounters; /* disable counters match value
789 * interrupts */
749 pci1760_mbxrequest(dev, omb, imb); 790 pci1760_mbxrequest(dev, omb, imb);
750 devpriv->IDICntMatchEnable = 0; 791 devpriv->IDICntMatchEnable = 0;
751 792
@@ -766,7 +807,8 @@ static int pci1760_reset(struct comedi_device *dev)
766 } 807 }
767 808
768 omb[0] = 0xff; 809 omb[0] = 0xff;
769 omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset values */ 810 omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset
811 * values */
770 pci1760_mbxrequest(dev, omb, imb); 812 pci1760_mbxrequest(dev, omb, imb);
771 813
772 omb[0] = 0x00; 814 omb[0] = 0x00;
@@ -807,9 +849,12 @@ static int pci_dio_reset(struct comedi_device *dev)
807 outb(0, dev->iobase + PCI1730_IDO + 1); 849 outb(0, dev->iobase + PCI1730_IDO + 1);
808 /* NO break there! */ 850 /* NO break there! */
809 case TYPE_PCI1733: 851 case TYPE_PCI1733:
810 outb(0, dev->iobase + PCI1730_3_INT_EN); /* disable interrupts */ 852 /* disable interrupts */
811 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR); /* clear interrupts */ 853 outb(0, dev->iobase + PCI1730_3_INT_EN);
812 outb(0, dev->iobase + PCI1730_3_INT_RF); /* set rising edge trigger */ 854 /* clear interrupts */
855 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
856 /* set rising edge trigger */
857 outb(0, dev->iobase + PCI1730_3_INT_RF);
813 break; 858 break;
814 case TYPE_PCI1734: 859 case TYPE_PCI1734:
815 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */ 860 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
@@ -830,43 +875,53 @@ static int pci_dio_reset(struct comedi_device *dev)
830 case TYPE_PCI1736: 875 case TYPE_PCI1736:
831 outb(0, dev->iobase + PCI1736_IDO); 876 outb(0, dev->iobase + PCI1736_IDO);
832 outb(0, dev->iobase + PCI1736_IDO + 1); 877 outb(0, dev->iobase + PCI1736_IDO + 1);
833 outb(0, dev->iobase + PCI1736_3_INT_EN); /* disable interrupts */ 878 /* disable interrupts */
834 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR); /* clear interrupts */ 879 outb(0, dev->iobase + PCI1736_3_INT_EN);
835 outb(0, dev->iobase + PCI1736_3_INT_RF); /* set rising edge trigger */ 880 /* clear interrupts */
881 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
882 /* set rising edge trigger */
883 outb(0, dev->iobase + PCI1736_3_INT_RF);
836 break; 884 break;
837 885
838 case TYPE_PCI1750: 886 case TYPE_PCI1750:
839 case TYPE_PCI1751: 887 case TYPE_PCI1751:
840 outb(0x88, dev->iobase + PCI1750_ICR); /* disable & clear interrupts */ 888 /* disable & clear interrupts */
889 outb(0x88, dev->iobase + PCI1750_ICR);
841 break; 890 break;
842 case TYPE_PCI1752: 891 case TYPE_PCI1752:
843 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze function */ 892 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
893 * function */
844 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */ 894 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
845 outw(0, dev->iobase + PCI1752_IDO + 2); 895 outw(0, dev->iobase + PCI1752_IDO + 2);
846 outw(0, dev->iobase + PCI1752_IDO2); 896 outw(0, dev->iobase + PCI1752_IDO2);
847 outw(0, dev->iobase + PCI1752_IDO2 + 2); 897 outw(0, dev->iobase + PCI1752_IDO2 + 2);
848 break; 898 break;
849 case TYPE_PCI1753E: 899 case TYPE_PCI1753E:
850 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear interrupts */ 900 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
901 * interrupts */
851 outb(0x80, dev->iobase + PCI1753E_ICR1); 902 outb(0x80, dev->iobase + PCI1753E_ICR1);
852 outb(0x80, dev->iobase + PCI1753E_ICR2); 903 outb(0x80, dev->iobase + PCI1753E_ICR2);
853 outb(0x80, dev->iobase + PCI1753E_ICR3); 904 outb(0x80, dev->iobase + PCI1753E_ICR3);
854 /* NO break there! */ 905 /* NO break there! */
855 case TYPE_PCI1753: 906 case TYPE_PCI1753:
856 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear interrupts */ 907 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
908 * interrupts */
857 outb(0x80, dev->iobase + PCI1753_ICR1); 909 outb(0x80, dev->iobase + PCI1753_ICR1);
858 outb(0x80, dev->iobase + PCI1753_ICR2); 910 outb(0x80, dev->iobase + PCI1753_ICR2);
859 outb(0x80, dev->iobase + PCI1753_ICR3); 911 outb(0x80, dev->iobase + PCI1753_ICR3);
860 break; 912 break;
861 case TYPE_PCI1754: 913 case TYPE_PCI1754:
862 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear interrupts */ 914 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
915 * interrupts */
863 outw(0x08, dev->iobase + PCI1754_6_ICR1); 916 outw(0x08, dev->iobase + PCI1754_6_ICR1);
864 outw(0x08, dev->iobase + PCI1754_ICR2); 917 outw(0x08, dev->iobase + PCI1754_ICR2);
865 outw(0x08, dev->iobase + PCI1754_ICR3); 918 outw(0x08, dev->iobase + PCI1754_ICR3);
866 break; 919 break;
867 case TYPE_PCI1756: 920 case TYPE_PCI1756:
868 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze function */ 921 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
869 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear interrupts */ 922 * function */
923 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
924 * interrupts */
870 outw(0x08, dev->iobase + PCI1754_6_ICR1); 925 outw(0x08, dev->iobase + PCI1754_6_ICR1);
871 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */ 926 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
872 outw(0, dev->iobase + PCI1756_IDO + 2); 927 outw(0, dev->iobase + PCI1756_IDO + 2);
@@ -875,7 +930,8 @@ static int pci_dio_reset(struct comedi_device *dev)
875 pci1760_reset(dev); 930 pci1760_reset(dev);
876 break; 931 break;
877 case TYPE_PCI1762: 932 case TYPE_PCI1762:
878 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear interrupts */ 933 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
934 * interrupts */
879 break; 935 break;
880 } 936 }
881 937
@@ -996,7 +1052,7 @@ static int pci_dio_add_do(struct comedi_device *dev, struct comedi_subdevice *s,
996============================================================================== 1052==============================================================================
997*/ 1053*/
998static int pci_dio_add_8254(struct comedi_device *dev, 1054static int pci_dio_add_8254(struct comedi_device *dev,
999 struct comedi_subdevice * s, 1055 struct comedi_subdevice *s,
1000 const struct diosubd_data *d, int subdev) 1056 const struct diosubd_data *d, int subdev)
1001{ 1057{
1002 s->type = COMEDI_SUBD_COUNTER; 1058 s->type = COMEDI_SUBD_COUNTER;
@@ -1023,7 +1079,7 @@ static int CheckAndAllocCard(struct comedi_device *dev,
1023 1079
1024 for (pr = pci_priv, prev = NULL; pr != NULL; prev = pr, pr = pr->next) { 1080 for (pr = pci_priv, prev = NULL; pr != NULL; prev = pr, pr = pr->next) {
1025 if (pr->pcidev == pcidev) 1081 if (pr->pcidev == pcidev)
1026 return 0; /* this card is used, look for another */ 1082 return 0; /* this card is used, look for another */
1027 1083
1028 } 1084 }
1029 1085
@@ -1215,15 +1271,12 @@ static int pci_dio_detach(struct comedi_device *dev)
1215 } 1271 }
1216 } 1272 }
1217 1273
1218 if (this_board->boardid.chans) { 1274 if (this_board->boardid.chans)
1219 subdev++; 1275 subdev++;
1220 }
1221 1276
1222 for (i = 0; i < MAX_8254_SUBDEVS; i++) { 1277 for (i = 0; i < MAX_8254_SUBDEVS; i++)
1223 if (this_board->s8254[i].chans) { 1278 if (this_board->s8254[i].chans)
1224 subdev++; 1279 subdev++;
1225 }
1226 }
1227 1280
1228 for (i = 0; i < dev->n_subdevices; i++) { 1281 for (i = 0; i < dev->n_subdevices; i++) {
1229 s = dev->subdevices + i; 1282 s = dev->subdevices + i;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 01:00:25 -0400