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authorGreg Kroah-Hartman <gregkh@suse.de>2010-10-07 20:04:47 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-10-07 20:04:47 -0400
commit7d4df48eba4cea654ee6fe6e1a51a0600807ed7b (patch)
tree7c4e3cbb7d576ac3a0b273b5908bbed460eceb0a /drivers/staging/brcm80211/include/spid.h
parent4128dd9afb986321edf0baa8a3aaa3c7c5aa3730 (diff)
Staging: brcm80211: s/uint16/u16/
Use the kernel types, don't invent your own. Cc: Brett Rudley <brudley@broadcom.com> Cc: Henry Ptasinski <henryp@broadcom.com> Cc: Nohee Ko <noheek@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/brcm80211/include/spid.h')
-rw-r--r--drivers/staging/brcm80211/include/spid.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/staging/brcm80211/include/spid.h b/drivers/staging/brcm80211/include/spid.h
index 935c6f8f8fd..45932be07c1 100644
--- a/drivers/staging/brcm80211/include/spid.h
+++ b/drivers/staging/brcm80211/include/spid.h
@@ -29,12 +29,12 @@ typedef volatile struct {
29 * function selection, command/data error check 29 * function selection, command/data error check
30 */ 30 */
31 u8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */ 31 u8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
32 uint16 intr_reg; /* 0x04, Intr status register */ 32 u16 intr_reg; /* 0x04, Intr status register */
33 uint16 intr_en_reg; /* 0x06, Intr mask register */ 33 u16 intr_en_reg; /* 0x06, Intr mask register */
34 uint32 status_reg; /* 0x08, RO, Status bits of last spi transfer */ 34 uint32 status_reg; /* 0x08, RO, Status bits of last spi transfer */
35 uint16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */ 35 u16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */
36 uint16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */ 36 u16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */
37 uint16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */ 37 u16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */
38 uint32 test_read; /* 0x14, RO 0xfeedbead signature */ 38 uint32 test_read; /* 0x14, RO 0xfeedbead signature */
39 uint32 test_rw; /* 0x18, RW */ 39 uint32 test_rw; /* 0x18, RW */
40 u8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */ 40 u8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */