diff options
author | Stephen Warren <swarren@nvidia.com> | 2012-09-28 12:15:48 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2012-10-01 08:29:49 -0400 |
commit | 536a53a300d0d40152796eefb0a9e6e36ca37f7d (patch) | |
tree | e644203945ee780d8a1a4cdc656d9b4984f5361d /drivers/spi | |
parent | f4b81dd83e38277a3d1e6661f0fa8eea8cfe784b (diff) |
spi: remove completely broken Tegra driver
The current SPI driver has many issues. Examples are:
* Segfaulting on most transfers due to expecting all transfers to have
both RX and TX buffers.
* Hanging on TX transfers since the whole driver flow is driven by RX
DMA completion, but the HW is only told to enable RX for RX transfers.
* Use of clk_disable_unprepare() from atomic context.
* Once those and other minor issues are fixed, the driver still doesn't
actually work.
* The driver also implements a deprecated API to the SPI core.
For this reason, simply remove the driver completely. This has two
advantages:
1) This will remove the last use of Tegra's <mach/dma.h>, which will
allow that file to be removed, which is required for single zImage
work.
2) The downstream driver is significaly different from the current
code. I believe a patch to re-add the downstream driver (with
appropriate cleanup) will be much simpler to review if it's a new
file rather than randomly interspered with essentially unrelated
existing code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'drivers/spi')
-rw-r--r-- | drivers/spi/Kconfig | 6 | ||||
-rw-r--r-- | drivers/spi/Makefile | 1 | ||||
-rw-r--r-- | drivers/spi/spi-tegra.c | 702 |
3 files changed, 0 insertions, 709 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 63a79437aca..ecc31a1f73f 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig | |||
@@ -377,12 +377,6 @@ config SPI_MXS | |||
377 | help | 377 | help |
378 | SPI driver for Freescale MXS devices. | 378 | SPI driver for Freescale MXS devices. |
379 | 379 | ||
380 | config SPI_TEGRA | ||
381 | tristate "Nvidia Tegra SPI controller" | ||
382 | depends on ARCH_TEGRA && (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA) | ||
383 | help | ||
384 | SPI driver for NVidia Tegra SoCs | ||
385 | |||
386 | config SPI_TI_SSP | 380 | config SPI_TI_SSP |
387 | tristate "TI Sequencer Serial Port - SPI Support" | 381 | tristate "TI Sequencer Serial Port - SPI Support" |
388 | depends on MFD_TI_SSP | 382 | depends on MFD_TI_SSP |
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 938705644bb..22fd3a7251b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile | |||
@@ -59,7 +59,6 @@ obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o | |||
59 | obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o | 59 | obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o |
60 | obj-$(CONFIG_SPI_SIRF) += spi-sirf.o | 60 | obj-$(CONFIG_SPI_SIRF) += spi-sirf.o |
61 | obj-$(CONFIG_SPI_STMP3XXX) += spi-stmp.o | 61 | obj-$(CONFIG_SPI_STMP3XXX) += spi-stmp.o |
62 | obj-$(CONFIG_SPI_TEGRA) += spi-tegra.o | ||
63 | obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o | 62 | obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o |
64 | obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o | 63 | obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o |
65 | obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o | 64 | obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o |
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c deleted file mode 100644 index e28445d8d27..00000000000 --- a/drivers/spi/spi-tegra.c +++ /dev/null | |||
@@ -1,702 +0,0 @@ | |||
1 | /* | ||
2 | * Driver for Nvidia TEGRA spi controller. | ||
3 | * | ||
4 | * Copyright (C) 2010 Google, Inc. | ||
5 | * | ||
6 | * Author: | ||
7 | * Erik Gilling <konkers@android.com> | ||
8 | * | ||
9 | * This software is licensed under the terms of the GNU General Public | ||
10 | * License version 2, as published by the Free Software Foundation, and | ||
11 | * may be copied, distributed, and modified under those terms. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | */ | ||
19 | |||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/module.h> | ||
22 | #include <linux/init.h> | ||
23 | #include <linux/err.h> | ||
24 | #include <linux/platform_device.h> | ||
25 | #include <linux/io.h> | ||
26 | #include <linux/dma-mapping.h> | ||
27 | #include <linux/dmapool.h> | ||
28 | #include <linux/clk.h> | ||
29 | #include <linux/interrupt.h> | ||
30 | #include <linux/delay.h> | ||
31 | |||
32 | #include <linux/spi/spi.h> | ||
33 | #include <linux/dmaengine.h> | ||
34 | |||
35 | #include <mach/dma.h> | ||
36 | |||
37 | #define SLINK_COMMAND 0x000 | ||
38 | #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) | ||
39 | #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) | ||
40 | #define SLINK_BOTH_EN (1 << 10) | ||
41 | #define SLINK_CS_SW (1 << 11) | ||
42 | #define SLINK_CS_VALUE (1 << 12) | ||
43 | #define SLINK_CS_POLARITY (1 << 13) | ||
44 | #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16) | ||
45 | #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16) | ||
46 | #define SLINK_IDLE_SDA_PULL_LOW (2 << 16) | ||
47 | #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16) | ||
48 | #define SLINK_IDLE_SDA_MASK (3 << 16) | ||
49 | #define SLINK_CS_POLARITY1 (1 << 20) | ||
50 | #define SLINK_CK_SDA (1 << 21) | ||
51 | #define SLINK_CS_POLARITY2 (1 << 22) | ||
52 | #define SLINK_CS_POLARITY3 (1 << 23) | ||
53 | #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24) | ||
54 | #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24) | ||
55 | #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24) | ||
56 | #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24) | ||
57 | #define SLINK_IDLE_SCLK_MASK (3 << 24) | ||
58 | #define SLINK_M_S (1 << 28) | ||
59 | #define SLINK_WAIT (1 << 29) | ||
60 | #define SLINK_GO (1 << 30) | ||
61 | #define SLINK_ENB (1 << 31) | ||
62 | |||
63 | #define SLINK_COMMAND2 0x004 | ||
64 | #define SLINK_LSBFE (1 << 0) | ||
65 | #define SLINK_SSOE (1 << 1) | ||
66 | #define SLINK_SPIE (1 << 4) | ||
67 | #define SLINK_BIDIROE (1 << 6) | ||
68 | #define SLINK_MODFEN (1 << 7) | ||
69 | #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8) | ||
70 | #define SLINK_CS_ACTIVE_BETWEEN (1 << 17) | ||
71 | #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18) | ||
72 | #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20) | ||
73 | #define SLINK_FIFO_REFILLS_0 (0 << 22) | ||
74 | #define SLINK_FIFO_REFILLS_1 (1 << 22) | ||
75 | #define SLINK_FIFO_REFILLS_2 (2 << 22) | ||
76 | #define SLINK_FIFO_REFILLS_3 (3 << 22) | ||
77 | #define SLINK_FIFO_REFILLS_MASK (3 << 22) | ||
78 | #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26) | ||
79 | #define SLINK_SPC0 (1 << 29) | ||
80 | #define SLINK_TXEN (1 << 30) | ||
81 | #define SLINK_RXEN (1 << 31) | ||
82 | |||
83 | #define SLINK_STATUS 0x008 | ||
84 | #define SLINK_COUNT(val) (((val) >> 0) & 0x1f) | ||
85 | #define SLINK_WORD(val) (((val) >> 5) & 0x1f) | ||
86 | #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff) | ||
87 | #define SLINK_MODF (1 << 16) | ||
88 | #define SLINK_RX_UNF (1 << 18) | ||
89 | #define SLINK_TX_OVF (1 << 19) | ||
90 | #define SLINK_TX_FULL (1 << 20) | ||
91 | #define SLINK_TX_EMPTY (1 << 21) | ||
92 | #define SLINK_RX_FULL (1 << 22) | ||
93 | #define SLINK_RX_EMPTY (1 << 23) | ||
94 | #define SLINK_TX_UNF (1 << 24) | ||
95 | #define SLINK_RX_OVF (1 << 25) | ||
96 | #define SLINK_TX_FLUSH (1 << 26) | ||
97 | #define SLINK_RX_FLUSH (1 << 27) | ||
98 | #define SLINK_SCLK (1 << 28) | ||
99 | #define SLINK_ERR (1 << 29) | ||
100 | #define SLINK_RDY (1 << 30) | ||
101 | #define SLINK_BSY (1 << 31) | ||
102 | |||
103 | #define SLINK_MAS_DATA 0x010 | ||
104 | #define SLINK_SLAVE_DATA 0x014 | ||
105 | |||
106 | #define SLINK_DMA_CTL 0x018 | ||
107 | #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0) | ||
108 | #define SLINK_TX_TRIG_1 (0 << 16) | ||
109 | #define SLINK_TX_TRIG_4 (1 << 16) | ||
110 | #define SLINK_TX_TRIG_8 (2 << 16) | ||
111 | #define SLINK_TX_TRIG_16 (3 << 16) | ||
112 | #define SLINK_TX_TRIG_MASK (3 << 16) | ||
113 | #define SLINK_RX_TRIG_1 (0 << 18) | ||
114 | #define SLINK_RX_TRIG_4 (1 << 18) | ||
115 | #define SLINK_RX_TRIG_8 (2 << 18) | ||
116 | #define SLINK_RX_TRIG_16 (3 << 18) | ||
117 | #define SLINK_RX_TRIG_MASK (3 << 18) | ||
118 | #define SLINK_PACKED (1 << 20) | ||
119 | #define SLINK_PACK_SIZE_4 (0 << 21) | ||
120 | #define SLINK_PACK_SIZE_8 (1 << 21) | ||
121 | #define SLINK_PACK_SIZE_16 (2 << 21) | ||
122 | #define SLINK_PACK_SIZE_32 (3 << 21) | ||
123 | #define SLINK_PACK_SIZE_MASK (3 << 21) | ||
124 | #define SLINK_IE_TXC (1 << 26) | ||
125 | #define SLINK_IE_RXC (1 << 27) | ||
126 | #define SLINK_DMA_EN (1 << 31) | ||
127 | |||
128 | #define SLINK_STATUS2 0x01c | ||
129 | #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0) | ||
130 | #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f) >> 16) | ||
131 | |||
132 | #define SLINK_TX_FIFO 0x100 | ||
133 | #define SLINK_RX_FIFO 0x180 | ||
134 | |||
135 | static const unsigned long spi_tegra_req_sels[] = { | ||
136 | TEGRA_DMA_REQ_SEL_SL2B1, | ||
137 | TEGRA_DMA_REQ_SEL_SL2B2, | ||
138 | TEGRA_DMA_REQ_SEL_SL2B3, | ||
139 | TEGRA_DMA_REQ_SEL_SL2B4, | ||
140 | }; | ||
141 | |||
142 | #define BB_LEN 32 | ||
143 | |||
144 | struct spi_tegra_data { | ||
145 | struct spi_master *master; | ||
146 | struct platform_device *pdev; | ||
147 | spinlock_t lock; | ||
148 | |||
149 | struct clk *clk; | ||
150 | void __iomem *base; | ||
151 | unsigned long phys; | ||
152 | |||
153 | u32 cur_speed; | ||
154 | |||
155 | struct list_head queue; | ||
156 | struct spi_transfer *cur; | ||
157 | unsigned cur_pos; | ||
158 | unsigned cur_len; | ||
159 | unsigned cur_bytes_per_word; | ||
160 | |||
161 | /* The tegra spi controller has a bug which causes the first word | ||
162 | * in PIO transactions to be garbage. Since packed DMA transactions | ||
163 | * require transfers to be 4 byte aligned we need a bounce buffer | ||
164 | * for the generic case. | ||
165 | */ | ||
166 | int dma_req_len; | ||
167 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
168 | struct tegra_dma_req rx_dma_req; | ||
169 | struct tegra_dma_channel *rx_dma; | ||
170 | #else | ||
171 | struct dma_chan *rx_dma; | ||
172 | struct dma_slave_config sconfig; | ||
173 | struct dma_async_tx_descriptor *rx_dma_desc; | ||
174 | dma_cookie_t rx_cookie; | ||
175 | #endif | ||
176 | u32 *rx_bb; | ||
177 | dma_addr_t rx_bb_phys; | ||
178 | }; | ||
179 | |||
180 | #if !defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
181 | static void tegra_spi_rx_dma_complete(void *args); | ||
182 | #endif | ||
183 | |||
184 | static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi, | ||
185 | unsigned long reg) | ||
186 | { | ||
187 | return readl(tspi->base + reg); | ||
188 | } | ||
189 | |||
190 | static inline void spi_tegra_writel(struct spi_tegra_data *tspi, | ||
191 | unsigned long val, | ||
192 | unsigned long reg) | ||
193 | { | ||
194 | writel(val, tspi->base + reg); | ||
195 | } | ||
196 | |||
197 | static void spi_tegra_go(struct spi_tegra_data *tspi) | ||
198 | { | ||
199 | unsigned long val; | ||
200 | |||
201 | wmb(); | ||
202 | |||
203 | val = spi_tegra_readl(tspi, SLINK_DMA_CTL); | ||
204 | val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN; | ||
205 | val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1); | ||
206 | spi_tegra_writel(tspi, val, SLINK_DMA_CTL); | ||
207 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
208 | tspi->rx_dma_req.size = tspi->dma_req_len; | ||
209 | tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req); | ||
210 | #else | ||
211 | tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma, | ||
212 | tspi->rx_bb_phys, tspi->dma_req_len, | ||
213 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); | ||
214 | if (!tspi->rx_dma_desc) { | ||
215 | dev_err(&tspi->pdev->dev, "dmaengine slave prep failed\n"); | ||
216 | return; | ||
217 | } | ||
218 | tspi->rx_dma_desc->callback = tegra_spi_rx_dma_complete; | ||
219 | tspi->rx_dma_desc->callback_param = tspi; | ||
220 | tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc); | ||
221 | dma_async_issue_pending(tspi->rx_dma); | ||
222 | #endif | ||
223 | |||
224 | val |= SLINK_DMA_EN; | ||
225 | spi_tegra_writel(tspi, val, SLINK_DMA_CTL); | ||
226 | } | ||
227 | |||
228 | static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi, | ||
229 | struct spi_transfer *t) | ||
230 | { | ||
231 | unsigned len = min(t->len - tspi->cur_pos, BB_LEN * | ||
232 | tspi->cur_bytes_per_word); | ||
233 | u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_pos; | ||
234 | int i, j; | ||
235 | unsigned long val; | ||
236 | |||
237 | val = spi_tegra_readl(tspi, SLINK_COMMAND); | ||
238 | val &= ~SLINK_WORD_SIZE(~0); | ||
239 | val |= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1); | ||
240 | spi_tegra_writel(tspi, val, SLINK_COMMAND); | ||
241 | |||
242 | for (i = 0; i < len; i += tspi->cur_bytes_per_word) { | ||
243 | val = 0; | ||
244 | for (j = 0; j < tspi->cur_bytes_per_word; j++) | ||
245 | val |= tx_buf[i + j] << j * 8; | ||
246 | |||
247 | spi_tegra_writel(tspi, val, SLINK_TX_FIFO); | ||
248 | } | ||
249 | |||
250 | tspi->dma_req_len = len / tspi->cur_bytes_per_word * 4; | ||
251 | |||
252 | return len; | ||
253 | } | ||
254 | |||
255 | static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi, | ||
256 | struct spi_transfer *t) | ||
257 | { | ||
258 | unsigned len = tspi->cur_len; | ||
259 | u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_pos; | ||
260 | int i, j; | ||
261 | unsigned long val; | ||
262 | |||
263 | for (i = 0; i < len; i += tspi->cur_bytes_per_word) { | ||
264 | val = tspi->rx_bb[i / tspi->cur_bytes_per_word]; | ||
265 | for (j = 0; j < tspi->cur_bytes_per_word; j++) | ||
266 | rx_buf[i + j] = (val >> (j * 8)) & 0xff; | ||
267 | } | ||
268 | |||
269 | return len; | ||
270 | } | ||
271 | |||
272 | static void spi_tegra_start_transfer(struct spi_device *spi, | ||
273 | struct spi_transfer *t) | ||
274 | { | ||
275 | struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master); | ||
276 | u32 speed; | ||
277 | u8 bits_per_word; | ||
278 | unsigned long val; | ||
279 | |||
280 | speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz; | ||
281 | bits_per_word = t->bits_per_word ? t->bits_per_word : | ||
282 | spi->bits_per_word; | ||
283 | |||
284 | tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1; | ||
285 | |||
286 | if (speed != tspi->cur_speed) | ||
287 | clk_set_rate(tspi->clk, speed); | ||
288 | |||
289 | if (tspi->cur_speed == 0) | ||
290 | clk_prepare_enable(tspi->clk); | ||
291 | |||
292 | tspi->cur_speed = speed; | ||
293 | |||
294 | val = spi_tegra_readl(tspi, SLINK_COMMAND2); | ||
295 | val &= ~SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN; | ||
296 | if (t->rx_buf) | ||
297 | val |= SLINK_RXEN; | ||
298 | if (t->tx_buf) | ||
299 | val |= SLINK_TXEN; | ||
300 | val |= SLINK_SS_EN_CS(spi->chip_select); | ||
301 | val |= SLINK_SPIE; | ||
302 | spi_tegra_writel(tspi, val, SLINK_COMMAND2); | ||
303 | |||
304 | val = spi_tegra_readl(tspi, SLINK_COMMAND); | ||
305 | val &= ~SLINK_BIT_LENGTH(~0); | ||
306 | val |= SLINK_BIT_LENGTH(bits_per_word - 1); | ||
307 | |||
308 | /* FIXME: should probably control CS manually so that we can be sure | ||
309 | * it does not go low between transfer and to support delay_usecs | ||
310 | * correctly. | ||
311 | */ | ||
312 | val &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA & ~SLINK_CS_SW; | ||
313 | |||
314 | if (spi->mode & SPI_CPHA) | ||
315 | val |= SLINK_CK_SDA; | ||
316 | |||
317 | if (spi->mode & SPI_CPOL) | ||
318 | val |= SLINK_IDLE_SCLK_DRIVE_HIGH; | ||
319 | else | ||
320 | val |= SLINK_IDLE_SCLK_DRIVE_LOW; | ||
321 | |||
322 | val |= SLINK_M_S; | ||
323 | |||
324 | spi_tegra_writel(tspi, val, SLINK_COMMAND); | ||
325 | |||
326 | spi_tegra_writel(tspi, SLINK_RX_FLUSH | SLINK_TX_FLUSH, SLINK_STATUS); | ||
327 | |||
328 | tspi->cur = t; | ||
329 | tspi->cur_pos = 0; | ||
330 | tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t); | ||
331 | |||
332 | spi_tegra_go(tspi); | ||
333 | } | ||
334 | |||
335 | static void spi_tegra_start_message(struct spi_device *spi, | ||
336 | struct spi_message *m) | ||
337 | { | ||
338 | struct spi_transfer *t; | ||
339 | |||
340 | m->actual_length = 0; | ||
341 | m->status = 0; | ||
342 | |||
343 | t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list); | ||
344 | spi_tegra_start_transfer(spi, t); | ||
345 | } | ||
346 | |||
347 | static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi) | ||
348 | { | ||
349 | unsigned long flags; | ||
350 | struct spi_message *m; | ||
351 | struct spi_device *spi; | ||
352 | int timeout = 0; | ||
353 | unsigned long val; | ||
354 | |||
355 | /* the SPI controller may come back with both the BSY and RDY bits | ||
356 | * set. In this case we need to wait for the BSY bit to clear so | ||
357 | * that we are sure the DMA is finished. 1000 reads was empirically | ||
358 | * determined to be long enough. | ||
359 | */ | ||
360 | while (timeout++ < 1000) { | ||
361 | if (!(spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY)) | ||
362 | break; | ||
363 | } | ||
364 | |||
365 | spin_lock_irqsave(&tspi->lock, flags); | ||
366 | |||
367 | val = spi_tegra_readl(tspi, SLINK_STATUS); | ||
368 | val |= SLINK_RDY; | ||
369 | spi_tegra_writel(tspi, val, SLINK_STATUS); | ||
370 | |||
371 | m = list_first_entry(&tspi->queue, struct spi_message, queue); | ||
372 | |||
373 | if (timeout >= 1000) | ||
374 | m->status = -EIO; | ||
375 | |||
376 | spi = m->state; | ||
377 | |||
378 | tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur); | ||
379 | m->actual_length += tspi->cur_pos; | ||
380 | |||
381 | if (tspi->cur_pos < tspi->cur->len) { | ||
382 | tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, tspi->cur); | ||
383 | spi_tegra_go(tspi); | ||
384 | } else if (!list_is_last(&tspi->cur->transfer_list, | ||
385 | &m->transfers)) { | ||
386 | tspi->cur = list_first_entry(&tspi->cur->transfer_list, | ||
387 | struct spi_transfer, | ||
388 | transfer_list); | ||
389 | spi_tegra_start_transfer(spi, tspi->cur); | ||
390 | } else { | ||
391 | list_del(&m->queue); | ||
392 | |||
393 | m->complete(m->context); | ||
394 | |||
395 | if (!list_empty(&tspi->queue)) { | ||
396 | m = list_first_entry(&tspi->queue, struct spi_message, | ||
397 | queue); | ||
398 | spi = m->state; | ||
399 | spi_tegra_start_message(spi, m); | ||
400 | } else { | ||
401 | clk_disable_unprepare(tspi->clk); | ||
402 | tspi->cur_speed = 0; | ||
403 | } | ||
404 | } | ||
405 | |||
406 | spin_unlock_irqrestore(&tspi->lock, flags); | ||
407 | } | ||
408 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
409 | static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req) | ||
410 | { | ||
411 | struct spi_tegra_data *tspi = req->dev; | ||
412 | handle_spi_rx_dma_complete(tspi); | ||
413 | } | ||
414 | #else | ||
415 | static void tegra_spi_rx_dma_complete(void *args) | ||
416 | { | ||
417 | struct spi_tegra_data *tspi = args; | ||
418 | handle_spi_rx_dma_complete(tspi); | ||
419 | } | ||
420 | #endif | ||
421 | |||
422 | static int spi_tegra_setup(struct spi_device *spi) | ||
423 | { | ||
424 | struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master); | ||
425 | unsigned long cs_bit; | ||
426 | unsigned long val; | ||
427 | unsigned long flags; | ||
428 | |||
429 | dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", | ||
430 | spi->bits_per_word, | ||
431 | spi->mode & SPI_CPOL ? "" : "~", | ||
432 | spi->mode & SPI_CPHA ? "" : "~", | ||
433 | spi->max_speed_hz); | ||
434 | |||
435 | |||
436 | switch (spi->chip_select) { | ||
437 | case 0: | ||
438 | cs_bit = SLINK_CS_POLARITY; | ||
439 | break; | ||
440 | |||
441 | case 1: | ||
442 | cs_bit = SLINK_CS_POLARITY1; | ||
443 | break; | ||
444 | |||
445 | case 2: | ||
446 | cs_bit = SLINK_CS_POLARITY2; | ||
447 | break; | ||
448 | |||
449 | case 4: | ||
450 | cs_bit = SLINK_CS_POLARITY3; | ||
451 | break; | ||
452 | |||
453 | default: | ||
454 | return -EINVAL; | ||
455 | } | ||
456 | |||
457 | spin_lock_irqsave(&tspi->lock, flags); | ||
458 | |||
459 | val = spi_tegra_readl(tspi, SLINK_COMMAND); | ||
460 | if (spi->mode & SPI_CS_HIGH) | ||
461 | val |= cs_bit; | ||
462 | else | ||
463 | val &= ~cs_bit; | ||
464 | spi_tegra_writel(tspi, val, SLINK_COMMAND); | ||
465 | |||
466 | spin_unlock_irqrestore(&tspi->lock, flags); | ||
467 | |||
468 | return 0; | ||
469 | } | ||
470 | |||
471 | static int spi_tegra_transfer(struct spi_device *spi, struct spi_message *m) | ||
472 | { | ||
473 | struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master); | ||
474 | struct spi_transfer *t; | ||
475 | unsigned long flags; | ||
476 | int was_empty; | ||
477 | |||
478 | if (list_empty(&m->transfers) || !m->complete) | ||
479 | return -EINVAL; | ||
480 | |||
481 | list_for_each_entry(t, &m->transfers, transfer_list) { | ||
482 | if (t->bits_per_word < 0 || t->bits_per_word > 32) | ||
483 | return -EINVAL; | ||
484 | |||
485 | if (t->len == 0) | ||
486 | return -EINVAL; | ||
487 | |||
488 | if (!t->rx_buf && !t->tx_buf) | ||
489 | return -EINVAL; | ||
490 | } | ||
491 | |||
492 | m->state = spi; | ||
493 | |||
494 | spin_lock_irqsave(&tspi->lock, flags); | ||
495 | was_empty = list_empty(&tspi->queue); | ||
496 | list_add_tail(&m->queue, &tspi->queue); | ||
497 | |||
498 | if (was_empty) | ||
499 | spi_tegra_start_message(spi, m); | ||
500 | |||
501 | spin_unlock_irqrestore(&tspi->lock, flags); | ||
502 | |||
503 | return 0; | ||
504 | } | ||
505 | |||
506 | static int __devinit spi_tegra_probe(struct platform_device *pdev) | ||
507 | { | ||
508 | struct spi_master *master; | ||
509 | struct spi_tegra_data *tspi; | ||
510 | struct resource *r; | ||
511 | int ret; | ||
512 | #if !defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
513 | dma_cap_mask_t mask; | ||
514 | #endif | ||
515 | |||
516 | master = spi_alloc_master(&pdev->dev, sizeof *tspi); | ||
517 | if (master == NULL) { | ||
518 | dev_err(&pdev->dev, "master allocation failed\n"); | ||
519 | return -ENOMEM; | ||
520 | } | ||
521 | |||
522 | /* the spi->mode bits understood by this driver: */ | ||
523 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | ||
524 | |||
525 | master->bus_num = pdev->id; | ||
526 | |||
527 | master->setup = spi_tegra_setup; | ||
528 | master->transfer = spi_tegra_transfer; | ||
529 | master->num_chipselect = 4; | ||
530 | |||
531 | dev_set_drvdata(&pdev->dev, master); | ||
532 | tspi = spi_master_get_devdata(master); | ||
533 | tspi->master = master; | ||
534 | tspi->pdev = pdev; | ||
535 | spin_lock_init(&tspi->lock); | ||
536 | |||
537 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
538 | if (r == NULL) { | ||
539 | ret = -ENODEV; | ||
540 | goto err0; | ||
541 | } | ||
542 | |||
543 | if (!request_mem_region(r->start, resource_size(r), | ||
544 | dev_name(&pdev->dev))) { | ||
545 | ret = -EBUSY; | ||
546 | goto err0; | ||
547 | } | ||
548 | |||
549 | tspi->phys = r->start; | ||
550 | tspi->base = ioremap(r->start, resource_size(r)); | ||
551 | if (!tspi->base) { | ||
552 | dev_err(&pdev->dev, "can't ioremap iomem\n"); | ||
553 | ret = -ENOMEM; | ||
554 | goto err1; | ||
555 | } | ||
556 | |||
557 | tspi->clk = clk_get(&pdev->dev, NULL); | ||
558 | if (IS_ERR(tspi->clk)) { | ||
559 | dev_err(&pdev->dev, "can not get clock\n"); | ||
560 | ret = PTR_ERR(tspi->clk); | ||
561 | goto err2; | ||
562 | } | ||
563 | |||
564 | INIT_LIST_HEAD(&tspi->queue); | ||
565 | |||
566 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
567 | tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT); | ||
568 | if (!tspi->rx_dma) { | ||
569 | dev_err(&pdev->dev, "can not allocate rx dma channel\n"); | ||
570 | ret = -ENODEV; | ||
571 | goto err3; | ||
572 | } | ||
573 | #else | ||
574 | dma_cap_zero(mask); | ||
575 | dma_cap_set(DMA_SLAVE, mask); | ||
576 | tspi->rx_dma = dma_request_channel(mask, NULL, NULL); | ||
577 | if (!tspi->rx_dma) { | ||
578 | dev_err(&pdev->dev, "can not allocate rx dma channel\n"); | ||
579 | ret = -ENODEV; | ||
580 | goto err3; | ||
581 | } | ||
582 | |||
583 | #endif | ||
584 | |||
585 | tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN, | ||
586 | &tspi->rx_bb_phys, GFP_KERNEL); | ||
587 | if (!tspi->rx_bb) { | ||
588 | dev_err(&pdev->dev, "can not allocate rx bounce buffer\n"); | ||
589 | ret = -ENOMEM; | ||
590 | goto err4; | ||
591 | } | ||
592 | |||
593 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
594 | tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete; | ||
595 | tspi->rx_dma_req.to_memory = 1; | ||
596 | tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys; | ||
597 | tspi->rx_dma_req.dest_bus_width = 32; | ||
598 | tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO; | ||
599 | tspi->rx_dma_req.source_bus_width = 32; | ||
600 | tspi->rx_dma_req.source_wrap = 4; | ||
601 | tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id]; | ||
602 | tspi->rx_dma_req.dev = tspi; | ||
603 | #else | ||
604 | /* Dmaengine Dma slave config */ | ||
605 | tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; | ||
606 | tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO; | ||
607 | tspi->sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
608 | tspi->sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
609 | tspi->sconfig.slave_id = spi_tegra_req_sels[pdev->id]; | ||
610 | tspi->sconfig.src_maxburst = 1; | ||
611 | tspi->sconfig.dst_maxburst = 1; | ||
612 | ret = dmaengine_device_control(tspi->rx_dma, | ||
613 | DMA_SLAVE_CONFIG, (unsigned long) &tspi->sconfig); | ||
614 | if (ret < 0) { | ||
615 | dev_err(&pdev->dev, "can not do slave configure for dma %d\n", | ||
616 | ret); | ||
617 | goto err4; | ||
618 | } | ||
619 | #endif | ||
620 | |||
621 | master->dev.of_node = pdev->dev.of_node; | ||
622 | ret = spi_register_master(master); | ||
623 | |||
624 | if (ret < 0) | ||
625 | goto err5; | ||
626 | |||
627 | return ret; | ||
628 | |||
629 | err5: | ||
630 | dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN, | ||
631 | tspi->rx_bb, tspi->rx_bb_phys); | ||
632 | err4: | ||
633 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
634 | tegra_dma_free_channel(tspi->rx_dma); | ||
635 | #else | ||
636 | dma_release_channel(tspi->rx_dma); | ||
637 | #endif | ||
638 | err3: | ||
639 | clk_put(tspi->clk); | ||
640 | err2: | ||
641 | iounmap(tspi->base); | ||
642 | err1: | ||
643 | release_mem_region(r->start, resource_size(r)); | ||
644 | err0: | ||
645 | spi_master_put(master); | ||
646 | return ret; | ||
647 | } | ||
648 | |||
649 | static int __devexit spi_tegra_remove(struct platform_device *pdev) | ||
650 | { | ||
651 | struct spi_master *master; | ||
652 | struct spi_tegra_data *tspi; | ||
653 | struct resource *r; | ||
654 | |||
655 | master = spi_master_get(dev_get_drvdata(&pdev->dev)); | ||
656 | tspi = spi_master_get_devdata(master); | ||
657 | |||
658 | spi_unregister_master(master); | ||
659 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
660 | tegra_dma_free_channel(tspi->rx_dma); | ||
661 | #else | ||
662 | dma_release_channel(tspi->rx_dma); | ||
663 | #endif | ||
664 | |||
665 | dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN, | ||
666 | tspi->rx_bb, tspi->rx_bb_phys); | ||
667 | |||
668 | clk_put(tspi->clk); | ||
669 | iounmap(tspi->base); | ||
670 | |||
671 | spi_master_put(master); | ||
672 | |||
673 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
674 | release_mem_region(r->start, resource_size(r)); | ||
675 | |||
676 | return 0; | ||
677 | } | ||
678 | |||
679 | MODULE_ALIAS("platform:spi_tegra"); | ||
680 | |||
681 | #ifdef CONFIG_OF | ||
682 | static struct of_device_id spi_tegra_of_match_table[] __devinitdata = { | ||
683 | { .compatible = "nvidia,tegra20-spi", }, | ||
684 | {} | ||
685 | }; | ||
686 | MODULE_DEVICE_TABLE(of, spi_tegra_of_match_table); | ||
687 | #else /* CONFIG_OF */ | ||
688 | #define spi_tegra_of_match_table NULL | ||
689 | #endif /* CONFIG_OF */ | ||
690 | |||
691 | static struct platform_driver spi_tegra_driver = { | ||
692 | .driver = { | ||
693 | .name = "spi_tegra", | ||
694 | .owner = THIS_MODULE, | ||
695 | .of_match_table = spi_tegra_of_match_table, | ||
696 | }, | ||
697 | .probe = spi_tegra_probe, | ||
698 | .remove = __devexit_p(spi_tegra_remove), | ||
699 | }; | ||
700 | module_platform_driver(spi_tegra_driver); | ||
701 | |||
702 | MODULE_LICENSE("GPL"); | ||