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authorJayamohan Kallickal <jayamohan.kallickal@emulex.com>2011-04-29 15:30:06 -0400
committerJames Bottomley <James.Bottomley@suse.de>2011-05-01 17:33:46 -0400
commit665d6d94b73f1d706d6c006264cce7537ac708f4 (patch)
tree905e08cf48d99976d8b0ad456b810f0c015d67f7 /drivers/scsi
parent87f76152dfb1bf3de18dc01cf97c70a5c9d2583e (diff)
[SCSI] be2iscsi: fix boot hang due to interrupts not getting rearmed
This patch fixes a bug where the interrupts were not rearmed if the Interrupt Mask was enabled. This patch checks for Interrupt mask enabled and still rearms interrupt generation even if the Interrupt mask was enabled Signed-off-by: Jayamohan Kallickal <jayamohan.kallickal@emulex.com> Signed-off-by: Mike Christie <michaelc@cs.wisc.edu> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat (limited to 'drivers/scsi')
-rw-r--r--drivers/scsi/be2iscsi/be_main.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c
index d83413658a9..cea9b275965 100644
--- a/drivers/scsi/be2iscsi/be_main.c
+++ b/drivers/scsi/be2iscsi/be_main.c
@@ -3465,23 +3465,23 @@ static void hwi_enable_intr(struct beiscsi_hba *phba)
3465 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg + 3465 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
3466 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET); 3466 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
3467 reg = ioread32(addr); 3467 reg = ioread32(addr);
3468 SE_DEBUG(DBG_LVL_8, "reg =x%08x\n", reg);
3469 3468
3470 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 3469 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
3471 if (!enabled) { 3470 if (!enabled) {
3472 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 3471 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
3473 SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p\n", reg, addr); 3472 SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p\n", reg, addr);
3474 iowrite32(reg, addr); 3473 iowrite32(reg, addr);
3475 if (!phba->msix_enabled) { 3474 }
3476 eq = &phwi_context->be_eq[0].q; 3475
3476 if (!phba->msix_enabled) {
3477 eq = &phwi_context->be_eq[0].q;
3478 SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
3479 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
3480 } else {
3481 for (i = 0; i <= phba->num_cpus; i++) {
3482 eq = &phwi_context->be_eq[i].q;
3477 SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id); 3483 SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
3478 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); 3484 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
3479 } else {
3480 for (i = 0; i <= phba->num_cpus; i++) {
3481 eq = &phwi_context->be_eq[i].q;
3482 SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
3483 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
3484 }
3485 } 3485 }
3486 } 3486 }
3487} 3487}