[SCSI] lpfc 8.3.17: SLI Additions and Fixes

- Added driver support for management application to pass down two security
  specific mailbox commands (MBX_SECURITY_MGMT and MBX_AUTH_PORT)
- Added driver support for handling FIPS zeroization trap of host ERATT ER8,
  performing selective reset and bringing the device up.
- Added code to detect INIT_LINK mailbox command completion returning status
  MBXERR_SEC_NO_PERMISSION.
- Increased the wait timeout on host status register HS_FFRDY and HS_MBRDY
  being set.
- Remove the port offline code from the Heartbeat TMO handler.

Signed-off-by: Alex Iannicelli <alex.iannicelli@emulex.com>
Signed-off-by: James Smart <james.smart@emulex.com>
Signed-off-by: James Bottomley <James.Bottomley@suse.de>

1 files changed, 39 insertions, 16 deletions

diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c
index bbbd8ba5c1a..34dd87f542c 100644
--- a/drivers/scsi/lpfc/lpfc_sli.c
+++ b/drivers/scsi/lpfc/lpfc_sli.c
@@ -1677,6 +1677,8 @@ lpfc_sli_chk_mbx_command(uint8_t mbxCommand)
         case MBX_RESUME_RPI:
         case MBX_READ_EVENT_LOG_STATUS:
         case MBX_READ_EVENT_LOG:
+        case MBX_SECURITY_MGMT:
+        case MBX_AUTH_PORT:
                 ret = mbxCommand;
                 break;
         default:
@@ -1781,6 +1783,13 @@ lpfc_sli_def_mbox_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb)
                 pmb->context2 = NULL;
         }
 
+        /* Check security permission status on INIT_LINK mailbox command */
+        if ((pmb->u.mb.mbxCommand == MBX_INIT_LINK) &&
+            (pmb->u.mb.mbxStatus == MBXERR_SEC_NO_PERMISSION))
+                lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
+                                "2860 SLI authentication is required "
+                                "for INIT_LINK but has not done yet\n");
+
         if (bf_get(lpfc_mqe_command, &pmb->u.mqe) == MBX_SLI4_CONFIG)
                 lpfc_sli4_mbox_cmd_free(phba, pmb);
         else
@@ -3658,11 +3667,15 @@ lpfc_sli_chipset_init(struct lpfc_hba *phba)
         i = 0;
         while ((status & (HS_FFRDY | HS_MBRDY)) != (HS_FFRDY | HS_MBRDY)) {
 
-                /* Check every 100ms for 5 retries, then every 500ms for 5, then
-                 * every 2.5 sec for 5, then reset board and every 2.5 sec for
-                 * 4.
+                /* Check every 10ms for 10 retries, then every 100ms for 90
+                 * retries, then every 1 sec for 50 retires for a total of
+                 * ~60 seconds before reset the board again and check every
+                 * 1 sec for 50 retries. The up to 60 seconds before the
+                 * board ready is required by the Falcon FIPS zeroization
+                 * complete, and any reset the board in between shall cause
+                 * restart of zeroization, further delay the board ready.
                  */
-                if (i++ >= 20) {
+                if (i++ >= 200) {
                         /* Adapter failed to init, timeout, status reg
                            <status> */
                         lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
@@ -3690,16 +3703,15 @@ lpfc_sli_chipset_init(struct lpfc_hba *phba)
                         return -EIO;
                 }
 
-                if (i <= 5) {
+                if (i <= 10)
                         msleep(10);
-                } else if (i <= 10) {
-                        msleep(500);
-                } else {
-                        msleep(2500);
-                }
+                else if (i <= 100)
+                        msleep(100);
+                else
+                        msleep(1000);
 
-                if (i == 15) {
-                                /* Do post */
+                if (i == 150) {
+                        /* Do post */
                         phba->pport->port_state = LPFC_VPORT_UNKNOWN;
                         lpfc_sli_brdrestart(phba);
                 }
@@ -5950,6 +5962,8 @@ lpfc_sli4_iocb2wqe(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq,
         uint8_t command_type = ELS_COMMAND_NON_FIP;
         uint8_t cmnd;
         uint16_t xritag;
+        uint16_t abrt_iotag;
+        struct lpfc_iocbq *abrtiocbq;
         struct ulp_bde64 *bpl = NULL;
         uint32_t els_id = ELS_ID_DEFAULT;
         int numBdes, i;
@@ -6162,9 +6176,17 @@ lpfc_sli4_iocb2wqe(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq,
         case CMD_ABORT_XRI_CX:
                 /* words 0-2 memcpy should be 0 rserved */
                 /* port will send abts */
-                if (iocbq->iocb.ulpCommand == CMD_CLOSE_XRI_CN)
+                abrt_iotag = iocbq->iocb.un.acxri.abortContextTag;
+                if (abrt_iotag != 0 && abrt_iotag <= phba->sli.last_iotag) {
+                        abrtiocbq = phba->sli.iocbq_lookup[abrt_iotag];
+                        fip = abrtiocbq->iocb_flag & LPFC_FIP_ELS_ID_MASK;
+                } else
+                        fip = 0;
+
+                if ((iocbq->iocb.ulpCommand == CMD_CLOSE_XRI_CN) || fip)
                         /*
-                         * The link is down so the fw does not need to send abts
+                         * The link is down, or the command was ELS_FIP
+                         * so the fw does not need to send abts
                          * on the wire.
                          */
                         bf_set(abort_cmd_ia, &wqe->abort_cmd, 1);
@@ -7895,7 +7917,7 @@ lpfc_sli_eratt_read(struct lpfc_hba *phba)
                 /* Check if there is a deferred error condition is active */
                 if ((HS_FFER1 & phba->work_hs) &&
                     ((HS_FFER2 | HS_FFER3 | HS_FFER4 | HS_FFER5 |
-                     HS_FFER6 | HS_FFER7) & phba->work_hs)) {
+                      HS_FFER6 | HS_FFER7 | HS_FFER8) & phba->work_hs)) {
                         phba->hba_flag |= DEFER_ERATT;
                         /* Clear all interrupt enable conditions */
                         writel(0, phba->HCregaddr);
@@ -8211,7 +8233,8 @@ lpfc_sli_sp_intr_handler(int irq, void *dev_id)
                          */
                         if ((HS_FFER1 & phba->work_hs) &&
                                 ((HS_FFER2 | HS_FFER3 | HS_FFER4 | HS_FFER5 |
-                                HS_FFER6 | HS_FFER7) & phba->work_hs)) {
+                                  HS_FFER6 | HS_FFER7 | HS_FFER8) &
+                                  phba->work_hs)) {
                                 phba->hba_flag |= DEFER_ERATT;
                                 /* Clear all interrupt enable conditions */
                                 writel(0, phba->HCregaddr);