diff options
author | Jeff Garzik <jeff@garzik.org> | 2006-03-23 00:32:03 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2006-03-23 00:32:03 -0500 |
commit | 2cc432eed0491df66e14b578139bba2c75fb3f9a (patch) | |
tree | 5629388698a637ac8b211dff2d0168b5f9d6aa81 /drivers/scsi/libata-core.c | |
parent | 50106c5a0366c9e02bf872e85c672732aa517fb4 (diff) |
[libata] Move some bmdma-specific code to libata-bmdma.c
No code changes, just moving code between files.
Diffstat (limited to 'drivers/scsi/libata-core.c')
-rw-r--r-- | drivers/scsi/libata-core.c | 234 |
1 files changed, 0 insertions, 234 deletions
diff --git a/drivers/scsi/libata-core.c b/drivers/scsi/libata-core.c index 0314abd97f2..f3c115b5568 100644 --- a/drivers/scsi/libata-core.c +++ b/drivers/scsi/libata-core.c | |||
@@ -4065,240 +4065,6 @@ unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc) | |||
4065 | } | 4065 | } |
4066 | 4066 | ||
4067 | /** | 4067 | /** |
4068 | * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction | ||
4069 | * @qc: Info associated with this ATA transaction. | ||
4070 | * | ||
4071 | * LOCKING: | ||
4072 | * spin_lock_irqsave(host_set lock) | ||
4073 | */ | ||
4074 | |||
4075 | static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc) | ||
4076 | { | ||
4077 | struct ata_port *ap = qc->ap; | ||
4078 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | ||
4079 | u8 dmactl; | ||
4080 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
4081 | |||
4082 | /* load PRD table addr. */ | ||
4083 | mb(); /* make sure PRD table writes are visible to controller */ | ||
4084 | writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS); | ||
4085 | |||
4086 | /* specify data direction, triple-check start bit is clear */ | ||
4087 | dmactl = readb(mmio + ATA_DMA_CMD); | ||
4088 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | ||
4089 | if (!rw) | ||
4090 | dmactl |= ATA_DMA_WR; | ||
4091 | writeb(dmactl, mmio + ATA_DMA_CMD); | ||
4092 | |||
4093 | /* issue r/w command */ | ||
4094 | ap->ops->exec_command(ap, &qc->tf); | ||
4095 | } | ||
4096 | |||
4097 | /** | ||
4098 | * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction | ||
4099 | * @qc: Info associated with this ATA transaction. | ||
4100 | * | ||
4101 | * LOCKING: | ||
4102 | * spin_lock_irqsave(host_set lock) | ||
4103 | */ | ||
4104 | |||
4105 | static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc) | ||
4106 | { | ||
4107 | struct ata_port *ap = qc->ap; | ||
4108 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
4109 | u8 dmactl; | ||
4110 | |||
4111 | /* start host DMA transaction */ | ||
4112 | dmactl = readb(mmio + ATA_DMA_CMD); | ||
4113 | writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); | ||
4114 | |||
4115 | /* Strictly, one may wish to issue a readb() here, to | ||
4116 | * flush the mmio write. However, control also passes | ||
4117 | * to the hardware at this point, and it will interrupt | ||
4118 | * us when we are to resume control. So, in effect, | ||
4119 | * we don't care when the mmio write flushes. | ||
4120 | * Further, a read of the DMA status register _immediately_ | ||
4121 | * following the write may not be what certain flaky hardware | ||
4122 | * is expected, so I think it is best to not add a readb() | ||
4123 | * without first all the MMIO ATA cards/mobos. | ||
4124 | * Or maybe I'm just being paranoid. | ||
4125 | */ | ||
4126 | } | ||
4127 | |||
4128 | /** | ||
4129 | * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO) | ||
4130 | * @qc: Info associated with this ATA transaction. | ||
4131 | * | ||
4132 | * LOCKING: | ||
4133 | * spin_lock_irqsave(host_set lock) | ||
4134 | */ | ||
4135 | |||
4136 | static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc) | ||
4137 | { | ||
4138 | struct ata_port *ap = qc->ap; | ||
4139 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | ||
4140 | u8 dmactl; | ||
4141 | |||
4142 | /* load PRD table addr. */ | ||
4143 | outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | ||
4144 | |||
4145 | /* specify data direction, triple-check start bit is clear */ | ||
4146 | dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
4147 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | ||
4148 | if (!rw) | ||
4149 | dmactl |= ATA_DMA_WR; | ||
4150 | outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
4151 | |||
4152 | /* issue r/w command */ | ||
4153 | ap->ops->exec_command(ap, &qc->tf); | ||
4154 | } | ||
4155 | |||
4156 | /** | ||
4157 | * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO) | ||
4158 | * @qc: Info associated with this ATA transaction. | ||
4159 | * | ||
4160 | * LOCKING: | ||
4161 | * spin_lock_irqsave(host_set lock) | ||
4162 | */ | ||
4163 | |||
4164 | static void ata_bmdma_start_pio (struct ata_queued_cmd *qc) | ||
4165 | { | ||
4166 | struct ata_port *ap = qc->ap; | ||
4167 | u8 dmactl; | ||
4168 | |||
4169 | /* start host DMA transaction */ | ||
4170 | dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
4171 | outb(dmactl | ATA_DMA_START, | ||
4172 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
4173 | } | ||
4174 | |||
4175 | |||
4176 | /** | ||
4177 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | ||
4178 | * @qc: Info associated with this ATA transaction. | ||
4179 | * | ||
4180 | * Writes the ATA_DMA_START flag to the DMA command register. | ||
4181 | * | ||
4182 | * May be used as the bmdma_start() entry in ata_port_operations. | ||
4183 | * | ||
4184 | * LOCKING: | ||
4185 | * spin_lock_irqsave(host_set lock) | ||
4186 | */ | ||
4187 | void ata_bmdma_start(struct ata_queued_cmd *qc) | ||
4188 | { | ||
4189 | if (qc->ap->flags & ATA_FLAG_MMIO) | ||
4190 | ata_bmdma_start_mmio(qc); | ||
4191 | else | ||
4192 | ata_bmdma_start_pio(qc); | ||
4193 | } | ||
4194 | |||
4195 | |||
4196 | /** | ||
4197 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | ||
4198 | * @qc: Info associated with this ATA transaction. | ||
4199 | * | ||
4200 | * Writes address of PRD table to device's PRD Table Address | ||
4201 | * register, sets the DMA control register, and calls | ||
4202 | * ops->exec_command() to start the transfer. | ||
4203 | * | ||
4204 | * May be used as the bmdma_setup() entry in ata_port_operations. | ||
4205 | * | ||
4206 | * LOCKING: | ||
4207 | * spin_lock_irqsave(host_set lock) | ||
4208 | */ | ||
4209 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | ||
4210 | { | ||
4211 | if (qc->ap->flags & ATA_FLAG_MMIO) | ||
4212 | ata_bmdma_setup_mmio(qc); | ||
4213 | else | ||
4214 | ata_bmdma_setup_pio(qc); | ||
4215 | } | ||
4216 | |||
4217 | |||
4218 | /** | ||
4219 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | ||
4220 | * @ap: Port associated with this ATA transaction. | ||
4221 | * | ||
4222 | * Clear interrupt and error flags in DMA status register. | ||
4223 | * | ||
4224 | * May be used as the irq_clear() entry in ata_port_operations. | ||
4225 | * | ||
4226 | * LOCKING: | ||
4227 | * spin_lock_irqsave(host_set lock) | ||
4228 | */ | ||
4229 | |||
4230 | void ata_bmdma_irq_clear(struct ata_port *ap) | ||
4231 | { | ||
4232 | if (!ap->ioaddr.bmdma_addr) | ||
4233 | return; | ||
4234 | |||
4235 | if (ap->flags & ATA_FLAG_MMIO) { | ||
4236 | void __iomem *mmio = | ||
4237 | ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS; | ||
4238 | writeb(readb(mmio), mmio); | ||
4239 | } else { | ||
4240 | unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS; | ||
4241 | outb(inb(addr), addr); | ||
4242 | } | ||
4243 | } | ||
4244 | |||
4245 | |||
4246 | /** | ||
4247 | * ata_bmdma_status - Read PCI IDE BMDMA status | ||
4248 | * @ap: Port associated with this ATA transaction. | ||
4249 | * | ||
4250 | * Read and return BMDMA status register. | ||
4251 | * | ||
4252 | * May be used as the bmdma_status() entry in ata_port_operations. | ||
4253 | * | ||
4254 | * LOCKING: | ||
4255 | * spin_lock_irqsave(host_set lock) | ||
4256 | */ | ||
4257 | |||
4258 | u8 ata_bmdma_status(struct ata_port *ap) | ||
4259 | { | ||
4260 | u8 host_stat; | ||
4261 | if (ap->flags & ATA_FLAG_MMIO) { | ||
4262 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
4263 | host_stat = readb(mmio + ATA_DMA_STATUS); | ||
4264 | } else | ||
4265 | host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | ||
4266 | return host_stat; | ||
4267 | } | ||
4268 | |||
4269 | |||
4270 | /** | ||
4271 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | ||
4272 | * @qc: Command we are ending DMA for | ||
4273 | * | ||
4274 | * Clears the ATA_DMA_START flag in the dma control register | ||
4275 | * | ||
4276 | * May be used as the bmdma_stop() entry in ata_port_operations. | ||
4277 | * | ||
4278 | * LOCKING: | ||
4279 | * spin_lock_irqsave(host_set lock) | ||
4280 | */ | ||
4281 | |||
4282 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | ||
4283 | { | ||
4284 | struct ata_port *ap = qc->ap; | ||
4285 | if (ap->flags & ATA_FLAG_MMIO) { | ||
4286 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | ||
4287 | |||
4288 | /* clear start/stop bit */ | ||
4289 | writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | ||
4290 | mmio + ATA_DMA_CMD); | ||
4291 | } else { | ||
4292 | /* clear start/stop bit */ | ||
4293 | outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START, | ||
4294 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | ||
4295 | } | ||
4296 | |||
4297 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | ||
4298 | ata_altstatus(ap); /* dummy read */ | ||
4299 | } | ||
4300 | |||
4301 | /** | ||
4302 | * ata_host_intr - Handle host interrupt for given (port, task) | 4068 | * ata_host_intr - Handle host interrupt for given (port, task) |
4303 | * @ap: Port on which interrupt arrived (possibly...) | 4069 | * @ap: Port on which interrupt arrived (possibly...) |
4304 | * @qc: Taskfile currently active in engine | 4070 | * @qc: Taskfile currently active in engine |