diff options
author | Dan Williams <dan.j.williams@intel.com> | 2011-09-02 00:18:26 -0400 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2011-09-22 07:00:56 -0400 |
commit | 13257cfbc57e9cf84fd9fe0cb7a909b3fb4f7482 (patch) | |
tree | 3be778524380e5113b5898db900fc00a25de20d8 /drivers/scsi/isci | |
parent | 8ec6552f4a77d15f446b00aed364e3c12d38aa6c (diff) |
[SCSI] isci: fix sgpio register definitions
output_data_select registers are off by one u32
delete the macros we will never use.
Reported-by: Artur Wojcik <artur.wojcik@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/isci')
-rw-r--r-- | drivers/scsi/isci/registers.h | 122 |
1 files changed, 4 insertions, 118 deletions
diff --git a/drivers/scsi/isci/registers.h b/drivers/scsi/isci/registers.h index 00afc738bbe..eaa541afc75 100644 --- a/drivers/scsi/isci/registers.h +++ b/drivers/scsi/isci/registers.h | |||
@@ -875,122 +875,6 @@ struct scu_iit_entry { | |||
875 | #define SCU_PTSxSR_GEN_BIT(name) \ | 875 | #define SCU_PTSxSR_GEN_BIT(name) \ |
876 | SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ ## name) | 876 | SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ ## name) |
877 | 877 | ||
878 | |||
879 | /* | ||
880 | * ***************************************************************************** | ||
881 | * * SGPIO Register shift and mask values | ||
882 | * ***************************************************************************** */ | ||
883 | #define SCU_SGPIO_CONTROL_SGPIO_ENABLE_SHIFT (0) | ||
884 | #define SCU_SGPIO_CONTROL_SGPIO_ENABLE_MASK (0x00000001) | ||
885 | #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_SHIFT (1) | ||
886 | #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_MASK (0x00000002) | ||
887 | #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_SHIFT (2) | ||
888 | #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_MASK (0x00000004) | ||
889 | #define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_SHIFT (15) | ||
890 | #define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_MASK (0x00008000) | ||
891 | #define SCU_SGPIO_CONTROL_SGPIO_RESERVED_MASK (0xFFFF7FF8) | ||
892 | |||
893 | #define SCU_SGICRx_GEN_BIT(name) \ | ||
894 | SCU_GEN_BIT(SCU_SGPIO_CONTROL_SGPIO_ ## name) | ||
895 | |||
896 | #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_SHIFT (0) | ||
897 | #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_MASK (0x0000000F) | ||
898 | #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_SHIFT (4) | ||
899 | #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_MASK (0x000000F0) | ||
900 | #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_SHIFT (8) | ||
901 | #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_MASK (0x00000F00) | ||
902 | #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_SHIFT (12) | ||
903 | #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_MASK (0x0000F000) | ||
904 | #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_RESERVED_MASK (0xFFFF0000) | ||
905 | |||
906 | #define SCU_SGPBRx_GEN_VAL(name, value) \ | ||
907 | SCU_GEN_VALUE(SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_ ## name, value) | ||
908 | |||
909 | #define SCU_SGPIO_START_DRIVE_LOWER_R0_SHIFT (0) | ||
910 | #define SCU_SGPIO_START_DRIVE_LOWER_R0_MASK (0x00000003) | ||
911 | #define SCU_SGPIO_START_DRIVE_LOWER_R1_SHIFT (4) | ||
912 | #define SCU_SGPIO_START_DRIVE_LOWER_R1_MASK (0x00000030) | ||
913 | #define SCU_SGPIO_START_DRIVE_LOWER_R2_SHIFT (8) | ||
914 | #define SCU_SGPIO_START_DRIVE_LOWER_R2_MASK (0x00000300) | ||
915 | #define SCU_SGPIO_START_DRIVE_LOWER_R3_SHIFT (12) | ||
916 | #define SCU_SGPIO_START_DRIVE_LOWER_R3_MASK (0x00003000) | ||
917 | #define SCU_SGPIO_START_DRIVE_LOWER_RESERVED_MASK (0xFFFF8888) | ||
918 | |||
919 | #define SCU_SGSDLRx_GEN_VAL(name, value) \ | ||
920 | SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_ ## name, value) | ||
921 | |||
922 | #define SCU_SGPIO_START_DRIVE_UPPER_R0_SHIFT (0) | ||
923 | #define SCU_SGPIO_START_DRIVE_UPPER_R0_MASK (0x00000003) | ||
924 | #define SCU_SGPIO_START_DRIVE_UPPER_R1_SHIFT (4) | ||
925 | #define SCU_SGPIO_START_DRIVE_UPPER_R1_MASK (0x00000030) | ||
926 | #define SCU_SGPIO_START_DRIVE_UPPER_R2_SHIFT (8) | ||
927 | #define SCU_SGPIO_START_DRIVE_UPPER_R2_MASK (0x00000300) | ||
928 | #define SCU_SGPIO_START_DRIVE_UPPER_R3_SHIFT (12) | ||
929 | #define SCU_SGPIO_START_DRIVE_UPPER_R3_MASK (0x00003000) | ||
930 | #define SCU_SGPIO_START_DRIVE_UPPER_RESERVED_MASK (0xFFFF8888) | ||
931 | |||
932 | #define SCU_SGSDURx_GEN_VAL(name, value) \ | ||
933 | SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_ ## name, value) | ||
934 | |||
935 | #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_SHIFT (0) | ||
936 | #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_MASK (0x00000003) | ||
937 | #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_SHIFT (4) | ||
938 | #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_MASK (0x00000030) | ||
939 | #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_SHIFT (8) | ||
940 | #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_MASK (0x00000300) | ||
941 | #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_SHIFT (12) | ||
942 | #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_MASK (0x00003000) | ||
943 | #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_RESERVED_MASK (0xFFFF8888) | ||
944 | |||
945 | #define SCU_SGSIDLRx_GEN_VAL(name, value) \ | ||
946 | SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_ ## name, value) | ||
947 | |||
948 | #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_SHIFT (0) | ||
949 | #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_MASK (0x00000003) | ||
950 | #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_SHIFT (4) | ||
951 | #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_MASK (0x00000030) | ||
952 | #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_SHIFT (8) | ||
953 | #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_MASK (0x00000300) | ||
954 | #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_SHIFT (12) | ||
955 | #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_MASK (0x00003000) | ||
956 | #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_RESERVED_MASK (0xFFFF8888) | ||
957 | |||
958 | #define SCU_SGSIDURx_GEN_VAL(name, value) \ | ||
959 | SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_ ## name, value) | ||
960 | |||
961 | #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_SHIFT (0) | ||
962 | #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_MASK (0x0000000F) | ||
963 | #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_RESERVED_MASK (0xFFFFFFF0) | ||
964 | |||
965 | #define SCU_SGVSCR_GEN_VAL(value) \ | ||
966 | SCU_GEN_VALUE(SCU_SGPIO_VENDOR_SPECIFIC_CODE ## name, value) | ||
967 | |||
968 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_SHIFT (0) | ||
969 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_MASK (0x00000003) | ||
970 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_SHIFT (2) | ||
971 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_MASK (0x00000004) | ||
972 | #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_SHIFT (3) | ||
973 | #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_MASK (0x00000008) | ||
974 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_SHIFT (4) | ||
975 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_MASK (0x00000030) | ||
976 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_SHIFT (6) | ||
977 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_MASK (0x00000040) | ||
978 | #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_SHIFT (7) | ||
979 | #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_MASK (0x00000080) | ||
980 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_SHIFT (8) | ||
981 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_MASK (0x00000300) | ||
982 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_SHIFT (10) | ||
983 | #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_MASK (0x00000400) | ||
984 | #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_SHIFT (11) | ||
985 | #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_MASK (0x00000800) | ||
986 | #define SCU_SGPIO_OUPUT_DATA_SELECT_RESERVED_MASK (0xFFFFF000) | ||
987 | |||
988 | #define SCU_SGODSR_GEN_VAL(name, value) \ | ||
989 | SCU_GEN_VALUE(SCU_SGPIO_OUPUT_DATA_SELECT_ ## name, value) | ||
990 | |||
991 | #define SCU_SGODSR_GEN_BIT(name) \ | ||
992 | SCU_GEN_BIT(SCU_SGPIO_OUPUT_DATA_SELECT_ ## name) | ||
993 | |||
994 | /* | 878 | /* |
995 | * ***************************************************************************** | 879 | * ***************************************************************************** |
996 | * * SMU Registers | 880 | * * SMU Registers |
@@ -1529,10 +1413,12 @@ struct scu_sgpio_registers { | |||
1529 | u32 serial_input_upper; | 1413 | u32 serial_input_upper; |
1530 | /* 0x0018 SGPIO_SGVSCR */ | 1414 | /* 0x0018 SGPIO_SGVSCR */ |
1531 | u32 vendor_specific_code; | 1415 | u32 vendor_specific_code; |
1416 | /* 0x001C Reserved */ | ||
1417 | u32 reserved_001c; | ||
1532 | /* 0x0020 SGPIO_SGODSR */ | 1418 | /* 0x0020 SGPIO_SGODSR */ |
1533 | u32 ouput_data_select[8]; | 1419 | u32 output_data_select[8]; |
1534 | /* Remainder of memory space 256 bytes */ | 1420 | /* Remainder of memory space 256 bytes */ |
1535 | u32 reserved_1444_14ff[0x31]; | 1421 | u32 reserved_1444_14ff[0x30]; |
1536 | 1422 | ||
1537 | }; | 1423 | }; |
1538 | 1424 | ||