aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci
diff options
context:
space:
mode:
authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>2005-11-23 23:44:01 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2006-01-09 15:13:16 -0500
commit6558b6ab145ceead45632e4214cd5ef14f48f412 (patch)
tree9316df4d5e28567a4e6f6da4c4cc73b0d98acb0d /drivers/pci
parente00e57efa3448b18c0deedce32732e28683cb73d (diff)
[PATCH] shpchp: fix improper reference to Slot Avail Regsister
The hpc_get_max_bus_speed() function of the SHPCHP driver seems to refer wrong bits in the "Slot Avail Register I" and "Slot Avail Register II". This patch fixes this bug. And this also cleanup the code. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c33
1 files changed, 16 insertions, 17 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index 9987a6fd65b..3c1d3b4b040 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -1121,7 +1121,6 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1121 int retval = 0; 1121 int retval = 0;
1122 u8 pi; 1122 u8 pi;
1123 u32 slot_avail1, slot_avail2; 1123 u32 slot_avail1, slot_avail2;
1124 int slot_num;
1125 1124
1126 DBG_ENTER_ROUTINE 1125 DBG_ENTER_ROUTINE
1127 1126
@@ -1140,39 +1139,39 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1140 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2); 1139 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
1141 1140
1142 if (pi == 2) { 1141 if (pi == 2) {
1143 if ((slot_num = ((slot_avail2 & SLOT_133MHZ_PCIX_533) >> 27) ) != 0 ) 1142 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
1144 bus_speed = PCIX_133MHZ_533; 1143 bus_speed = PCIX_133MHZ_533;
1145 else if ((slot_num = ((slot_avail2 & SLOT_100MHZ_PCIX_533) >> 23) ) != 0 ) 1144 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
1146 bus_speed = PCIX_100MHZ_533; 1145 bus_speed = PCIX_100MHZ_533;
1147 else if ((slot_num = ((slot_avail2 & SLOT_66MHZ_PCIX_533) >> 19) ) != 0 ) 1146 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
1148 bus_speed = PCIX_66MHZ_533; 1147 bus_speed = PCIX_66MHZ_533;
1149 else if ((slot_num = ((slot_avail2 & SLOT_133MHZ_PCIX_266) >> 15) ) != 0 ) 1148 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
1150 bus_speed = PCIX_133MHZ_266; 1149 bus_speed = PCIX_133MHZ_266;
1151 else if ((slot_num = ((slot_avail2 & SLOT_100MHZ_PCIX_266) >> 11) ) != 0 ) 1150 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
1152 bus_speed = PCIX_100MHZ_266; 1151 bus_speed = PCIX_100MHZ_266;
1153 else if ((slot_num = ((slot_avail2 & SLOT_66MHZ_PCIX_266) >> 7) ) != 0 ) 1152 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
1154 bus_speed = PCIX_66MHZ_266; 1153 bus_speed = PCIX_66MHZ_266;
1155 else if ((slot_num = ((slot_avail1 & SLOT_133MHZ_PCIX) >> 23) ) != 0 ) 1154 else if (slot_avail1 & SLOT_133MHZ_PCIX)
1156 bus_speed = PCIX_133MHZ; 1155 bus_speed = PCIX_133MHZ;
1157 else if ((slot_num = ((slot_avail1 & SLOT_100MHZ_PCIX) >> 15) ) != 0 ) 1156 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1158 bus_speed = PCIX_100MHZ; 1157 bus_speed = PCIX_100MHZ;
1159 else if ((slot_num = ((slot_avail1 & SLOT_66MHZ_PCIX) >> 7) ) != 0 ) 1158 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1160 bus_speed = PCIX_66MHZ; 1159 bus_speed = PCIX_66MHZ;
1161 else if ((slot_num = (slot_avail2 & SLOT_66MHZ)) != 0 ) 1160 else if (slot_avail2 & SLOT_66MHZ)
1162 bus_speed = PCI_66MHZ; 1161 bus_speed = PCI_66MHZ;
1163 else if ((slot_num = (slot_avail1 & SLOT_33MHZ)) != 0 ) 1162 else if (slot_avail1 & SLOT_33MHZ)
1164 bus_speed = PCI_33MHZ; 1163 bus_speed = PCI_33MHZ;
1165 else bus_speed = PCI_SPEED_UNKNOWN; 1164 else bus_speed = PCI_SPEED_UNKNOWN;
1166 } else { 1165 } else {
1167 if ((slot_num = ((slot_avail1 & SLOT_133MHZ_PCIX) >> 23) ) != 0 ) 1166 if (slot_avail1 & SLOT_133MHZ_PCIX)
1168 bus_speed = PCIX_133MHZ; 1167 bus_speed = PCIX_133MHZ;
1169 else if ((slot_num = ((slot_avail1 & SLOT_100MHZ_PCIX) >> 15) ) != 0 ) 1168 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1170 bus_speed = PCIX_100MHZ; 1169 bus_speed = PCIX_100MHZ;
1171 else if ((slot_num = ((slot_avail1 & SLOT_66MHZ_PCIX) >> 7) ) != 0 ) 1170 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1172 bus_speed = PCIX_66MHZ; 1171 bus_speed = PCIX_66MHZ;
1173 else if ((slot_num = (slot_avail2 & SLOT_66MHZ)) != 0 ) 1172 else if (slot_avail2 & SLOT_66MHZ)
1174 bus_speed = PCI_66MHZ; 1173 bus_speed = PCI_66MHZ;
1175 else if ((slot_num = (slot_avail1 & SLOT_33MHZ)) != 0 ) 1174 else if (slot_avail1 & SLOT_33MHZ)
1176 bus_speed = PCI_33MHZ; 1175 bus_speed = PCI_33MHZ;
1177 else bus_speed = PCI_SPEED_UNKNOWN; 1176 else bus_speed = PCI_SPEED_UNKNOWN;
1178 } 1177 }