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authorLen Brown <len.brown@intel.com>2005-09-03 02:44:09 -0400
committerLen Brown <len.brown@intel.com>2005-09-03 02:44:09 -0400
commit129521dcc94f781890f8f668219ab79f0073ff9f (patch)
tree9f70707c88da65577f38814fe37b24c4b4957d64 /drivers/pci
parent824b558bbe2c298b165cdb54c33718994dda30bb (diff)
parentf505380ba7b98ec97bf25300c2a58aeae903530b (diff)
Merge linux-2.6 into linux-acpi-2.6 test
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/rom.c24
-rw-r--r--drivers/pci/setup-bus.c2
2 files changed, 18 insertions, 8 deletions
diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c
index 713c78f3a65..49bd2170231 100644
--- a/drivers/pci/rom.c
+++ b/drivers/pci/rom.c
@@ -21,13 +21,21 @@
21 * between the ROM and other resources, so enabling it may disable access 21 * between the ROM and other resources, so enabling it may disable access
22 * to MMIO registers or other card memory. 22 * to MMIO registers or other card memory.
23 */ 23 */
24static void pci_enable_rom(struct pci_dev *pdev) 24static int pci_enable_rom(struct pci_dev *pdev)
25{ 25{
26 struct resource *res = pdev->resource + PCI_ROM_RESOURCE;
27 struct pci_bus_region region;
26 u32 rom_addr; 28 u32 rom_addr;
27 29
30 if (!res->flags)
31 return -1;
32
33 pcibios_resource_to_bus(pdev, &region, res);
28 pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); 34 pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
29 rom_addr |= PCI_ROM_ADDRESS_ENABLE; 35 rom_addr &= ~PCI_ROM_ADDRESS_MASK;
36 rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;
30 pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); 37 pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
38 return 0;
31} 39}
32 40
33/** 41/**
@@ -71,19 +79,21 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
71 } else { 79 } else {
72 if (res->flags & IORESOURCE_ROM_COPY) { 80 if (res->flags & IORESOURCE_ROM_COPY) {
73 *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); 81 *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
74 return (void __iomem *)pci_resource_start(pdev, PCI_ROM_RESOURCE); 82 return (void __iomem *)pci_resource_start(pdev,
83 PCI_ROM_RESOURCE);
75 } else { 84 } else {
76 /* assign the ROM an address if it doesn't have one */ 85 /* assign the ROM an address if it doesn't have one */
77 if (res->parent == NULL) 86 if (res->parent == NULL &&
78 pci_assign_resource(pdev, PCI_ROM_RESOURCE); 87 pci_assign_resource(pdev,PCI_ROM_RESOURCE))
79 88 return NULL;
80 start = pci_resource_start(pdev, PCI_ROM_RESOURCE); 89 start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
81 *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); 90 *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
82 if (*size == 0) 91 if (*size == 0)
83 return NULL; 92 return NULL;
84 93
85 /* Enable ROM space decodes */ 94 /* Enable ROM space decodes */
86 pci_enable_rom(pdev); 95 if (pci_enable_rom(pdev))
96 return NULL;
87 } 97 }
88 } 98 }
89 99
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 6d864c502a1..6b0e6464eb3 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -40,7 +40,7 @@
40 * FIXME: IO should be max 256 bytes. However, since we may 40 * FIXME: IO should be max 256 bytes. However, since we may
41 * have a P2P bridge below a cardbus bridge, we need 4K. 41 * have a P2P bridge below a cardbus bridge, we need 4K.
42 */ 42 */
43#define CARDBUS_IO_SIZE (256) 43#define CARDBUS_IO_SIZE (4*1024)
44#define CARDBUS_MEM_SIZE (32*1024*1024) 44#define CARDBUS_MEM_SIZE (32*1024*1024)
45 45
46static void __devinit 46static void __devinit