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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /drivers/pci/quirks.c
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c749
1 files changed, 217 insertions, 532 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 0369fb6fc1d..37d35c938b5 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -17,7 +17,6 @@
17 17
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/export.h>
21#include <linux/pci.h> 20#include <linux/pci.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/delay.h> 22#include <linux/delay.h>
@@ -26,29 +25,90 @@
26#include <linux/dmi.h> 25#include <linux/dmi.h>
27#include <linux/pci-aspm.h> 26#include <linux/pci-aspm.h>
28#include <linux/ioport.h> 27#include <linux/ioport.h>
29#include <linux/sched.h>
30#include <linux/ktime.h>
31#include <asm/dma.h> /* isa_dma_bridge_buggy */ 28#include <asm/dma.h> /* isa_dma_bridge_buggy */
32#include "pci.h" 29#include "pci.h"
33 30
34/* 31/*
32 * This quirk function disables memory decoding and releases memory resources
33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
34 * It also rounds up size to specified alignment.
35 * Later on, the kernel will assign page-aligned memory resource back
36 * to the device.
37 */
38static void __devinit quirk_resource_alignment(struct pci_dev *dev)
39{
40 int i;
41 struct resource *r;
42 resource_size_t align, size;
43 u16 command;
44
45 if (!pci_is_reassigndev(dev))
46 return;
47
48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
50 dev_warn(&dev->dev,
51 "Can't reassign resources to host bridge.\n");
52 return;
53 }
54
55 dev_info(&dev->dev,
56 "Disabling memory decoding and releasing memory resources.\n");
57 pci_read_config_word(dev, PCI_COMMAND, &command);
58 command &= ~PCI_COMMAND_MEMORY;
59 pci_write_config_word(dev, PCI_COMMAND, command);
60
61 align = pci_specified_resource_alignment(dev);
62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
63 r = &dev->resource[i];
64 if (!(r->flags & IORESOURCE_MEM))
65 continue;
66 size = resource_size(r);
67 if (size < align) {
68 size = align;
69 dev_info(&dev->dev,
70 "Rounding up size of resource #%d to %#llx.\n",
71 i, (unsigned long long)size);
72 }
73 r->end = size - 1;
74 r->start = 0;
75 }
76 /* Need to disable bridge's resource window,
77 * to enable the kernel to reassign new resource
78 * window later on.
79 */
80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
83 r = &dev->resource[i];
84 if (!(r->flags & IORESOURCE_MEM))
85 continue;
86 r->end = resource_size(r) - 1;
87 r->start = 0;
88 }
89 pci_disable_bridge_window(dev);
90 }
91}
92DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
93
94/*
35 * Decoding should be disabled for a PCI device during BAR sizing to avoid 95 * Decoding should be disabled for a PCI device during BAR sizing to avoid
36 * conflict. But doing so may cause problems on host bridge and perhaps other 96 * conflict. But doing so may cause problems on host bridge and perhaps other
37 * key system devices. For devices that need to have mmio decoding always-on, 97 * key system devices. For devices that need to have mmio decoding always-on,
38 * we need to set the dev->mmio_always_on bit. 98 * we need to set the dev->mmio_always_on bit.
39 */ 99 */
40static void quirk_mmio_always_on(struct pci_dev *dev) 100static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
41{ 101{
42 dev->mmio_always_on = 1; 102 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
103 dev->mmio_always_on = 1;
43} 104}
44DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 105DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on);
45 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
46 106
47/* The Mellanox Tavor device gives false positive parity errors 107/* The Mellanox Tavor device gives false positive parity errors
48 * Mark this device with a broken_parity_status, to allow 108 * Mark this device with a broken_parity_status, to allow
49 * PCI scanning code to "skip" this now blacklisted device. 109 * PCI scanning code to "skip" this now blacklisted device.
50 */ 110 */
51static void quirk_mellanox_tavor(struct pci_dev *dev) 111static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
52{ 112{
53 dev->broken_parity_status = 1; /* This device gives false positives */ 113 dev->broken_parity_status = 1; /* This device gives false positives */
54} 114}
@@ -83,7 +143,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_p
83 This appears to be BIOS not version dependent. So presumably there is a 143 This appears to be BIOS not version dependent. So presumably there is a
84 chipset level fix */ 144 chipset level fix */
85 145
86static void quirk_isa_dma_hangs(struct pci_dev *dev) 146static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
87{ 147{
88 if (!isa_dma_bridge_buggy) { 148 if (!isa_dma_bridge_buggy) {
89 isa_dma_bridge_buggy=1; 149 isa_dma_bridge_buggy=1;
@@ -106,7 +166,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_d
106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear 166 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
107 * for some HT machines to use C4 w/o hanging. 167 * for some HT machines to use C4 w/o hanging.
108 */ 168 */
109static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 169static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
110{ 170{
111 u32 pmbase; 171 u32 pmbase;
112 u16 pm1a; 172 u16 pm1a;
@@ -125,7 +185,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk
125/* 185/*
126 * Chipsets where PCI->PCI transfers vanish or hang 186 * Chipsets where PCI->PCI transfers vanish or hang
127 */ 187 */
128static void quirk_nopcipci(struct pci_dev *dev) 188static void __devinit quirk_nopcipci(struct pci_dev *dev)
129{ 189{
130 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 190 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
131 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); 191 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
@@ -135,7 +195,7 @@ static void quirk_nopcipci(struct pci_dev *dev)
135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
137 197
138static void quirk_nopciamd(struct pci_dev *dev) 198static void __devinit quirk_nopciamd(struct pci_dev *dev)
139{ 199{
140 u8 rev; 200 u8 rev;
141 pci_read_config_byte(dev, 0x08, &rev); 201 pci_read_config_byte(dev, 0x08, &rev);
@@ -150,7 +210,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopci
150/* 210/*
151 * Triton requires workarounds to be used by the drivers 211 * Triton requires workarounds to be used by the drivers
152 */ 212 */
153static void quirk_triton(struct pci_dev *dev) 213static void __devinit quirk_triton(struct pci_dev *dev)
154{ 214{
155 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 215 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
156 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 216 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
@@ -229,7 +289,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_viala
229/* 289/*
230 * VIA Apollo VP3 needs ETBF on BT848/878 290 * VIA Apollo VP3 needs ETBF on BT848/878
231 */ 291 */
232static void quirk_viaetbf(struct pci_dev *dev) 292static void __devinit quirk_viaetbf(struct pci_dev *dev)
233{ 293{
234 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 294 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
235 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 295 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
@@ -238,7 +298,7 @@ static void quirk_viaetbf(struct pci_dev *dev)
238} 298}
239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
240 300
241static void quirk_vsfx(struct pci_dev *dev) 301static void __devinit quirk_vsfx(struct pci_dev *dev)
242{ 302{
243 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 303 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
244 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 304 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
@@ -253,7 +313,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx)
253 * workaround applied too 313 * workaround applied too
254 * [Info kindly provided by ALi] 314 * [Info kindly provided by ALi]
255 */ 315 */
256static void quirk_alimagik(struct pci_dev *dev) 316static void __init quirk_alimagik(struct pci_dev *dev)
257{ 317{
258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 318 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 319 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
@@ -267,7 +327,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimag
267 * Natoma has some interesting boundary conditions with Zoran stuff 327 * Natoma has some interesting boundary conditions with Zoran stuff
268 * at least 328 * at least
269 */ 329 */
270static void quirk_natoma(struct pci_dev *dev) 330static void __devinit quirk_natoma(struct pci_dev *dev)
271{ 331{
272 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 332 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
273 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 333 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
@@ -285,7 +345,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, qu
285 * This chip can cause PCI parity errors if config register 0xA0 is read 345 * This chip can cause PCI parity errors if config register 0xA0 is read
286 * while DMAs are occurring. 346 * while DMAs are occurring.
287 */ 347 */
288static void quirk_citrine(struct pci_dev *dev) 348static void __devinit quirk_citrine(struct pci_dev *dev)
289{ 349{
290 dev->cfg_size = 0xA0; 350 dev->cfg_size = 0xA0;
291} 351}
@@ -295,7 +355,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_cit
295 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 355 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
296 * If it's needed, re-allocate the region. 356 * If it's needed, re-allocate the region.
297 */ 357 */
298static void quirk_s3_64M(struct pci_dev *dev) 358static void __devinit quirk_s3_64M(struct pci_dev *dev)
299{ 359{
300 struct resource *r = &dev->resource[0]; 360 struct resource *r = &dev->resource[0];
301 361
@@ -313,7 +373,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
313 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 373 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
314 * (which conflicts w/ BAR1's memory range). 374 * (which conflicts w/ BAR1's memory range).
315 */ 375 */
316static void quirk_cs5536_vsa(struct pci_dev *dev) 376static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
317{ 377{
318 if (pci_resource_len(dev, 0) != 8) { 378 if (pci_resource_len(dev, 0) != 8) {
319 struct resource *res = &dev->resource[0]; 379 struct resource *res = &dev->resource[0];
@@ -324,7 +384,7 @@ static void quirk_cs5536_vsa(struct pci_dev *dev)
324} 384}
325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
326 386
327static void quirk_io_region(struct pci_dev *dev, unsigned region, 387static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
328 unsigned size, int nr, const char *name) 388 unsigned size, int nr, const char *name)
329{ 389{
330 region &= ~(size-1); 390 region &= ~(size-1);
@@ -352,7 +412,7 @@ static void quirk_io_region(struct pci_dev *dev, unsigned region,
352 * ATI Northbridge setups MCE the processor if you even 412 * ATI Northbridge setups MCE the processor if you even
353 * read somewhere between 0x3b0->0x3bb or read 0x3d3 413 * read somewhere between 0x3b0->0x3bb or read 0x3d3
354 */ 414 */
355static void quirk_ati_exploding_mce(struct pci_dev *dev) 415static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
356{ 416{
357 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 417 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
358 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 418 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
@@ -372,7 +432,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_
372 * 0xE0 (64 bytes of ACPI registers) 432 * 0xE0 (64 bytes of ACPI registers)
373 * 0xE2 (32 bytes of SMB registers) 433 * 0xE2 (32 bytes of SMB registers)
374 */ 434 */
375static void quirk_ali7101_acpi(struct pci_dev *dev) 435static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
376{ 436{
377 u16 region; 437 u16 region;
378 438
@@ -440,7 +500,7 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int
440 * 0x90 (16 bytes of SMB registers) 500 * 0x90 (16 bytes of SMB registers)
441 * and a few strange programmable PIIX4 device resources. 501 * and a few strange programmable PIIX4 device resources.
442 */ 502 */
443static void quirk_piix4_acpi(struct pci_dev *dev) 503static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
444{ 504{
445 u32 region, res_a; 505 u32 region, res_a;
446 506
@@ -489,7 +549,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, qui
489 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 549 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
490 * 0x58 (64 bytes of GPIO I/O space) 550 * 0x58 (64 bytes of GPIO I/O space)
491 */ 551 */
492static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 552static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
493{ 553{
494 u32 region; 554 u32 region;
495 u8 enable; 555 u8 enable;
@@ -531,7 +591,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
531DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
532DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
533 593
534static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 594static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
535{ 595{
536 u32 region; 596 u32 region;
537 u8 enable; 597 u8 enable;
@@ -555,7 +615,7 @@ static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
555 } 615 }
556} 616}
557 617
558static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 618static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
559{ 619{
560 u32 val; 620 u32 val;
561 u32 size, base; 621 u32 size, base;
@@ -583,7 +643,7 @@ static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
583 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 643 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
584} 644}
585 645
586static void quirk_ich6_lpc(struct pci_dev *dev) 646static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
587{ 647{
588 /* Shared ACPI/GPIO decode with all ICH6+ */ 648 /* Shared ACPI/GPIO decode with all ICH6+ */
589 ich6_lpc_acpi_gpio(dev); 649 ich6_lpc_acpi_gpio(dev);
@@ -595,7 +655,7 @@ static void quirk_ich6_lpc(struct pci_dev *dev)
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 655DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
597 657
598static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 658static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
599{ 659{
600 u32 val; 660 u32 val;
601 u32 mask, base; 661 u32 mask, base;
@@ -619,7 +679,7 @@ static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
619} 679}
620 680
621/* ICH7-10 has the same common LPC generic IO decode registers */ 681/* ICH7-10 has the same common LPC generic IO decode registers */
622static void quirk_ich7_lpc(struct pci_dev *dev) 682static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
623{ 683{
624 /* We share the common ACPI/GPIO decode with ICH6 */ 684 /* We share the common ACPI/GPIO decode with ICH6 */
625 ich6_lpc_acpi_gpio(dev); 685 ich6_lpc_acpi_gpio(dev);
@@ -648,7 +708,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, qui
648 * VIA ACPI: One IO region pointed to by longword at 708 * VIA ACPI: One IO region pointed to by longword at
649 * 0x48 or 0x20 (256 bytes of ACPI registers) 709 * 0x48 or 0x20 (256 bytes of ACPI registers)
650 */ 710 */
651static void quirk_vt82c586_acpi(struct pci_dev *dev) 711static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
652{ 712{
653 u32 region; 713 u32 region;
654 714
@@ -666,7 +726,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt
666 * 0x70 (128 bytes of hardware monitoring register) 726 * 0x70 (128 bytes of hardware monitoring register)
667 * 0x90 (16 bytes of SMB registers) 727 * 0x90 (16 bytes of SMB registers)
668 */ 728 */
669static void quirk_vt82c686_acpi(struct pci_dev *dev) 729static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
670{ 730{
671 u16 hm; 731 u16 hm;
672 u32 smb; 732 u32 smb;
@@ -688,7 +748,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt
688 * 0x88 (128 bytes of power management registers) 748 * 0x88 (128 bytes of power management registers)
689 * 0xd0 (16 bytes of SMB registers) 749 * 0xd0 (16 bytes of SMB registers)
690 */ 750 */
691static void quirk_vt8235_acpi(struct pci_dev *dev) 751static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
692{ 752{
693 u16 pm, smb; 753 u16 pm, smb;
694 754
@@ -706,7 +766,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235
706 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 766 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
707 * Disable fast back-to-back on the secondary bus segment 767 * Disable fast back-to-back on the secondary bus segment
708 */ 768 */
709static void quirk_xio2000a(struct pci_dev *dev) 769static void __devinit quirk_xio2000a(struct pci_dev *dev)
710{ 770{
711 struct pci_dev *pdev; 771 struct pci_dev *pdev;
712 u16 command; 772 u16 command;
@@ -780,7 +840,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk
780 * noapic specified. For the moment we assume it's the erratum. We may be wrong 840 * noapic specified. For the moment we assume it's the erratum. We may be wrong
781 * of course. However the advice is demonstrably good even if so.. 841 * of course. However the advice is demonstrably good even if so..
782 */ 842 */
783static void quirk_amd_ioapic(struct pci_dev *dev) 843static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
784{ 844{
785 if (dev->revision >= 0x02) { 845 if (dev->revision >= 0x02) {
786 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 846 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
@@ -789,7 +849,7 @@ static void quirk_amd_ioapic(struct pci_dev *dev)
789} 849}
790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 850DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
791 851
792static void quirk_ioapic_rmw(struct pci_dev *dev) 852static void __init quirk_ioapic_rmw(struct pci_dev *dev)
793{ 853{
794 if (dev->devfn == 0 && dev->bus->number == 0) 854 if (dev->devfn == 0 && dev->bus->number == 0)
795 sis_apic_bug = 1; 855 sis_apic_bug = 1;
@@ -801,7 +861,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
801 * Some settings of MMRBC can lead to data corruption so block changes. 861 * Some settings of MMRBC can lead to data corruption so block changes.
802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 862 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
803 */ 863 */
804static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 864static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
805{ 865{
806 if (dev->subordinate && dev->revision <= 0x12) { 866 if (dev->subordinate && dev->revision <= 0x12) {
807 dev_info(&dev->dev, "AMD8131 rev %x detected; " 867 dev_info(&dev->dev, "AMD8131 rev %x detected; "
@@ -819,7 +879,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_
819 * value of the ACPI SCI interrupt is only done for convenience. 879 * value of the ACPI SCI interrupt is only done for convenience.
820 * -jgarzik 880 * -jgarzik
821 */ 881 */
822static void quirk_via_acpi(struct pci_dev *d) 882static void __devinit quirk_via_acpi(struct pci_dev *d)
823{ 883{
824 /* 884 /*
825 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 885 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
@@ -926,7 +986,7 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
926 * We need to switch it off to be able to recognize the real 986 * We need to switch it off to be able to recognize the real
927 * type of the chip. 987 * type of the chip.
928 */ 988 */
929static void quirk_vt82c598_id(struct pci_dev *dev) 989static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
930{ 990{
931 pci_write_config_byte(dev, 0xfc, 0); 991 pci_write_config_byte(dev, 0xfc, 0);
932 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 992 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
@@ -941,12 +1001,12 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt
941 */ 1001 */
942static void quirk_cardbus_legacy(struct pci_dev *dev) 1002static void quirk_cardbus_legacy(struct pci_dev *dev)
943{ 1003{
1004 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
1005 return;
944 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1006 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
945} 1007}
946DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1008DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
947 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1009DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
948DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
949 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
950 1010
951/* 1011/*
952 * Following the PCI ordering rules is optional on the AMD762. I'm not 1012 * Following the PCI ordering rules is optional on the AMD762. I'm not
@@ -978,7 +1038,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C
978 * assigned to it. We force a larger allocation to ensure that 1038 * assigned to it. We force a larger allocation to ensure that
979 * nothing gets put too close to it. 1039 * nothing gets put too close to it.
980 */ 1040 */
981static void quirk_dunord(struct pci_dev *dev) 1041static void __devinit quirk_dunord ( struct pci_dev * dev )
982{ 1042{
983 struct resource *r = &dev->resource [1]; 1043 struct resource *r = &dev->resource [1];
984 r->start = 0; 1044 r->start = 0;
@@ -992,7 +1052,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk
992 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1052 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
993 * instead of 0x01. 1053 * instead of 0x01.
994 */ 1054 */
995static void quirk_transparent_bridge(struct pci_dev *dev) 1055static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
996{ 1056{
997 dev->transparent = 1; 1057 dev->transparent = 1;
998} 1058}
@@ -1039,7 +1099,7 @@ static void quirk_disable_pxb(struct pci_dev *pdev)
1039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1099DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1040DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1100DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1041 1101
1042static void quirk_amd_ide_mode(struct pci_dev *pdev) 1102static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1043{ 1103{
1044 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1104 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1045 u8 tmp; 1105 u8 tmp;
@@ -1066,7 +1126,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA
1066/* 1126/*
1067 * Serverworks CSB5 IDE does not fully support native mode 1127 * Serverworks CSB5 IDE does not fully support native mode
1068 */ 1128 */
1069static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1129static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1070{ 1130{
1071 u8 prog; 1131 u8 prog;
1072 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1132 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
@@ -1082,7 +1142,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB
1082/* 1142/*
1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1143 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1084 */ 1144 */
1085static void quirk_ide_samemode(struct pci_dev *pdev) 1145static void __init quirk_ide_samemode(struct pci_dev *pdev)
1086{ 1146{
1087 u8 prog; 1147 u8 prog;
1088 1148
@@ -1101,27 +1161,24 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, qui
1101 * Some ATA devices break if put into D3 1161 * Some ATA devices break if put into D3
1102 */ 1162 */
1103 1163
1104static void quirk_no_ata_d3(struct pci_dev *pdev) 1164static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1105{ 1165{
1106 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1166 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1167 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1168 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1107} 1169}
1108/* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1170DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1109DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1171DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1110 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1111DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1112 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1113/* ALi loses some register settings that we cannot then restore */ 1172/* ALi loses some register settings that we cannot then restore */
1114DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1173DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1115 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1116/* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1174/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1117 occur when mode detecting */ 1175 occur when mode detecting */
1118DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1176DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
1119 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1120 1177
1121/* This was originally an Alpha specific thing, but it really fits here. 1178/* This was originally an Alpha specific thing, but it really fits here.
1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1179 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1123 */ 1180 */
1124static void quirk_eisa_bridge(struct pci_dev *dev) 1181static void __init quirk_eisa_bridge(struct pci_dev *dev)
1125{ 1182{
1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1183 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1127} 1184}
@@ -1155,7 +1212,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_e
1155 */ 1212 */
1156static int asus_hides_smbus; 1213static int asus_hides_smbus;
1157 1214
1158static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1215static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1159{ 1216{
1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1217 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1218 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
@@ -1538,7 +1595,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB3
1538#endif 1595#endif
1539 1596
1540#ifdef CONFIG_X86_IO_APIC 1597#ifdef CONFIG_X86_IO_APIC
1541static void quirk_alder_ioapic(struct pci_dev *pdev) 1598static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1542{ 1599{
1543 int i; 1600 int i;
1544 1601
@@ -1561,7 +1618,7 @@ static void quirk_alder_ioapic(struct pci_dev *pdev)
1561DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1618DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1562#endif 1619#endif
1563 1620
1564static void quirk_pcie_mch(struct pci_dev *pdev) 1621static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1565{ 1622{
1566 pci_msi_off(pdev); 1623 pci_msi_off(pdev);
1567 pdev->no_msi = 1; 1624 pdev->no_msi = 1;
@@ -1575,7 +1632,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quir
1575 * It's possible for the MSI to get corrupted if shpc and acpi 1632 * It's possible for the MSI to get corrupted if shpc and acpi
1576 * are used together on certain PXH-based systems. 1633 * are used together on certain PXH-based systems.
1577 */ 1634 */
1578static void quirk_pcie_pxh(struct pci_dev *dev) 1635static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1579{ 1636{
1580 pci_msi_off(dev); 1637 pci_msi_off(dev);
1581 dev->no_msi = 1; 1638 dev->no_msi = 1;
@@ -1777,7 +1834,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, qui
1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1834 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1778 * Re-allocate the region if needed... 1835 * Re-allocate the region if needed...
1779 */ 1836 */
1780static void quirk_tc86c001_ide(struct pci_dev *dev) 1837static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1781{ 1838{
1782 struct resource *r = &dev->resource[0]; 1839 struct resource *r = &dev->resource[0];
1783 1840
@@ -1790,46 +1847,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1790 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 1847 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1791 quirk_tc86c001_ide); 1848 quirk_tc86c001_ide);
1792 1849
1793/* 1850static void __devinit quirk_netmos(struct pci_dev *dev)
1794 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1795 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1796 * being read correctly if bit 7 of the base address is set.
1797 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1798 * Re-allocate the regions to a 256-byte boundary if necessary.
1799 */
1800static void quirk_plx_pci9050(struct pci_dev *dev)
1801{
1802 unsigned int bar;
1803
1804 /* Fixed in revision 2 (PCI 9052). */
1805 if (dev->revision >= 2)
1806 return;
1807 for (bar = 0; bar <= 1; bar++)
1808 if (pci_resource_len(dev, bar) == 0x80 &&
1809 (pci_resource_start(dev, bar) & 0x80)) {
1810 struct resource *r = &dev->resource[bar];
1811 dev_info(&dev->dev,
1812 "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1813 bar);
1814 r->start = 0;
1815 r->end = 0xff;
1816 }
1817}
1818DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1819 quirk_plx_pci9050);
1820/*
1821 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1822 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1823 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1824 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1825 *
1826 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1827 * driver.
1828 */
1829DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1830DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1831
1832static void quirk_netmos(struct pci_dev *dev)
1833{ 1851{
1834 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 1852 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1835 unsigned int num_serial = dev->subsystem_device & 0xf; 1853 unsigned int num_serial = dev->subsystem_device & 0xf;
@@ -1854,7 +1872,8 @@ static void quirk_netmos(struct pci_dev *dev)
1854 case PCI_DEVICE_ID_NETMOS_9745: 1872 case PCI_DEVICE_ID_NETMOS_9745:
1855 case PCI_DEVICE_ID_NETMOS_9845: 1873 case PCI_DEVICE_ID_NETMOS_9845:
1856 case PCI_DEVICE_ID_NETMOS_9855: 1874 case PCI_DEVICE_ID_NETMOS_9855:
1857 if (num_parallel) { 1875 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1876 num_parallel) {
1858 dev_info(&dev->dev, "Netmos %04x (%u parallel, " 1877 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1859 "%u serial); changing class SERIAL to OTHER " 1878 "%u serial); changing class SERIAL to OTHER "
1860 "(use parport_serial)\n", 1879 "(use parport_serial)\n",
@@ -1864,10 +1883,9 @@ static void quirk_netmos(struct pci_dev *dev)
1864 } 1883 }
1865 } 1884 }
1866} 1885}
1867DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 1886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1868 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1869 1887
1870static void quirk_e100_interrupt(struct pci_dev *dev) 1888static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1871{ 1889{
1872 u16 command, pmcsr; 1890 u16 command, pmcsr;
1873 u8 __iomem *csr; 1891 u8 __iomem *csr;
@@ -1933,14 +1951,13 @@ static void quirk_e100_interrupt(struct pci_dev *dev)
1933 1951
1934 iounmap(csr); 1952 iounmap(csr);
1935} 1953}
1936DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1954DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1937 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1938 1955
1939/* 1956/*
1940 * The 82575 and 82598 may experience data corruption issues when transitioning 1957 * The 82575 and 82598 may experience data corruption issues when transitioning
1941 * out of L0S. To prevent this we need to disable L0S on the pci-e link 1958 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1942 */ 1959 */
1943static void quirk_disable_aspm_l0s(struct pci_dev *dev) 1960static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1944{ 1961{
1945 dev_info(&dev->dev, "Disabling L0s\n"); 1962 dev_info(&dev->dev, "Disabling L0s\n");
1946 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 1963 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
@@ -1960,7 +1977,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1960DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 1977DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1961DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 1978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1962 1979
1963static void fixup_rev1_53c810(struct pci_dev *dev) 1980static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1964{ 1981{
1965 /* rev 1 ncr53c810 chips don't set the class at all which means 1982 /* rev 1 ncr53c810 chips don't set the class at all which means
1966 * they don't get their resources remapped. Fix that here. 1983 * they don't get their resources remapped. Fix that here.
@@ -1974,19 +1991,56 @@ static void fixup_rev1_53c810(struct pci_dev *dev)
1974DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 1991DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1975 1992
1976/* Enable 1k I/O space granularity on the Intel P64H2 */ 1993/* Enable 1k I/O space granularity on the Intel P64H2 */
1977static void quirk_p64h2_1k_io(struct pci_dev *dev) 1994static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1978{ 1995{
1979 u16 en1k; 1996 u16 en1k;
1997 u8 io_base_lo, io_limit_lo;
1998 unsigned long base, limit;
1999 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1980 2000
1981 pci_read_config_word(dev, 0x40, &en1k); 2001 pci_read_config_word(dev, 0x40, &en1k);
1982 2002
1983 if (en1k & 0x200) { 2003 if (en1k & 0x200) {
1984 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); 2004 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1985 dev->io_window_1k = 1; 2005
2006 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
2007 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
2008 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2009 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2010
2011 if (base <= limit) {
2012 res->start = base;
2013 res->end = limit + 0x3ff;
2014 }
1986 } 2015 }
1987} 2016}
1988DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2017DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1989 2018
2019/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
2020 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
2021 * in drivers/pci/setup-bus.c
2022 */
2023static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
2024{
2025 u16 en1k, iobl_adr, iobl_adr_1k;
2026 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2027
2028 pci_read_config_word(dev, 0x40, &en1k);
2029
2030 if (en1k & 0x200) {
2031 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
2032
2033 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
2034
2035 if (iobl_adr != iobl_adr_1k) {
2036 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
2037 iobl_adr,iobl_adr_1k);
2038 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
2039 }
2040 }
2041}
2042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
2043
1990/* Under some circumstances, AER is not linked with extended capabilities. 2044/* Under some circumstances, AER is not linked with extended capabilities.
1991 * Force it to be linked by setting the corresponding control bit in the 2045 * Force it to be linked by setting the corresponding control bit in the
1992 * config space. 2046 * config space.
@@ -2007,7 +2061,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2007DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2061DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2008 quirk_nvidia_ck804_pcie_aer_ext_cap); 2062 quirk_nvidia_ck804_pcie_aer_ext_cap);
2009 2063
2010static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2064static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2011{ 2065{
2012 /* 2066 /*
2013 * Disable PCI Bus Parking and PCI Master read caching on CX700 2067 * Disable PCI Bus Parking and PCI Master read caching on CX700
@@ -2070,7 +2124,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_c
2070 * We believe that it is legal to read beyond the end tag and 2124 * We believe that it is legal to read beyond the end tag and
2071 * therefore the solution is to limit the read/write length. 2125 * therefore the solution is to limit the read/write length.
2072 */ 2126 */
2073static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) 2127static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2074{ 2128{
2075 /* 2129 /*
2076 * Only disable the VPD capability for 5706, 5706S, 5708, 2130 * Only disable the VPD capability for 5706, 5706S, 5708,
@@ -2106,31 +2160,13 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2106 PCI_DEVICE_ID_NX2_5709S, 2160 PCI_DEVICE_ID_NX2_5709S,
2107 quirk_brcm_570x_limit_vpd); 2161 quirk_brcm_570x_limit_vpd);
2108 2162
2109static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2110{
2111 u32 rev;
2112
2113 pci_read_config_dword(dev, 0xf4, &rev);
2114
2115 /* Only CAP the MRRS if the device is a 5719 A0 */
2116 if (rev == 0x05719000) {
2117 int readrq = pcie_get_readrq(dev);
2118 if (readrq > 2048)
2119 pcie_set_readrq(dev, 2048);
2120 }
2121}
2122
2123DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2124 PCI_DEVICE_ID_TIGON3_5719,
2125 quirk_brcm_5719_limit_mrrs);
2126
2127/* Originally in EDAC sources for i82875P: 2163/* Originally in EDAC sources for i82875P:
2128 * Intel tells BIOS developers to hide device 6 which 2164 * Intel tells BIOS developers to hide device 6 which
2129 * configures the overflow device access containing 2165 * configures the overflow device access containing
2130 * the DRBs - this is where we expose device 6. 2166 * the DRBs - this is where we expose device 6.
2131 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2167 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2132 */ 2168 */
2133static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2169static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2134{ 2170{
2135 u8 reg; 2171 u8 reg;
2136 2172
@@ -2145,16 +2181,16 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2145DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2181DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2146 quirk_unhide_mch_dev6); 2182 quirk_unhide_mch_dev6);
2147 2183
2148#ifdef CONFIG_TILEPRO 2184#ifdef CONFIG_TILE
2149/* 2185/*
2150 * The Tilera TILEmpower tilepro platform needs to set the link speed 2186 * The Tilera TILEmpower platform needs to set the link speed
2151 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2187 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2152 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2188 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2153 * capability register of the PEX8624 PCIe switch. The switch 2189 * capability register of the PEX8624 PCIe switch. The switch
2154 * supports link speed auto negotiation, but falsely sets 2190 * supports link speed auto negotiation, but falsely sets
2155 * the link speed to 5GT/s. 2191 * the link speed to 5GT/s.
2156 */ 2192 */
2157static void quirk_tile_plx_gen1(struct pci_dev *dev) 2193static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2158{ 2194{
2159 if (tile_plx_gen1) { 2195 if (tile_plx_gen1) {
2160 pci_write_config_dword(dev, 0x98, 0x1); 2196 pci_write_config_dword(dev, 0x98, 0x1);
@@ -2162,7 +2198,7 @@ static void quirk_tile_plx_gen1(struct pci_dev *dev)
2162 } 2198 }
2163} 2199}
2164DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2200DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2165#endif /* CONFIG_TILEPRO */ 2201#endif /* CONFIG_TILE */
2166 2202
2167#ifdef CONFIG_PCI_MSI 2203#ifdef CONFIG_PCI_MSI
2168/* Some chipsets do not support MSI. We cannot easily rely on setting 2204/* Some chipsets do not support MSI. We cannot easily rely on setting
@@ -2171,7 +2207,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2171 * aware of it. Instead of setting the flag on all busses in the 2207 * aware of it. Instead of setting the flag on all busses in the
2172 * machine, simply disable MSI globally. 2208 * machine, simply disable MSI globally.
2173 */ 2209 */
2174static void quirk_disable_all_msi(struct pci_dev *dev) 2210static void __init quirk_disable_all_msi(struct pci_dev *dev)
2175{ 2211{
2176 pci_no_msi(); 2212 pci_no_msi();
2177 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2213 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
@@ -2185,7 +2221,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disab
2185DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2186 2222
2187/* Disable MSI on chipsets that are known to not support it */ 2223/* Disable MSI on chipsets that are known to not support it */
2188static void quirk_disable_msi(struct pci_dev *dev) 2224static void __devinit quirk_disable_msi(struct pci_dev *dev)
2189{ 2225{
2190 if (dev->subordinate) { 2226 if (dev->subordinate) {
2191 dev_warn(&dev->dev, "MSI quirk detected; " 2227 dev_warn(&dev->dev, "MSI quirk detected; "
@@ -2203,7 +2239,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2203 * we use the possible vendor/device IDs of the host bridge for the 2239 * we use the possible vendor/device IDs of the host bridge for the
2204 * declared quirk, and search for the APC bridge by slot number. 2240 * declared quirk, and search for the APC bridge by slot number.
2205 */ 2241 */
2206static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2242static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2207{ 2243{
2208 struct pci_dev *apc_bridge; 2244 struct pci_dev *apc_bridge;
2209 2245
@@ -2219,7 +2255,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2219 2255
2220/* Go through the list of Hypertransport capabilities and 2256/* Go through the list of Hypertransport capabilities and
2221 * return 1 if a HT MSI capability is found and enabled */ 2257 * return 1 if a HT MSI capability is found and enabled */
2222static int msi_ht_cap_enabled(struct pci_dev *dev) 2258static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2223{ 2259{
2224 int pos, ttl = 48; 2260 int pos, ttl = 48;
2225 2261
@@ -2243,7 +2279,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev)
2243} 2279}
2244 2280
2245/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2281/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2246static void quirk_msi_ht_cap(struct pci_dev *dev) 2282static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2247{ 2283{
2248 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2284 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2249 dev_warn(&dev->dev, "MSI quirk detected; " 2285 dev_warn(&dev->dev, "MSI quirk detected; "
@@ -2257,7 +2293,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2
2257/* The nVidia CK804 chipset may have 2 HT MSI mappings. 2293/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2258 * MSI are supported if the MSI capability set in any of these mappings. 2294 * MSI are supported if the MSI capability set in any of these mappings.
2259 */ 2295 */
2260static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2296static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2261{ 2297{
2262 struct pci_dev *pdev; 2298 struct pci_dev *pdev;
2263 2299
@@ -2281,7 +2317,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2281 quirk_nvidia_ck804_msi_ht_cap); 2317 quirk_nvidia_ck804_msi_ht_cap);
2282 2318
2283/* Force enable MSI mapping capability on HT bridges */ 2319/* Force enable MSI mapping capability on HT bridges */
2284static void ht_enable_msi_mapping(struct pci_dev *dev) 2320static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2285{ 2321{
2286 int pos, ttl = 48; 2322 int pos, ttl = 48;
2287 2323
@@ -2311,7 +2347,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2311 * for the MCP55 NIC. It is not yet determined whether the msi problem 2347 * for the MCP55 NIC. It is not yet determined whether the msi problem
2312 * also affects other devices. As for now, turn off msi for this device. 2348 * also affects other devices. As for now, turn off msi for this device.
2313 */ 2349 */
2314static void nvenet_msi_disable(struct pci_dev *dev) 2350static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2315{ 2351{
2316 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2352 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2317 2353
@@ -2337,7 +2373,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2337 * we have it set correctly. 2373 * we have it set correctly.
2338 * Note this is an undocumented register. 2374 * Note this is an undocumented register.
2339 */ 2375 */
2340static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2376static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2341{ 2377{
2342 u32 cfg; 2378 u32 cfg;
2343 2379
@@ -2361,7 +2397,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2361 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2397 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2362 nvbridge_check_legacy_irq_routing); 2398 nvbridge_check_legacy_irq_routing);
2363 2399
2364static int ht_check_msi_mapping(struct pci_dev *dev) 2400static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2365{ 2401{
2366 int pos, ttl = 48; 2402 int pos, ttl = 48;
2367 int found = 0; 2403 int found = 0;
@@ -2389,7 +2425,7 @@ static int ht_check_msi_mapping(struct pci_dev *dev)
2389 return found; 2425 return found;
2390} 2426}
2391 2427
2392static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2428static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2393{ 2429{
2394 struct pci_dev *dev; 2430 struct pci_dev *dev;
2395 int pos; 2431 int pos;
@@ -2423,7 +2459,7 @@ static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2423#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 2459#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2424#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 2460#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2425 2461
2426static int is_end_of_ht_chain(struct pci_dev *dev) 2462static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2427{ 2463{
2428 int pos, ctrl_off; 2464 int pos, ctrl_off;
2429 int end = 0; 2465 int end = 0;
@@ -2447,7 +2483,7 @@ out:
2447 return end; 2483 return end;
2448} 2484}
2449 2485
2450static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 2486static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2451{ 2487{
2452 struct pci_dev *host_bridge; 2488 struct pci_dev *host_bridge;
2453 int pos; 2489 int pos;
@@ -2486,7 +2522,7 @@ out:
2486 pci_dev_put(host_bridge); 2522 pci_dev_put(host_bridge);
2487} 2523}
2488 2524
2489static void ht_disable_msi_mapping(struct pci_dev *dev) 2525static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2490{ 2526{
2491 int pos, ttl = 48; 2527 int pos, ttl = 48;
2492 2528
@@ -2506,7 +2542,7 @@ static void ht_disable_msi_mapping(struct pci_dev *dev)
2506 } 2542 }
2507} 2543}
2508 2544
2509static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 2545static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2510{ 2546{
2511 struct pci_dev *host_bridge; 2547 struct pci_dev *host_bridge;
2512 int pos; 2548 int pos;
@@ -2543,26 +2579,23 @@ static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2543 else 2579 else
2544 nv_ht_enable_msi_mapping(dev); 2580 nv_ht_enable_msi_mapping(dev);
2545 } 2581 }
2546 goto out; 2582 return;
2547 } 2583 }
2548 2584
2549 /* HT MSI is not enabled */ 2585 /* HT MSI is not enabled */
2550 if (found == 1) 2586 if (found == 1)
2551 goto out; 2587 return;
2552 2588
2553 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 2589 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2554 ht_disable_msi_mapping(dev); 2590 ht_disable_msi_mapping(dev);
2555
2556out:
2557 pci_dev_put(host_bridge);
2558} 2591}
2559 2592
2560static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 2593static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2561{ 2594{
2562 return __nv_msi_ht_cap_quirk(dev, 1); 2595 return __nv_msi_ht_cap_quirk(dev, 1);
2563} 2596}
2564 2597
2565static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2598static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2566{ 2599{
2567 return __nv_msi_ht_cap_quirk(dev, 0); 2600 return __nv_msi_ht_cap_quirk(dev, 0);
2568} 2601}
@@ -2573,11 +2606,11 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_q
2573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2574DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 2607DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2575 2608
2576static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2609static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2577{ 2610{
2578 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2611 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2579} 2612}
2580static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2613static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2581{ 2614{
2582 struct pci_dev *p; 2615 struct pci_dev *p;
2583 2616
@@ -2631,18 +2664,6 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 2664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2632 quirk_msi_intx_disable_bug); 2665 quirk_msi_intx_disable_bug);
2633 2666
2634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2635 quirk_msi_intx_disable_bug);
2636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2637 quirk_msi_intx_disable_bug);
2638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2639 quirk_msi_intx_disable_bug);
2640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2641 quirk_msi_intx_disable_bug);
2642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2643 quirk_msi_intx_disable_bug);
2644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2645 quirk_msi_intx_disable_bug);
2646#endif /* CONFIG_PCI_MSI */ 2667#endif /* CONFIG_PCI_MSI */
2647 2668
2648/* Allow manual resource allocation for PCI hotplug bridges 2669/* Allow manual resource allocation for PCI hotplug bridges
@@ -2651,7 +2672,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2651 * kernel fails to allocate resources when hotplug device is 2672 * kernel fails to allocate resources when hotplug device is
2652 * inserted and PCI bus is rescanned. 2673 * inserted and PCI bus is rescanned.
2653 */ 2674 */
2654static void quirk_hotplug_bridge(struct pci_dev *dev) 2675static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2655{ 2676{
2656 dev->is_hotplug_bridge = 1; 2677 dev->is_hotplug_bridge = 1;
2657} 2678}
@@ -2725,7 +2746,7 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2725 if (PCI_FUNC(dev->devfn)) 2746 if (PCI_FUNC(dev->devfn))
2726 return; 2747 return;
2727 /* 2748 /*
2728 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2749 * RICOH 0xe823 SD/MMC card reader fails to recognize
2729 * certain types of SD/MMC cards. Lowering the SD base 2750 * certain types of SD/MMC cards. Lowering the SD base
2730 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2751 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2731 * 2752 *
@@ -2736,8 +2757,7 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2736 * 0xf9 - Key register for 0x150 2757 * 0xf9 - Key register for 0x150
2737 * 0xfc - key register for 0xe1 2758 * 0xfc - key register for 0xe1
2738 */ 2759 */
2739 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 2760 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2740 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2741 pci_write_config_byte(dev, 0xf9, 0xfc); 2761 pci_write_config_byte(dev, 0xf9, 0xfc);
2742 pci_write_config_byte(dev, 0x150, 0x10); 2762 pci_write_config_byte(dev, 0x150, 0x10);
2743 pci_write_config_byte(dev, 0xf9, 0x00); 2763 pci_write_config_byte(dev, 0xf9, 0x00);
@@ -2764,8 +2784,6 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2764} 2784}
2765DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2785DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2766DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 2786DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2767DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2768DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2769DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2787DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2770DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 2788DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2771#endif /*CONFIG_MMC_RICOH_MMC*/ 2789#endif /*CONFIG_MMC_RICOH_MMC*/
@@ -2794,193 +2812,27 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2794DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 2812DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2795#endif 2813#endif
2796 2814
2797static void fixup_ti816x_class(struct pci_dev *dev) 2815static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2798{ 2816{
2799 /* TI 816x devices do not have class code set when in PCIe boot mode */ 2817 /* TI 816x devices do not have class code set when in PCIe boot mode */
2800 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n"); 2818 if (dev->class == PCI_CLASS_NOT_DEFINED) {
2801 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; 2819 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2802} 2820 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2803DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2804 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2805
2806/* Some PCIe devices do not work reliably with the claimed maximum
2807 * payload size supported.
2808 */
2809static void fixup_mpss_256(struct pci_dev *dev)
2810{
2811 dev->pcie_mpss = 1; /* 256 bytes */
2812}
2813DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2814 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2815DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2816 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2817DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2818 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2819
2820/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2821 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2822 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2823 * until all of the devices are discovered and buses walked, read completion
2824 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2825 * it is possible to hotplug a device with MPS of 256B.
2826 */
2827static void quirk_intel_mc_errata(struct pci_dev *dev)
2828{
2829 int err;
2830 u16 rcc;
2831
2832 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2833 return;
2834
2835 /* Intel errata specifies bits to change but does not say what they are.
2836 * Keeping them magical until such time as the registers and values can
2837 * be explained.
2838 */
2839 err = pci_read_config_word(dev, 0x48, &rcc);
2840 if (err) {
2841 dev_err(&dev->dev, "Error attempting to read the read "
2842 "completion coalescing register.\n");
2843 return;
2844 }
2845
2846 if (!(rcc & (1 << 10)))
2847 return;
2848
2849 rcc &= ~(1 << 10);
2850
2851 err = pci_write_config_word(dev, 0x48, rcc);
2852 if (err) {
2853 dev_err(&dev->dev, "Error attempting to write the read "
2854 "completion coalescing register.\n");
2855 return;
2856 }
2857
2858 pr_info_once("Read completion coalescing disabled due to hardware "
2859 "errata relating to 256B MPS.\n");
2860}
2861/* Intel 5000 series memory controllers and ports 2-7 */
2862DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2863DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2866DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2868DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2869DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2874DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2875DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2876/* Intel 5100 series memory controllers and ports 2-7 */
2877DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2878DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2879DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2880DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2881DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2882DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2883DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2884DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2888
2889
2890static ktime_t fixup_debug_start(struct pci_dev *dev,
2891 void (*fn)(struct pci_dev *dev))
2892{
2893 ktime_t calltime = ktime_set(0, 0);
2894
2895 dev_dbg(&dev->dev, "calling %pF\n", fn);
2896 if (initcall_debug) {
2897 pr_debug("calling %pF @ %i for %s\n",
2898 fn, task_pid_nr(current), dev_name(&dev->dev));
2899 calltime = ktime_get();
2900 }
2901
2902 return calltime;
2903}
2904
2905static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2906 void (*fn)(struct pci_dev *dev))
2907{
2908 ktime_t delta, rettime;
2909 unsigned long long duration;
2910
2911 if (initcall_debug) {
2912 rettime = ktime_get();
2913 delta = ktime_sub(rettime, calltime);
2914 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2915 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2916 fn, duration, dev_name(&dev->dev));
2917 }
2918}
2919
2920/*
2921 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2922 * even though no one is handling them (f.e. i915 driver is never loaded).
2923 * Additionally the interrupt destination is not set up properly
2924 * and the interrupt ends up -somewhere-.
2925 *
2926 * These spurious interrupts are "sticky" and the kernel disables
2927 * the (shared) interrupt line after 100.000+ generated interrupts.
2928 *
2929 * Fix it by disabling the still enabled interrupts.
2930 * This resolves crashes often seen on monitor unplug.
2931 */
2932#define I915_DEIER_REG 0x4400c
2933static void disable_igfx_irq(struct pci_dev *dev)
2934{
2935 void __iomem *regs = pci_iomap(dev, 0, 0);
2936 if (regs == NULL) {
2937 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2938 return;
2939 }
2940
2941 /* Check if any interrupt line is still enabled */
2942 if (readl(regs + I915_DEIER_REG) != 0) {
2943 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2944 "disabling\n");
2945
2946 writel(0, regs + I915_DEIER_REG);
2947 } 2821 }
2948
2949 pci_iounmap(dev, regs);
2950}
2951DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2952DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2953
2954/*
2955 * Some devices may pass our check in pci_intx_mask_supported if
2956 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
2957 * support this feature.
2958 */
2959static void quirk_broken_intx_masking(struct pci_dev *dev)
2960{
2961 dev->broken_intx_masking = 1;
2962} 2822}
2963DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030, 2823DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class);
2964 quirk_broken_intx_masking);
2965DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2966 quirk_broken_intx_masking);
2967 2824
2968static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 2825static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2969 struct pci_fixup *end) 2826 struct pci_fixup *end)
2970{ 2827{
2971 ktime_t calltime; 2828 while (f < end) {
2972 2829 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
2973 for (; f < end; f++) 2830 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
2974 if ((f->class == (u32) (dev->class >> f->class_shift) || 2831 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2975 f->class == (u32) PCI_ANY_ID) &&
2976 (f->vendor == dev->vendor ||
2977 f->vendor == (u16) PCI_ANY_ID) &&
2978 (f->device == dev->device ||
2979 f->device == (u16) PCI_ANY_ID)) {
2980 calltime = fixup_debug_start(dev, f->hook);
2981 f->hook(dev); 2832 f->hook(dev);
2982 fixup_debug_report(dev, calltime, f->hook);
2983 } 2833 }
2834 f++;
2835 }
2984} 2836}
2985 2837
2986extern struct pci_fixup __start_pci_fixups_early[]; 2838extern struct pci_fixup __start_pci_fixups_early[];
@@ -2998,7 +2850,6 @@ extern struct pci_fixup __end_pci_fixups_resume_early[];
2998extern struct pci_fixup __start_pci_fixups_suspend[]; 2850extern struct pci_fixup __start_pci_fixups_suspend[];
2999extern struct pci_fixup __end_pci_fixups_suspend[]; 2851extern struct pci_fixup __end_pci_fixups_suspend[];
3000 2852
3001static bool pci_apply_fixup_final_quirks;
3002 2853
3003void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 2854void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3004{ 2855{
@@ -3016,8 +2867,6 @@ void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3016 break; 2867 break;
3017 2868
3018 case pci_fixup_final: 2869 case pci_fixup_final:
3019 if (!pci_apply_fixup_final_quirks)
3020 return;
3021 start = __start_pci_fixups_final; 2870 start = __start_pci_fixups_final;
3022 end = __end_pci_fixups_final; 2871 end = __end_pci_fixups_final;
3023 break; 2872 break;
@@ -3050,7 +2899,6 @@ void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3050} 2899}
3051EXPORT_SYMBOL(pci_fixup_device); 2900EXPORT_SYMBOL(pci_fixup_device);
3052 2901
3053
3054static int __init pci_apply_final_quirks(void) 2902static int __init pci_apply_final_quirks(void)
3055{ 2903{
3056 struct pci_dev *dev = NULL; 2904 struct pci_dev *dev = NULL;
@@ -3061,7 +2909,6 @@ static int __init pci_apply_final_quirks(void)
3061 printk(KERN_DEBUG "PCI: CLS %u bytes\n", 2909 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3062 pci_cache_line_size << 2); 2910 pci_cache_line_size << 2);
3063 2911
3064 pci_apply_fixup_final_quirks = true;
3065 for_each_pci_dev(dev) { 2912 for_each_pci_dev(dev) {
3066 pci_fixup_device(pci_fixup_final, dev); 2913 pci_fixup_device(pci_fixup_final, dev);
3067 /* 2914 /*
@@ -3082,7 +2929,6 @@ static int __init pci_apply_final_quirks(void)
3082 pci_cache_line_size = pci_dfl_cache_line_size; 2929 pci_cache_line_size = pci_dfl_cache_line_size;
3083 } 2930 }
3084 } 2931 }
3085
3086 if (!pci_cache_line_size) { 2932 if (!pci_cache_line_size) {
3087 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", 2933 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3088 cls << 2, pci_dfl_cache_line_size << 2); 2934 cls << 2, pci_dfl_cache_line_size << 2);
@@ -3123,109 +2969,32 @@ static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3123 2969
3124static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) 2970static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3125{ 2971{
3126 int i; 2972 int pos;
3127 u16 status;
3128 2973
3129 /* 2974 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
3130 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 2975 if (!pos)
3131 * 2976 return -ENOTTY;
3132 * The 82599 supports FLR on VFs, but FLR support is reported only
3133 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3134 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3135 */
3136 2977
3137 if (probe) 2978 if (probe)
3138 return 0; 2979 return 0;
3139 2980
3140 /* Wait for Transaction Pending bit clean */ 2981 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
3141 for (i = 0; i < 4; i++) { 2982 PCI_EXP_DEVCTL_BCR_FLR);
3142 if (i)
3143 msleep((1 << (i - 1)) * 100);
3144
3145 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3146 if (!(status & PCI_EXP_DEVSTA_TRPND))
3147 goto clear;
3148 }
3149
3150 dev_err(&dev->dev, "transaction is not cleared; "
3151 "proceeding with reset anyway\n");
3152
3153clear:
3154 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3155
3156 msleep(100); 2983 msleep(100);
3157 2984
3158 return 0; 2985 return 0;
3159} 2986}
3160 2987
3161#include "../gpu/drm/i915/i915_reg.h"
3162#define MSG_CTL 0x45010
3163#define NSDE_PWR_STATE 0xd0100
3164#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3165
3166static int reset_ivb_igd(struct pci_dev *dev, int probe)
3167{
3168 void __iomem *mmio_base;
3169 unsigned long timeout;
3170 u32 val;
3171
3172 if (probe)
3173 return 0;
3174
3175 mmio_base = pci_iomap(dev, 0, 0);
3176 if (!mmio_base)
3177 return -ENOMEM;
3178
3179 iowrite32(0x00000002, mmio_base + MSG_CTL);
3180
3181 /*
3182 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3183 * driver loaded sets the right bits. However, this's a reset and
3184 * the bits have been set by i915 previously, so we clobber
3185 * SOUTH_CHICKEN2 register directly here.
3186 */
3187 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3188
3189 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3190 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3191
3192 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3193 do {
3194 val = ioread32(mmio_base + PCH_PP_STATUS);
3195 if ((val & 0xb0000000) == 0)
3196 goto reset_complete;
3197 msleep(10);
3198 } while (time_before(jiffies, timeout));
3199 dev_warn(&dev->dev, "timeout during reset\n");
3200
3201reset_complete:
3202 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3203
3204 pci_iounmap(dev, mmio_base);
3205 return 0;
3206}
3207
3208#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 2988#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3209#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3210#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3211 2989
3212static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 2990static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3213 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 2991 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3214 reset_intel_82599_sfp_virtfn }, 2992 reset_intel_82599_sfp_virtfn },
3215 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3216 reset_ivb_igd },
3217 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3218 reset_ivb_igd },
3219 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2993 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3220 reset_intel_generic_dev }, 2994 reset_intel_generic_dev },
3221 { 0 } 2995 { 0 }
3222}; 2996};
3223 2997
3224/*
3225 * These device-specific reset methods are here rather than in a driver
3226 * because when a host assigns a device to a guest VM, the host may need
3227 * to reset the device but probably doesn't have a driver for it.
3228 */
3229int pci_dev_specific_reset(struct pci_dev *dev, int probe) 2998int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3230{ 2999{
3231 const struct pci_dev_reset_methods *i; 3000 const struct pci_dev_reset_methods *i;
@@ -3240,87 +3009,3 @@ int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3240 3009
3241 return -ENOTTY; 3010 return -ENOTTY;
3242} 3011}
3243
3244static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3245{
3246 if (!PCI_FUNC(dev->devfn))
3247 return pci_dev_get(dev);
3248
3249 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3250}
3251
3252static const struct pci_dev_dma_source {
3253 u16 vendor;
3254 u16 device;
3255 struct pci_dev *(*dma_source)(struct pci_dev *dev);
3256} pci_dev_dma_source[] = {
3257 /*
3258 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3259 *
3260 * Some Ricoh devices use the function 0 source ID for DMA on
3261 * other functions of a multifunction device. The DMA devices
3262 * is therefore function 0, which will have implications of the
3263 * iommu grouping of these devices.
3264 */
3265 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3266 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3267 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3268 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3269 { 0 }
3270};
3271
3272/*
3273 * IOMMUs with isolation capabilities need to be programmed with the
3274 * correct source ID of a device. In most cases, the source ID matches
3275 * the device doing the DMA, but sometimes hardware is broken and will
3276 * tag the DMA as being sourced from a different device. This function
3277 * allows that translation. Note that the reference count of the
3278 * returned device is incremented on all paths.
3279 */
3280struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3281{
3282 const struct pci_dev_dma_source *i;
3283
3284 for (i = pci_dev_dma_source; i->dma_source; i++) {
3285 if ((i->vendor == dev->vendor ||
3286 i->vendor == (u16)PCI_ANY_ID) &&
3287 (i->device == dev->device ||
3288 i->device == (u16)PCI_ANY_ID))
3289 return i->dma_source(dev);
3290 }
3291
3292 return pci_dev_get(dev);
3293}
3294
3295static const struct pci_dev_acs_enabled {
3296 u16 vendor;
3297 u16 device;
3298 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3299} pci_dev_acs_enabled[] = {
3300 { 0 }
3301};
3302
3303int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3304{
3305 const struct pci_dev_acs_enabled *i;
3306 int ret;
3307
3308 /*
3309 * Allow devices that do not expose standard PCIe ACS capabilities
3310 * or control to indicate their support here. Multi-function express
3311 * devices which do not allow internal peer-to-peer between functions,
3312 * but do not implement PCIe ACS may wish to return true here.
3313 */
3314 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3315 if ((i->vendor == dev->vendor ||
3316 i->vendor == (u16)PCI_ANY_ID) &&
3317 (i->device == dev->device ||
3318 i->device == (u16)PCI_ANY_ID)) {
3319 ret = i->acs_enabled(dev, acs_flags);
3320 if (ret >= 0)
3321 return ret;
3322 }
3323 }
3324
3325 return -ENOTTY;
3326}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 16:31:27 -0400