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authorMatthew Wilcox <matthew@wil.cx>2009-12-13 08:11:32 -0500
committerJesse Barnes <jbarnes@virtuousgeek.org>2010-02-22 19:15:17 -0500
commit3749c51ac6c1560aa1cb1520066bed84c6f8152a (patch)
tree3cbfb6a6d2df821e3e80ccce29ede8011b94246e /drivers/pci/hotplug/pciehp_hpc.c
parent536c8cb49eccd4f753b4782e7e975ef87359cb44 (diff)
PCI: Make current and maximum bus speeds part of the PCI core
Move the max_bus_speed and cur_bus_speed into the pci_bus. Expose the values through the PCI slot driver instead of the hotplug slot driver. Update all the hotplug drivers to use the pci_bus instead of their own data structures. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/hotplug/pciehp_hpc.c')
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c72
1 files changed, 9 insertions, 63 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 6744ca1d8d0..40b48f569b1 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -492,6 +492,7 @@ int pciehp_power_on_slot(struct slot * slot)
492 u16 slot_cmd; 492 u16 slot_cmd;
493 u16 cmd_mask; 493 u16 cmd_mask;
494 u16 slot_status; 494 u16 slot_status;
495 u16 lnk_status;
495 int retval = 0; 496 int retval = 0;
496 497
497 /* Clear sticky power-fault bit from previous power failures */ 498 /* Clear sticky power-fault bit from previous power failures */
@@ -523,6 +524,14 @@ int pciehp_power_on_slot(struct slot * slot)
523 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 524 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
524 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 525 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
525 526
527 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
528 if (retval) {
529 ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n",
530 __func__);
531 return retval;
532 }
533 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
534
526 return retval; 535 return retval;
527} 536}
528 537
@@ -610,37 +619,6 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
610 return IRQ_HANDLED; 619 return IRQ_HANDLED;
611} 620}
612 621
613int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *value)
614{
615 struct controller *ctrl = slot->ctrl;
616 enum pci_bus_speed lnk_speed;
617 u32 lnk_cap;
618 int retval = 0;
619
620 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
621 if (retval) {
622 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
623 return retval;
624 }
625
626 switch (lnk_cap & 0x000F) {
627 case 1:
628 lnk_speed = PCIE_SPEED_2_5GT;
629 break;
630 case 2:
631 lnk_speed = PCIE_SPEED_5_0GT;
632 break;
633 default:
634 lnk_speed = PCI_SPEED_UNKNOWN;
635 break;
636 }
637
638 *value = lnk_speed;
639 ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
640
641 return retval;
642}
643
644int pciehp_get_max_lnk_width(struct slot *slot, 622int pciehp_get_max_lnk_width(struct slot *slot,
645 enum pcie_link_width *value) 623 enum pcie_link_width *value)
646{ 624{
@@ -691,38 +669,6 @@ int pciehp_get_max_lnk_width(struct slot *slot,
691 return retval; 669 return retval;
692} 670}
693 671
694int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *value)
695{
696 struct controller *ctrl = slot->ctrl;
697 enum pci_bus_speed lnk_speed = PCI_SPEED_UNKNOWN;
698 int retval = 0;
699 u16 lnk_status;
700
701 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
702 if (retval) {
703 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
704 __func__);
705 return retval;
706 }
707
708 switch (lnk_status & PCI_EXP_LNKSTA_CLS) {
709 case 1:
710 lnk_speed = PCIE_SPEED_2_5GT;
711 break;
712 case 2:
713 lnk_speed = PCIE_SPEED_5_0GT;
714 break;
715 default:
716 lnk_speed = PCI_SPEED_UNKNOWN;
717 break;
718 }
719
720 *value = lnk_speed;
721 ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
722
723 return retval;
724}
725
726int pciehp_get_cur_lnk_width(struct slot *slot, 672int pciehp_get_cur_lnk_width(struct slot *slot,
727 enum pcie_link_width *value) 673 enum pcie_link_width *value)
728{ 674{