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authorTomas Winkler <tomas.winkler@intel.com>2008-03-04 21:09:28 -0500
committerJohn W. Linville <linville@tuxdriver.com>2008-03-07 16:03:00 -0500
commit6f83eaa170c05324fb33668eace007ea24c277d2 (patch)
tree8d2b263c08b0449bf4f9de407fa161c750aff702 /drivers/net
parent4c424e4cc7bc9d3c4c22b408904c36b44afddc3e (diff)
iwlwifi: extract iwl-csr.h
This patch extract CSR Register definition into separate header files as most of the definition are commons to both 3945 and 4965. Definitions specific for 3945 and 4965 are properly prefixed Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-hw.h135
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c18
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.h3
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-hw.h131
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c6
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.h1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-csr.h217
-rw-r--r--drivers/net/wireless/iwlwifi/iwl3945-base.c4
-rw-r--r--drivers/net/wireless/iwlwifi/iwl4965-base.c4
9 files changed, 236 insertions, 283 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
index 6693767adc9..269224ba23b 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
@@ -321,141 +321,6 @@ struct iwl3945_eeprom {
321#define PCI_REG_WUM8 0x0E8 321#define PCI_REG_WUM8 0x0E8
322#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) 322#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
323 323
324/*=== CSR (control and status registers) ===*/
325#define CSR_BASE (0x000)
326
327#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
328#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
329#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
330#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
331#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
332#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
333#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
334#define CSR_GP_CNTRL (CSR_BASE+0x024)
335
336/*
337 * Hardware revision info
338 * Bit fields:
339 * 31-8: Reserved
340 * 7-4: Type of device: 0x0 = 4965, 0xd = 3945
341 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
342 * 1-0: "Dash" value, as in A-1, etc.
343 */
344#define CSR_HW_REV (CSR_BASE+0x028)
345
346/* EEPROM reads */
347#define CSR_EEPROM_REG (CSR_BASE+0x02c)
348#define CSR_EEPROM_GP (CSR_BASE+0x030)
349#define CSR_GP_UCODE (CSR_BASE+0x044)
350#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
351#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
352#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
353#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
354#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
355
356/* Analog phase-lock-loop configuration (3945 only)
357 * Set bit 24. */
358#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
359
360/* Bits for CSR_HW_IF_CONFIG_REG */
361#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100)
362#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200)
363#define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
364#define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
365#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
366#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
367#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
368
369/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
370 * acknowledged (reset) by host writing "1" to flagged bits. */
371#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
372#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
373#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */
374#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
375#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
376#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
377#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
378#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
379#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
380#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
381#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
382
383#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
384 CSR_INT_BIT_HW_ERR | \
385 CSR_INT_BIT_FH_TX | \
386 CSR_INT_BIT_SW_ERR | \
387 CSR_INT_BIT_RF_KILL | \
388 CSR_INT_BIT_SW_RX | \
389 CSR_INT_BIT_WAKEUP | \
390 CSR_INT_BIT_ALIVE)
391
392/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
393#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
394#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
395#define CSR_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */
396#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
397#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
398#define CSR_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */
399#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
400#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
401
402#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
403 CSR_FH_INT_BIT_RX_CHNL2 | \
404 CSR_FH_INT_BIT_RX_CHNL1 | \
405 CSR_FH_INT_BIT_RX_CHNL0)
406
407#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL6 | \
408 CSR_FH_INT_BIT_TX_CHNL1 | \
409 CSR_FH_INT_BIT_TX_CHNL0)
410
411
412/* RESET */
413#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
414#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
415#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
416#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
417#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
418
419/* GP (general purpose) CONTROL */
420#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
421#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
422#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
423#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
424
425#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
426
427#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
428#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
429#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
430
431
432/* EEPROM REG */
433#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
434#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
435
436/* EEPROM GP */
437#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
438#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
439#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
440
441/* UCODE DRV GP */
442#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
443#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
444#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
445#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
446
447/* GPIO */
448#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
449#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
450#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
451
452/* GI Chicken Bits */
453#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
454#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
455
456/* CSR_ANA_PLL_CFG */
457#define CSR_ANA_PLL_CFG_SH (0x00880300)
458
459/*=== HBUS (Host-side Bus) ===*/ 324/*=== HBUS (Host-side Bus) ===*/
460#define HBUS_BASE (0x400) 325#define HBUS_BASE (0x400)
461 326
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 63e832cdba7..0fca35650ad 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -1154,19 +1154,19 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
1154 if (rev_id & PCI_CFG_REV_ID_BIT_RTP) 1154 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1155 IWL_DEBUG_INFO("RTP type \n"); 1155 IWL_DEBUG_INFO("RTP type \n");
1156 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) { 1156 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1157 IWL_DEBUG_INFO("ALM-MB type\n"); 1157 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1158 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1158 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1159 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB); 1159 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1160 } else { 1160 } else {
1161 IWL_DEBUG_INFO("ALM-MM type\n"); 1161 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1162 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1162 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1163 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM); 1163 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1164 } 1164 }
1165 1165
1166 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) { 1166 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1167 IWL_DEBUG_INFO("SKU OP mode is mrc\n"); 1167 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1168 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1168 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1169 CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC); 1169 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1170 } else 1170 } else
1171 IWL_DEBUG_INFO("SKU OP mode is basic\n"); 1171 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1172 1172
@@ -1174,24 +1174,24 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
1174 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", 1174 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1175 priv->eeprom.board_revision); 1175 priv->eeprom.board_revision);
1176 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1176 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1177 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 1177 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1178 } else { 1178 } else {
1179 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", 1179 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1180 priv->eeprom.board_revision); 1180 priv->eeprom.board_revision);
1181 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG, 1181 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1182 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 1182 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1183 } 1183 }
1184 1184
1185 if (priv->eeprom.almgor_m_version <= 1) { 1185 if (priv->eeprom.almgor_m_version <= 1) {
1186 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1186 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1187 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A); 1187 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1188 IWL_DEBUG_INFO("Card M type A version is 0x%X\n", 1188 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1189 priv->eeprom.almgor_m_version); 1189 priv->eeprom.almgor_m_version);
1190 } else { 1190 } else {
1191 IWL_DEBUG_INFO("Card M type B version is 0x%X\n", 1191 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1192 priv->eeprom.almgor_m_version); 1192 priv->eeprom.almgor_m_version);
1193 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1193 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1194 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B); 1194 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1195 } 1195 }
1196 spin_unlock_irqrestore(&priv->lock, flags); 1196 spin_unlock_irqrestore(&priv->lock, flags);
1197 1197
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.h b/drivers/net/wireless/iwlwifi/iwl-3945.h
index d281e42964d..1701e0b9b87 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.h
@@ -40,8 +40,9 @@
40extern struct pci_device_id iwl3945_hw_card_ids[]; 40extern struct pci_device_id iwl3945_hw_card_ids[];
41 41
42#define DRV_NAME "iwl3945" 42#define DRV_NAME "iwl3945"
43#include "iwl-3945-hw.h" 43#include "iwl-csr.h"
44#include "iwl-prph.h" 44#include "iwl-prph.h"
45#include "iwl-3945-hw.h"
45#include "iwl-3945-debug.h" 46#include "iwl-3945-debug.h"
46 47
47/* Default noise level to report when noise measurement is not available. 48/* Default noise level to report when noise measurement is not available.
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
index cc726215ab9..7e8cc9928b5 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
@@ -410,137 +410,6 @@ struct iwl4965_eeprom {
410#define PCI_REG_WUM8 0x0E8 410#define PCI_REG_WUM8 0x0E8
411#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) 411#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
412 412
413/*=== CSR (control and status registers) ===*/
414#define CSR_BASE (0x000)
415
416#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
417#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
418#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
419#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
420#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
421#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
422#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
423#define CSR_GP_CNTRL (CSR_BASE+0x024)
424
425/*
426 * Hardware revision info
427 * Bit fields:
428 * 31-8: Reserved
429 * 7-4: Type of device: 0x0 = 4965, 0xd = 3945
430 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
431 * 1-0: "Dash" value, as in A-1, etc.
432 *
433 * NOTE: Revision step affects calculation of CCK txpower for 4965.
434 */
435#define CSR_HW_REV (CSR_BASE+0x028)
436
437/* EEPROM reads */
438#define CSR_EEPROM_REG (CSR_BASE+0x02c)
439#define CSR_EEPROM_GP (CSR_BASE+0x030)
440#define CSR_GP_UCODE (CSR_BASE+0x044)
441#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
442#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
443#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
444#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
445#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
446
447/*
448 * Indicates hardware rev, to determine CCK backoff for txpower calculation.
449 * Bit fields:
450 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
451 */
452#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
453
454/* Hardware interface configuration bits */
455#define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010)
456#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
457#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
458#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
459#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
460
461/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
462 * acknowledged (reset) by host writing "1" to flagged bits. */
463#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
464#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
465#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */
466#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
467#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
468#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
469#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
470#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
471#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
472#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
473#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
474
475#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
476 CSR_INT_BIT_HW_ERR | \
477 CSR_INT_BIT_FH_TX | \
478 CSR_INT_BIT_SW_ERR | \
479 CSR_INT_BIT_RF_KILL | \
480 CSR_INT_BIT_SW_RX | \
481 CSR_INT_BIT_WAKEUP | \
482 CSR_INT_BIT_ALIVE)
483
484/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
485#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
486#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
487#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
488#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
489#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
490#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
491
492#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
493 CSR_FH_INT_BIT_RX_CHNL1 | \
494 CSR_FH_INT_BIT_RX_CHNL0)
495
496#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
497 CSR_FH_INT_BIT_TX_CHNL0)
498
499
500/* RESET */
501#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
502#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
503#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
504#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
505#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
506
507/* GP (general purpose) CONTROL */
508#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
509#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
510#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
511#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
512
513#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
514
515#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
516#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
517#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
518
519
520/* EEPROM REG */
521#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
522#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
523
524/* EEPROM GP */
525#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
526#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
527#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
528
529/* UCODE DRV GP */
530#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
531#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
532#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
533#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
534
535/* GPIO */
536#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
537#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
538#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
539
540/* GI Chicken Bits */
541#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
542#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
543
544/*=== HBUS (Host-side Bus) ===*/ 413/*=== HBUS (Host-side Bus) ===*/
545#define HBUS_BASE (0x400) 414#define HBUS_BASE (0x400)
546 415
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 05ad5a9a1a5..2da153331a7 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -604,9 +604,9 @@ int iwl4965_hw_nic_init(struct iwl4965_priv *priv)
604 /* set CSR_HW_CONFIG_REG for uCode use */ 604 /* set CSR_HW_CONFIG_REG for uCode use */
605 605
606 iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG, 606 iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG,
607 CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R | 607 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
608 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 608 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
609 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 609 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
610 610
611 rc = iwl4965_grab_nic_access(priv); 611 rc = iwl4965_grab_nic_access(priv);
612 if (rc < 0) { 612 if (rc < 0) {
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.h b/drivers/net/wireless/iwlwifi/iwl-4965.h
index 5c605129dfb..a782c454e0d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.h
@@ -41,6 +41,7 @@ extern struct pci_device_id iwl4965_hw_card_ids[];
41 41
42#define DRV_NAME "iwl4965" 42#define DRV_NAME "iwl4965"
43#include "iwl-4965-hw.h" 43#include "iwl-4965-hw.h"
44#include "iwl-csr.h"
44#include "iwl-prph.h" 45#include "iwl-prph.h"
45#include "iwl-4965-debug.h" 46#include "iwl-4965-debug.h"
46 47
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h
new file mode 100644
index 00000000000..276ba281604
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-csr.h
@@ -0,0 +1,217 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63/*=== CSR (control and status registers) ===*/
64#define CSR_BASE (0x000)
65
66#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
67#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
68#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
69#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
70#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
71#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
72#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
73#define CSR_GP_CNTRL (CSR_BASE+0x024)
74
75/*
76 * Hardware revision info
77 * Bit fields:
78 * 31-8: Reserved
79 * 7-4: Type of device: 0x0 = 4965, 0xd = 3945
80 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
81 * 1-0: "Dash" value, as in A-1, etc.
82 *
83 * NOTE: Revision step affects calculation of CCK txpower for 4965.
84 */
85#define CSR_HW_REV (CSR_BASE+0x028)
86
87/* EEPROM reads */
88#define CSR_EEPROM_REG (CSR_BASE+0x02c)
89#define CSR_EEPROM_GP (CSR_BASE+0x030)
90#define CSR_GP_UCODE (CSR_BASE+0x044)
91#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
92#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
93#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
94#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
95#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
96
97/* Analog phase-lock-loop configuration (3945 only)
98 * Set bit 24. */
99#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
100/*
101 * Indicates hardware rev, to determine CCK backoff for txpower calculation.
102 * Bit fields:
103 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
104 */
105#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
106
107/* Bits for CSR_HW_IF_CONFIG_REG */
108#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010)
109#define CSR49_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
110#define CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
111#define CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
112
113#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100)
114#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200)
115#define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
116#define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
117#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
118#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
119
120#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
121
122/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
123 * acknowledged (reset) by host writing "1" to flagged bits. */
124#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
125#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
126#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */
127#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
128#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
129#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
130#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
131#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
132#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
133#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
134#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
135
136#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
137 CSR_INT_BIT_HW_ERR | \
138 CSR_INT_BIT_FH_TX | \
139 CSR_INT_BIT_SW_ERR | \
140 CSR_INT_BIT_RF_KILL | \
141 CSR_INT_BIT_SW_RX | \
142 CSR_INT_BIT_WAKEUP | \
143 CSR_INT_BIT_ALIVE)
144
145/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
146#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
147#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
148#define CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */
149#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
150#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
151#define CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */
152#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
153#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
154
155#define CSR39_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
156 CSR39_FH_INT_BIT_RX_CHNL2 | \
157 CSR_FH_INT_BIT_RX_CHNL1 | \
158 CSR_FH_INT_BIT_RX_CHNL0)
159
160
161#define CSR39_FH_INT_TX_MASK (CSR39_FH_INT_BIT_TX_CHNL6 | \
162 CSR_FH_INT_BIT_TX_CHNL1 | \
163 CSR_FH_INT_BIT_TX_CHNL0)
164
165#define CSR49_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
166 CSR_FH_INT_BIT_RX_CHNL1 | \
167 CSR_FH_INT_BIT_RX_CHNL0)
168
169#define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
170 CSR_FH_INT_BIT_TX_CHNL0)
171
172
173/* RESET */
174#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
175#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
176#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
177#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
178#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
179
180/* GP (general purpose) CONTROL */
181#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
182#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
183#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
184#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
185
186#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
187
188#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
189#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
190#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
191
192
193/* EEPROM REG */
194#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
195#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
196
197/* EEPROM GP */
198#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
199#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
200#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
201
202/* UCODE DRV GP */
203#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
204#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
205#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
206#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
207
208/* GPIO */
209#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
210#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
211#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
212
213/* GI Chicken Bits */
214#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
215#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
216
217
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index 7a72048b0f4..cc71bdc8035 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -4570,9 +4570,9 @@ static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
4570 * atomic, make sure that inta covers all the interrupts that 4570 * atomic, make sure that inta covers all the interrupts that
4571 * we've discovered, even if FH interrupt came in just after 4571 * we've discovered, even if FH interrupt came in just after
4572 * reading CSR_INT. */ 4572 * reading CSR_INT. */
4573 if (inta_fh & CSR_FH_INT_RX_MASK) 4573 if (inta_fh & CSR39_FH_INT_RX_MASK)
4574 inta |= CSR_INT_BIT_FH_RX; 4574 inta |= CSR_INT_BIT_FH_RX;
4575 if (inta_fh & CSR_FH_INT_TX_MASK) 4575 if (inta_fh & CSR39_FH_INT_TX_MASK)
4576 inta |= CSR_INT_BIT_FH_TX; 4576 inta |= CSR_INT_BIT_FH_TX;
4577 4577
4578 /* Now service all interrupt bits discovered above. */ 4578 /* Now service all interrupt bits discovered above. */
diff --git a/drivers/net/wireless/iwlwifi/iwl4965-base.c b/drivers/net/wireless/iwlwifi/iwl4965-base.c
index f273395d4a3..0c60f594dfe 100644
--- a/drivers/net/wireless/iwlwifi/iwl4965-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl4965-base.c
@@ -4918,9 +4918,9 @@ static void iwl4965_irq_tasklet(struct iwl4965_priv *priv)
4918 * atomic, make sure that inta covers all the interrupts that 4918 * atomic, make sure that inta covers all the interrupts that
4919 * we've discovered, even if FH interrupt came in just after 4919 * we've discovered, even if FH interrupt came in just after
4920 * reading CSR_INT. */ 4920 * reading CSR_INT. */
4921 if (inta_fh & CSR_FH_INT_RX_MASK) 4921 if (inta_fh & CSR49_FH_INT_RX_MASK)
4922 inta |= CSR_INT_BIT_FH_RX; 4922 inta |= CSR_INT_BIT_FH_RX;
4923 if (inta_fh & CSR_FH_INT_TX_MASK) 4923 if (inta_fh & CSR49_FH_INT_TX_MASK)
4924 inta |= CSR_INT_BIT_FH_TX; 4924 inta |= CSR_INT_BIT_FH_TX;
4925 4925
4926 /* Now service all interrupt bits discovered above. */ 4926 /* Now service all interrupt bits discovered above. */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 05:36:32 -0400