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authorLinus Torvalds <torvalds@woody.osdl.org>2006-12-07 12:05:15 -0500
committerLinus Torvalds <torvalds@woody.osdl.org>2006-12-07 12:05:15 -0500
commit2685b267bce34c9b66626cb11664509c32a761a5 (patch)
treece8b4ad47b4a1aa1b0e7634298d63c4cb0ca46c5 /drivers/net
parent4522d58275f124105819723e24e912c8e5bf3cdd (diff)
parent272491ef423b6976a230a998b10f46976aa91342 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6: (48 commits) [NETFILTER]: Fix non-ANSI func. decl. [TG3]: Identify Serdes devices more clearly. [TG3]: Use msleep. [TG3]: Use netif_msg_*. [TG3]: Allow partial speed advertisement. [TG3]: Add TG3_FLG2_IS_NIC flag. [TG3]: Add 5787F device ID. [TG3]: Fix Phy loopback. [WANROUTER]: Kill kmalloc debugging code. [TCP] inet_twdr_hangman: Delete unnecessary memory barrier(). [NET]: Memory barrier cleanups [IPSEC]: Fix inetpeer leak in ipv4 xfrm dst entries. audit: disable ipsec auditing when CONFIG_AUDITSYSCALL=n audit: Add auditing to ipsec [IRDA] irlan: Fix compile warning when CONFIG_PROC_FS=n [IrDA]: Incorrect TTP header reservation [IrDA]: PXA FIR code device model conversion [GENETLINK]: Fix misplaced command flags. [NETLIK]: Add a pointer to the Generic Netlink wiki page. [IPV6] RAW: Don't release unlocked sock. ...
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/irda/pxaficp_ir.c26
-rw-r--r--drivers/net/tg3.c142
-rw-r--r--drivers/net/tg3.h1
3 files changed, 96 insertions, 73 deletions
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index f9a1c88a428..9137e239fac 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -704,9 +704,9 @@ static int pxa_irda_stop(struct net_device *dev)
704 return 0; 704 return 0;
705} 705}
706 706
707static int pxa_irda_suspend(struct device *_dev, pm_message_t state) 707static int pxa_irda_suspend(struct platform_device *_dev, pm_message_t state)
708{ 708{
709 struct net_device *dev = dev_get_drvdata(_dev); 709 struct net_device *dev = platform_get_drvdata(_dev);
710 struct pxa_irda *si; 710 struct pxa_irda *si;
711 711
712 if (dev && netif_running(dev)) { 712 if (dev && netif_running(dev)) {
@@ -718,9 +718,9 @@ static int pxa_irda_suspend(struct device *_dev, pm_message_t state)
718 return 0; 718 return 0;
719} 719}
720 720
721static int pxa_irda_resume(struct device *_dev) 721static int pxa_irda_resume(struct platform_device *_dev)
722{ 722{
723 struct net_device *dev = dev_get_drvdata(_dev); 723 struct net_device *dev = platform_get_drvdata(_dev);
724 struct pxa_irda *si; 724 struct pxa_irda *si;
725 725
726 if (dev && netif_running(dev)) { 726 if (dev && netif_running(dev)) {
@@ -746,9 +746,8 @@ static int pxa_irda_init_iobuf(iobuff_t *io, int size)
746 return io->head ? 0 : -ENOMEM; 746 return io->head ? 0 : -ENOMEM;
747} 747}
748 748
749static int pxa_irda_probe(struct device *_dev) 749static int pxa_irda_probe(struct platform_device *pdev)
750{ 750{
751 struct platform_device *pdev = to_platform_device(_dev);
752 struct net_device *dev; 751 struct net_device *dev;
753 struct pxa_irda *si; 752 struct pxa_irda *si;
754 unsigned int baudrate_mask; 753 unsigned int baudrate_mask;
@@ -822,9 +821,9 @@ err_mem_1:
822 return err; 821 return err;
823} 822}
824 823
825static int pxa_irda_remove(struct device *_dev) 824static int pxa_irda_remove(struct platform_device *_dev)
826{ 825{
827 struct net_device *dev = dev_get_drvdata(_dev); 826 struct net_device *dev = platform_get_drvdata(_dev);
828 827
829 if (dev) { 828 if (dev) {
830 struct pxa_irda *si = netdev_priv(dev); 829 struct pxa_irda *si = netdev_priv(dev);
@@ -840,9 +839,10 @@ static int pxa_irda_remove(struct device *_dev)
840 return 0; 839 return 0;
841} 840}
842 841
843static struct device_driver pxa_ir_driver = { 842static struct platform_driver pxa_ir_driver = {
844 .name = "pxa2xx-ir", 843 .driver = {
845 .bus = &platform_bus_type, 844 .name = "pxa2xx-ir",
845 },
846 .probe = pxa_irda_probe, 846 .probe = pxa_irda_probe,
847 .remove = pxa_irda_remove, 847 .remove = pxa_irda_remove,
848 .suspend = pxa_irda_suspend, 848 .suspend = pxa_irda_suspend,
@@ -851,12 +851,12 @@ static struct device_driver pxa_ir_driver = {
851 851
852static int __init pxa_irda_init(void) 852static int __init pxa_irda_init(void)
853{ 853{
854 return driver_register(&pxa_ir_driver); 854 return platform_driver_register(&pxa_ir_driver);
855} 855}
856 856
857static void __exit pxa_irda_exit(void) 857static void __exit pxa_irda_exit(void)
858{ 858{
859 driver_unregister(&pxa_ir_driver); 859 platform_driver_unregister(&pxa_ir_driver);
860} 860}
861 861
862module_init(pxa_irda_init); 862module_init(pxa_irda_init);
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d9123c9adc1..571320ae87a 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -68,8 +68,8 @@
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": " 70#define PFX DRV_MODULE_NAME ": "
71#define DRV_MODULE_VERSION "3.69" 71#define DRV_MODULE_VERSION "3.70"
72#define DRV_MODULE_RELDATE "November 15, 2006" 72#define DRV_MODULE_RELDATE "December 1, 2006"
73 73
74#define TG3_DEF_MAC_MODE 0 74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0 75#define TG3_DEF_RX_MODE 0
@@ -192,6 +192,7 @@ static struct pci_device_id tg3_pci_tbl[] = {
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, 192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, 193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, 194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, 196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, 197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, 198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
@@ -1061,7 +1062,7 @@ static void tg3_frob_aux_power(struct tg3 *tp)
1061{ 1062{
1062 struct tg3 *tp_peer = tp; 1063 struct tg3 *tp_peer = tp;
1063 1064
1064 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0) 1065 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1065 return; 1066 return;
1066 1067
1067 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || 1068 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
@@ -1212,8 +1213,8 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1212 power_control); 1213 power_control);
1213 udelay(100); /* Delay after power state change */ 1214 udelay(100); /* Delay after power state change */
1214 1215
1215 /* Switch out of Vaux if it is not a LOM */ 1216 /* Switch out of Vaux if it is a NIC */
1216 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) 1217 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1217 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); 1218 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1218 1219
1219 return 0; 1220 return 0;
@@ -1401,8 +1402,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1401static void tg3_link_report(struct tg3 *tp) 1402static void tg3_link_report(struct tg3 *tp)
1402{ 1403{
1403 if (!netif_carrier_ok(tp->dev)) { 1404 if (!netif_carrier_ok(tp->dev)) {
1404 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name); 1405 if (netif_msg_link(tp))
1405 } else { 1406 printk(KERN_INFO PFX "%s: Link is down.\n",
1407 tp->dev->name);
1408 } else if (netif_msg_link(tp)) {
1406 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n", 1409 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1407 tp->dev->name, 1410 tp->dev->name,
1408 (tp->link_config.active_speed == SPEED_1000 ? 1411 (tp->link_config.active_speed == SPEED_1000 ?
@@ -1557,12 +1560,6 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
1557 1560
1558 tg3_writephy(tp, MII_ADVERTISE, new_adv); 1561 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1559 } else if (tp->link_config.speed == SPEED_INVALID) { 1562 } else if (tp->link_config.speed == SPEED_INVALID) {
1560 tp->link_config.advertising =
1561 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1562 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1563 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1564 ADVERTISED_Autoneg | ADVERTISED_MII);
1565
1566 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) 1563 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1567 tp->link_config.advertising &= 1564 tp->link_config.advertising &=
1568 ~(ADVERTISED_1000baseT_Half | 1565 ~(ADVERTISED_1000baseT_Half |
@@ -1706,25 +1703,36 @@ static int tg3_init_5401phy_dsp(struct tg3 *tp)
1706 return err; 1703 return err;
1707} 1704}
1708 1705
1709static int tg3_copper_is_advertising_all(struct tg3 *tp) 1706static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1710{ 1707{
1711 u32 adv_reg, all_mask; 1708 u32 adv_reg, all_mask = 0;
1709
1710 if (mask & ADVERTISED_10baseT_Half)
1711 all_mask |= ADVERTISE_10HALF;
1712 if (mask & ADVERTISED_10baseT_Full)
1713 all_mask |= ADVERTISE_10FULL;
1714 if (mask & ADVERTISED_100baseT_Half)
1715 all_mask |= ADVERTISE_100HALF;
1716 if (mask & ADVERTISED_100baseT_Full)
1717 all_mask |= ADVERTISE_100FULL;
1712 1718
1713 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) 1719 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1714 return 0; 1720 return 0;
1715 1721
1716 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1717 ADVERTISE_100HALF | ADVERTISE_100FULL);
1718 if ((adv_reg & all_mask) != all_mask) 1722 if ((adv_reg & all_mask) != all_mask)
1719 return 0; 1723 return 0;
1720 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { 1724 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1721 u32 tg3_ctrl; 1725 u32 tg3_ctrl;
1722 1726
1727 all_mask = 0;
1728 if (mask & ADVERTISED_1000baseT_Half)
1729 all_mask |= ADVERTISE_1000HALF;
1730 if (mask & ADVERTISED_1000baseT_Full)
1731 all_mask |= ADVERTISE_1000FULL;
1732
1723 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) 1733 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1724 return 0; 1734 return 0;
1725 1735
1726 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1727 MII_TG3_CTRL_ADV_1000_FULL);
1728 if ((tg3_ctrl & all_mask) != all_mask) 1736 if ((tg3_ctrl & all_mask) != all_mask)
1729 return 0; 1737 return 0;
1730 } 1738 }
@@ -1884,7 +1892,8 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1884 /* Force autoneg restart if we are exiting 1892 /* Force autoneg restart if we are exiting
1885 * low power mode. 1893 * low power mode.
1886 */ 1894 */
1887 if (!tg3_copper_is_advertising_all(tp)) 1895 if (!tg3_copper_is_advertising_all(tp,
1896 tp->link_config.advertising))
1888 current_link_up = 0; 1897 current_link_up = 0;
1889 } else { 1898 } else {
1890 current_link_up = 0; 1899 current_link_up = 0;
@@ -3703,8 +3712,9 @@ static void tg3_tx_timeout(struct net_device *dev)
3703{ 3712{
3704 struct tg3 *tp = netdev_priv(dev); 3713 struct tg3 *tp = netdev_priv(dev);
3705 3714
3706 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n", 3715 if (netif_msg_tx_err(tp))
3707 dev->name); 3716 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3717 dev->name);
3708 3718
3709 schedule_work(&tp->reset_task); 3719 schedule_work(&tp->reset_task);
3710} 3720}
@@ -6396,16 +6406,17 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6396 udelay(40); 6406 udelay(40);
6397 6407
6398 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). 6408 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6399 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the 6409 * If TG3_FLG2_IS_NIC is zero, we should read the
6400 * register to preserve the GPIO settings for LOMs. The GPIOs, 6410 * register to preserve the GPIO settings for LOMs. The GPIOs,
6401 * whether used as inputs or outputs, are set by boot code after 6411 * whether used as inputs or outputs, are set by boot code after
6402 * reset. 6412 * reset.
6403 */ 6413 */
6404 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { 6414 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6405 u32 gpio_mask; 6415 u32 gpio_mask;
6406 6416
6407 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 | 6417 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6408 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2; 6418 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6419 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6409 6420
6410 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) 6421 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6411 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | 6422 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
@@ -6417,8 +6428,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6417 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; 6428 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6418 6429
6419 /* GPIO1 must be driven high for eeprom write protect */ 6430 /* GPIO1 must be driven high for eeprom write protect */
6420 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | 6431 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6421 GRC_LCLCTRL_GPIO_OUTPUT1); 6432 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6433 GRC_LCLCTRL_GPIO_OUTPUT1);
6422 } 6434 }
6423 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 6435 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6424 udelay(100); 6436 udelay(100);
@@ -8656,7 +8668,9 @@ static int tg3_test_registers(struct tg3 *tp)
8656 return 0; 8668 return 0;
8657 8669
8658out: 8670out:
8659 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset); 8671 if (netif_msg_hw(tp))
8672 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8673 offset);
8660 tw32(offset, save_val); 8674 tw32(offset, save_val);
8661 return -EIO; 8675 return -EIO;
8662} 8676}
@@ -8781,17 +8795,20 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8781 tg3_writephy(tp, 0x10, phy & ~0x4000); 8795 tg3_writephy(tp, 0x10, phy & ~0x4000);
8782 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest); 8796 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8783 } 8797 }
8784 } 8798 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8785 val = BMCR_LOOPBACK | BMCR_FULLDPLX; 8799 } else
8786 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) 8800 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8787 val |= BMCR_SPEED100;
8788 else
8789 val |= BMCR_SPEED1000;
8790 8801
8791 tg3_writephy(tp, MII_BMCR, val); 8802 tg3_writephy(tp, MII_BMCR, val);
8792 udelay(40); 8803 udelay(40);
8793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 8804
8805 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8806 MAC_MODE_LINK_POLARITY;
8807 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8794 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800); 8808 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8809 mac_mode |= MAC_MODE_PORT_MODE_MII;
8810 } else
8811 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8795 8812
8796 /* reset to prevent losing 1st rx packet intermittently */ 8813 /* reset to prevent losing 1st rx packet intermittently */
8797 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { 8814 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
@@ -8799,12 +8816,6 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8799 udelay(10); 8816 udelay(10);
8800 tw32_f(MAC_RX_MODE, tp->rx_mode); 8817 tw32_f(MAC_RX_MODE, tp->rx_mode);
8801 } 8818 }
8802 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8803 MAC_MODE_LINK_POLARITY;
8804 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8805 mac_mode |= MAC_MODE_PORT_MODE_MII;
8806 else
8807 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8808 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 8819 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8809 mac_mode &= ~MAC_MODE_LINK_POLARITY; 8820 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8810 tg3_writephy(tp, MII_TG3_EXT_CTRL, 8821 tg3_writephy(tp, MII_TG3_EXT_CTRL,
@@ -9456,16 +9467,12 @@ static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9456/* Chips other than 5700/5701 use the NVRAM for fetching info. */ 9467/* Chips other than 5700/5701 use the NVRAM for fetching info. */
9457static void __devinit tg3_nvram_init(struct tg3 *tp) 9468static void __devinit tg3_nvram_init(struct tg3 *tp)
9458{ 9469{
9459 int j;
9460
9461 tw32_f(GRC_EEPROM_ADDR, 9470 tw32_f(GRC_EEPROM_ADDR,
9462 (EEPROM_ADDR_FSM_RESET | 9471 (EEPROM_ADDR_FSM_RESET |
9463 (EEPROM_DEFAULT_CLOCK_PERIOD << 9472 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9464 EEPROM_ADDR_CLKPERD_SHIFT))); 9473 EEPROM_ADDR_CLKPERD_SHIFT)));
9465 9474
9466 /* XXX schedule_timeout() ... */ 9475 msleep(1);
9467 for (j = 0; j < 100; j++)
9468 udelay(10);
9469 9476
9470 /* Enable seeprom accesses. */ 9477 /* Enable seeprom accesses. */
9471 tw32_f(GRC_LOCAL_CTRL, 9478 tw32_f(GRC_LOCAL_CTRL,
@@ -9526,12 +9533,12 @@ static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9526 EEPROM_ADDR_ADDR_MASK) | 9533 EEPROM_ADDR_ADDR_MASK) |
9527 EEPROM_ADDR_READ | EEPROM_ADDR_START); 9534 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9528 9535
9529 for (i = 0; i < 10000; i++) { 9536 for (i = 0; i < 1000; i++) {
9530 tmp = tr32(GRC_EEPROM_ADDR); 9537 tmp = tr32(GRC_EEPROM_ADDR);
9531 9538
9532 if (tmp & EEPROM_ADDR_COMPLETE) 9539 if (tmp & EEPROM_ADDR_COMPLETE)
9533 break; 9540 break;
9534 udelay(100); 9541 msleep(1);
9535 } 9542 }
9536 if (!(tmp & EEPROM_ADDR_COMPLETE)) 9543 if (!(tmp & EEPROM_ADDR_COMPLETE))
9537 return -EBUSY; 9544 return -EBUSY;
@@ -9656,12 +9663,12 @@ static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9656 EEPROM_ADDR_START | 9663 EEPROM_ADDR_START |
9657 EEPROM_ADDR_WRITE); 9664 EEPROM_ADDR_WRITE);
9658 9665
9659 for (j = 0; j < 10000; j++) { 9666 for (j = 0; j < 1000; j++) {
9660 val = tr32(GRC_EEPROM_ADDR); 9667 val = tr32(GRC_EEPROM_ADDR);
9661 9668
9662 if (val & EEPROM_ADDR_COMPLETE) 9669 if (val & EEPROM_ADDR_COMPLETE)
9663 break; 9670 break;
9664 udelay(100); 9671 msleep(1);
9665 } 9672 }
9666 if (!(val & EEPROM_ADDR_COMPLETE)) { 9673 if (!(val & EEPROM_ADDR_COMPLETE)) {
9667 rc = -EBUSY; 9674 rc = -EBUSY;
@@ -9965,8 +9972,10 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9965 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; 9972 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9966 9973
9967 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 9974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9968 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) 9975 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
9969 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; 9976 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9977 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
9978 }
9970 return; 9979 return;
9971 } 9980 }
9972 9981
@@ -10066,10 +10075,17 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10066 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) 10075 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10067 tp->led_ctrl = LED_CTRL_MODE_PHY_2; 10076 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10068 10077
10069 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) 10078 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10070 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; 10079 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10071 else 10080 if ((tp->pdev->subsystem_vendor ==
10081 PCI_VENDOR_ID_ARIMA) &&
10082 (tp->pdev->subsystem_device == 0x205a ||
10083 tp->pdev->subsystem_device == 0x2063))
10084 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10085 } else {
10072 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; 10086 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10087 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10088 }
10073 10089
10074 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 10090 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10075 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 10091 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
@@ -10147,7 +10163,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
10147 10163
10148 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) && 10164 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10149 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { 10165 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10150 u32 bmsr, adv_reg, tg3_ctrl; 10166 u32 bmsr, adv_reg, tg3_ctrl, mask;
10151 10167
10152 tg3_readphy(tp, MII_BMSR, &bmsr); 10168 tg3_readphy(tp, MII_BMSR, &bmsr);
10153 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && 10169 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
@@ -10171,7 +10187,10 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
10171 MII_TG3_CTRL_ENABLE_AS_MASTER); 10187 MII_TG3_CTRL_ENABLE_AS_MASTER);
10172 } 10188 }
10173 10189
10174 if (!tg3_copper_is_advertising_all(tp)) { 10190 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10191 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10192 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10193 if (!tg3_copper_is_advertising_all(tp, mask)) {
10175 tg3_writephy(tp, MII_ADVERTISE, adv_reg); 10194 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10176 10195
10177 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) 10196 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
@@ -10695,7 +10714,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10695 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; 10714 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10696 10715
10697 /* Get eeprom hw config before calling tg3_set_power_state(). 10716 /* Get eeprom hw config before calling tg3_set_power_state().
10698 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be 10717 * In particular, the TG3_FLG2_IS_NIC flag must be
10699 * determined before calling tg3_set_power_state() so that 10718 * determined before calling tg3_set_power_state() so that
10700 * we know whether or not to switch out of Vaux power. 10719 * we know whether or not to switch out of Vaux power.
10701 * When the flag is set, it means that GPIO1 is used for eeprom 10720 * When the flag is set, it means that GPIO1 is used for eeprom
@@ -10862,7 +10881,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10862 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || 10881 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10863 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && 10882 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10864 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || 10883 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10865 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)) || 10884 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10885 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10866 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 10886 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10867 tp->tg3_flags |= TG3_FLAG_10_100_ONLY; 10887 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10868 10888
@@ -11912,13 +11932,15 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
11912 11932
11913 pci_set_drvdata(pdev, dev); 11933 pci_set_drvdata(pdev, dev);
11914 11934
11915 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ", 11935 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11916 dev->name, 11936 dev->name,
11917 tp->board_part_number, 11937 tp->board_part_number,
11918 tp->pci_chip_rev_id, 11938 tp->pci_chip_rev_id,
11919 tg3_phy_string(tp), 11939 tg3_phy_string(tp),
11920 tg3_bus_string(tp, str), 11940 tg3_bus_string(tp, str),
11921 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000"); 11941 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11942 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11943 "10/100/1000Base-T")));
11922 11944
11923 for (i = 0; i < 6; i++) 11945 for (i = 0; i < 6; i++)
11924 printk("%2.2x%c", dev->dev_addr[i], 11946 printk("%2.2x%c", dev->dev_addr[i],
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 92f53000bce..dfaf4ed127b 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2233,6 +2233,7 @@ struct tg3 {
2233#define TG3_FLG2_PCI_EXPRESS 0x00000200 2233#define TG3_FLG2_PCI_EXPRESS 0x00000200
2234#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400 2234#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2235#define TG3_FLG2_HW_AUTONEG 0x00000800 2235#define TG3_FLG2_HW_AUTONEG 0x00000800
2236#define TG3_FLG2_IS_NIC 0x00001000
2236#define TG3_FLG2_PHY_SERDES 0x00002000 2237#define TG3_FLG2_PHY_SERDES 0x00002000
2237#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000 2238#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
2238#define TG3_FLG2_FLASH 0x00008000 2239#define TG3_FLG2_FLASH 0x00008000