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authorPeter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>2009-04-09 18:28:50 -0400
committerDavid S. Miller <davem@davemloft.net>2009-04-11 05:48:02 -0400
commit04193058c1005551af93f04a4b975fbd7f95cad5 (patch)
tree2c6292e6cc7e277c9ff579eb99a51ee19123cc1b /drivers/net
parent1eb99d5ac44e2a9ac0b2856c579ba4d7cc349ada (diff)
ixgbe: Update get_physical_layer() calls, plus a version bump
Not all physical connection types are being correctly identified. This fixes that issue, and cleans up the logic to make it more maintainable. Also clean up the code for device capabilities from the EEPROM to support multiple SKUs of the same hardware. Bump the version to reflect all the updates since the 82599 merge. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c85
-rw-r--r--drivers/net/ixgbe/ixgbe_82599.c134
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.c8
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h10
5 files changed, 169 insertions, 70 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 361c9d1d011..a7ae4d45b53 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -1089,35 +1089,56 @@ out:
1089static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1089static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1090{ 1090{
1091 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1091 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1092 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1093 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1094 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1095 u16 ext_ability = 0;
1096
1097 hw->phy.ops.identify(hw);
1098
1099 /* Copper PHY must be checked before AUTOC LMS to determine correct
1100 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1101 if (hw->phy.type == ixgbe_phy_tn ||
1102 hw->phy.type == ixgbe_phy_cu_unknown) {
1103 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1104 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1105 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1106 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1107 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1108 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1109 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1110 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1111 goto out;
1112 }
1092 1113
1093 switch (hw->device_id) { 1114 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1094 case IXGBE_DEV_ID_82598: 1115 case IXGBE_AUTOC_LMS_1G_AN:
1095 /* Default device ID is mezzanine card KX/KX4 */ 1116 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1096 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 1117 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1097 IXGBE_PHYSICAL_LAYER_1000BASE_KX); 1118 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1098 break; 1119 else
1099 case IXGBE_DEV_ID_82598_BX: 1120 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1100 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1101 case IXGBE_DEV_ID_82598EB_CX4:
1102 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1103 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1104 break;
1105 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1106 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1107 break; 1121 break;
1108 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1122 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1109 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1123 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1110 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1124 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1111 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1125 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1126 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1127 else /* XAUI */
1128 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1112 break; 1129 break;
1113 case IXGBE_DEV_ID_82598EB_XF_LR: 1130 case IXGBE_AUTOC_LMS_KX4_AN:
1114 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1131 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1132 if (autoc & IXGBE_AUTOC_KX_SUPP)
1133 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1134 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1135 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1115 break; 1136 break;
1116 case IXGBE_DEV_ID_82598AT: 1137 default:
1117 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1118 IXGBE_PHYSICAL_LAYER_1000BASE_T);
1119 break; 1138 break;
1120 case IXGBE_DEV_ID_82598EB_SFP_LOM: 1139 }
1140
1141 if (hw->phy.type == ixgbe_phy_nl) {
1121 hw->phy.ops.identify_sfp(hw); 1142 hw->phy.ops.identify_sfp(hw);
1122 1143
1123 switch (hw->phy.sfp_type) { 1144 switch (hw->phy.sfp_type) {
@@ -1134,13 +1155,25 @@ static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1134 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1155 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1135 break; 1156 break;
1136 } 1157 }
1137 break; 1158 }
1138 1159
1160 switch (hw->device_id) {
1161 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1162 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1163 break;
1164 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1165 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1166 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1167 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1168 break;
1169 case IXGBE_DEV_ID_82598EB_XF_LR:
1170 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1171 break;
1139 default: 1172 default:
1140 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1141 break; 1173 break;
1142 } 1174 }
1143 1175
1176out:
1144 return physical_layer; 1177 return physical_layer;
1145} 1178}
1146 1179
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index 50b399c1e87..b3f4e96a018 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -1177,53 +1177,98 @@ s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1177u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1177u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1178{ 1178{
1179 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1179 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1180 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1181 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1182 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1183 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1184 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1185 u16 ext_ability = 0;
1180 u8 comp_codes_10g = 0; 1186 u8 comp_codes_10g = 0;
1181 1187
1182 switch (hw->device_id) { 1188 hw->phy.ops.identify(hw);
1183 case IXGBE_DEV_ID_82599: 1189
1184 case IXGBE_DEV_ID_82599_KX4: 1190 if (hw->phy.type == ixgbe_phy_tn ||
1185 /* Default device ID is mezzanine card KX/KX4 */ 1191 hw->phy.type == ixgbe_phy_cu_unknown) {
1186 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 1192 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1187 IXGBE_PHYSICAL_LAYER_1000BASE_KX); 1193 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1194 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1195 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1196 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1197 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1198 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1199 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1200 goto out;
1201 }
1202
1203 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1204 case IXGBE_AUTOC_LMS_1G_AN:
1205 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1206 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1207 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1208 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1209 goto out;
1210 } else
1211 /* SFI mode so read SFP module */
1212 goto sfp_check;
1188 break; 1213 break;
1189 case IXGBE_DEV_ID_82599_SFP: 1214 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1190 hw->phy.ops.identify_sfp(hw); 1215 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1216 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1217 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1218 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1219 goto out;
1220 break;
1221 case IXGBE_AUTOC_LMS_10G_SERIAL:
1222 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1223 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1224 goto out;
1225 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1226 goto sfp_check;
1227 break;
1228 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1229 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1230 if (autoc & IXGBE_AUTOC_KX_SUPP)
1231 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1232 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1233 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1234 if (autoc & IXGBE_AUTOC_KR_SUPP)
1235 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1236 goto out;
1237 break;
1238 default:
1239 goto out;
1240 break;
1241 }
1191 1242
1192 switch (hw->phy.sfp_type) { 1243sfp_check:
1193 case ixgbe_sfp_type_da_cu: 1244 /* SFP check must be done last since DA modules are sometimes used to
1194 case ixgbe_sfp_type_da_cu_core0: 1245 * test KR mode - we need to id KR mode correctly before SFP module.
1195 case ixgbe_sfp_type_da_cu_core1: 1246 * Call identify_sfp because the pluggable module may have changed */
1196 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1247 hw->phy.ops.identify_sfp(hw);
1197 break; 1248 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1198 case ixgbe_sfp_type_sr: 1249 goto out;
1250
1251 switch (hw->phy.type) {
1252 case ixgbe_phy_tw_tyco:
1253 case ixgbe_phy_tw_unknown:
1254 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1255 break;
1256 case ixgbe_phy_sfp_avago:
1257 case ixgbe_phy_sfp_ftl:
1258 case ixgbe_phy_sfp_intel:
1259 case ixgbe_phy_sfp_unknown:
1260 hw->phy.ops.read_i2c_eeprom(hw,
1261 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1262 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1199 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1263 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1200 break; 1264 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1201 case ixgbe_sfp_type_lr:
1202 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1265 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1203 break;
1204 case ixgbe_sfp_type_srlr_core0:
1205 case ixgbe_sfp_type_srlr_core1:
1206 hw->phy.ops.read_i2c_eeprom(hw,
1207 IXGBE_SFF_10GBE_COMP_CODES,
1208 &comp_codes_10g);
1209 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1210 physical_layer =
1211 IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1212 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1213 physical_layer =
1214 IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1215 else
1216 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1217 default:
1218 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1219 break;
1220 }
1221 break; 1266 break;
1222 default: 1267 default:
1223 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1224 break; 1268 break;
1225 } 1269 }
1226 1270
1271out:
1227 return physical_layer; 1272 return physical_layer;
1228} 1273}
1229 1274
@@ -1271,6 +1316,22 @@ s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1271 return 0; 1316 return 0;
1272} 1317}
1273 1318
1319/**
1320 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1321 * @hw: pointer to hardware structure
1322 * @device_caps: the EEPROM word with the extra device capabilities
1323 *
1324 * This function will read the EEPROM location for the device capabilities,
1325 * and return the word through device_caps.
1326 **/
1327s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1328{
1329 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1330
1331 return 0;
1332}
1333
1334
1274static struct ixgbe_mac_operations mac_ops_82599 = { 1335static struct ixgbe_mac_operations mac_ops_82599 = {
1275 .init_hw = &ixgbe_init_hw_generic, 1336 .init_hw = &ixgbe_init_hw_generic,
1276 .reset_hw = &ixgbe_reset_hw_82599, 1337 .reset_hw = &ixgbe_reset_hw_82599,
@@ -1280,6 +1341,7 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
1280 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, 1341 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1281 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 1342 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1282 .get_mac_addr = &ixgbe_get_mac_addr_generic, 1343 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1344 .get_device_caps = &ixgbe_get_device_caps_82599,
1283 .stop_adapter = &ixgbe_stop_adapter_generic, 1345 .stop_adapter = &ixgbe_stop_adapter_generic,
1284 .get_bus_info = &ixgbe_get_bus_info_generic, 1346 .get_bus_info = &ixgbe_get_bus_info_generic,
1285 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 1347 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 936a3efb362..2856486e165 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -47,7 +47,7 @@ char ixgbe_driver_name[] = "ixgbe";
47static const char ixgbe_driver_string[] = 47static const char ixgbe_driver_string[] =
48 "Intel(R) 10 Gigabit PCI Express Network Driver"; 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
49 49
50#define DRV_VERSION "2.0.8-k2" 50#define DRV_VERSION "2.0.16-k2"
51const char ixgbe_driver_version[] = DRV_VERSION; 51const char ixgbe_driver_version[] = DRV_VERSION;
52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; 52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
53 53
diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
index 6f11df756da..f3258ec901f 100644
--- a/drivers/net/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -632,7 +632,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
632 hw->phy.multispeed_fiber = true; 632 hw->phy.multispeed_fiber = true;
633 633
634 /* Determine PHY vendor */ 634 /* Determine PHY vendor */
635 if (hw->phy.type == ixgbe_phy_unknown) { 635 if (hw->phy.type != ixgbe_phy_nl) {
636 hw->phy.id = identifier; 636 hw->phy.id = identifier;
637 hw->phy.ops.read_i2c_eeprom(hw, 637 hw->phy.ops.read_i2c_eeprom(hw,
638 IXGBE_SFF_VENDOR_OUI_BYTE0, 638 IXGBE_SFF_VENDOR_OUI_BYTE0,
@@ -682,9 +682,9 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
682 goto out; 682 goto out;
683 } 683 }
684 684
685 hw->eeprom.ops.read(hw, IXGBE_PHY_ENFORCE_INTEL_SFP_OFFSET, 685 /* This is guaranteed to be 82599, no need to check for NULL */
686 &enforce_sfp); 686 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
687 if (!(enforce_sfp & IXGBE_PHY_ALLOW_ANY_SFP)) { 687 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
688 /* Make sure we're a supported PHY type */ 688 /* Make sure we're a supported PHY type */
689 if (hw->phy.type == ixgbe_phy_sfp_intel) { 689 if (hw->phy.type == ixgbe_phy_sfp_intel) {
690 status = 0; 690 status = 0;
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index db65c05773a..a3317d8fbf6 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -862,6 +862,7 @@
862#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ 862#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */
863#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ 863#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */
864#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ 864#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */
865#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */
865 866
866#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 867#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
867#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 868#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
@@ -898,8 +899,6 @@
898#define IXGBE_CONTROL_NL 0x000F 899#define IXGBE_CONTROL_NL 0x000F
899#define IXGBE_CONTROL_EOL_NL 0x0FFF 900#define IXGBE_CONTROL_EOL_NL 0x0FFF
900#define IXGBE_CONTROL_SOL_NL 0x0000 901#define IXGBE_CONTROL_SOL_NL 0x0000
901#define IXGBE_PHY_ENFORCE_INTEL_SFP_OFFSET 0x002C
902#define IXGBE_PHY_ALLOW_ANY_SFP 0x1
903 902
904/* General purpose Interrupt Enable */ 903/* General purpose Interrupt Enable */
905#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 904#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
@@ -1385,6 +1384,7 @@
1385#define IXGBE_FW_PTR 0x0F 1384#define IXGBE_FW_PTR 0x0F
1386#define IXGBE_PBANUM0_PTR 0x15 1385#define IXGBE_PBANUM0_PTR 0x15
1387#define IXGBE_PBANUM1_PTR 0x16 1386#define IXGBE_PBANUM1_PTR 0x16
1387#define IXGBE_DEVICE_CAPS 0x2C
1388#define IXGBE_PCIE_MSIX_82599_CAPS 0x72 1388#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
1389#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 1389#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1390 1390
@@ -1428,6 +1428,8 @@
1428#define IXGBE_EERD_ATTEMPTS 100000 1428#define IXGBE_EERD_ATTEMPTS 100000
1429#endif 1429#endif
1430 1430
1431#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
1432
1431/* PCI Bus Info */ 1433/* PCI Bus Info */
1432#define IXGBE_PCI_LINK_STATUS 0xB2 1434#define IXGBE_PCI_LINK_STATUS 0xB2
1433#define IXGBE_PCI_LINK_WIDTH 0x3F0 1435#define IXGBE_PCI_LINK_WIDTH 0x3F0
@@ -1865,7 +1867,7 @@ typedef u32 ixgbe_physical_layer;
1865#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 1867#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
1866#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 1868#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
1867#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 1869#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
1868#define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004 1870#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
1869#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 1871#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
1870#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 1872#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
1871#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 1873#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
@@ -1874,6 +1876,7 @@ typedef u32 ixgbe_physical_layer;
1874#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 1876#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
1875#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 1877#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
1876#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 1878#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
1879#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
1877 1880
1878enum ixgbe_eeprom_type { 1881enum ixgbe_eeprom_type {
1879 ixgbe_eeprom_uninitialized = 0, 1882 ixgbe_eeprom_uninitialized = 0,
@@ -2105,6 +2108,7 @@ struct ixgbe_mac_operations {
2105 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 2108 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2106 u32 (*get_supported_physical_layer)(struct ixgbe_hw *); 2109 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2107 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 2110 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2111 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
2108 s32 (*stop_adapter)(struct ixgbe_hw *); 2112 s32 (*stop_adapter)(struct ixgbe_hw *);
2109 s32 (*get_bus_info)(struct ixgbe_hw *); 2113 s32 (*get_bus_info)(struct ixgbe_hw *);
2110 void (*set_lan_id)(struct ixgbe_hw *); 2114 void (*set_lan_id)(struct ixgbe_hw *);