diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
---|---|---|
committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
commit | fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch) | |
tree | a57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/net/wireless/wl12xx/boot.c | |
parent | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff) |
Diffstat (limited to 'drivers/net/wireless/wl12xx/boot.c')
-rw-r--r-- | drivers/net/wireless/wl12xx/boot.c | 876 |
1 files changed, 876 insertions, 0 deletions
diff --git a/drivers/net/wireless/wl12xx/boot.c b/drivers/net/wireless/wl12xx/boot.c new file mode 100644 index 00000000000..454e913bec6 --- /dev/null +++ b/drivers/net/wireless/wl12xx/boot.c | |||
@@ -0,0 +1,876 @@ | |||
1 | /* | ||
2 | * This file is part of wl1271 | ||
3 | * | ||
4 | * Copyright (C) 2008-2010 Nokia Corporation | ||
5 | * | ||
6 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or | ||
9 | * modify it under the terms of the GNU General Public License | ||
10 | * version 2 as published by the Free Software Foundation. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, but | ||
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
15 | * General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | ||
20 | * 02110-1301 USA | ||
21 | * | ||
22 | */ | ||
23 | |||
24 | #include <linux/slab.h> | ||
25 | #include <linux/wl12xx.h> | ||
26 | |||
27 | #include "acx.h" | ||
28 | #include "reg.h" | ||
29 | #include "boot.h" | ||
30 | #include "io.h" | ||
31 | #include "event.h" | ||
32 | #include "rx.h" | ||
33 | |||
34 | static struct wl1271_partition_set part_table[PART_TABLE_LEN] = { | ||
35 | [PART_DOWN] = { | ||
36 | .mem = { | ||
37 | .start = 0x00000000, | ||
38 | .size = 0x000177c0 | ||
39 | }, | ||
40 | .reg = { | ||
41 | .start = REGISTERS_BASE, | ||
42 | .size = 0x00008800 | ||
43 | }, | ||
44 | .mem2 = { | ||
45 | .start = 0x00000000, | ||
46 | .size = 0x00000000 | ||
47 | }, | ||
48 | .mem3 = { | ||
49 | .start = 0x00000000, | ||
50 | .size = 0x00000000 | ||
51 | }, | ||
52 | }, | ||
53 | |||
54 | [PART_WORK] = { | ||
55 | .mem = { | ||
56 | .start = 0x00040000, | ||
57 | .size = 0x00014fc0 | ||
58 | }, | ||
59 | .reg = { | ||
60 | .start = REGISTERS_BASE, | ||
61 | .size = 0x0000a000 | ||
62 | }, | ||
63 | .mem2 = { | ||
64 | .start = 0x003004f8, | ||
65 | .size = 0x00000004 | ||
66 | }, | ||
67 | .mem3 = { | ||
68 | .start = 0x00040404, | ||
69 | .size = 0x00000000 | ||
70 | }, | ||
71 | }, | ||
72 | |||
73 | [PART_DRPW] = { | ||
74 | .mem = { | ||
75 | .start = 0x00040000, | ||
76 | .size = 0x00014fc0 | ||
77 | }, | ||
78 | .reg = { | ||
79 | .start = DRPW_BASE, | ||
80 | .size = 0x00006000 | ||
81 | }, | ||
82 | .mem2 = { | ||
83 | .start = 0x00000000, | ||
84 | .size = 0x00000000 | ||
85 | }, | ||
86 | .mem3 = { | ||
87 | .start = 0x00000000, | ||
88 | .size = 0x00000000 | ||
89 | } | ||
90 | } | ||
91 | }; | ||
92 | |||
93 | static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag) | ||
94 | { | ||
95 | u32 cpu_ctrl; | ||
96 | |||
97 | /* 10.5.0 run the firmware (I) */ | ||
98 | cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL); | ||
99 | |||
100 | /* 10.5.1 run the firmware (II) */ | ||
101 | cpu_ctrl |= flag; | ||
102 | wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); | ||
103 | } | ||
104 | |||
105 | static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271 *wl) | ||
106 | { | ||
107 | unsigned int quirks = 0; | ||
108 | unsigned int *fw_ver = wl->chip.fw_ver; | ||
109 | |||
110 | /* Only for wl127x */ | ||
111 | if ((fw_ver[FW_VER_CHIP] == FW_VER_CHIP_WL127X) && | ||
112 | /* Check STA version */ | ||
113 | (((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) && | ||
114 | (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_1_SPARE_STA_MIN)) || | ||
115 | /* Check AP version */ | ||
116 | ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP) && | ||
117 | (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_1_SPARE_AP_MIN)))) | ||
118 | quirks |= WL12XX_QUIRK_USE_2_SPARE_BLOCKS; | ||
119 | |||
120 | /* Only new station firmwares support routing fw logs to the host */ | ||
121 | if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) && | ||
122 | (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN)) | ||
123 | quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED; | ||
124 | |||
125 | /* This feature is not yet supported for AP mode */ | ||
126 | if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP) | ||
127 | quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED; | ||
128 | |||
129 | return quirks; | ||
130 | } | ||
131 | |||
132 | static void wl1271_parse_fw_ver(struct wl1271 *wl) | ||
133 | { | ||
134 | int ret; | ||
135 | |||
136 | ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u", | ||
137 | &wl->chip.fw_ver[0], &wl->chip.fw_ver[1], | ||
138 | &wl->chip.fw_ver[2], &wl->chip.fw_ver[3], | ||
139 | &wl->chip.fw_ver[4]); | ||
140 | |||
141 | if (ret != 5) { | ||
142 | wl1271_warning("fw version incorrect value"); | ||
143 | memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver)); | ||
144 | return; | ||
145 | } | ||
146 | |||
147 | /* Check if any quirks are needed with older fw versions */ | ||
148 | wl->quirks |= wl12xx_get_fw_ver_quirks(wl); | ||
149 | } | ||
150 | |||
151 | static void wl1271_boot_fw_version(struct wl1271 *wl) | ||
152 | { | ||
153 | struct wl1271_static_data static_data; | ||
154 | |||
155 | wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data), | ||
156 | false); | ||
157 | |||
158 | strncpy(wl->chip.fw_ver_str, static_data.fw_version, | ||
159 | sizeof(wl->chip.fw_ver_str)); | ||
160 | |||
161 | /* make sure the string is NULL-terminated */ | ||
162 | wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0'; | ||
163 | |||
164 | wl1271_parse_fw_ver(wl); | ||
165 | } | ||
166 | |||
167 | static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf, | ||
168 | size_t fw_data_len, u32 dest) | ||
169 | { | ||
170 | struct wl1271_partition_set partition; | ||
171 | int addr, chunk_num, partition_limit; | ||
172 | u8 *p, *chunk; | ||
173 | |||
174 | /* whal_FwCtrl_LoadFwImageSm() */ | ||
175 | |||
176 | wl1271_debug(DEBUG_BOOT, "starting firmware upload"); | ||
177 | |||
178 | wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d", | ||
179 | fw_data_len, CHUNK_SIZE); | ||
180 | |||
181 | if ((fw_data_len % 4) != 0) { | ||
182 | wl1271_error("firmware length not multiple of four"); | ||
183 | return -EIO; | ||
184 | } | ||
185 | |||
186 | chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL); | ||
187 | if (!chunk) { | ||
188 | wl1271_error("allocation for firmware upload chunk failed"); | ||
189 | return -ENOMEM; | ||
190 | } | ||
191 | |||
192 | memcpy(&partition, &part_table[PART_DOWN], sizeof(partition)); | ||
193 | partition.mem.start = dest; | ||
194 | wl1271_set_partition(wl, &partition); | ||
195 | |||
196 | /* 10.1 set partition limit and chunk num */ | ||
197 | chunk_num = 0; | ||
198 | partition_limit = part_table[PART_DOWN].mem.size; | ||
199 | |||
200 | while (chunk_num < fw_data_len / CHUNK_SIZE) { | ||
201 | /* 10.2 update partition, if needed */ | ||
202 | addr = dest + (chunk_num + 2) * CHUNK_SIZE; | ||
203 | if (addr > partition_limit) { | ||
204 | addr = dest + chunk_num * CHUNK_SIZE; | ||
205 | partition_limit = chunk_num * CHUNK_SIZE + | ||
206 | part_table[PART_DOWN].mem.size; | ||
207 | partition.mem.start = addr; | ||
208 | wl1271_set_partition(wl, &partition); | ||
209 | } | ||
210 | |||
211 | /* 10.3 upload the chunk */ | ||
212 | addr = dest + chunk_num * CHUNK_SIZE; | ||
213 | p = buf + chunk_num * CHUNK_SIZE; | ||
214 | memcpy(chunk, p, CHUNK_SIZE); | ||
215 | wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", | ||
216 | p, addr); | ||
217 | wl1271_write(wl, addr, chunk, CHUNK_SIZE, false); | ||
218 | |||
219 | chunk_num++; | ||
220 | } | ||
221 | |||
222 | /* 10.4 upload the last chunk */ | ||
223 | addr = dest + chunk_num * CHUNK_SIZE; | ||
224 | p = buf + chunk_num * CHUNK_SIZE; | ||
225 | memcpy(chunk, p, fw_data_len % CHUNK_SIZE); | ||
226 | wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x", | ||
227 | fw_data_len % CHUNK_SIZE, p, addr); | ||
228 | wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false); | ||
229 | |||
230 | kfree(chunk); | ||
231 | return 0; | ||
232 | } | ||
233 | |||
234 | static int wl1271_boot_upload_firmware(struct wl1271 *wl) | ||
235 | { | ||
236 | u32 chunks, addr, len; | ||
237 | int ret = 0; | ||
238 | u8 *fw; | ||
239 | |||
240 | fw = wl->fw; | ||
241 | chunks = be32_to_cpup((__be32 *) fw); | ||
242 | fw += sizeof(u32); | ||
243 | |||
244 | wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks); | ||
245 | |||
246 | while (chunks--) { | ||
247 | addr = be32_to_cpup((__be32 *) fw); | ||
248 | fw += sizeof(u32); | ||
249 | len = be32_to_cpup((__be32 *) fw); | ||
250 | fw += sizeof(u32); | ||
251 | |||
252 | if (len > 300000) { | ||
253 | wl1271_info("firmware chunk too long: %u", len); | ||
254 | return -EINVAL; | ||
255 | } | ||
256 | wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u", | ||
257 | chunks, addr, len); | ||
258 | ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr); | ||
259 | if (ret != 0) | ||
260 | break; | ||
261 | fw += len; | ||
262 | } | ||
263 | |||
264 | return ret; | ||
265 | } | ||
266 | |||
267 | static int wl1271_boot_upload_nvs(struct wl1271 *wl) | ||
268 | { | ||
269 | size_t nvs_len, burst_len; | ||
270 | int i; | ||
271 | u32 dest_addr, val; | ||
272 | u8 *nvs_ptr, *nvs_aligned; | ||
273 | |||
274 | if (wl->nvs == NULL) | ||
275 | return -ENODEV; | ||
276 | |||
277 | if (wl->chip.id == CHIP_ID_1283_PG20) { | ||
278 | struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs; | ||
279 | |||
280 | if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) { | ||
281 | if (nvs->general_params.dual_mode_select) | ||
282 | wl->enable_11a = true; | ||
283 | } else { | ||
284 | wl1271_error("nvs size is not as expected: %zu != %zu", | ||
285 | wl->nvs_len, | ||
286 | sizeof(struct wl128x_nvs_file)); | ||
287 | kfree(wl->nvs); | ||
288 | wl->nvs = NULL; | ||
289 | wl->nvs_len = 0; | ||
290 | return -EILSEQ; | ||
291 | } | ||
292 | |||
293 | /* only the first part of the NVS needs to be uploaded */ | ||
294 | nvs_len = sizeof(nvs->nvs); | ||
295 | nvs_ptr = (u8 *)nvs->nvs; | ||
296 | |||
297 | } else { | ||
298 | struct wl1271_nvs_file *nvs = | ||
299 | (struct wl1271_nvs_file *)wl->nvs; | ||
300 | /* | ||
301 | * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz | ||
302 | * band configurations) can be removed when those NVS files stop | ||
303 | * floating around. | ||
304 | */ | ||
305 | if (wl->nvs_len == sizeof(struct wl1271_nvs_file) || | ||
306 | wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) { | ||
307 | /* for now 11a is unsupported in AP mode */ | ||
308 | if (wl->bss_type != BSS_TYPE_AP_BSS && | ||
309 | nvs->general_params.dual_mode_select) | ||
310 | wl->enable_11a = true; | ||
311 | } | ||
312 | |||
313 | if (wl->nvs_len != sizeof(struct wl1271_nvs_file) && | ||
314 | (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE || | ||
315 | wl->enable_11a)) { | ||
316 | wl1271_error("nvs size is not as expected: %zu != %zu", | ||
317 | wl->nvs_len, sizeof(struct wl1271_nvs_file)); | ||
318 | kfree(wl->nvs); | ||
319 | wl->nvs = NULL; | ||
320 | wl->nvs_len = 0; | ||
321 | return -EILSEQ; | ||
322 | } | ||
323 | |||
324 | /* only the first part of the NVS needs to be uploaded */ | ||
325 | nvs_len = sizeof(nvs->nvs); | ||
326 | nvs_ptr = (u8 *) nvs->nvs; | ||
327 | } | ||
328 | |||
329 | /* update current MAC address to NVS */ | ||
330 | nvs_ptr[11] = wl->mac_addr[0]; | ||
331 | nvs_ptr[10] = wl->mac_addr[1]; | ||
332 | nvs_ptr[6] = wl->mac_addr[2]; | ||
333 | nvs_ptr[5] = wl->mac_addr[3]; | ||
334 | nvs_ptr[4] = wl->mac_addr[4]; | ||
335 | nvs_ptr[3] = wl->mac_addr[5]; | ||
336 | |||
337 | /* | ||
338 | * Layout before the actual NVS tables: | ||
339 | * 1 byte : burst length. | ||
340 | * 2 bytes: destination address. | ||
341 | * n bytes: data to burst copy. | ||
342 | * | ||
343 | * This is ended by a 0 length, then the NVS tables. | ||
344 | */ | ||
345 | |||
346 | /* FIXME: Do we need to check here whether the LSB is 1? */ | ||
347 | while (nvs_ptr[0]) { | ||
348 | burst_len = nvs_ptr[0]; | ||
349 | dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8)); | ||
350 | |||
351 | /* | ||
352 | * Due to our new wl1271_translate_reg_addr function, | ||
353 | * we need to add the REGISTER_BASE to the destination | ||
354 | */ | ||
355 | dest_addr += REGISTERS_BASE; | ||
356 | |||
357 | /* We move our pointer to the data */ | ||
358 | nvs_ptr += 3; | ||
359 | |||
360 | for (i = 0; i < burst_len; i++) { | ||
361 | if (nvs_ptr + 3 >= (u8 *) wl->nvs + nvs_len) | ||
362 | goto out_badnvs; | ||
363 | |||
364 | val = (nvs_ptr[0] | (nvs_ptr[1] << 8) | ||
365 | | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24)); | ||
366 | |||
367 | wl1271_debug(DEBUG_BOOT, | ||
368 | "nvs burst write 0x%x: 0x%x", | ||
369 | dest_addr, val); | ||
370 | wl1271_write32(wl, dest_addr, val); | ||
371 | |||
372 | nvs_ptr += 4; | ||
373 | dest_addr += 4; | ||
374 | } | ||
375 | |||
376 | if (nvs_ptr >= (u8 *) wl->nvs + nvs_len) | ||
377 | goto out_badnvs; | ||
378 | } | ||
379 | |||
380 | /* | ||
381 | * We've reached the first zero length, the first NVS table | ||
382 | * is located at an aligned offset which is at least 7 bytes further. | ||
383 | * NOTE: The wl->nvs->nvs element must be first, in order to | ||
384 | * simplify the casting, we assume it is at the beginning of | ||
385 | * the wl->nvs structure. | ||
386 | */ | ||
387 | nvs_ptr = (u8 *)wl->nvs + | ||
388 | ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4); | ||
389 | |||
390 | if (nvs_ptr >= (u8 *) wl->nvs + nvs_len) | ||
391 | goto out_badnvs; | ||
392 | |||
393 | nvs_len -= nvs_ptr - (u8 *)wl->nvs; | ||
394 | |||
395 | /* Now we must set the partition correctly */ | ||
396 | wl1271_set_partition(wl, &part_table[PART_WORK]); | ||
397 | |||
398 | /* Copy the NVS tables to a new block to ensure alignment */ | ||
399 | nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL); | ||
400 | if (!nvs_aligned) | ||
401 | return -ENOMEM; | ||
402 | |||
403 | /* And finally we upload the NVS tables */ | ||
404 | wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false); | ||
405 | |||
406 | kfree(nvs_aligned); | ||
407 | return 0; | ||
408 | |||
409 | out_badnvs: | ||
410 | wl1271_error("nvs data is malformed"); | ||
411 | return -EILSEQ; | ||
412 | } | ||
413 | |||
414 | static void wl1271_boot_enable_interrupts(struct wl1271 *wl) | ||
415 | { | ||
416 | wl1271_enable_interrupts(wl); | ||
417 | wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, | ||
418 | WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); | ||
419 | wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL); | ||
420 | } | ||
421 | |||
422 | static int wl1271_boot_soft_reset(struct wl1271 *wl) | ||
423 | { | ||
424 | unsigned long timeout; | ||
425 | u32 boot_data; | ||
426 | |||
427 | /* perform soft reset */ | ||
428 | wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT); | ||
429 | |||
430 | /* SOFT_RESET is self clearing */ | ||
431 | timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME); | ||
432 | while (1) { | ||
433 | boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET); | ||
434 | wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data); | ||
435 | if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0) | ||
436 | break; | ||
437 | |||
438 | if (time_after(jiffies, timeout)) { | ||
439 | /* 1.2 check pWhalBus->uSelfClearTime if the | ||
440 | * timeout was reached */ | ||
441 | wl1271_error("soft reset timeout"); | ||
442 | return -1; | ||
443 | } | ||
444 | |||
445 | udelay(SOFT_RESET_STALL_TIME); | ||
446 | } | ||
447 | |||
448 | /* disable Rx/Tx */ | ||
449 | wl1271_write32(wl, ENABLE, 0x0); | ||
450 | |||
451 | /* disable auto calibration on start*/ | ||
452 | wl1271_write32(wl, SPARE_A2, 0xffff); | ||
453 | |||
454 | return 0; | ||
455 | } | ||
456 | |||
457 | static int wl1271_boot_run_firmware(struct wl1271 *wl) | ||
458 | { | ||
459 | int loop, ret; | ||
460 | u32 chip_id, intr; | ||
461 | |||
462 | wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT); | ||
463 | |||
464 | chip_id = wl1271_read32(wl, CHIP_ID_B); | ||
465 | |||
466 | wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id); | ||
467 | |||
468 | if (chip_id != wl->chip.id) { | ||
469 | wl1271_error("chip id doesn't match after firmware boot"); | ||
470 | return -EIO; | ||
471 | } | ||
472 | |||
473 | /* wait for init to complete */ | ||
474 | loop = 0; | ||
475 | while (loop++ < INIT_LOOP) { | ||
476 | udelay(INIT_LOOP_DELAY); | ||
477 | intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); | ||
478 | |||
479 | if (intr == 0xffffffff) { | ||
480 | wl1271_error("error reading hardware complete " | ||
481 | "init indication"); | ||
482 | return -EIO; | ||
483 | } | ||
484 | /* check that ACX_INTR_INIT_COMPLETE is enabled */ | ||
485 | else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) { | ||
486 | wl1271_write32(wl, ACX_REG_INTERRUPT_ACK, | ||
487 | WL1271_ACX_INTR_INIT_COMPLETE); | ||
488 | break; | ||
489 | } | ||
490 | } | ||
491 | |||
492 | if (loop > INIT_LOOP) { | ||
493 | wl1271_error("timeout waiting for the hardware to " | ||
494 | "complete initialization"); | ||
495 | return -EIO; | ||
496 | } | ||
497 | |||
498 | /* get hardware config command mail box */ | ||
499 | wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR); | ||
500 | |||
501 | /* get hardware config event mail box */ | ||
502 | wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR); | ||
503 | |||
504 | /* set the working partition to its "running" mode offset */ | ||
505 | wl1271_set_partition(wl, &part_table[PART_WORK]); | ||
506 | |||
507 | wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x", | ||
508 | wl->cmd_box_addr, wl->event_box_addr); | ||
509 | |||
510 | wl1271_boot_fw_version(wl); | ||
511 | |||
512 | /* | ||
513 | * in case of full asynchronous mode the firmware event must be | ||
514 | * ready to receive event from the command mailbox | ||
515 | */ | ||
516 | |||
517 | /* unmask required mbox events */ | ||
518 | wl->event_mask = BSS_LOSE_EVENT_ID | | ||
519 | SCAN_COMPLETE_EVENT_ID | | ||
520 | PS_REPORT_EVENT_ID | | ||
521 | JOIN_EVENT_COMPLETE_ID | | ||
522 | DISCONNECT_EVENT_COMPLETE_ID | | ||
523 | RSSI_SNR_TRIGGER_0_EVENT_ID | | ||
524 | PSPOLL_DELIVERY_FAILURE_EVENT_ID | | ||
525 | SOFT_GEMINI_SENSE_EVENT_ID | | ||
526 | PERIODIC_SCAN_REPORT_EVENT_ID | | ||
527 | PERIODIC_SCAN_COMPLETE_EVENT_ID; | ||
528 | |||
529 | if (wl->bss_type == BSS_TYPE_AP_BSS) | ||
530 | wl->event_mask |= STA_REMOVE_COMPLETE_EVENT_ID | | ||
531 | INACTIVE_STA_EVENT_ID | | ||
532 | MAX_TX_RETRY_EVENT_ID; | ||
533 | else | ||
534 | wl->event_mask |= DUMMY_PACKET_EVENT_ID | | ||
535 | BA_SESSION_RX_CONSTRAINT_EVENT_ID; | ||
536 | |||
537 | ret = wl1271_event_unmask(wl); | ||
538 | if (ret < 0) { | ||
539 | wl1271_error("EVENT mask setting failed"); | ||
540 | return ret; | ||
541 | } | ||
542 | |||
543 | wl1271_event_mbox_config(wl); | ||
544 | |||
545 | /* firmware startup completed */ | ||
546 | return 0; | ||
547 | } | ||
548 | |||
549 | static int wl1271_boot_write_irq_polarity(struct wl1271 *wl) | ||
550 | { | ||
551 | u32 polarity; | ||
552 | |||
553 | polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY); | ||
554 | |||
555 | /* We use HIGH polarity, so unset the LOW bit */ | ||
556 | polarity &= ~POLARITY_LOW; | ||
557 | wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity); | ||
558 | |||
559 | return 0; | ||
560 | } | ||
561 | |||
562 | static void wl1271_boot_hw_version(struct wl1271 *wl) | ||
563 | { | ||
564 | u32 fuse; | ||
565 | |||
566 | fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1); | ||
567 | fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET; | ||
568 | |||
569 | wl->hw_pg_ver = (s8)fuse; | ||
570 | |||
571 | if (((wl->hw_pg_ver & PG_MAJOR_VER_MASK) >> PG_MAJOR_VER_OFFSET) < 3) | ||
572 | wl->quirks |= WL12XX_QUIRK_END_OF_TRANSACTION; | ||
573 | } | ||
574 | |||
575 | static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl) | ||
576 | { | ||
577 | u16 spare_reg; | ||
578 | |||
579 | /* Mask bits [2] & [8:4] in the sys_clk_cfg register */ | ||
580 | spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG); | ||
581 | if (spare_reg == 0xFFFF) | ||
582 | return -EFAULT; | ||
583 | spare_reg |= (BIT(3) | BIT(5) | BIT(6)); | ||
584 | wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg); | ||
585 | |||
586 | /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */ | ||
587 | wl1271_top_reg_write(wl, SYS_CLK_CFG_REG, | ||
588 | WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF); | ||
589 | |||
590 | /* Delay execution for 15msec, to let the HW settle */ | ||
591 | mdelay(15); | ||
592 | |||
593 | return 0; | ||
594 | } | ||
595 | |||
596 | static bool wl128x_is_tcxo_valid(struct wl1271 *wl) | ||
597 | { | ||
598 | u16 tcxo_detection; | ||
599 | |||
600 | tcxo_detection = wl1271_top_reg_read(wl, TCXO_CLK_DETECT_REG); | ||
601 | if (tcxo_detection & TCXO_DET_FAILED) | ||
602 | return false; | ||
603 | |||
604 | return true; | ||
605 | } | ||
606 | |||
607 | static bool wl128x_is_fref_valid(struct wl1271 *wl) | ||
608 | { | ||
609 | u16 fref_detection; | ||
610 | |||
611 | fref_detection = wl1271_top_reg_read(wl, FREF_CLK_DETECT_REG); | ||
612 | if (fref_detection & FREF_CLK_DETECT_FAIL) | ||
613 | return false; | ||
614 | |||
615 | return true; | ||
616 | } | ||
617 | |||
618 | static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl) | ||
619 | { | ||
620 | wl1271_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL); | ||
621 | wl1271_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL); | ||
622 | wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, MCS_PLL_CONFIG_REG_VAL); | ||
623 | |||
624 | return 0; | ||
625 | } | ||
626 | |||
627 | static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk) | ||
628 | { | ||
629 | u16 spare_reg; | ||
630 | u16 pll_config; | ||
631 | u8 input_freq; | ||
632 | |||
633 | /* Mask bits [3:1] in the sys_clk_cfg register */ | ||
634 | spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG); | ||
635 | if (spare_reg == 0xFFFF) | ||
636 | return -EFAULT; | ||
637 | spare_reg |= BIT(2); | ||
638 | wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg); | ||
639 | |||
640 | /* Handle special cases of the TCXO clock */ | ||
641 | if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_8 || | ||
642 | wl->tcxo_clock == WL12XX_TCXOCLOCK_33_6) | ||
643 | return wl128x_manually_configure_mcs_pll(wl); | ||
644 | |||
645 | /* Set the input frequency according to the selected clock source */ | ||
646 | input_freq = (clk & 1) + 1; | ||
647 | |||
648 | pll_config = wl1271_top_reg_read(wl, MCS_PLL_CONFIG_REG); | ||
649 | if (pll_config == 0xFFFF) | ||
650 | return -EFAULT; | ||
651 | pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT); | ||
652 | pll_config |= MCS_PLL_ENABLE_HP; | ||
653 | wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config); | ||
654 | |||
655 | return 0; | ||
656 | } | ||
657 | |||
658 | /* | ||
659 | * WL128x has two clocks input - TCXO and FREF. | ||
660 | * TCXO is the main clock of the device, while FREF is used to sync | ||
661 | * between the GPS and the cellular modem. | ||
662 | * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used | ||
663 | * as the WLAN/BT main clock. | ||
664 | */ | ||
665 | static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock) | ||
666 | { | ||
667 | u16 sys_clk_cfg; | ||
668 | |||
669 | /* For XTAL-only modes, FREF will be used after switching from TCXO */ | ||
670 | if (wl->ref_clock == WL12XX_REFCLOCK_26_XTAL || | ||
671 | wl->ref_clock == WL12XX_REFCLOCK_38_XTAL) { | ||
672 | if (!wl128x_switch_tcxo_to_fref(wl)) | ||
673 | return -EINVAL; | ||
674 | goto fref_clk; | ||
675 | } | ||
676 | |||
677 | /* Query the HW, to determine which clock source we should use */ | ||
678 | sys_clk_cfg = wl1271_top_reg_read(wl, SYS_CLK_CFG_REG); | ||
679 | if (sys_clk_cfg == 0xFFFF) | ||
680 | return -EINVAL; | ||
681 | if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF) | ||
682 | goto fref_clk; | ||
683 | |||
684 | /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */ | ||
685 | if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_368 || | ||
686 | wl->tcxo_clock == WL12XX_TCXOCLOCK_32_736) { | ||
687 | if (!wl128x_switch_tcxo_to_fref(wl)) | ||
688 | return -EINVAL; | ||
689 | goto fref_clk; | ||
690 | } | ||
691 | |||
692 | /* TCXO clock is selected */ | ||
693 | if (!wl128x_is_tcxo_valid(wl)) | ||
694 | return -EINVAL; | ||
695 | *selected_clock = wl->tcxo_clock; | ||
696 | goto config_mcs_pll; | ||
697 | |||
698 | fref_clk: | ||
699 | /* FREF clock is selected */ | ||
700 | if (!wl128x_is_fref_valid(wl)) | ||
701 | return -EINVAL; | ||
702 | *selected_clock = wl->ref_clock; | ||
703 | |||
704 | config_mcs_pll: | ||
705 | return wl128x_configure_mcs_pll(wl, *selected_clock); | ||
706 | } | ||
707 | |||
708 | static int wl127x_boot_clk(struct wl1271 *wl) | ||
709 | { | ||
710 | u32 pause; | ||
711 | u32 clk; | ||
712 | |||
713 | wl1271_boot_hw_version(wl); | ||
714 | |||
715 | if (wl->ref_clock == CONF_REF_CLK_19_2_E || | ||
716 | wl->ref_clock == CONF_REF_CLK_38_4_E || | ||
717 | wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL) | ||
718 | /* ref clk: 19.2/38.4/38.4-XTAL */ | ||
719 | clk = 0x3; | ||
720 | else if (wl->ref_clock == CONF_REF_CLK_26_E || | ||
721 | wl->ref_clock == CONF_REF_CLK_52_E) | ||
722 | /* ref clk: 26/52 */ | ||
723 | clk = 0x5; | ||
724 | else | ||
725 | return -EINVAL; | ||
726 | |||
727 | if (wl->ref_clock != CONF_REF_CLK_19_2_E) { | ||
728 | u16 val; | ||
729 | /* Set clock type (open drain) */ | ||
730 | val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE); | ||
731 | val &= FREF_CLK_TYPE_BITS; | ||
732 | wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val); | ||
733 | |||
734 | /* Set clock pull mode (no pull) */ | ||
735 | val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL); | ||
736 | val |= NO_PULL; | ||
737 | wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val); | ||
738 | } else { | ||
739 | u16 val; | ||
740 | /* Set clock polarity */ | ||
741 | val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY); | ||
742 | val &= FREF_CLK_POLARITY_BITS; | ||
743 | val |= CLK_REQ_OUTN_SEL; | ||
744 | wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val); | ||
745 | } | ||
746 | |||
747 | wl1271_write32(wl, PLL_PARAMETERS, clk); | ||
748 | |||
749 | pause = wl1271_read32(wl, PLL_PARAMETERS); | ||
750 | |||
751 | wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause); | ||
752 | |||
753 | pause &= ~(WU_COUNTER_PAUSE_VAL); | ||
754 | pause |= WU_COUNTER_PAUSE_VAL; | ||
755 | wl1271_write32(wl, WU_COUNTER_PAUSE, pause); | ||
756 | |||
757 | return 0; | ||
758 | } | ||
759 | |||
760 | /* uploads NVS and firmware */ | ||
761 | int wl1271_load_firmware(struct wl1271 *wl) | ||
762 | { | ||
763 | int ret = 0; | ||
764 | u32 tmp, clk; | ||
765 | int selected_clock = -1; | ||
766 | |||
767 | if (wl->chip.id == CHIP_ID_1283_PG20) { | ||
768 | ret = wl128x_boot_clk(wl, &selected_clock); | ||
769 | if (ret < 0) | ||
770 | goto out; | ||
771 | } else { | ||
772 | ret = wl127x_boot_clk(wl); | ||
773 | if (ret < 0) | ||
774 | goto out; | ||
775 | } | ||
776 | |||
777 | /* Continue the ELP wake up sequence */ | ||
778 | wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); | ||
779 | udelay(500); | ||
780 | |||
781 | wl1271_set_partition(wl, &part_table[PART_DRPW]); | ||
782 | |||
783 | /* Read-modify-write DRPW_SCRATCH_START register (see next state) | ||
784 | to be used by DRPw FW. The RTRIM value will be added by the FW | ||
785 | before taking DRPw out of reset */ | ||
786 | |||
787 | wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START); | ||
788 | clk = wl1271_read32(wl, DRPW_SCRATCH_START); | ||
789 | |||
790 | wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk); | ||
791 | |||
792 | if (wl->chip.id == CHIP_ID_1283_PG20) { | ||
793 | clk |= ((selected_clock & 0x3) << 1) << 4; | ||
794 | } else { | ||
795 | clk |= (wl->ref_clock << 1) << 4; | ||
796 | } | ||
797 | |||
798 | if (wl->quirks & WL12XX_QUIRK_LPD_MODE) | ||
799 | clk |= SCRATCH_ENABLE_LPD; | ||
800 | |||
801 | wl1271_write32(wl, DRPW_SCRATCH_START, clk); | ||
802 | |||
803 | wl1271_set_partition(wl, &part_table[PART_WORK]); | ||
804 | |||
805 | /* Disable interrupts */ | ||
806 | wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); | ||
807 | |||
808 | ret = wl1271_boot_soft_reset(wl); | ||
809 | if (ret < 0) | ||
810 | goto out; | ||
811 | |||
812 | /* 2. start processing NVS file */ | ||
813 | ret = wl1271_boot_upload_nvs(wl); | ||
814 | if (ret < 0) | ||
815 | goto out; | ||
816 | |||
817 | /* write firmware's last address (ie. it's length) to | ||
818 | * ACX_EEPROMLESS_IND_REG */ | ||
819 | wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG"); | ||
820 | |||
821 | wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG); | ||
822 | |||
823 | tmp = wl1271_read32(wl, CHIP_ID_B); | ||
824 | |||
825 | wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); | ||
826 | |||
827 | /* 6. read the EEPROM parameters */ | ||
828 | tmp = wl1271_read32(wl, SCR_PAD2); | ||
829 | |||
830 | /* WL1271: The reference driver skips steps 7 to 10 (jumps directly | ||
831 | * to upload_fw) */ | ||
832 | |||
833 | if (wl->chip.id == CHIP_ID_1283_PG20) | ||
834 | wl1271_top_reg_write(wl, SDIO_IO_DS, wl->conf.hci_io_ds); | ||
835 | |||
836 | ret = wl1271_boot_upload_firmware(wl); | ||
837 | if (ret < 0) | ||
838 | goto out; | ||
839 | |||
840 | out: | ||
841 | return ret; | ||
842 | } | ||
843 | EXPORT_SYMBOL_GPL(wl1271_load_firmware); | ||
844 | |||
845 | int wl1271_boot(struct wl1271 *wl) | ||
846 | { | ||
847 | int ret; | ||
848 | |||
849 | /* upload NVS and firmware */ | ||
850 | ret = wl1271_load_firmware(wl); | ||
851 | if (ret) | ||
852 | return ret; | ||
853 | |||
854 | /* 10.5 start firmware */ | ||
855 | ret = wl1271_boot_run_firmware(wl); | ||
856 | if (ret < 0) | ||
857 | goto out; | ||
858 | |||
859 | ret = wl1271_boot_write_irq_polarity(wl); | ||
860 | if (ret < 0) | ||
861 | goto out; | ||
862 | |||
863 | wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, | ||
864 | WL1271_ACX_ALL_EVENTS_VECTOR); | ||
865 | |||
866 | /* Enable firmware interrupts now */ | ||
867 | wl1271_boot_enable_interrupts(wl); | ||
868 | |||
869 | /* set the wl1271 default filters */ | ||
870 | wl1271_set_default_filters(wl); | ||
871 | |||
872 | wl1271_event_mbox_config(wl); | ||
873 | |||
874 | out: | ||
875 | return ret; | ||
876 | } | ||