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authorChaoming Li <chaoming_li@realsil.com.cn>2011-06-10 16:11:40 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-06-27 15:09:38 -0400
commit674f0523ec07a7c716f5ed8a2debe6632be750f8 (patch)
tree44b7072a8b58a68555b96477d7660eb567facb11 /drivers/net/wireless/rtlwifi
parente501016884dc2112b3742045834302c8adfe3944 (diff)
rtlwifi: rtl8192de: Merge TX and RX routines
Merge routines trx.c and trx.h for RTL8192DE. Signed-off-by: Chaoming_Li <chaoming_li@realsil.com.cn> Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/trx.c959
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/trx.h756
2 files changed, 1715 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
new file mode 100644
index 00000000000..bf1462f69b5
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
@@ -0,0 +1,959 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../base.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "trx.h"
37#include "led.h"
38
39static u8 _rtl92de_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
40{
41 __le16 fc = rtl_get_fc(skb);
42
43 if (unlikely(ieee80211_is_beacon(fc)))
44 return QSLT_BEACON;
45 if (ieee80211_is_mgmt(fc))
46 return QSLT_MGNT;
47
48 return skb->priority;
49}
50
51static int _rtl92de_rate_mapping(bool isht, u8 desc_rate)
52{
53 int rate_idx;
54
55 if (false == isht) {
56 switch (desc_rate) {
57 case DESC92D_RATE1M:
58 rate_idx = 0;
59 break;
60 case DESC92D_RATE2M:
61 rate_idx = 1;
62 break;
63 case DESC92D_RATE5_5M:
64 rate_idx = 2;
65 break;
66 case DESC92D_RATE11M:
67 rate_idx = 3;
68 break;
69 case DESC92D_RATE6M:
70 rate_idx = 4;
71 break;
72 case DESC92D_RATE9M:
73 rate_idx = 5;
74 break;
75 case DESC92D_RATE12M:
76 rate_idx = 6;
77 break;
78 case DESC92D_RATE18M:
79 rate_idx = 7;
80 break;
81 case DESC92D_RATE24M:
82 rate_idx = 8;
83 break;
84 case DESC92D_RATE36M:
85 rate_idx = 9;
86 break;
87 case DESC92D_RATE48M:
88 rate_idx = 10;
89 break;
90 case DESC92D_RATE54M:
91 rate_idx = 11;
92 break;
93 default:
94 rate_idx = 0;
95 break;
96 }
97 return rate_idx;
98 } else {
99 switch (desc_rate) {
100 case DESC92D_RATE1M:
101 rate_idx = 0;
102 break;
103 case DESC92D_RATE2M:
104 rate_idx = 1;
105 break;
106 case DESC92D_RATE5_5M:
107 rate_idx = 2;
108 break;
109 case DESC92D_RATE11M:
110 rate_idx = 3;
111 break;
112 case DESC92D_RATE6M:
113 rate_idx = 4;
114 break;
115 case DESC92D_RATE9M:
116 rate_idx = 5;
117 break;
118 case DESC92D_RATE12M:
119 rate_idx = 6;
120 break;
121 case DESC92D_RATE18M:
122 rate_idx = 7;
123 break;
124 case DESC92D_RATE24M:
125 rate_idx = 8;
126 break;
127 case DESC92D_RATE36M:
128 rate_idx = 9;
129 break;
130 case DESC92D_RATE48M:
131 rate_idx = 10;
132 break;
133 case DESC92D_RATE54M:
134 rate_idx = 11;
135 break;
136 default:
137 rate_idx = 11;
138 break;
139 }
140 return rate_idx;
141 }
142}
143
144static u8 _rtl92d_query_rxpwrpercentage(char antpower)
145{
146 if ((antpower <= -100) || (antpower >= 20))
147 return 0;
148 else if (antpower >= 0)
149 return 100;
150 else
151 return 100 + antpower;
152}
153
154static u8 _rtl92d_evm_db_to_percentage(char value)
155{
156 char ret_val = value;
157
158 if (ret_val >= 0)
159 ret_val = 0;
160 if (ret_val <= -33)
161 ret_val = -33;
162 ret_val = 0 - ret_val;
163 ret_val *= 3;
164 if (ret_val == 99)
165 ret_val = 100;
166 return ret_val;
167}
168
169static long _rtl92de_translate_todbm(struct ieee80211_hw *hw,
170 u8 signal_strength_index)
171{
172 long signal_power;
173
174 signal_power = (long)((signal_strength_index + 1) >> 1);
175 signal_power -= 95;
176 return signal_power;
177}
178
179static long _rtl92de_signal_scale_mapping(struct ieee80211_hw *hw, long currsig)
180{
181 long retsig;
182
183 if (currsig >= 61 && currsig <= 100)
184 retsig = 90 + ((currsig - 60) / 4);
185 else if (currsig >= 41 && currsig <= 60)
186 retsig = 78 + ((currsig - 40) / 2);
187 else if (currsig >= 31 && currsig <= 40)
188 retsig = 66 + (currsig - 30);
189 else if (currsig >= 21 && currsig <= 30)
190 retsig = 54 + (currsig - 20);
191 else if (currsig >= 5 && currsig <= 20)
192 retsig = 42 + (((currsig - 5) * 2) / 3);
193 else if (currsig == 4)
194 retsig = 36;
195 else if (currsig == 3)
196 retsig = 27;
197 else if (currsig == 2)
198 retsig = 18;
199 else if (currsig == 1)
200 retsig = 9;
201 else
202 retsig = currsig;
203 return retsig;
204}
205
206static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw,
207 struct rtl_stats *pstats,
208 struct rx_desc_92d *pdesc,
209 struct rx_fwinfo_92d *p_drvinfo,
210 bool packet_match_bssid,
211 bool packet_toself,
212 bool packet_beacon)
213{
214 struct rtl_priv *rtlpriv = rtl_priv(hw);
215 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
216 struct phy_sts_cck_8192d *cck_buf;
217 s8 rx_pwr_all, rx_pwr[4];
218 u8 rf_rx_num = 0, evm, pwdb_all;
219 u8 i, max_spatial_stream;
220 u32 rssi, total_rssi = 0;
221 bool is_cck_rate;
222
223 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
224 pstats->packet_matchbssid = packet_match_bssid;
225 pstats->packet_toself = packet_toself;
226 pstats->packet_beacon = packet_beacon;
227 pstats->is_cck = is_cck_rate;
228 pstats->rx_mimo_signalquality[0] = -1;
229 pstats->rx_mimo_signalquality[1] = -1;
230
231 if (is_cck_rate) {
232 u8 report, cck_highpwr;
233 cck_buf = (struct phy_sts_cck_8192d *)p_drvinfo;
234 if (ppsc->rfpwr_state == ERFON)
235 cck_highpwr = (u8) rtl_get_bbreg(hw,
236 RFPGA0_XA_HSSIPARAMETER2,
237 BIT(9));
238 else
239 cck_highpwr = false;
240 if (!cck_highpwr) {
241 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
242 report = cck_buf->cck_agc_rpt & 0xc0;
243 report = report >> 6;
244 switch (report) {
245 case 0x3:
246 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
247 break;
248 case 0x2:
249 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
250 break;
251 case 0x1:
252 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
253 break;
254 case 0x0:
255 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
256 break;
257 }
258 } else {
259 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
260 report = p_drvinfo->cfosho[0] & 0x60;
261 report = report >> 5;
262 switch (report) {
263 case 0x3:
264 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
265 break;
266 case 0x2:
267 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
268 break;
269 case 0x1:
270 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
271 break;
272 case 0x0:
273 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
274 break;
275 }
276 }
277 pwdb_all = _rtl92d_query_rxpwrpercentage(rx_pwr_all);
278 /* CCK gain is smaller than OFDM/MCS gain, */
279 /* so we add gain diff by experiences, the val is 6 */
280 pwdb_all += 6;
281 if (pwdb_all > 100)
282 pwdb_all = 100;
283 /* modify the offset to make the same gain index with OFDM. */
284 if (pwdb_all > 34 && pwdb_all <= 42)
285 pwdb_all -= 2;
286 else if (pwdb_all > 26 && pwdb_all <= 34)
287 pwdb_all -= 6;
288 else if (pwdb_all > 14 && pwdb_all <= 26)
289 pwdb_all -= 8;
290 else if (pwdb_all > 4 && pwdb_all <= 14)
291 pwdb_all -= 4;
292 pstats->rx_pwdb_all = pwdb_all;
293 pstats->recvsignalpower = rx_pwr_all;
294 if (packet_match_bssid) {
295 u8 sq;
296 if (pstats->rx_pwdb_all > 40) {
297 sq = 100;
298 } else {
299 sq = cck_buf->sq_rpt;
300 if (sq > 64)
301 sq = 0;
302 else if (sq < 20)
303 sq = 100;
304 else
305 sq = ((64 - sq) * 100) / 44;
306 }
307 pstats->signalquality = sq;
308 pstats->rx_mimo_signalquality[0] = sq;
309 pstats->rx_mimo_signalquality[1] = -1;
310 }
311 } else {
312 rtlpriv->dm.rfpath_rxenable[0] = true;
313 rtlpriv->dm.rfpath_rxenable[1] = true;
314 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
315 if (rtlpriv->dm.rfpath_rxenable[i])
316 rf_rx_num++;
317 rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f) * 2)
318 - 110;
319 rssi = _rtl92d_query_rxpwrpercentage(rx_pwr[i]);
320 total_rssi += rssi;
321 rtlpriv->stats.rx_snr_db[i] =
322 (long)(p_drvinfo->rxsnr[i] / 2);
323 if (packet_match_bssid)
324 pstats->rx_mimo_signalstrength[i] = (u8) rssi;
325 }
326 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 106;
327 pwdb_all = _rtl92d_query_rxpwrpercentage(rx_pwr_all);
328 pstats->rx_pwdb_all = pwdb_all;
329 pstats->rxpower = rx_pwr_all;
330 pstats->recvsignalpower = rx_pwr_all;
331 if (pdesc->rxht && pdesc->rxmcs >= DESC92D_RATEMCS8 &&
332 pdesc->rxmcs <= DESC92D_RATEMCS15)
333 max_spatial_stream = 2;
334 else
335 max_spatial_stream = 1;
336 for (i = 0; i < max_spatial_stream; i++) {
337 evm = _rtl92d_evm_db_to_percentage(p_drvinfo->rxevm[i]);
338 if (packet_match_bssid) {
339 if (i == 0)
340 pstats->signalquality =
341 (u8)(evm & 0xff);
342 pstats->rx_mimo_signalquality[i] =
343 (u8)(evm & 0xff);
344 }
345 }
346 }
347 if (is_cck_rate)
348 pstats->signalstrength = (u8)(_rtl92de_signal_scale_mapping(hw,
349 pwdb_all));
350 else if (rf_rx_num != 0)
351 pstats->signalstrength = (u8)(_rtl92de_signal_scale_mapping(hw,
352 total_rssi /= rf_rx_num));
353}
354
355static void rtl92d_loop_over_paths(struct ieee80211_hw *hw,
356 struct rtl_stats *pstats)
357{
358 struct rtl_priv *rtlpriv = rtl_priv(hw);
359 struct rtl_phy *rtlphy = &(rtlpriv->phy);
360 u8 rfpath;
361
362 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
363 rfpath++) {
364 if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
365 rtlpriv->stats.rx_rssi_percentage[rfpath] =
366 pstats->rx_mimo_signalstrength[rfpath];
367
368 }
369 if (pstats->rx_mimo_signalstrength[rfpath] >
370 rtlpriv->stats.rx_rssi_percentage[rfpath]) {
371 rtlpriv->stats.rx_rssi_percentage[rfpath] =
372 ((rtlpriv->stats.rx_rssi_percentage[rfpath] *
373 (RX_SMOOTH_FACTOR - 1)) +
374 (pstats->rx_mimo_signalstrength[rfpath])) /
375 (RX_SMOOTH_FACTOR);
376 rtlpriv->stats.rx_rssi_percentage[rfpath] =
377 rtlpriv->stats.rx_rssi_percentage[rfpath] + 1;
378 } else {
379 rtlpriv->stats.rx_rssi_percentage[rfpath] =
380 ((rtlpriv->stats.rx_rssi_percentage[rfpath] *
381 (RX_SMOOTH_FACTOR - 1)) +
382 (pstats->rx_mimo_signalstrength[rfpath])) /
383 (RX_SMOOTH_FACTOR);
384 }
385 }
386}
387
388static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw,
389 struct rtl_stats *pstats)
390{
391 struct rtl_priv *rtlpriv = rtl_priv(hw);
392 u32 last_rssi, tmpval;
393
394 if (pstats->packet_toself || pstats->packet_beacon) {
395 rtlpriv->stats.rssi_calculate_cnt++;
396 if (rtlpriv->stats.ui_rssi.total_num++ >=
397 PHY_RSSI_SLID_WIN_MAX) {
398 rtlpriv->stats.ui_rssi.total_num =
399 PHY_RSSI_SLID_WIN_MAX;
400 last_rssi = rtlpriv->stats.ui_rssi.elements[
401 rtlpriv->stats.ui_rssi.index];
402 rtlpriv->stats.ui_rssi.total_val -= last_rssi;
403 }
404 rtlpriv->stats.ui_rssi.total_val += pstats->signalstrength;
405 rtlpriv->stats.ui_rssi.elements
406 [rtlpriv->stats.ui_rssi.index++] =
407 pstats->signalstrength;
408 if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
409 rtlpriv->stats.ui_rssi.index = 0;
410 tmpval = rtlpriv->stats.ui_rssi.total_val /
411 rtlpriv->stats.ui_rssi.total_num;
412 rtlpriv->stats.signal_strength = _rtl92de_translate_todbm(hw,
413 (u8) tmpval);
414 pstats->rssi = rtlpriv->stats.signal_strength;
415 }
416 if (!pstats->is_cck && pstats->packet_toself)
417 rtl92d_loop_over_paths(hw, pstats);
418}
419
420static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw,
421 struct rtl_stats *pstats)
422{
423 struct rtl_priv *rtlpriv = rtl_priv(hw);
424 int weighting = 0;
425
426 if (rtlpriv->stats.recv_signal_power == 0)
427 rtlpriv->stats.recv_signal_power = pstats->recvsignalpower;
428 if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power)
429 weighting = 5;
430 else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power)
431 weighting = (-5);
432 rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power *
433 5 + pstats->recvsignalpower + weighting) / 6;
434}
435
436static void _rtl92de_process_pwdb(struct ieee80211_hw *hw,
437 struct rtl_stats *pstats)
438{
439 struct rtl_priv *rtlpriv = rtl_priv(hw);
440 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
441 long undecorated_smoothed_pwdb;
442
443 if (mac->opmode == NL80211_IFTYPE_ADHOC ||
444 mac->opmode == NL80211_IFTYPE_AP)
445 return;
446 else
447 undecorated_smoothed_pwdb =
448 rtlpriv->dm.undecorated_smoothed_pwdb;
449
450 if (pstats->packet_toself || pstats->packet_beacon) {
451 if (undecorated_smoothed_pwdb < 0)
452 undecorated_smoothed_pwdb = pstats->rx_pwdb_all;
453 if (pstats->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
454 undecorated_smoothed_pwdb =
455 (((undecorated_smoothed_pwdb) *
456 (RX_SMOOTH_FACTOR - 1)) +
457 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
458 undecorated_smoothed_pwdb =
459 undecorated_smoothed_pwdb + 1;
460 } else {
461 undecorated_smoothed_pwdb =
462 (((undecorated_smoothed_pwdb) *
463 (RX_SMOOTH_FACTOR - 1)) +
464 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
465 }
466 rtlpriv->dm.undecorated_smoothed_pwdb =
467 undecorated_smoothed_pwdb;
468 _rtl92de_update_rxsignalstatistics(hw, pstats);
469 }
470}
471
472static void rtl92d_loop_over_streams(struct ieee80211_hw *hw,
473 struct rtl_stats *pstats)
474{
475 struct rtl_priv *rtlpriv = rtl_priv(hw);
476 int stream;
477
478 for (stream = 0; stream < 2; stream++) {
479 if (pstats->rx_mimo_signalquality[stream] != -1) {
480 if (rtlpriv->stats.rx_evm_percentage[stream] == 0) {
481 rtlpriv->stats.rx_evm_percentage[stream] =
482 pstats->rx_mimo_signalquality[stream];
483 }
484 rtlpriv->stats.rx_evm_percentage[stream] =
485 ((rtlpriv->stats.rx_evm_percentage[stream]
486 * (RX_SMOOTH_FACTOR - 1)) +
487 (pstats->rx_mimo_signalquality[stream] * 1)) /
488 (RX_SMOOTH_FACTOR);
489 }
490 }
491}
492
493static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw,
494 struct rtl_stats *pstats)
495{
496 struct rtl_priv *rtlpriv = rtl_priv(hw);
497 u32 last_evm, tmpval;
498
499 if (pstats->signalquality == 0)
500 return;
501 if (pstats->packet_toself || pstats->packet_beacon) {
502 if (rtlpriv->stats.ui_link_quality.total_num++ >=
503 PHY_LINKQUALITY_SLID_WIN_MAX) {
504 rtlpriv->stats.ui_link_quality.total_num =
505 PHY_LINKQUALITY_SLID_WIN_MAX;
506 last_evm = rtlpriv->stats.ui_link_quality.elements[
507 rtlpriv->stats.ui_link_quality.index];
508 rtlpriv->stats.ui_link_quality.total_val -= last_evm;
509 }
510 rtlpriv->stats.ui_link_quality.total_val +=
511 pstats->signalquality;
512 rtlpriv->stats.ui_link_quality.elements[
513 rtlpriv->stats.ui_link_quality.index++] =
514 pstats->signalquality;
515 if (rtlpriv->stats.ui_link_quality.index >=
516 PHY_LINKQUALITY_SLID_WIN_MAX)
517 rtlpriv->stats.ui_link_quality.index = 0;
518 tmpval = rtlpriv->stats.ui_link_quality.total_val /
519 rtlpriv->stats.ui_link_quality.total_num;
520 rtlpriv->stats.signal_quality = tmpval;
521 rtlpriv->stats.last_sigstrength_inpercent = tmpval;
522 rtl92d_loop_over_streams(hw, pstats);
523 }
524}
525
526static void _rtl92de_process_phyinfo(struct ieee80211_hw *hw,
527 u8 *buffer,
528 struct rtl_stats *pcurrent_stats)
529{
530
531 if (!pcurrent_stats->packet_matchbssid &&
532 !pcurrent_stats->packet_beacon)
533 return;
534
535 _rtl92de_process_ui_rssi(hw, pcurrent_stats);
536 _rtl92de_process_pwdb(hw, pcurrent_stats);
537 _rtl92de_process_ui_link_quality(hw, pcurrent_stats);
538}
539
540static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw,
541 struct sk_buff *skb,
542 struct rtl_stats *pstats,
543 struct rx_desc_92d *pdesc,
544 struct rx_fwinfo_92d *p_drvinfo)
545{
546 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
547 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
548 struct ieee80211_hdr *hdr;
549 u8 *tmp_buf;
550 u8 *praddr;
551 u16 type, cfc;
552 __le16 fc;
553 bool packet_matchbssid, packet_toself, packet_beacon;
554
555 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
556 hdr = (struct ieee80211_hdr *)tmp_buf;
557 fc = hdr->frame_control;
558 cfc = le16_to_cpu(fc);
559 type = WLAN_FC_GET_TYPE(fc);
560 praddr = hdr->addr1;
561 packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) &&
562 (!compare_ether_addr(mac->bssid, (cfc & IEEE80211_FCTL_TODS) ?
563 hdr->addr1 : (cfc & IEEE80211_FCTL_FROMDS) ?
564 hdr->addr2 : hdr->addr3)) && (!pstats->hwerror) &&
565 (!pstats->crc) && (!pstats->icv));
566 packet_toself = packet_matchbssid &&
567 (!compare_ether_addr(praddr, rtlefuse->dev_addr));
568 if (ieee80211_is_beacon(fc))
569 packet_beacon = true;
570 _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
571 packet_matchbssid, packet_toself,
572 packet_beacon);
573 _rtl92de_process_phyinfo(hw, tmp_buf, pstats);
574}
575
576bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats,
577 struct ieee80211_rx_status *rx_status,
578 u8 *p_desc, struct sk_buff *skb)
579{
580 struct rx_fwinfo_92d *p_drvinfo;
581 struct rx_desc_92d *pdesc = (struct rx_desc_92d *)p_desc;
582 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
583
584 stats->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
585 stats->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
586 RX_DRV_INFO_SIZE_UNIT;
587 stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
588 stats->icv = (u16) GET_RX_DESC_ICV(pdesc);
589 stats->crc = (u16) GET_RX_DESC_CRC32(pdesc);
590 stats->hwerror = (stats->crc | stats->icv);
591 stats->decrypted = !GET_RX_DESC_SWDEC(pdesc);
592 stats->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
593 stats->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
594 stats->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
595 stats->isfirst_ampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
596 && (GET_RX_DESC_FAGGR(pdesc) == 1));
597 stats->timestamp_low = GET_RX_DESC_TSFL(pdesc);
598 stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
599 rx_status->freq = hw->conf.channel->center_freq;
600 rx_status->band = hw->conf.channel->band;
601 if (GET_RX_DESC_CRC32(pdesc))
602 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
603 if (!GET_RX_DESC_SWDEC(pdesc))
604 rx_status->flag |= RX_FLAG_DECRYPTED;
605 if (GET_RX_DESC_BW(pdesc))
606 rx_status->flag |= RX_FLAG_40MHZ;
607 if (GET_RX_DESC_RXHT(pdesc))
608 rx_status->flag |= RX_FLAG_HT;
609 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
610 if (stats->decrypted)
611 rx_status->flag |= RX_FLAG_DECRYPTED;
612 rx_status->rate_idx = _rtl92de_rate_mapping((bool)
613 GET_RX_DESC_RXHT(pdesc),
614 (u8)
615 GET_RX_DESC_RXMCS(pdesc));
616 rx_status->mactime = GET_RX_DESC_TSFL(pdesc);
617 if (phystatus == true) {
618 p_drvinfo = (struct rx_fwinfo_92d *)(skb->data +
619 stats->rx_bufshift);
620 _rtl92de_translate_rx_signal_stuff(hw,
621 skb, stats, pdesc,
622 p_drvinfo);
623 }
624 /*rx_status->qual = stats->signal; */
625 rx_status->signal = stats->rssi + 10;
626 /*rx_status->noise = -stats->noise; */
627 return true;
628}
629
630static void _rtl92de_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
631 u8 *virtualaddress)
632{
633 memset(virtualaddress, 0, 8);
634
635 SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
636 SET_EARLYMODE_LEN0(virtualaddress, ptcb_desc->empkt_len[0]);
637 SET_EARLYMODE_LEN1(virtualaddress, ptcb_desc->empkt_len[1]);
638 SET_EARLYMODE_LEN2_1(virtualaddress, ptcb_desc->empkt_len[2] & 0xF);
639 SET_EARLYMODE_LEN2_2(virtualaddress, ptcb_desc->empkt_len[2] >> 4);
640 SET_EARLYMODE_LEN3(virtualaddress, ptcb_desc->empkt_len[3]);
641 SET_EARLYMODE_LEN4(virtualaddress, ptcb_desc->empkt_len[4]);
642}
643
644void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
645 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
646 struct ieee80211_tx_info *info, struct sk_buff *skb,
647 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
648{
649 struct rtl_priv *rtlpriv = rtl_priv(hw);
650 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
651 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
652 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
653 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
654 struct ieee80211_sta *sta = info->control.sta;
655 u8 *pdesc = (u8 *) pdesc_tx;
656 u16 seq_number;
657 __le16 fc = hdr->frame_control;
658 unsigned int buf_len = 0;
659 unsigned int skb_len = skb->len;
660 u8 fw_qsel = _rtl92de_map_hwqueue_to_fwqueue(skb, hw_queue);
661 bool firstseg = ((hdr->seq_ctrl &
662 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
663 bool lastseg = ((hdr->frame_control &
664 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
665 dma_addr_t mapping;
666 u8 bw_40 = 0;
667
668 if (mac->opmode == NL80211_IFTYPE_STATION) {
669 bw_40 = mac->bw_40;
670 } else if (mac->opmode == NL80211_IFTYPE_AP ||
671 mac->opmode == NL80211_IFTYPE_ADHOC) {
672 if (sta)
673 bw_40 = sta->ht_cap.cap &
674 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
675 }
676 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
677 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
678 /* reserve 8 byte for AMPDU early mode */
679 if (rtlhal->earlymode_enable) {
680 skb_push(skb, EM_HDR_LEN);
681 memset(skb->data, 0, EM_HDR_LEN);
682 }
683 buf_len = skb->len;
684 mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
685 PCI_DMA_TODEVICE);
686 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_92d));
687 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
688 firstseg = true;
689 lastseg = true;
690 }
691 if (firstseg) {
692 if (rtlhal->earlymode_enable) {
693 SET_TX_DESC_PKT_OFFSET(pdesc, 1);
694 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN +
695 EM_HDR_LEN);
696 if (ptcb_desc->empkt_num) {
697 RT_TRACE(rtlpriv, COMP_SEND, DBG_LOUD,
698 ("Insert 8 byte.pTcb->EMPktNum:%d\n",
699 ptcb_desc->empkt_num));
700 _rtl92de_insert_emcontent(ptcb_desc,
701 (u8 *)(skb->data));
702 }
703 } else {
704 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
705 }
706 /* 5G have no CCK rate */
707 if (rtlhal->current_bandtype == BAND_ON_5G)
708 if (ptcb_desc->hw_rate < DESC92D_RATE6M)
709 ptcb_desc->hw_rate = DESC92D_RATE6M;
710 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
711 if (ptcb_desc->use_shortgi || ptcb_desc->use_shortpreamble)
712 SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
713
714 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
715 ptcb_desc->hw_rate == DESC92D_RATEMCS7)
716 SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
717
718 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
719 SET_TX_DESC_AGG_ENABLE(pdesc, 1);
720 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
721 }
722 SET_TX_DESC_SEQ(pdesc, seq_number);
723 SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable &&
724 !ptcb_desc->cts_enable) ? 1 : 0));
725 SET_TX_DESC_HW_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable
726 || ptcb_desc->cts_enable) ? 1 : 0));
727 SET_TX_DESC_CTS2SELF(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0));
728 SET_TX_DESC_RTS_STBC(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0));
729 /* 5G have no CCK rate */
730 if (rtlhal->current_bandtype == BAND_ON_5G)
731 if (ptcb_desc->rts_rate < DESC92D_RATE6M)
732 ptcb_desc->rts_rate = DESC92D_RATE6M;
733 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
734 SET_TX_DESC_RTS_BW(pdesc, 0);
735 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
736 SET_TX_DESC_RTS_SHORT(pdesc, ((ptcb_desc->rts_rate <=
737 DESC92D_RATE54M) ?
738 (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
739 (ptcb_desc->rts_use_shortgi ? 1 : 0)));
740 if (bw_40) {
741 if (ptcb_desc->packet_bw) {
742 SET_TX_DESC_DATA_BW(pdesc, 1);
743 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
744 } else {
745 SET_TX_DESC_DATA_BW(pdesc, 0);
746 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
747 mac->cur_40_prime_sc);
748 }
749 } else {
750 SET_TX_DESC_DATA_BW(pdesc, 0);
751 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
752 }
753 SET_TX_DESC_LINIP(pdesc, 0);
754 SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb_len);
755 if (sta) {
756 u8 ampdu_density = sta->ht_cap.ampdu_density;
757 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
758 }
759 if (info->control.hw_key) {
760 struct ieee80211_key_conf *keyconf;
761
762 keyconf = info->control.hw_key;
763 switch (keyconf->cipher) {
764 case WLAN_CIPHER_SUITE_WEP40:
765 case WLAN_CIPHER_SUITE_WEP104:
766 case WLAN_CIPHER_SUITE_TKIP:
767 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
768 break;
769 case WLAN_CIPHER_SUITE_CCMP:
770 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
771 break;
772 default:
773 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
774 break;
775
776 }
777 }
778 SET_TX_DESC_PKT_ID(pdesc, 0);
779 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
780 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
781 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
782 SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ?
783 1 : 0);
784 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
785
786 /* Set TxRate and RTSRate in TxDesc */
787 /* This prevent Tx initial rate of new-coming packets */
788 /* from being overwritten by retried packet rate.*/
789 if (!ptcb_desc->use_driver_rate) {
790 SET_TX_DESC_RTS_RATE(pdesc, 0x08);
791 /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
792 }
793 if (ieee80211_is_data_qos(fc)) {
794 if (mac->rdg_en) {
795 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
796 ("Enable RDG function.\n"));
797 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
798 SET_TX_DESC_HTC(pdesc, 1);
799 }
800 }
801 }
802
803 SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
804 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
805 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) buf_len);
806 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
807 if (rtlpriv->dm.useramask) {
808 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
809 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
810 } else {
811 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
812 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
813 }
814 if (ieee80211_is_data_qos(fc))
815 SET_TX_DESC_QOS(pdesc, 1);
816
817 if ((!ieee80211_is_data_qos(fc)) && ppsc->fwctrl_lps) {
818 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
819 SET_TX_DESC_PKT_ID(pdesc, 8);
820 }
821 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
822 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, ("\n"));
823}
824
825void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw,
826 u8 *pdesc, bool firstseg,
827 bool lastseg, struct sk_buff *skb)
828{
829 struct rtl_priv *rtlpriv = rtl_priv(hw);
830 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
831 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
832 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
833 u8 fw_queue = QSLT_BEACON;
834 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
835 skb->data, skb->len, PCI_DMA_TODEVICE);
836 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
837 __le16 fc = hdr->frame_control;
838
839 CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
840 if (firstseg)
841 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
842 /* 5G have no CCK rate
843 * Caution: The macros below are multi-line expansions.
844 * The braces are needed no matter what checkpatch says
845 */
846 if (rtlhal->current_bandtype == BAND_ON_5G) {
847 SET_TX_DESC_TX_RATE(pdesc, DESC92D_RATE6M);
848 } else {
849 SET_TX_DESC_TX_RATE(pdesc, DESC92D_RATE1M);
850 }
851 SET_TX_DESC_SEQ(pdesc, 0);
852 SET_TX_DESC_LINIP(pdesc, 0);
853 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
854 SET_TX_DESC_FIRST_SEG(pdesc, 1);
855 SET_TX_DESC_LAST_SEG(pdesc, 1);
856 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) (skb->len));
857 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
858 SET_TX_DESC_RATE_ID(pdesc, 7);
859 SET_TX_DESC_MACID(pdesc, 0);
860 SET_TX_DESC_PKT_SIZE((u8 *) pdesc, (u16) (skb->len));
861 SET_TX_DESC_FIRST_SEG(pdesc, 1);
862 SET_TX_DESC_LAST_SEG(pdesc, 1);
863 SET_TX_DESC_OFFSET(pdesc, 0x20);
864 SET_TX_DESC_USE_RATE(pdesc, 1);
865
866 if (!ieee80211_is_data_qos(fc) && ppsc->fwctrl_lps) {
867 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
868 SET_TX_DESC_PKT_ID(pdesc, 8);
869 }
870
871 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
872 "H2C Tx Cmd Content\n", pdesc, TX_DESC_SIZE);
873 wmb();
874 SET_TX_DESC_OWN(pdesc, 1);
875}
876
877void rtl92de_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
878{
879 if (istx == true) {
880 switch (desc_name) {
881 case HW_DESC_OWN:
882 wmb();
883 SET_TX_DESC_OWN(pdesc, 1);
884 break;
885 case HW_DESC_TX_NEXTDESC_ADDR:
886 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val);
887 break;
888 default:
889 RT_ASSERT(false, ("ERR txdesc :%d"
890 " not process\n", desc_name));
891 break;
892 }
893 } else {
894 switch (desc_name) {
895 case HW_DESC_RXOWN:
896 wmb();
897 SET_RX_DESC_OWN(pdesc, 1);
898 break;
899 case HW_DESC_RXBUFF_ADDR:
900 SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *) val);
901 break;
902 case HW_DESC_RXPKT_LEN:
903 SET_RX_DESC_PKT_LEN(pdesc, *(u32 *) val);
904 break;
905 case HW_DESC_RXERO:
906 SET_RX_DESC_EOR(pdesc, 1);
907 break;
908 default:
909 RT_ASSERT(false, ("ERR rxdesc :%d "
910 "not process\n", desc_name));
911 break;
912 }
913 }
914}
915
916u32 rtl92de_get_desc(u8 *p_desc, bool istx, u8 desc_name)
917{
918 u32 ret = 0;
919
920 if (istx == true) {
921 switch (desc_name) {
922 case HW_DESC_OWN:
923 ret = GET_TX_DESC_OWN(p_desc);
924 break;
925 case HW_DESC_TXBUFF_ADDR:
926 ret = GET_TX_DESC_TX_BUFFER_ADDRESS(p_desc);
927 break;
928 default:
929 RT_ASSERT(false, ("ERR txdesc :%d "
930 "not process\n", desc_name));
931 break;
932 }
933 } else {
934 struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
935 switch (desc_name) {
936 case HW_DESC_OWN:
937 ret = GET_RX_DESC_OWN(pdesc);
938 break;
939 case HW_DESC_RXPKT_LEN:
940 ret = GET_RX_DESC_PKT_LEN(pdesc);
941 break;
942 default:
943 RT_ASSERT(false, ("ERR rxdesc :%d "
944 "not process\n", desc_name));
945 break;
946 }
947 }
948 return ret;
949}
950
951void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
952{
953 struct rtl_priv *rtlpriv = rtl_priv(hw);
954 if (hw_queue == BEACON_QUEUE)
955 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4));
956 else
957 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG,
958 BIT(0) << (hw_queue));
959}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/rtlwifi/rtl8192de/trx.h
new file mode 100644
index 00000000000..992d6766e66
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/trx.h
@@ -0,0 +1,756 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92DE_TRX_H__
31#define __RTL92DE_TRX_H__
32
33#define TX_DESC_SIZE 64
34#define TX_DESC_AGGR_SUBFRAME_SIZE 32
35
36#define RX_DESC_SIZE 32
37#define RX_DRV_INFO_SIZE_UNIT 8
38
39#define TX_DESC_NEXT_DESC_OFFSET 40
40#define USB_HWDESC_HEADER_LEN 32
41#define CRCLENGTH 4
42
43/* Define a macro that takes a le32 word, converts it to host ordering,
44 * right shifts by a specified count, creates a mask of the specified
45 * bit count, and extracts that number of bits.
46 */
47
48#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
49 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
50 BIT_LEN_MASK_32(__mask))
51
52/* Define a macro that clears a bit field in an le32 word and
53 * sets the specified value into that bit field. The resulting
54 * value remains in le32 ordering; however, it is properly converted
55 * to host ordering for the clear and set operations before conversion
56 * back to le32.
57 */
58
59#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
60 (*(__le32 *)(__pdesc) = \
61 (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
62 (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
63 (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
64
65/* macros to read/write various fields in RX or TX descriptors */
66
67#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
68 SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
69#define SET_TX_DESC_OFFSET(__pdesc, __val) \
70 SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
71#define SET_TX_DESC_BMC(__pdesc, __val) \
72 SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
73#define SET_TX_DESC_HTC(__pdesc, __val) \
74 SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
75#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
76 SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
77#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
78 SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
79#define SET_TX_DESC_LINIP(__pdesc, __val) \
80 SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
81#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
82 SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
83#define SET_TX_DESC_GF(__pdesc, __val) \
84 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
85#define SET_TX_DESC_OWN(__pdesc, __val) \
86 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
87
88#define GET_TX_DESC_PKT_SIZE(__pdesc) \
89 SHIFT_AND_MASK_LE(__pdesc, 0, 16)
90#define GET_TX_DESC_OFFSET(__pdesc) \
91 SHIFT_AND_MASK_LE(__pdesc, 16, 8)
92#define GET_TX_DESC_BMC(__pdesc) \
93 SHIFT_AND_MASK_LE(__pdesc, 24, 1)
94#define GET_TX_DESC_HTC(__pdesc) \
95 SHIFT_AND_MASK_LE(__pdesc, 25, 1)
96#define GET_TX_DESC_LAST_SEG(__pdesc) \
97 SHIFT_AND_MASK_LE(__pdesc, 26, 1)
98#define GET_TX_DESC_FIRST_SEG(__pdesc) \
99 SHIFT_AND_MASK_LE(__pdesc, 27, 1)
100#define GET_TX_DESC_LINIP(__pdesc) \
101 SHIFT_AND_MASK_LE(__pdesc, 28, 1)
102#define GET_TX_DESC_NO_ACM(__pdesc) \
103 SHIFT_AND_MASK_LE(__pdesc, 29, 1)
104#define GET_TX_DESC_GF(__pdesc) \
105 SHIFT_AND_MASK_LE(__pdesc, 30, 1)
106#define GET_TX_DESC_OWN(__pdesc) \
107 SHIFT_AND_MASK_LE(__pdesc, 31, 1)
108
109#define SET_TX_DESC_MACID(__pdesc, __val) \
110 SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
111#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
112 SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
113#define SET_TX_DESC_BK(__pdesc, __val) \
114 SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val)
115#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
116 SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
117#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
118 SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
119#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
120 SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val)
121#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
122 SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val)
123#define SET_TX_DESC_PIFS(__pdesc, __val) \
124 SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val)
125#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
126 SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
127#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
128 SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val)
129#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
130 SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val)
131#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
132 SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
133#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
134 SET_BITS_OFFSET_LE(__pdesc+4, 26, 8, __val)
135
136#define GET_TX_DESC_MACID(__pdesc) \
137 SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
138#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
139 SHIFT_AND_MASK_LE(__pdesc+4, 5, 1)
140#define GET_TX_DESC_AGG_BREAK(__pdesc) \
141 SHIFT_AND_MASK_LE(__pdesc+4, 6, 1)
142#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
143 SHIFT_AND_MASK_LE(__pdesc+4, 7, 1)
144#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
145 SHIFT_AND_MASK_LE(__pdesc+4, 8, 5)
146#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
147 SHIFT_AND_MASK_LE(__pdesc+4, 13, 1)
148#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
149 SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
150#define GET_TX_DESC_PIFS(__pdesc) \
151 SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
152#define GET_TX_DESC_RATE_ID(__pdesc) \
153 SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
154#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
155 SHIFT_AND_MASK_LE(__pdesc+4, 20, 1)
156#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
157 SHIFT_AND_MASK_LE(__pdesc+4, 21, 1)
158#define GET_TX_DESC_SEC_TYPE(__pdesc) \
159 SHIFT_AND_MASK_LE(__pdesc+4, 22, 2)
160#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
161 SHIFT_AND_MASK_LE(__pdesc+4, 24, 8)
162
163#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
164 SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val)
165#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
166 SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val)
167#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
168 SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val)
169#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
170 SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
171#define SET_TX_DESC_RAW(__pdesc, __val) \
172 SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val)
173#define SET_TX_DESC_CCX(__pdesc, __val) \
174 SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val)
175#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
176 SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
177#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
178 SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val)
179#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
180 SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val)
181#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \
182 SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val)
183#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \
184 SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val)
185#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
186 SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val)
187
188#define GET_TX_DESC_RTS_RC(__pdesc) \
189 SHIFT_AND_MASK_LE(__pdesc+8, 0, 6)
190#define GET_TX_DESC_DATA_RC(__pdesc) \
191 SHIFT_AND_MASK_LE(__pdesc+8, 6, 6)
192#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
193 SHIFT_AND_MASK_LE(__pdesc+8, 14, 2)
194#define GET_TX_DESC_MORE_FRAG(__pdesc) \
195 SHIFT_AND_MASK_LE(__pdesc+8, 17, 1)
196#define GET_TX_DESC_RAW(__pdesc) \
197 SHIFT_AND_MASK_LE(__pdesc+8, 18, 1)
198#define GET_TX_DESC_CCX(__pdesc) \
199 SHIFT_AND_MASK_LE(__pdesc+8, 19, 1)
200#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
201 SHIFT_AND_MASK_LE(__pdesc+8, 20, 3)
202#define GET_TX_DESC_ANTSEL_A(__pdesc) \
203 SHIFT_AND_MASK_LE(__pdesc+8, 24, 1)
204#define GET_TX_DESC_ANTSEL_B(__pdesc) \
205 SHIFT_AND_MASK_LE(__pdesc+8, 25, 1)
206#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
207 SHIFT_AND_MASK_LE(__pdesc+8, 26, 2)
208#define GET_TX_DESC_TX_ANTL(__pdesc) \
209 SHIFT_AND_MASK_LE(__pdesc+8, 28, 2)
210#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
211 SHIFT_AND_MASK_LE(__pdesc+8, 30, 2)
212
213#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
214 SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val)
215#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
216 SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val)
217#define SET_TX_DESC_SEQ(__pdesc, __val) \
218 SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
219#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
220 SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
221
222#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
223 SHIFT_AND_MASK_LE(__pdesc+12, 0, 8)
224#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
225 SHIFT_AND_MASK_LE(__pdesc+12, 8, 8)
226#define GET_TX_DESC_SEQ(__pdesc) \
227 SHIFT_AND_MASK_LE(__pdesc+12, 16, 12)
228#define GET_TX_DESC_PKT_ID(__pdesc) \
229 SHIFT_AND_MASK_LE(__pdesc+12, 28, 4)
230
231#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
232 SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
233#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
234 SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val)
235#define SET_TX_DESC_QOS(__pdesc, __val) \
236 SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
237#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
238 SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
239#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
240 SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
241#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
242 SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val)
243#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
244 SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
245#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
246 SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
247#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
248 SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
249#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
250 SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
251#define SET_TX_DESC_PORT_ID(__pdesc, __val) \
252 SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val)
253#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \
254 SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
255#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \
256 SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val)
257#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
258 SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
259#define SET_TX_DESC_TX_STBC(__pdesc, __val) \
260 SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val)
261#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
262 SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
263#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
264 SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
265#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
266 SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
267#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
268 SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
269#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
270 SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
271#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
272 SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
273
274#define GET_TX_DESC_RTS_RATE(__pdesc) \
275 SHIFT_AND_MASK_LE(__pdesc+16, 0, 5)
276#define GET_TX_DESC_AP_DCFE(__pdesc) \
277 SHIFT_AND_MASK_LE(__pdesc+16, 5, 1)
278#define GET_TX_DESC_QOS(__pdesc) \
279 SHIFT_AND_MASK_LE(__pdesc+16, 6, 1)
280#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
281 SHIFT_AND_MASK_LE(__pdesc+16, 7, 1)
282#define GET_TX_DESC_USE_RATE(__pdesc) \
283 SHIFT_AND_MASK_LE(__pdesc+16, 8, 1)
284#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
285 SHIFT_AND_MASK_LE(__pdesc+16, 9, 1)
286#define GET_TX_DESC_DISABLE_FB(__pdesc) \
287 SHIFT_AND_MASK_LE(__pdesc+16, 10, 1)
288#define GET_TX_DESC_CTS2SELF(__pdesc) \
289 SHIFT_AND_MASK_LE(__pdesc+16, 11, 1)
290#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
291 SHIFT_AND_MASK_LE(__pdesc+16, 12, 1)
292#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
293 SHIFT_AND_MASK_LE(__pdesc+16, 13, 1)
294#define GET_TX_DESC_PORT_ID(__pdesc) \
295 SHIFT_AND_MASK_LE(__pdesc+16, 14, 1)
296#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
297 SHIFT_AND_MASK_LE(__pdesc+16, 18, 1)
298#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
299 SHIFT_AND_MASK_LE(__pdesc+16, 19, 1)
300#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
301 SHIFT_AND_MASK_LE(__pdesc+16, 20, 2)
302#define GET_TX_DESC_TX_STBC(__pdesc) \
303 SHIFT_AND_MASK_LE(__pdesc+16, 22, 2)
304#define GET_TX_DESC_DATA_SHORT(__pdesc) \
305 SHIFT_AND_MASK_LE(__pdesc+16, 24, 1)
306#define GET_TX_DESC_DATA_BW(__pdesc) \
307 SHIFT_AND_MASK_LE(__pdesc+16, 25, 1)
308#define GET_TX_DESC_RTS_SHORT(__pdesc) \
309 SHIFT_AND_MASK_LE(__pdesc+16, 26, 1)
310#define GET_TX_DESC_RTS_BW(__pdesc) \
311 SHIFT_AND_MASK_LE(__pdesc+16, 27, 1)
312#define GET_TX_DESC_RTS_SC(__pdesc) \
313 SHIFT_AND_MASK_LE(__pdesc+16, 28, 2)
314#define GET_TX_DESC_RTS_STBC(__pdesc) \
315 SHIFT_AND_MASK_LE(__pdesc+16, 30, 2)
316
317#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
318 SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
319#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
320 SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
321#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
322 SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
323#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
324 SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
325#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
326 SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
327#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
328 SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val)
329#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
330 SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val)
331#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
332 SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val)
333
334#define GET_TX_DESC_TX_RATE(__pdesc) \
335 SHIFT_AND_MASK_LE(__pdesc+20, 0, 6)
336#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
337 SHIFT_AND_MASK_LE(__pdesc+20, 6, 1)
338#define GET_TX_DESC_CCX_TAG(__pdesc) \
339 SHIFT_AND_MASK_LE(__pdesc+20, 7, 1)
340#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
341 SHIFT_AND_MASK_LE(__pdesc+20, 8, 5)
342#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
343 SHIFT_AND_MASK_LE(__pdesc+20, 13, 4)
344#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
345 SHIFT_AND_MASK_LE(__pdesc+20, 17, 1)
346#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
347 SHIFT_AND_MASK_LE(__pdesc+20, 18, 6)
348#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \
349 SHIFT_AND_MASK_LE(__pdesc+20, 24, 8)
350
351#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \
352 SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val)
353#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
354 SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val)
355#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
356 SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val)
357#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
358 SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
359#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
360 SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val)
361#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \
362 SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val)
363#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \
364 SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val)
365#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \
366 SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val)
367
368#define GET_TX_DESC_TXAGC_A(__pdesc) \
369 SHIFT_AND_MASK_LE(__pdesc+24, 0, 5)
370#define GET_TX_DESC_TXAGC_B(__pdesc) \
371 SHIFT_AND_MASK_LE(__pdesc+24, 5, 5)
372#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
373 SHIFT_AND_MASK_LE(__pdesc+24, 10, 1)
374#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
375 SHIFT_AND_MASK_LE(__pdesc+24, 11, 5)
376#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
377 SHIFT_AND_MASK_LE(__pdesc+24, 16, 4)
378#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
379 SHIFT_AND_MASK_LE(__pdesc+24, 20, 4)
380#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
381 SHIFT_AND_MASK_LE(__pdesc+24, 24, 4)
382#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
383 SHIFT_AND_MASK_LE(__pdesc+24, 28, 4)
384
385#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
386 SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
387#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \
388 SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val)
389#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \
390 SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val)
391#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \
392 SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val)
393#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \
394 SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val)
395
396#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
397 SHIFT_AND_MASK_LE(__pdesc+28, 0, 16)
398#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
399 SHIFT_AND_MASK_LE(__pdesc+28, 16, 4)
400#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
401 SHIFT_AND_MASK_LE(__pdesc+28, 20, 4)
402#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
403 SHIFT_AND_MASK_LE(__pdesc+28, 24, 4)
404#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
405 SHIFT_AND_MASK_LE(__pdesc+28, 28, 4)
406
407#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
408 SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
409#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
410 SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
411
412#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
413 SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
414#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
415 SHIFT_AND_MASK_LE(__pdesc+36, 0, 32)
416
417#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
418 SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
419#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
420 SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val)
421
422#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
423 SHIFT_AND_MASK_LE(__pdesc+40, 0, 32)
424#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \
425 SHIFT_AND_MASK_LE(__pdesc+44, 0, 32)
426
427#define GET_RX_DESC_PKT_LEN(__pdesc) \
428 SHIFT_AND_MASK_LE(__pdesc, 0, 14)
429#define GET_RX_DESC_CRC32(__pdesc) \
430 SHIFT_AND_MASK_LE(__pdesc, 14, 1)
431#define GET_RX_DESC_ICV(__pdesc) \
432 SHIFT_AND_MASK_LE(__pdesc, 15, 1)
433#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
434 SHIFT_AND_MASK_LE(__pdesc, 16, 4)
435#define GET_RX_DESC_SECURITY(__pdesc) \
436 SHIFT_AND_MASK_LE(__pdesc, 20, 3)
437#define GET_RX_DESC_QOS(__pdesc) \
438 SHIFT_AND_MASK_LE(__pdesc, 23, 1)
439#define GET_RX_DESC_SHIFT(__pdesc) \
440 SHIFT_AND_MASK_LE(__pdesc, 24, 2)
441#define GET_RX_DESC_PHYST(__pdesc) \
442 SHIFT_AND_MASK_LE(__pdesc, 26, 1)
443#define GET_RX_DESC_SWDEC(__pdesc) \
444 SHIFT_AND_MASK_LE(__pdesc, 27, 1)
445#define GET_RX_DESC_LS(__pdesc) \
446 SHIFT_AND_MASK_LE(__pdesc, 28, 1)
447#define GET_RX_DESC_FS(__pdesc) \
448 SHIFT_AND_MASK_LE(__pdesc, 29, 1)
449#define GET_RX_DESC_EOR(__pdesc) \
450 SHIFT_AND_MASK_LE(__pdesc, 30, 1)
451#define GET_RX_DESC_OWN(__pdesc) \
452 SHIFT_AND_MASK_LE(__pdesc, 31, 1)
453
454#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
455 SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
456#define SET_RX_DESC_EOR(__pdesc, __val) \
457 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
458#define SET_RX_DESC_OWN(__pdesc, __val) \
459 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
460
461#define GET_RX_DESC_MACID(__pdesc) \
462 SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
463#define GET_RX_DESC_TID(__pdesc) \
464 SHIFT_AND_MASK_LE(__pdesc+4, 5, 4)
465#define GET_RX_DESC_HWRSVD(__pdesc) \
466 SHIFT_AND_MASK_LE(__pdesc+4, 9, 5)
467#define GET_RX_DESC_PAGGR(__pdesc) \
468 SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
469#define GET_RX_DESC_FAGGR(__pdesc) \
470 SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
471#define GET_RX_DESC_A1_FIT(__pdesc) \
472 SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
473#define GET_RX_DESC_A2_FIT(__pdesc) \
474 SHIFT_AND_MASK_LE(__pdesc+4, 20, 4)
475#define GET_RX_DESC_PAM(__pdesc) \
476 SHIFT_AND_MASK_LE(__pdesc+4, 24, 1)
477#define GET_RX_DESC_PWR(__pdesc) \
478 SHIFT_AND_MASK_LE(__pdesc+4, 25, 1)
479#define GET_RX_DESC_MD(__pdesc) \
480 SHIFT_AND_MASK_LE(__pdesc+4, 26, 1)
481#define GET_RX_DESC_MF(__pdesc) \
482 SHIFT_AND_MASK_LE(__pdesc+4, 27, 1)
483#define GET_RX_DESC_TYPE(__pdesc) \
484 SHIFT_AND_MASK_LE(__pdesc+4, 28, 2)
485#define GET_RX_DESC_MC(__pdesc) \
486 SHIFT_AND_MASK_LE(__pdesc+4, 30, 1)
487#define GET_RX_DESC_BC(__pdesc) \
488 SHIFT_AND_MASK_LE(__pdesc+4, 31, 1)
489#define GET_RX_DESC_SEQ(__pdesc) \
490 SHIFT_AND_MASK_LE(__pdesc+8, 0, 12)
491#define GET_RX_DESC_FRAG(__pdesc) \
492 SHIFT_AND_MASK_LE(__pdesc+8, 12, 4)
493#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
494 SHIFT_AND_MASK_LE(__pdesc+8, 16, 14)
495#define GET_RX_DESC_NEXT_IND(__pdesc) \
496 SHIFT_AND_MASK_LE(__pdesc+8, 30, 1)
497#define GET_RX_DESC_RSVD(__pdesc) \
498 SHIFT_AND_MASK_LE(__pdesc+8, 31, 1)
499
500#define GET_RX_DESC_RXMCS(__pdesc) \
501 SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
502#define GET_RX_DESC_RXHT(__pdesc) \
503 SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
504#define GET_RX_DESC_SPLCP(__pdesc) \
505 SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
506#define GET_RX_DESC_BW(__pdesc) \
507 SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
508#define GET_RX_DESC_HTC(__pdesc) \
509 SHIFT_AND_MASK_LE(__pdesc+12, 10, 1)
510#define GET_RX_DESC_HWPC_ERR(__pdesc) \
511 SHIFT_AND_MASK_LE(__pdesc+12, 14, 1)
512#define GET_RX_DESC_HWPC_IND(__pdesc) \
513 SHIFT_AND_MASK_LE(__pdesc+12, 15, 1)
514#define GET_RX_DESC_IV0(__pdesc) \
515 SHIFT_AND_MASK_LE(__pdesc+12, 16, 16)
516
517#define GET_RX_DESC_IV1(__pdesc) \
518 SHIFT_AND_MASK_LE(__pdesc+16, 0, 32)
519#define GET_RX_DESC_TSFL(__pdesc) \
520 SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
521
522#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
523 SHIFT_AND_MASK_LE(__pdesc+24, 0, 32)
524#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
525 SHIFT_AND_MASK_LE(__pdesc+28, 0, 32)
526
527#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
528 SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
529#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
530 SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
531
532#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
533do { \
534 if (_size > TX_DESC_NEXT_DESC_OFFSET) \
535 memset((void *)__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
536 else \
537 memset((void *)__pdesc, 0, _size); \
538} while (0);
539
540#define RX_HAL_IS_CCK_RATE(_pdesc)\
541 (_pdesc->rxmcs == DESC92D_RATE1M || \
542 _pdesc->rxmcs == DESC92D_RATE2M || \
543 _pdesc->rxmcs == DESC92D_RATE5_5M || \
544 _pdesc->rxmcs == DESC92D_RATE11M)
545
546/* For 92D early mode */
547#define SET_EARLYMODE_PKTNUM(__paddr, __value) \
548 SET_BITS_OFFSET_LE(__paddr, 0, 3, __value)
549#define SET_EARLYMODE_LEN0(__paddr, __value) \
550 SET_BITS_OFFSET_LE(__paddr, 4, 12, __value)
551#define SET_EARLYMODE_LEN1(__paddr, __value) \
552 SET_BITS_OFFSET_LE(__paddr, 16, 12, __value)
553#define SET_EARLYMODE_LEN2_1(__paddr, __value) \
554 SET_BITS_OFFSET_LE(__paddr, 28, 4, __value)
555#define SET_EARLYMODE_LEN2_2(__paddr, __value) \
556 SET_BITS_OFFSET_LE(__paddr+4, 0, 8, __value)
557#define SET_EARLYMODE_LEN3(__paddr, __value) \
558 SET_BITS_OFFSET_LE(__paddr+4, 8, 12, __value)
559#define SET_EARLYMODE_LEN4(__paddr, __value) \
560 SET_BITS_OFFSET_LE(__paddr+4, 20, 12, __value)
561
562struct rx_fwinfo_92d {
563 u8 gain_trsw[4];
564 u8 pwdb_all;
565 u8 cfosho[4];
566 u8 cfotail[4];
567 char rxevm[2];
568 char rxsnr[4];
569 u8 pdsnr[2];
570 u8 csi_current[2];
571 u8 csi_target[2];
572 u8 sigevm;
573 u8 max_ex_pwr;
574 u8 ex_intf_flag:1;
575 u8 sgi_en:1;
576 u8 rxsc:2;
577 u8 reserve:4;
578} __packed;
579
580struct tx_desc_92d {
581 u32 pktsize:16;
582 u32 offset:8;
583 u32 bmc:1;
584 u32 htc:1;
585 u32 lastseg:1;
586 u32 firstseg:1;
587 u32 linip:1;
588 u32 noacm:1;
589 u32 gf:1;
590 u32 own:1;
591
592 u32 macid:5;
593 u32 agg_en:1;
594 u32 bk:1;
595 u32 rdg_en:1;
596 u32 queuesel:5;
597 u32 rd_nav_ext:1;
598 u32 lsig_txop_en:1;
599 u32 pifs:1;
600 u32 rateid:4;
601 u32 nav_usehdr:1;
602 u32 en_descid:1;
603 u32 sectype:2;
604 u32 pktoffset:8;
605
606 u32 rts_rc:6;
607 u32 data_rc:6;
608 u32 rsvd0:2;
609 u32 bar_retryht:2;
610 u32 rsvd1:1;
611 u32 morefrag:1;
612 u32 raw:1;
613 u32 ccx:1;
614 u32 ampdudensity:3;
615 u32 rsvd2:1;
616 u32 ant_sela:1;
617 u32 ant_selb:1;
618 u32 txant_cck:2;
619 u32 txant_l:2;
620 u32 txant_ht:2;
621
622 u32 nextheadpage:8;
623 u32 tailpage:8;
624 u32 seq:12;
625 u32 pktid:4;
626
627 u32 rtsrate:5;
628 u32 apdcfe:1;
629 u32 qos:1;
630 u32 hwseq_enable:1;
631 u32 userrate:1;
632 u32 dis_rtsfb:1;
633 u32 dis_datafb:1;
634 u32 cts2self:1;
635 u32 rts_en:1;
636 u32 hwrts_en:1;
637 u32 portid:1;
638 u32 rsvd3:3;
639 u32 waitdcts:1;
640 u32 cts2ap_en:1;
641 u32 txsc:2;
642 u32 stbc:2;
643 u32 txshort:1;
644 u32 txbw:1;
645 u32 rtsshort:1;
646 u32 rtsbw:1;
647 u32 rtssc:2;
648 u32 rtsstbc:2;
649
650 u32 txrate:6;
651 u32 shortgi:1;
652 u32 ccxt:1;
653 u32 txrate_fb_lmt:5;
654 u32 rtsrate_fb_lmt:4;
655 u32 retrylmt_en:1;
656 u32 txretrylmt:6;
657 u32 usb_txaggnum:8;
658
659 u32 txagca:5;
660 u32 txagcb:5;
661 u32 usemaxlen:1;
662 u32 maxaggnum:5;
663 u32 mcsg1maxlen:4;
664 u32 mcsg2maxlen:4;
665 u32 mcsg3maxlen:4;
666 u32 mcs7sgimaxlen:4;
667
668 u32 txbuffersize:16;
669 u32 mcsg4maxlen:4;
670 u32 mcsg5maxlen:4;
671 u32 mcsg6maxlen:4;
672 u32 mcsg15sgimaxlen:4;
673
674 u32 txbuffaddr;
675 u32 txbufferaddr64;
676 u32 nextdescaddress;
677 u32 nextdescaddress64;
678
679 u32 reserve_pass_pcie_mm_limit[4];
680} __packed;
681
682struct rx_desc_92d {
683 u32 length:14;
684 u32 crc32:1;
685 u32 icverror:1;
686 u32 drv_infosize:4;
687 u32 security:3;
688 u32 qos:1;
689 u32 shift:2;
690 u32 phystatus:1;
691 u32 swdec:1;
692 u32 lastseg:1;
693 u32 firstseg:1;
694 u32 eor:1;
695 u32 own:1;
696
697 u32 macid:5;
698 u32 tid:4;
699 u32 hwrsvd:5;
700 u32 paggr:1;
701 u32 faggr:1;
702 u32 a1_fit:4;
703 u32 a2_fit:4;
704 u32 pam:1;
705 u32 pwr:1;
706 u32 moredata:1;
707 u32 morefrag:1;
708 u32 type:2;
709 u32 mc:1;
710 u32 bc:1;
711
712 u32 seq:12;
713 u32 frag:4;
714 u32 nextpktlen:14;
715 u32 nextind:1;
716 u32 rsvd:1;
717
718 u32 rxmcs:6;
719 u32 rxht:1;
720 u32 amsdu:1;
721 u32 splcp:1;
722 u32 bandwidth:1;
723 u32 htc:1;
724 u32 tcpchk_rpt:1;
725 u32 ipcchk_rpt:1;
726 u32 tcpchk_valid:1;
727 u32 hwpcerr:1;
728 u32 hwpcind:1;
729 u32 iv0:16;
730
731 u32 iv1;
732
733 u32 tsfl;
734
735 u32 bufferaddress;
736 u32 bufferaddress64;
737
738} __packed;
739
740void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
741 struct ieee80211_hdr *hdr,
742 u8 *pdesc, struct ieee80211_tx_info *info,
743 struct sk_buff *skb, u8 hw_queue,
744 struct rtl_tcb_desc *ptcb_desc);
745bool rtl92de_rx_query_desc(struct ieee80211_hw *hw,
746 struct rtl_stats *stats,
747 struct ieee80211_rx_status *rx_status,
748 u8 *pdesc, struct sk_buff *skb);
749void rtl92de_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val);
750u32 rtl92de_get_desc(u8 *pdesc, bool istx, u8 desc_name);
751void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
752void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
753 bool b_firstseg, bool b_lastseg,
754 struct sk_buff *skb);
755
756#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 01:49:17 -0400