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authorArend van Spriel <arend@broadcom.com>2011-12-12 18:15:09 -0500
committerJohn W. Linville <linville@tuxdriver.com>2011-12-13 15:48:26 -0500
commit3b758a68402fc5b1c2dbc246595dbdc062bf0da9 (patch)
tree60073a429024389b47585cad4ca1f880a81bc8c7 /drivers/net/wireless/brcm80211/brcmsmac/dma.c
parente3d5af56e1a50c9bc3c24810e6b25df91d37bc77 (diff)
brcm80211: smac: remove mapped core related function from aiutils.c
In aiutils.c the selected core was maintained by its index number. This is obsolete using BCMA functions so several functions using that index have been removed. Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Alwin Beukers <alwin@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/brcm80211/brcmsmac/dma.c')
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/dma.c101
1 files changed, 51 insertions, 50 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/dma.c b/drivers/net/wireless/brcm80211/brcmsmac/dma.c
index dab04bbedc8..b4cf617276c 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/dma.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/dma.c
@@ -227,7 +227,7 @@ struct dma_info {
227 uint *msg_level; /* message level pointer */ 227 uint *msg_level; /* message level pointer */
228 char name[MAXNAMEL]; /* callers name for diag msgs */ 228 char name[MAXNAMEL]; /* callers name for diag msgs */
229 229
230 struct bcma_device *d11core; 230 struct bcma_device *core;
231 struct device *dmadev; 231 struct device *dmadev;
232 232
233 bool dma64; /* this dma engine is operating in 64-bit mode */ 233 bool dma64; /* this dma engine is operating in 64-bit mode */
@@ -383,15 +383,15 @@ static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags)
383 if (dmactrlflags & DMA_CTRL_PEN) { 383 if (dmactrlflags & DMA_CTRL_PEN) {
384 u32 control; 384 u32 control;
385 385
386 control = bcma_read32(di->d11core, DMA64TXREGOFFS(di, control)); 386 control = bcma_read32(di->core, DMA64TXREGOFFS(di, control));
387 bcma_write32(di->d11core, DMA64TXREGOFFS(di, control), 387 bcma_write32(di->core, DMA64TXREGOFFS(di, control),
388 control | D64_XC_PD); 388 control | D64_XC_PD);
389 if (bcma_read32(di->d11core, DMA64TXREGOFFS(di, control)) & 389 if (bcma_read32(di->core, DMA64TXREGOFFS(di, control)) &
390 D64_XC_PD) 390 D64_XC_PD)
391 /* We *can* disable it so it is supported, 391 /* We *can* disable it so it is supported,
392 * restore control register 392 * restore control register
393 */ 393 */
394 bcma_write32(di->d11core, DMA64TXREGOFFS(di, control), 394 bcma_write32(di->core, DMA64TXREGOFFS(di, control),
395 control); 395 control);
396 else 396 else
397 /* Not supported, don't allow it to be enabled */ 397 /* Not supported, don't allow it to be enabled */
@@ -406,9 +406,9 @@ static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags)
406static bool _dma64_addrext(struct dma_info *di, uint ctrl_offset) 406static bool _dma64_addrext(struct dma_info *di, uint ctrl_offset)
407{ 407{
408 u32 w; 408 u32 w;
409 bcma_set32(di->d11core, ctrl_offset, D64_XC_AE); 409 bcma_set32(di->core, ctrl_offset, D64_XC_AE);
410 w = bcma_read32(di->d11core, ctrl_offset); 410 w = bcma_read32(di->core, ctrl_offset);
411 bcma_mask32(di->d11core, ctrl_offset, ~D64_XC_AE); 411 bcma_mask32(di->core, ctrl_offset, ~D64_XC_AE);
412 return (w & D64_XC_AE) == D64_XC_AE; 412 return (w & D64_XC_AE) == D64_XC_AE;
413} 413}
414 414
@@ -442,13 +442,13 @@ static bool _dma_descriptor_align(struct dma_info *di)
442 442
443 /* Check to see if the descriptors need to be aligned on 4K/8K or not */ 443 /* Check to see if the descriptors need to be aligned on 4K/8K or not */
444 if (di->d64txregbase != 0) { 444 if (di->d64txregbase != 0) {
445 bcma_write32(di->d11core, DMA64TXREGOFFS(di, addrlow), 0xff0); 445 bcma_write32(di->core, DMA64TXREGOFFS(di, addrlow), 0xff0);
446 addrl = bcma_read32(di->d11core, DMA64TXREGOFFS(di, addrlow)); 446 addrl = bcma_read32(di->core, DMA64TXREGOFFS(di, addrlow));
447 if (addrl != 0) 447 if (addrl != 0)
448 return false; 448 return false;
449 } else if (di->d64rxregbase != 0) { 449 } else if (di->d64rxregbase != 0) {
450 bcma_write32(di->d11core, DMA64RXREGOFFS(di, addrlow), 0xff0); 450 bcma_write32(di->core, DMA64RXREGOFFS(di, addrlow), 0xff0);
451 addrl = bcma_read32(di->d11core, DMA64RXREGOFFS(di, addrlow)); 451 addrl = bcma_read32(di->core, DMA64RXREGOFFS(di, addrlow));
452 if (addrl != 0) 452 if (addrl != 0)
453 return false; 453 return false;
454 } 454 }
@@ -565,12 +565,13 @@ static bool _dma_alloc(struct dma_info *di, uint direction)
565} 565}
566 566
567struct dma_pub *dma_attach(char *name, struct si_pub *sih, 567struct dma_pub *dma_attach(char *name, struct si_pub *sih,
568 struct bcma_device *d11core, 568 struct bcma_device *core,
569 uint txregbase, uint rxregbase, uint ntxd, uint nrxd, 569 uint txregbase, uint rxregbase, uint ntxd, uint nrxd,
570 uint rxbufsize, int rxextheadroom, 570 uint rxbufsize, int rxextheadroom,
571 uint nrxpost, uint rxoffset, uint *msg_level) 571 uint nrxpost, uint rxoffset, uint *msg_level)
572{ 572{
573 struct dma_info *di; 573 struct dma_info *di;
574 u8 rev = core->id.rev;
574 uint size; 575 uint size;
575 576
576 /* allocate private info structure */ 577 /* allocate private info structure */
@@ -582,10 +583,10 @@ struct dma_pub *dma_attach(char *name, struct si_pub *sih,
582 583
583 584
584 di->dma64 = 585 di->dma64 =
585 ((bcma_aread32(d11core, BCMA_IOST) & SISF_DMA64) == SISF_DMA64); 586 ((bcma_aread32(core, BCMA_IOST) & SISF_DMA64) == SISF_DMA64);
586 587
587 /* init dma reg info */ 588 /* init dma reg info */
588 di->d11core = d11core; 589 di->core = core;
589 di->d64txregbase = txregbase; 590 di->d64txregbase = txregbase;
590 di->d64rxregbase = rxregbase; 591 di->d64rxregbase = rxregbase;
591 592
@@ -606,7 +607,7 @@ struct dma_pub *dma_attach(char *name, struct si_pub *sih,
606 strncpy(di->name, name, MAXNAMEL); 607 strncpy(di->name, name, MAXNAMEL);
607 di->name[MAXNAMEL - 1] = '\0'; 608 di->name[MAXNAMEL - 1] = '\0';
608 609
609 di->dmadev = d11core->dma_dev; 610 di->dmadev = core->dma_dev;
610 611
611 /* save tunables */ 612 /* save tunables */
612 di->ntxd = (u16) ntxd; 613 di->ntxd = (u16) ntxd;
@@ -638,11 +639,11 @@ struct dma_pub *dma_attach(char *name, struct si_pub *sih,
638 di->dataoffsetlow = di->ddoffsetlow; 639 di->dataoffsetlow = di->ddoffsetlow;
639 di->dataoffsethigh = di->ddoffsethigh; 640 di->dataoffsethigh = di->ddoffsethigh;
640 /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */ 641 /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
641 if ((ai_coreid(sih) == SDIOD_CORE_ID) 642 if ((core->id.id == SDIOD_CORE_ID)
642 && ((ai_corerev(sih) > 0) && (ai_corerev(sih) <= 2))) 643 && ((rev > 0) && (rev <= 2)))
643 di->addrext = 0; 644 di->addrext = 0;
644 else if ((ai_coreid(sih) == I2S_CORE_ID) && 645 else if ((core->id.id == I2S_CORE_ID) &&
645 ((ai_corerev(sih) == 0) || (ai_corerev(sih) == 1))) 646 ((rev == 0) || (rev == 1)))
646 di->addrext = 0; 647 di->addrext = 0;
647 else 648 else
648 di->addrext = _dma_isaddrext(di); 649 di->addrext = _dma_isaddrext(di);
@@ -792,14 +793,14 @@ _dma_ddtable_init(struct dma_info *di, uint direction, dma_addr_t pa)
792 if ((di->ddoffsetlow == 0) 793 if ((di->ddoffsetlow == 0)
793 || !(pa & PCI32ADDR_HIGH)) { 794 || !(pa & PCI32ADDR_HIGH)) {
794 if (direction == DMA_TX) { 795 if (direction == DMA_TX) {
795 bcma_write32(di->d11core, DMA64TXREGOFFS(di, addrlow), 796 bcma_write32(di->core, DMA64TXREGOFFS(di, addrlow),
796 pa + di->ddoffsetlow); 797 pa + di->ddoffsetlow);
797 bcma_write32(di->d11core, DMA64TXREGOFFS(di, addrhigh), 798 bcma_write32(di->core, DMA64TXREGOFFS(di, addrhigh),
798 di->ddoffsethigh); 799 di->ddoffsethigh);
799 } else { 800 } else {
800 bcma_write32(di->d11core, DMA64RXREGOFFS(di, addrlow), 801 bcma_write32(di->core, DMA64RXREGOFFS(di, addrlow),
801 pa + di->ddoffsetlow); 802 pa + di->ddoffsetlow);
802 bcma_write32(di->d11core, DMA64RXREGOFFS(di, addrhigh), 803 bcma_write32(di->core, DMA64RXREGOFFS(di, addrhigh),
803 di->ddoffsethigh); 804 di->ddoffsethigh);
804 } 805 }
805 } else { 806 } else {
@@ -811,18 +812,18 @@ _dma_ddtable_init(struct dma_info *di, uint direction, dma_addr_t pa)
811 pa &= ~PCI32ADDR_HIGH; 812 pa &= ~PCI32ADDR_HIGH;
812 813
813 if (direction == DMA_TX) { 814 if (direction == DMA_TX) {
814 bcma_write32(di->d11core, DMA64TXREGOFFS(di, addrlow), 815 bcma_write32(di->core, DMA64TXREGOFFS(di, addrlow),
815 pa + di->ddoffsetlow); 816 pa + di->ddoffsetlow);
816 bcma_write32(di->d11core, DMA64TXREGOFFS(di, addrhigh), 817 bcma_write32(di->core, DMA64TXREGOFFS(di, addrhigh),
817 di->ddoffsethigh); 818 di->ddoffsethigh);
818 bcma_maskset32(di->d11core, DMA64TXREGOFFS(di, control), 819 bcma_maskset32(di->core, DMA64TXREGOFFS(di, control),
819 D64_XC_AE, (ae << D64_XC_AE_SHIFT)); 820 D64_XC_AE, (ae << D64_XC_AE_SHIFT));
820 } else { 821 } else {
821 bcma_write32(di->d11core, DMA64RXREGOFFS(di, addrlow), 822 bcma_write32(di->core, DMA64RXREGOFFS(di, addrlow),
822 pa + di->ddoffsetlow); 823 pa + di->ddoffsetlow);
823 bcma_write32(di->d11core, DMA64RXREGOFFS(di, addrhigh), 824 bcma_write32(di->core, DMA64RXREGOFFS(di, addrhigh),
824 di->ddoffsethigh); 825 di->ddoffsethigh);
825 bcma_maskset32(di->d11core, DMA64RXREGOFFS(di, control), 826 bcma_maskset32(di->core, DMA64RXREGOFFS(di, control),
826 D64_RC_AE, (ae << D64_RC_AE_SHIFT)); 827 D64_RC_AE, (ae << D64_RC_AE_SHIFT));
827 } 828 }
828 } 829 }
@@ -835,7 +836,7 @@ static void _dma_rxenable(struct dma_info *di)
835 836
836 DMA_TRACE("%s:\n", di->name); 837 DMA_TRACE("%s:\n", di->name);
837 838
838 control = D64_RC_RE | (bcma_read32(di->d11core, 839 control = D64_RC_RE | (bcma_read32(di->core,
839 DMA64RXREGOFFS(di, control)) & 840 DMA64RXREGOFFS(di, control)) &
840 D64_RC_AE); 841 D64_RC_AE);
841 842
@@ -845,7 +846,7 @@ static void _dma_rxenable(struct dma_info *di)
845 if (dmactrlflags & DMA_CTRL_ROC) 846 if (dmactrlflags & DMA_CTRL_ROC)
846 control |= D64_RC_OC; 847 control |= D64_RC_OC;
847 848
848 bcma_write32(di->d11core, DMA64RXREGOFFS(di, control), 849 bcma_write32(di->core, DMA64RXREGOFFS(di, control),
849 ((di->rxoffset << D64_RC_RO_SHIFT) | control)); 850 ((di->rxoffset << D64_RC_RO_SHIFT) | control));
850} 851}
851 852
@@ -888,7 +889,7 @@ static struct sk_buff *dma64_getnextrxp(struct dma_info *di, bool forceall)
888 return NULL; 889 return NULL;
889 890
890 curr = 891 curr =
891 B2I(((bcma_read32(di->d11core, 892 B2I(((bcma_read32(di->core,
892 DMA64RXREGOFFS(di, status0)) & D64_RS0_CD_MASK) - 893 DMA64RXREGOFFS(di, status0)) & D64_RS0_CD_MASK) -
893 di->rcvptrbase) & D64_RS0_CD_MASK, struct dma64desc); 894 di->rcvptrbase) & D64_RS0_CD_MASK, struct dma64desc);
894 895
@@ -971,7 +972,7 @@ int dma_rx(struct dma_pub *pub, struct sk_buff_head *skb_list)
971 if (resid > 0) { 972 if (resid > 0) {
972 uint cur; 973 uint cur;
973 cur = 974 cur =
974 B2I(((bcma_read32(di->d11core, 975 B2I(((bcma_read32(di->core,
975 DMA64RXREGOFFS(di, status0)) & 976 DMA64RXREGOFFS(di, status0)) &
976 D64_RS0_CD_MASK) - di->rcvptrbase) & 977 D64_RS0_CD_MASK) - di->rcvptrbase) &
977 D64_RS0_CD_MASK, struct dma64desc); 978 D64_RS0_CD_MASK, struct dma64desc);
@@ -1004,9 +1005,9 @@ static bool dma64_rxidle(struct dma_info *di)
1004 if (di->nrxd == 0) 1005 if (di->nrxd == 0)
1005 return true; 1006 return true;
1006 1007
1007 return ((bcma_read32(di->d11core, 1008 return ((bcma_read32(di->core,
1008 DMA64RXREGOFFS(di, status0)) & D64_RS0_CD_MASK) == 1009 DMA64RXREGOFFS(di, status0)) & D64_RS0_CD_MASK) ==
1009 (bcma_read32(di->d11core, DMA64RXREGOFFS(di, ptr)) & 1010 (bcma_read32(di->core, DMA64RXREGOFFS(di, ptr)) &
1010 D64_RS0_CD_MASK)); 1011 D64_RS0_CD_MASK));
1011} 1012}
1012 1013
@@ -1090,7 +1091,7 @@ bool dma_rxfill(struct dma_pub *pub)
1090 di->rxout = rxout; 1091 di->rxout = rxout;
1091 1092
1092 /* update the chip lastdscr pointer */ 1093 /* update the chip lastdscr pointer */
1093 bcma_write32(di->d11core, DMA64RXREGOFFS(di, ptr), 1094 bcma_write32(di->core, DMA64RXREGOFFS(di, ptr),
1094 di->rcvptrbase + I2B(rxout, struct dma64desc)); 1095 di->rcvptrbase + I2B(rxout, struct dma64desc));
1095 1096
1096 return ring_empty; 1097 return ring_empty;
@@ -1151,7 +1152,7 @@ void dma_txinit(struct dma_pub *pub)
1151 1152
1152 if ((di->dma.dmactrlflags & DMA_CTRL_PEN) == 0) 1153 if ((di->dma.dmactrlflags & DMA_CTRL_PEN) == 0)
1153 control |= D64_XC_PD; 1154 control |= D64_XC_PD;
1154 bcma_set32(di->d11core, DMA64TXREGOFFS(di, control), control); 1155 bcma_set32(di->core, DMA64TXREGOFFS(di, control), control);
1155 1156
1156 /* DMA engine with alignment requirement requires table to be inited 1157 /* DMA engine with alignment requirement requires table to be inited
1157 * before enabling the engine 1158 * before enabling the engine
@@ -1169,7 +1170,7 @@ void dma_txsuspend(struct dma_pub *pub)
1169 if (di->ntxd == 0) 1170 if (di->ntxd == 0)
1170 return; 1171 return;
1171 1172
1172 bcma_set32(di->d11core, DMA64TXREGOFFS(di, control), D64_XC_SE); 1173 bcma_set32(di->core, DMA64TXREGOFFS(di, control), D64_XC_SE);
1173} 1174}
1174 1175
1175void dma_txresume(struct dma_pub *pub) 1176void dma_txresume(struct dma_pub *pub)
@@ -1181,7 +1182,7 @@ void dma_txresume(struct dma_pub *pub)
1181 if (di->ntxd == 0) 1182 if (di->ntxd == 0)
1182 return; 1183 return;
1183 1184
1184 bcma_mask32(di->d11core, DMA64TXREGOFFS(di, control), ~D64_XC_SE); 1185 bcma_mask32(di->core, DMA64TXREGOFFS(di, control), ~D64_XC_SE);
1185} 1186}
1186 1187
1187bool dma_txsuspended(struct dma_pub *pub) 1188bool dma_txsuspended(struct dma_pub *pub)
@@ -1189,7 +1190,7 @@ bool dma_txsuspended(struct dma_pub *pub)
1189 struct dma_info *di = (struct dma_info *)pub; 1190 struct dma_info *di = (struct dma_info *)pub;
1190 1191
1191 return (di->ntxd == 0) || 1192 return (di->ntxd == 0) ||
1192 ((bcma_read32(di->d11core, 1193 ((bcma_read32(di->core,
1193 DMA64TXREGOFFS(di, control)) & D64_XC_SE) == 1194 DMA64TXREGOFFS(di, control)) & D64_XC_SE) ==
1194 D64_XC_SE); 1195 D64_XC_SE);
1195} 1196}
@@ -1224,16 +1225,16 @@ bool dma_txreset(struct dma_pub *pub)
1224 return true; 1225 return true;
1225 1226
1226 /* suspend tx DMA first */ 1227 /* suspend tx DMA first */
1227 bcma_write32(di->d11core, DMA64TXREGOFFS(di, control), D64_XC_SE); 1228 bcma_write32(di->core, DMA64TXREGOFFS(di, control), D64_XC_SE);
1228 SPINWAIT(((status = 1229 SPINWAIT(((status =
1229 (bcma_read32(di->d11core, DMA64TXREGOFFS(di, status0)) & 1230 (bcma_read32(di->core, DMA64TXREGOFFS(di, status0)) &
1230 D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED) && 1231 D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED) &&
1231 (status != D64_XS0_XS_IDLE) && (status != D64_XS0_XS_STOPPED), 1232 (status != D64_XS0_XS_IDLE) && (status != D64_XS0_XS_STOPPED),
1232 10000); 1233 10000);
1233 1234
1234 bcma_write32(di->d11core, DMA64TXREGOFFS(di, control), 0); 1235 bcma_write32(di->core, DMA64TXREGOFFS(di, control), 0);
1235 SPINWAIT(((status = 1236 SPINWAIT(((status =
1236 (bcma_read32(di->d11core, DMA64TXREGOFFS(di, status0)) & 1237 (bcma_read32(di->core, DMA64TXREGOFFS(di, status0)) &
1237 D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED), 10000); 1238 D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED), 10000);
1238 1239
1239 /* wait for the last transaction to complete */ 1240 /* wait for the last transaction to complete */
@@ -1250,9 +1251,9 @@ bool dma_rxreset(struct dma_pub *pub)
1250 if (di->nrxd == 0) 1251 if (di->nrxd == 0)
1251 return true; 1252 return true;
1252 1253
1253 bcma_write32(di->d11core, DMA64RXREGOFFS(di, control), 0); 1254 bcma_write32(di->core, DMA64RXREGOFFS(di, control), 0);
1254 SPINWAIT(((status = 1255 SPINWAIT(((status =
1255 (bcma_read32(di->d11core, DMA64RXREGOFFS(di, status0)) & 1256 (bcma_read32(di->core, DMA64RXREGOFFS(di, status0)) &
1256 D64_RS0_RS_MASK)) != D64_RS0_RS_DISABLED), 10000); 1257 D64_RS0_RS_MASK)) != D64_RS0_RS_DISABLED), 10000);
1257 1258
1258 return status == D64_RS0_RS_DISABLED; 1259 return status == D64_RS0_RS_DISABLED;
@@ -1315,7 +1316,7 @@ int dma_txfast(struct dma_pub *pub, struct sk_buff *p, bool commit)
1315 1316
1316 /* kick the chip */ 1317 /* kick the chip */
1317 if (commit) 1318 if (commit)
1318 bcma_write32(di->d11core, DMA64TXREGOFFS(di, ptr), 1319 bcma_write32(di->core, DMA64TXREGOFFS(di, ptr),
1319 di->xmtptrbase + I2B(txout, struct dma64desc)); 1320 di->xmtptrbase + I2B(txout, struct dma64desc));
1320 1321
1321 /* tx flow control */ 1322 /* tx flow control */
@@ -1363,14 +1364,14 @@ struct sk_buff *dma_getnexttxp(struct dma_pub *pub, enum txd_range range)
1363 if (range == DMA_RANGE_ALL) 1364 if (range == DMA_RANGE_ALL)
1364 end = di->txout; 1365 end = di->txout;
1365 else { 1366 else {
1366 end = (u16) (B2I(((bcma_read32(di->d11core, 1367 end = (u16) (B2I(((bcma_read32(di->core,
1367 DMA64TXREGOFFS(di, status0)) & 1368 DMA64TXREGOFFS(di, status0)) &
1368 D64_XS0_CD_MASK) - di->xmtptrbase) & 1369 D64_XS0_CD_MASK) - di->xmtptrbase) &
1369 D64_XS0_CD_MASK, struct dma64desc)); 1370 D64_XS0_CD_MASK, struct dma64desc));
1370 1371
1371 if (range == DMA_RANGE_TRANSFERED) { 1372 if (range == DMA_RANGE_TRANSFERED) {
1372 active_desc = 1373 active_desc =
1373 (u16)(bcma_read32(di->d11core, 1374 (u16)(bcma_read32(di->core,
1374 DMA64TXREGOFFS(di, status1)) & 1375 DMA64TXREGOFFS(di, status1)) &
1375 D64_XS1_AD_MASK); 1376 D64_XS1_AD_MASK);
1376 active_desc = 1377 active_desc =