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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/net/wireless/bcmdhd/dhd_sdio.c
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/net/wireless/bcmdhd/dhd_sdio.c')
-rw-r--r--drivers/net/wireless/bcmdhd/dhd_sdio.c6289
1 files changed, 6289 insertions, 0 deletions
diff --git a/drivers/net/wireless/bcmdhd/dhd_sdio.c b/drivers/net/wireless/bcmdhd/dhd_sdio.c
new file mode 100644
index 00000000000..57aee570545
--- /dev/null
+++ b/drivers/net/wireless/bcmdhd/dhd_sdio.c
@@ -0,0 +1,6289 @@
1/*
2 * DHD Bus Module for SDIO
3 *
4 * Copyright (C) 1999-2011, Broadcom Corporation
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 * $Id: dhd_sdio.c 288105 2011-10-06 01:58:02Z $
25 */
26
27#include <typedefs.h>
28#include <osl.h>
29#include <bcmsdh.h>
30
31#ifdef BCMEMBEDIMAGE
32#include BCMEMBEDIMAGE
33#endif /* BCMEMBEDIMAGE */
34
35#include <bcmdefs.h>
36#include <bcmutils.h>
37#include <bcmendian.h>
38#include <bcmdevs.h>
39
40#include <siutils.h>
41#include <hndpmu.h>
42#include <hndsoc.h>
43#include <bcmsdpcm.h>
44#if defined(DHD_DEBUG)
45#include <hndrte_armtrap.h>
46#include <hndrte_cons.h>
47#endif /* defined(DHD_DEBUG) */
48#include <sbchipc.h>
49#include <sbhnddma.h>
50
51#include <sdio.h>
52#include <sbsdio.h>
53#include <sbsdpcmdev.h>
54#include <bcmsdpcm.h>
55#include <bcmsdbus.h>
56
57#include <proto/ethernet.h>
58#include <proto/802.1d.h>
59#include <proto/802.11.h>
60
61#include <dngl_stats.h>
62#include <dhd.h>
63#include <dhd_bus.h>
64#include <dhd_proto.h>
65#include <dhd_dbg.h>
66#include <dhdioctl.h>
67#include <sdiovar.h>
68
69#ifndef DHDSDIO_MEM_DUMP_FNAME
70#define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
71#endif
72
73#define QLEN 256 /* bulk rx and tx queue lengths */
74#define FCHI (QLEN - 10)
75#define FCLOW (FCHI / 2)
76#define PRIOMASK 7
77
78#define TXRETRIES 2 /* # of retries for tx frames */
79
80#define DHD_RXBOUND 50 /* Default for max rx frames in one scheduling */
81
82#define DHD_TXBOUND 20 /* Default for max tx frames in one scheduling */
83
84#define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
85
86#define MEMBLOCK 2048 /* Block size used for downloading of dongle image */
87#define MAX_NVRAMBUF_SIZE 4096 /* max nvram buf size */
88#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold biggest possible glom */
89
90#ifndef DHD_FIRSTREAD
91#define DHD_FIRSTREAD 32
92#endif
93#if !ISPOWEROF2(DHD_FIRSTREAD)
94#error DHD_FIRSTREAD is not a power of 2!
95#endif
96
97/* Total length of frame header for dongle protocol */
98#define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
99#ifdef SDTEST
100#define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
101#else
102#define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
103#endif
104
105/* Space for header read, limit for data packets */
106#ifndef MAX_HDR_READ
107#define MAX_HDR_READ 32
108#endif
109#if !ISPOWEROF2(MAX_HDR_READ)
110#error MAX_HDR_READ is not a power of 2!
111#endif
112
113#define MAX_RX_DATASZ 2048
114
115/* Maximum milliseconds to wait for F2 to come up */
116#define DHD_WAIT_F2RDY 3000
117
118/* Bump up limit on waiting for HT to account for first startup;
119 * if the image is doing a CRC calculation before programming the PMU
120 * for HT availability, it could take a couple hundred ms more, so
121 * max out at a 1 second (1000000us).
122 */
123#if (PMU_MAX_TRANSITION_DLY <= 1000000)
124#undef PMU_MAX_TRANSITION_DLY
125#define PMU_MAX_TRANSITION_DLY 1000000
126#endif
127
128/* Value for ChipClockCSR during initial setup */
129#define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ)
130#define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
131
132/* Flags for SDH calls */
133#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
134
135/* Packet free applicable unconditionally for sdio and sdspi. Conditional if
136 * bufpool was present for gspi bus.
137 */
138#define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
139 PKTFREE(bus->dhd->osh, pkt, FALSE);
140DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
141#if defined(OOB_INTR_ONLY)
142extern void bcmsdh_set_irq(int flag);
143#endif /* defined(OOB_INTR_ONLY) */
144#ifdef PROP_TXSTATUS
145extern void dhd_wlfc_txcomplete(dhd_pub_t *dhd, void *txp, bool success);
146#endif
147
148#ifdef DHD_DEBUG
149/* Device console log buffer state */
150#define CONSOLE_LINE_MAX 192
151#define CONSOLE_BUFFER_MAX 2024
152typedef struct dhd_console {
153 uint count; /* Poll interval msec counter */
154 uint log_addr; /* Log struct address (fixed) */
155 hndrte_log_t log; /* Log struct (host copy) */
156 uint bufsize; /* Size of log buffer */
157 uint8 *buf; /* Log buffer (host copy) */
158 uint last; /* Last buffer read index */
159} dhd_console_t;
160#endif /* DHD_DEBUG */
161
162/* Private data for SDIO bus interaction */
163typedef struct dhd_bus {
164 dhd_pub_t *dhd;
165
166 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
167 si_t *sih; /* Handle for SI calls */
168 char *vars; /* Variables (from CIS and/or other) */
169 uint varsz; /* Size of variables buffer */
170 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
171
172 sdpcmd_regs_t *regs; /* Registers for SDIO core */
173 uint sdpcmrev; /* SDIO core revision */
174 uint armrev; /* CPU core revision */
175 uint ramrev; /* SOCRAM core revision */
176 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
177 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
178
179 uint32 bus; /* gSPI or SDIO bus */
180 uint32 hostintmask; /* Copy of Host Interrupt Mask */
181 uint32 intstatus; /* Intstatus bits (events) pending */
182 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
183 bool fcstate; /* State of dongle flow-control */
184
185 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
186 char *fw_path; /* module_param: path to firmware image */
187 char *nv_path; /* module_param: path to nvram vars file */
188 const char *nvram_params; /* user specified nvram params. */
189
190 uint blocksize; /* Block size of SDIO transfers */
191 uint roundup; /* Max roundup limit */
192
193 struct pktq txq; /* Queue length used for flow-control */
194 uint8 flowcontrol; /* per prio flow control bitmask */
195 uint8 tx_seq; /* Transmit sequence number (next) */
196 uint8 tx_max; /* Maximum transmit sequence allowed */
197
198 uint8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
199 uint8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
200 uint16 nextlen; /* Next Read Len from last header */
201 uint8 rx_seq; /* Receive sequence number (expected) */
202 bool rxskip; /* Skip receive (awaiting NAK ACK) */
203
204 void *glomd; /* Packet containing glomming descriptor */
205 void *glom; /* Packet chain for glommed superframe */
206 uint glomerr; /* Glom packet read errors */
207
208 uint8 *rxbuf; /* Buffer for receiving control packets */
209 uint rxblen; /* Allocated length of rxbuf */
210 uint8 *rxctl; /* Aligned pointer into rxbuf */
211 uint8 *databuf; /* Buffer for receiving big glom packet */
212 uint8 *dataptr; /* Aligned pointer into databuf */
213 uint rxlen; /* Length of valid data in buffer */
214
215 uint8 sdpcm_ver; /* Bus protocol reported by dongle */
216
217 bool intr; /* Use interrupts */
218 bool poll; /* Use polling */
219 bool ipend; /* Device interrupt is pending */
220 bool intdis; /* Interrupts disabled by isr */
221 uint intrcount; /* Count of device interrupt callbacks */
222 uint lastintrs; /* Count as of last watchdog timer */
223 uint spurious; /* Count of spurious interrupts */
224 uint pollrate; /* Ticks between device polls */
225 uint polltick; /* Tick counter */
226 uint pollcnt; /* Count of active polls */
227
228#ifdef DHD_DEBUG
229 dhd_console_t console; /* Console output polling support */
230 uint console_addr; /* Console address from shared struct */
231#endif /* DHD_DEBUG */
232
233 uint regfails; /* Count of R_REG/W_REG failures */
234
235 uint clkstate; /* State of sd and backplane clock(s) */
236 bool activity; /* Activity flag for clock down */
237 int32 idletime; /* Control for activity timeout */
238 int32 idlecount; /* Activity timeout counter */
239 int32 idleclock; /* How to set bus driver when idle */
240 int32 sd_divisor; /* Speed control to bus driver */
241 int32 sd_mode; /* Mode control to bus driver */
242 int32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
243 bool use_rxchain; /* If dhd should use PKT chains */
244 bool sleeping; /* Is SDIO bus sleeping? */
245 bool rxflow_mode; /* Rx flow control mode */
246 bool rxflow; /* Is rx flow control on */
247 uint prev_rxlim_hit; /* Is prev rx limit exceeded (per dpc schedule) */
248 bool alp_only; /* Don't use HT clock (ALP only) */
249 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
250 bool usebufpool;
251
252#ifdef SDTEST
253 /* external loopback */
254 bool ext_loop;
255 uint8 loopid;
256
257 /* pktgen configuration */
258 uint pktgen_freq; /* Ticks between bursts */
259 uint pktgen_count; /* Packets to send each burst */
260 uint pktgen_print; /* Bursts between count displays */
261 uint pktgen_total; /* Stop after this many */
262 uint pktgen_minlen; /* Minimum packet data len */
263 uint pktgen_maxlen; /* Maximum packet data len */
264 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
265 uint pktgen_stop; /* Number of tx failures causing stop */
266
267 /* active pktgen fields */
268 uint pktgen_tick; /* Tick counter for bursts */
269 uint pktgen_ptick; /* Burst counter for printing */
270 uint pktgen_sent; /* Number of test packets generated */
271 uint pktgen_rcvd; /* Number of test packets received */
272 uint pktgen_fail; /* Number of failed send attempts */
273 uint16 pktgen_len; /* Length of next packet to send */
274#define PKTGEN_RCV_IDLE (0)
275#define PKTGEN_RCV_ONGOING (1)
276 uint16 pktgen_rcv_state; /* receive state */
277 uint pktgen_rcvd_rcvsession; /* test pkts rcvd per rcv session. */
278#endif /* SDTEST */
279
280 /* Some additional counters */
281 uint tx_sderrs; /* Count of tx attempts with sd errors */
282 uint fcqueued; /* Tx packets that got queued */
283 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
284 uint rx_toolong; /* Receive frames too long to receive */
285 uint rxc_errors; /* SDIO errors when reading control frames */
286 uint rx_hdrfail; /* SDIO errors on header reads */
287 uint rx_badhdr; /* Bad received headers (roosync?) */
288 uint rx_badseq; /* Mismatched rx sequence number */
289 uint fc_rcvd; /* Number of flow-control events received */
290 uint fc_xoff; /* Number which turned on flow-control */
291 uint fc_xon; /* Number which turned off flow-control */
292 uint rxglomfail; /* Failed deglom attempts */
293 uint rxglomframes; /* Number of glom frames (superframes) */
294 uint rxglompkts; /* Number of packets from glom frames */
295 uint f2rxhdrs; /* Number of header reads */
296 uint f2rxdata; /* Number of frame data reads */
297 uint f2txdata; /* Number of f2 frame writes */
298 uint f1regdata; /* Number of f1 register accesses */
299
300 uint8 *ctrl_frame_buf;
301 uint32 ctrl_frame_len;
302 bool ctrl_frame_stat;
303 uint32 rxint_mode; /* rx interrupt mode */
304} dhd_bus_t;
305
306/* clkstate */
307#define CLK_NONE 0
308#define CLK_SDONLY 1
309#define CLK_PENDING 2 /* Not used yet */
310#define CLK_AVAIL 3
311
312#define DHD_NOPMU(dhd) (FALSE)
313
314#ifdef DHD_DEBUG
315static int qcount[NUMPRIO];
316static int tx_packets[NUMPRIO];
317#endif /* DHD_DEBUG */
318
319/* Deferred transmit */
320const uint dhd_deferred_tx = 1;
321
322extern uint dhd_watchdog_ms;
323extern void dhd_os_wd_timer(void *bus, uint wdtick);
324
325/* Tx/Rx bounds */
326uint dhd_txbound;
327uint dhd_rxbound;
328uint dhd_txminmax = DHD_TXMINMAX;
329
330/* override the RAM size if possible */
331#define DONGLE_MIN_MEMSIZE (128 *1024)
332int dhd_dongle_memsize;
333
334static bool dhd_doflow;
335static bool dhd_alignctl;
336
337static bool sd1idle;
338
339static bool retrydata;
340#define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
341
342static const uint watermark = 8;
343static const uint firstread = DHD_FIRSTREAD;
344
345#define HDATLEN (firstread - (SDPCM_HDRLEN))
346
347/* Retry count for register access failures */
348static const uint retry_limit = 2;
349
350/* Force even SD lengths (some host controllers mess up on odd bytes) */
351static bool forcealign;
352
353/* Flag to indicate if we should download firmware on driver load */
354uint dhd_download_fw_on_driverload = TRUE;
355
356#define ALIGNMENT 4
357
358#if defined(OOB_INTR_ONLY) && defined(HW_OOB)
359extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
360#endif
361
362#if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
363#error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
364#endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
365#define PKTALIGN(osh, p, len, align) \
366 do { \
367 uint datalign; \
368 datalign = (uintptr)PKTDATA((osh), (p)); \
369 datalign = ROUNDUP(datalign, (align)) - datalign; \
370 ASSERT(datalign < (align)); \
371 ASSERT(PKTLEN((osh), (p)) >= ((len) + datalign)); \
372 if (datalign) \
373 PKTPULL((osh), (p), datalign); \
374 PKTSETLEN((osh), (p), (len)); \
375 } while (0)
376
377/* Limit on rounding up frames */
378static const uint max_roundup = 512;
379
380/* Try doing readahead */
381static bool dhd_readahead;
382
383/* To check if there's window offered */
384#define DATAOK(bus) \
385 (((uint8)(bus->tx_max - bus->tx_seq) > 2) && \
386 (((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
387
388/* To check if there's window offered for ctrl frame */
389#define TXCTLOK(bus) \
390 (((uint8)(bus->tx_max - bus->tx_seq) != 0) && \
391 (((uint8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
392
393/* Macros to get register read/write status */
394/* NOTE: these assume a local dhdsdio_bus_t *bus! */
395#define R_SDREG(regvar, regaddr, retryvar) \
396do { \
397 retryvar = 0; \
398 do { \
399 regvar = R_REG(bus->dhd->osh, regaddr); \
400 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
401 if (retryvar) { \
402 bus->regfails += (retryvar-1); \
403 if (retryvar > retry_limit) { \
404 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
405 __FUNCTION__, __LINE__)); \
406 regvar = 0; \
407 } \
408 } \
409} while (0)
410
411#define W_SDREG(regval, regaddr, retryvar) \
412do { \
413 retryvar = 0; \
414 do { \
415 W_REG(bus->dhd->osh, regaddr, regval); \
416 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
417 if (retryvar) { \
418 bus->regfails += (retryvar-1); \
419 if (retryvar > retry_limit) \
420 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
421 __FUNCTION__, __LINE__)); \
422 } \
423} while (0)
424
425#define BUS_WAKE(bus) \
426 do { \
427 if ((bus)->sleeping) \
428 dhdsdio_bussleep((bus), FALSE); \
429 } while (0);
430
431/*
432 * pktavail interrupts from dongle to host can be managed in 3 different ways
433 * whenever there is a packet available in dongle to transmit to host.
434 *
435 * Mode 0: Dongle writes the software host mailbox and host is interrupted.
436 * Mode 1: (sdiod core rev >= 4)
437 * Device sets a new bit in the intstatus whenever there is a packet
438 * available in fifo. Host can't clear this specific status bit until all the
439 * packets are read from the FIFO. No need to ack dongle intstatus.
440 * Mode 2: (sdiod core rev >= 4)
441 * Device sets a bit in the intstatus, and host acks this by writing
442 * one to this bit. Dongle won't generate anymore packet interrupts
443 * until host reads all the packets from the dongle and reads a zero to
444 * figure that there are no more packets. No need to disable host ints.
445 * Need to ack the intstatus.
446 */
447
448#define SDIO_DEVICE_HMB_RXINT 0 /* default old way */
449#define SDIO_DEVICE_RXDATAINT_MODE_0 1 /* from sdiod rev 4 */
450#define SDIO_DEVICE_RXDATAINT_MODE_1 2 /* from sdiod rev 4 */
451
452
453#define FRAME_AVAIL_MASK(bus) \
454 ((bus->rxint_mode == SDIO_DEVICE_HMB_RXINT) ? I_HMB_FRAME_IND : I_XMTDATA_AVAIL)
455
456#define DHD_BUS SDIO_BUS
457
458#define PKT_AVAILABLE(bus, intstatus) ((intstatus) & (FRAME_AVAIL_MASK(bus)))
459
460#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
461
462#define GSPI_PR55150_BAILOUT
463
464
465#ifdef SDTEST
466static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
467static void dhdsdio_sdtest_set(dhd_bus_t *bus, uint8 count);
468#endif
469
470#ifdef DHD_DEBUG
471static int dhdsdio_checkdied(dhd_bus_t *bus, char *data, uint size);
472static int dhd_serialconsole(dhd_bus_t *bus, bool get, bool enable, int *bcmerror);
473#endif /* DHD_DEBUG */
474
475static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
476
477static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh);
478static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh);
479static void dhdsdio_disconnect(void *ptr);
480static bool dhdsdio_chipmatch(uint16 chipid);
481static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh,
482 void * regsva, uint16 devid);
483static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh);
484static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh);
485static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation,
486 bool reset_flag);
487
488static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
489static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
490 uint8 *buf, uint nbytes,
491 void *pkt, bcmsdh_cmplt_fn_t complete, void *handle);
492static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
493 uint8 *buf, uint nbytes,
494 void *pkt, bcmsdh_cmplt_fn_t complete, void *handle);
495
496static bool dhdsdio_download_firmware(dhd_bus_t *bus, osl_t *osh, void *sdh);
497static int _dhdsdio_download_firmware(dhd_bus_t *bus);
498
499static int dhdsdio_download_code_file(dhd_bus_t *bus, char *image_path);
500static int dhdsdio_download_nvram(dhd_bus_t *bus);
501#ifdef BCMEMBEDIMAGE
502static int dhdsdio_download_code_array(dhd_bus_t *bus);
503#endif
504
505#ifdef WLMEDIA_HTSF
506#include <htsf.h>
507extern uint32 dhd_get_htsf(void *dhd, int ifidx);
508#endif /* WLMEDIA_HTSF */
509
510static void
511dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
512{
513 int32 min_size = DONGLE_MIN_MEMSIZE;
514 /* Restrict the memsize to user specified limit */
515 DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n",
516 dhd_dongle_memsize, min_size));
517 if ((dhd_dongle_memsize > min_size) &&
518 (dhd_dongle_memsize < (int32)bus->orig_ramsize))
519 bus->ramsize = dhd_dongle_memsize;
520}
521
522static int
523dhdsdio_set_siaddr_window(dhd_bus_t *bus, uint32 address)
524{
525 int err = 0;
526 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
527 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
528 if (!err)
529 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
530 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
531 if (!err)
532 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
533 (address >> 24) & SBSDIO_SBADDRHIGH_MASK, &err);
534 return err;
535}
536
537
538/* Turn backplane clock on or off */
539static int
540dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
541{
542 int err;
543 uint8 clkctl, clkreq, devctl;
544 bcmsdh_info_t *sdh;
545
546 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
547
548#if defined(OOB_INTR_ONLY)
549 pendok = FALSE;
550#endif
551 clkctl = 0;
552 sdh = bus->sdh;
553
554
555 if (on) {
556 /* Request HT Avail */
557 clkreq = bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
558
559
560
561
562 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
563 if (err) {
564 DHD_ERROR(("%s: HT Avail request error: %d\n", __FUNCTION__, err));
565 return BCME_ERROR;
566 }
567
568 if (pendok &&
569 ((bus->sih->buscoretype == PCMCIA_CORE_ID) && (bus->sih->buscorerev == 9))) {
570 uint32 dummy, retries;
571 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
572 }
573
574 /* Check current status */
575 clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
576 if (err) {
577 DHD_ERROR(("%s: HT Avail read error: %d\n", __FUNCTION__, err));
578 return BCME_ERROR;
579 }
580
581 /* Go to pending and await interrupt if appropriate */
582 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
583 /* Allow only clock-available interrupt */
584 devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
585 if (err) {
586 DHD_ERROR(("%s: Devctl access error setting CA: %d\n",
587 __FUNCTION__, err));
588 return BCME_ERROR;
589 }
590
591 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
592 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
593 DHD_INFO(("CLKCTL: set PENDING\n"));
594 bus->clkstate = CLK_PENDING;
595 return BCME_OK;
596 } else if (bus->clkstate == CLK_PENDING) {
597 /* Cancel CA-only interrupt filter */
598 devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
599 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
600 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
601 }
602
603 /* Otherwise, wait here (polling) for HT Avail */
604 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
605 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
606 ((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
607 SBSDIO_FUNC1_CHIPCLKCSR, &err)),
608 !SBSDIO_CLKAV(clkctl, bus->alp_only)), PMU_MAX_TRANSITION_DLY);
609 }
610 if (err) {
611 DHD_ERROR(("%s: HT Avail request error: %d\n", __FUNCTION__, err));
612 return BCME_ERROR;
613 }
614 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
615 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
616 __FUNCTION__, PMU_MAX_TRANSITION_DLY, clkctl));
617 return BCME_ERROR;
618 }
619
620
621 /* Mark clock available */
622 bus->clkstate = CLK_AVAIL;
623 DHD_INFO(("CLKCTL: turned ON\n"));
624
625#if defined(DHD_DEBUG)
626 if (bus->alp_only == TRUE) {
627#if !defined(BCMLXSDMMC)
628 if (!SBSDIO_ALPONLY(clkctl)) {
629 DHD_ERROR(("%s: HT Clock, when ALP Only\n", __FUNCTION__));
630 }
631#endif /* !defined(BCMLXSDMMC) */
632 } else {
633 if (SBSDIO_ALPONLY(clkctl)) {
634 DHD_ERROR(("%s: HT Clock should be on.\n", __FUNCTION__));
635 }
636 }
637#endif /* defined (DHD_DEBUG) */
638
639 bus->activity = TRUE;
640 } else {
641 clkreq = 0;
642
643 if (bus->clkstate == CLK_PENDING) {
644 /* Cancel CA-only interrupt filter */
645 devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
646 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
647 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
648 }
649
650 bus->clkstate = CLK_SDONLY;
651 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
652 DHD_INFO(("CLKCTL: turned OFF\n"));
653 if (err) {
654 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
655 __FUNCTION__, err));
656 return BCME_ERROR;
657 }
658 }
659 return BCME_OK;
660}
661
662/* Change idle/active SD state */
663static int
664dhdsdio_sdclk(dhd_bus_t *bus, bool on)
665{
666 int err;
667 int32 iovalue;
668
669 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
670
671 if (on) {
672 if (bus->idleclock == DHD_IDLE_STOP) {
673 /* Turn on clock and restore mode */
674 iovalue = 1;
675 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
676 &iovalue, sizeof(iovalue), TRUE);
677 if (err) {
678 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
679 __FUNCTION__, err));
680 return BCME_ERROR;
681 }
682
683 iovalue = bus->sd_mode;
684 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
685 &iovalue, sizeof(iovalue), TRUE);
686 if (err) {
687 DHD_ERROR(("%s: error changing sd_mode: %d\n",
688 __FUNCTION__, err));
689 return BCME_ERROR;
690 }
691 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
692 /* Restore clock speed */
693 iovalue = bus->sd_divisor;
694 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
695 &iovalue, sizeof(iovalue), TRUE);
696 if (err) {
697 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
698 __FUNCTION__, err));
699 return BCME_ERROR;
700 }
701 }
702 bus->clkstate = CLK_SDONLY;
703 } else {
704 /* Stop or slow the SD clock itself */
705 if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
706 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
707 __FUNCTION__, bus->sd_divisor, bus->sd_mode));
708 return BCME_ERROR;
709 }
710 if (bus->idleclock == DHD_IDLE_STOP) {
711 if (sd1idle) {
712 /* Change to SD1 mode and turn off clock */
713 iovalue = 1;
714 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
715 &iovalue, sizeof(iovalue), TRUE);
716 if (err) {
717 DHD_ERROR(("%s: error changing sd_clock: %d\n",
718 __FUNCTION__, err));
719 return BCME_ERROR;
720 }
721 }
722
723 iovalue = 0;
724 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
725 &iovalue, sizeof(iovalue), TRUE);
726 if (err) {
727 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
728 __FUNCTION__, err));
729 return BCME_ERROR;
730 }
731 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
732 /* Set divisor to idle value */
733 iovalue = bus->idleclock;
734 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
735 &iovalue, sizeof(iovalue), TRUE);
736 if (err) {
737 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
738 __FUNCTION__, err));
739 return BCME_ERROR;
740 }
741 }
742 bus->clkstate = CLK_NONE;
743 }
744
745 return BCME_OK;
746}
747
748/* Transition SD and backplane clock readiness */
749static int
750dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
751{
752 int ret = BCME_OK;
753#ifdef DHD_DEBUG
754 uint oldstate = bus->clkstate;
755#endif /* DHD_DEBUG */
756
757 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
758
759 /* Early exit if we're already there */
760 if (bus->clkstate == target) {
761 if (target == CLK_AVAIL) {
762 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
763 bus->activity = TRUE;
764 }
765 return ret;
766 }
767
768 switch (target) {
769 case CLK_AVAIL:
770 /* Make sure SD clock is available */
771 if (bus->clkstate == CLK_NONE)
772 dhdsdio_sdclk(bus, TRUE);
773 /* Now request HT Avail on the backplane */
774 ret = dhdsdio_htclk(bus, TRUE, pendok);
775 if (ret == BCME_OK) {
776 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
777 bus->activity = TRUE;
778 }
779 break;
780
781 case CLK_SDONLY:
782 /* Remove HT request, or bring up SD clock */
783 if (bus->clkstate == CLK_NONE)
784 ret = dhdsdio_sdclk(bus, TRUE);
785 else if (bus->clkstate == CLK_AVAIL)
786 ret = dhdsdio_htclk(bus, FALSE, FALSE);
787 else
788 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
789 bus->clkstate, target));
790 if (ret == BCME_OK) {
791 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
792 }
793 break;
794
795 case CLK_NONE:
796 /* Make sure to remove HT request */
797 if (bus->clkstate == CLK_AVAIL)
798 ret = dhdsdio_htclk(bus, FALSE, FALSE);
799 /* Now remove the SD clock */
800 ret = dhdsdio_sdclk(bus, FALSE);
801#ifdef DHD_DEBUG
802 if (dhd_console_ms == 0)
803#endif /* DHD_DEBUG */
804 dhd_os_wd_timer(bus->dhd, 0);
805 break;
806 }
807#ifdef DHD_DEBUG
808 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
809#endif /* DHD_DEBUG */
810
811 return ret;
812}
813
814static int
815dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
816{
817 bcmsdh_info_t *sdh = bus->sdh;
818 sdpcmd_regs_t *regs = bus->regs;
819 uint retries = 0;
820
821 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
822 (sleep ? "SLEEP" : "WAKE"),
823 (bus->sleeping ? "SLEEP" : "WAKE")));
824
825 /* Done if we're already in the requested state */
826 if (sleep == bus->sleeping)
827 return BCME_OK;
828
829 /* Going to sleep: set the alarm and turn off the lights... */
830 if (sleep) {
831 /* Don't sleep if something is pending */
832 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
833 return BCME_BUSY;
834
835
836 /* Disable SDIO interrupts (no longer interested) */
837 bcmsdh_intr_disable(bus->sdh);
838
839 /* Make sure the controller has the bus up */
840 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
841
842 /* Tell device to start using OOB wakeup */
843 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
844 if (retries > retry_limit)
845 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
846
847 /* Turn off our contribution to the HT clock request */
848 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
849
850 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
851 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
852
853 /* Isolate the bus */
854 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
855 SBSDIO_DEVCTL_PADS_ISO, NULL);
856
857 /* Change state */
858 bus->sleeping = TRUE;
859
860 } else {
861 /* Waking up: bus power up is ok, set local state */
862
863 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
864 0, NULL);
865
866 /* Force pad isolation off if possible (in case power never toggled) */
867 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0, NULL);
868
869
870 /* Make sure the controller has the bus up */
871 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
872
873 /* Send misc interrupt to indicate OOB not needed */
874 W_SDREG(0, &regs->tosbmailboxdata, retries);
875 if (retries <= retry_limit)
876 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
877
878 if (retries > retry_limit)
879 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
880
881 /* Make sure we have SD bus access */
882 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
883
884 /* Change state */
885 bus->sleeping = FALSE;
886
887 /* Enable interrupts again */
888 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
889 bus->intdis = FALSE;
890 bcmsdh_intr_enable(bus->sdh);
891 }
892 }
893
894 return BCME_OK;
895}
896
897#if defined(OOB_INTR_ONLY)
898void
899dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
900{
901#if defined(HW_OOB)
902 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
903#else
904 sdpcmd_regs_t *regs = bus->regs;
905 uint retries = 0;
906
907 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
908 if (enable == TRUE) {
909
910 /* Tell device to start using OOB wakeup */
911 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
912 if (retries > retry_limit)
913 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
914
915 } else {
916 /* Send misc interrupt to indicate OOB not needed */
917 W_SDREG(0, &regs->tosbmailboxdata, retries);
918 if (retries <= retry_limit)
919 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
920 }
921
922 /* Turn off our contribution to the HT clock request */
923 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
924#endif /* !defined(HW_OOB) */
925}
926#endif /* defined(OOB_INTR_ONLY) */
927
928/* Writes a HW/SW header into the packet and sends it. */
929/* Assumes: (a) header space already there, (b) caller holds lock */
930static int
931dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt)
932{
933 int ret;
934 osl_t *osh;
935 uint8 *frame;
936 uint16 len, pad1 = 0;
937 uint32 swheader;
938 uint retries = 0;
939 bcmsdh_info_t *sdh;
940 void *new;
941 int i;
942#ifdef WLMEDIA_HTSF
943 char *p;
944 htsfts_t *htsf_ts;
945#endif
946
947
948 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
949
950 sdh = bus->sdh;
951 osh = bus->dhd->osh;
952
953 if (bus->dhd->dongle_reset) {
954 ret = BCME_NOTREADY;
955 goto done;
956 }
957
958 frame = (uint8*)PKTDATA(osh, pkt);
959
960#ifdef WLMEDIA_HTSF
961 if (PKTLEN(osh, pkt) >= 100) {
962 p = PKTDATA(osh, pkt);
963 htsf_ts = (htsfts_t*) (p + HTSF_HOSTOFFSET + 12);
964 if (htsf_ts->magic == HTSFMAGIC) {
965 htsf_ts->c20 = get_cycles();
966 htsf_ts->t20 = dhd_get_htsf(bus->dhd->info, 0);
967 }
968 }
969#endif /* WLMEDIA_HTSF */
970
971 /* Add alignment padding, allocate new packet if needed */
972 if ((pad1 = ((uintptr)frame % DHD_SDALIGN))) {
973 if (PKTHEADROOM(osh, pkt) < pad1) {
974 DHD_INFO(("%s: insufficient headroom %d for %d pad1\n",
975 __FUNCTION__, (int)PKTHEADROOM(osh, pkt), pad1));
976 bus->dhd->tx_realloc++;
977 new = PKTGET(osh, (PKTLEN(osh, pkt) + DHD_SDALIGN), TRUE);
978 if (!new) {
979 DHD_ERROR(("%s: couldn't allocate new %d-byte packet\n",
980 __FUNCTION__, PKTLEN(osh, pkt) + DHD_SDALIGN));
981 ret = BCME_NOMEM;
982 goto done;
983 }
984
985 PKTALIGN(osh, new, PKTLEN(osh, pkt), DHD_SDALIGN);
986 bcopy(PKTDATA(osh, pkt), PKTDATA(osh, new), PKTLEN(osh, pkt));
987 if (free_pkt)
988 PKTFREE(osh, pkt, TRUE);
989 /* free the pkt if canned one is not used */
990 free_pkt = TRUE;
991 pkt = new;
992 frame = (uint8*)PKTDATA(osh, pkt);
993 ASSERT(((uintptr)frame % DHD_SDALIGN) == 0);
994 pad1 = 0;
995 } else {
996 PKTPUSH(osh, pkt, pad1);
997 frame = (uint8*)PKTDATA(osh, pkt);
998
999 ASSERT((pad1 + SDPCM_HDRLEN) <= (int) PKTLEN(osh, pkt));
1000 bzero(frame, pad1 + SDPCM_HDRLEN);
1001 }
1002 }
1003 ASSERT(pad1 < DHD_SDALIGN);
1004
1005 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1006 len = (uint16)PKTLEN(osh, pkt);
1007 *(uint16*)frame = htol16(len);
1008 *(((uint16*)frame) + 1) = htol16(~len);
1009
1010 /* Software tag: channel, sequence number, data offset */
1011 swheader = ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1012 (((pad1 + SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1013 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
1014 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1015
1016#ifdef DHD_DEBUG
1017 if (PKTPRIO(pkt) < ARRAYSIZE(tx_packets)) {
1018 tx_packets[PKTPRIO(pkt)]++;
1019 }
1020 if (DHD_BYTES_ON() &&
1021 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1022 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1023 prhex("Tx Frame", frame, len);
1024 } else if (DHD_HDRS_ON()) {
1025 prhex("TxHdr", frame, MIN(len, 16));
1026 }
1027#endif
1028
1029 /* Raise len to next SDIO block to eliminate tail command */
1030 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1031 uint16 pad2 = bus->blocksize - (len % bus->blocksize);
1032 if ((pad2 <= bus->roundup) && (pad2 < bus->blocksize))
1033#ifdef NOTUSED
1034 if (pad2 <= PKTTAILROOM(osh, pkt))
1035#endif /* NOTUSED */
1036 len += pad2;
1037 } else if (len % DHD_SDALIGN) {
1038 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1039 }
1040
1041 /* Some controllers have trouble with odd bytes -- round to even */
1042 if (forcealign && (len & (ALIGNMENT - 1))) {
1043#ifdef NOTUSED
1044 if (PKTTAILROOM(osh, pkt))
1045#endif
1046 len = ROUNDUP(len, ALIGNMENT);
1047#ifdef NOTUSED
1048 else
1049 DHD_ERROR(("%s: sending unrounded %d-byte packet\n", __FUNCTION__, len));
1050#endif
1051 }
1052
1053 do {
1054 ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
1055 frame, len, pkt, NULL, NULL);
1056 bus->f2txdata++;
1057 ASSERT(ret != BCME_PENDING);
1058
1059 if (ret < 0) {
1060 /* On failure, abort the command and terminate the frame */
1061 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1062 __FUNCTION__, ret));
1063 bus->tx_sderrs++;
1064
1065 bcmsdh_abort(sdh, SDIO_FUNC_2);
1066 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL,
1067 SFC_WF_TERM, NULL);
1068 bus->f1regdata++;
1069
1070 for (i = 0; i < 3; i++) {
1071 uint8 hi, lo;
1072 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1073 SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1074 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1075 SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1076 bus->f1regdata += 2;
1077 if ((hi == 0) && (lo == 0))
1078 break;
1079 }
1080
1081 }
1082 if (ret == 0) {
1083 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1084 }
1085 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1086
1087done:
1088 /* restore pkt buffer pointer before calling tx complete routine */
1089 PKTPULL(osh, pkt, SDPCM_HDRLEN + pad1);
1090#ifdef PROP_TXSTATUS
1091 if (bus->dhd->wlfc_state) {
1092 dhd_os_sdunlock(bus->dhd);
1093 dhd_wlfc_txcomplete(bus->dhd, pkt, ret == 0);
1094 dhd_os_sdlock(bus->dhd);
1095 } else {
1096#endif /* PROP_TXSTATUS */
1097 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1098 if (free_pkt)
1099 PKTFREE(osh, pkt, TRUE);
1100
1101#ifdef PROP_TXSTATUS
1102 }
1103#endif
1104 return ret;
1105}
1106
1107int
1108dhd_bus_txdata(struct dhd_bus *bus, void *pkt)
1109{
1110 int ret = BCME_ERROR;
1111 osl_t *osh;
1112 uint datalen, prec;
1113
1114 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
1115
1116 osh = bus->dhd->osh;
1117 datalen = PKTLEN(osh, pkt);
1118
1119#ifdef SDTEST
1120 /* Push the test header if doing loopback */
1121 if (bus->ext_loop) {
1122 uint8* data;
1123 PKTPUSH(osh, pkt, SDPCM_TEST_HDRLEN);
1124 data = PKTDATA(osh, pkt);
1125 *data++ = SDPCM_TEST_ECHOREQ;
1126 *data++ = (uint8)bus->loopid++;
1127 *data++ = (datalen >> 0);
1128 *data++ = (datalen >> 8);
1129 datalen += SDPCM_TEST_HDRLEN;
1130 }
1131#endif /* SDTEST */
1132
1133 /* Add space for the header */
1134 PKTPUSH(osh, pkt, SDPCM_HDRLEN);
1135 ASSERT(ISALIGNED((uintptr)PKTDATA(osh, pkt), 2));
1136
1137 prec = PRIO2PREC((PKTPRIO(pkt) & PRIOMASK));
1138#ifndef DHDTHREAD
1139 /* Lock: we're about to use shared data/code (and SDIO) */
1140 dhd_os_sdlock(bus->dhd);
1141#endif /* DHDTHREAD */
1142
1143 /* Check for existing queue, current flow-control, pending event, or pending clock */
1144 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq) || bus->dpc_sched ||
1145 (!DATAOK(bus)) || (bus->flowcontrol & NBITVAL(prec)) ||
1146 (bus->clkstate != CLK_AVAIL)) {
1147 DHD_TRACE(("%s: deferring pktq len %d\n", __FUNCTION__,
1148 pktq_len(&bus->txq)));
1149 bus->fcqueued++;
1150
1151 /* Priority based enq */
1152 dhd_os_sdlock_txq(bus->dhd);
1153 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == FALSE) {
1154 PKTPULL(osh, pkt, SDPCM_HDRLEN);
1155#ifndef DHDTHREAD
1156 /* Need to also release txqlock before releasing sdlock.
1157 * This thread still has txqlock and releases sdlock.
1158 * Deadlock happens when dpc() grabs sdlock first then
1159 * attempts to grab txqlock.
1160 */
1161 dhd_os_sdunlock_txq(bus->dhd);
1162 dhd_os_sdunlock(bus->dhd);
1163#endif
1164#ifdef PROP_TXSTATUS
1165 if (bus->dhd->wlfc_state)
1166 dhd_wlfc_txcomplete(bus->dhd, pkt, FALSE);
1167 else
1168#endif
1169 dhd_txcomplete(bus->dhd, pkt, FALSE);
1170#ifndef DHDTHREAD
1171 dhd_os_sdlock(bus->dhd);
1172 dhd_os_sdlock_txq(bus->dhd);
1173#endif
1174#ifdef PROP_TXSTATUS
1175 /* let the caller decide whether to free the packet */
1176 if (!bus->dhd->wlfc_state)
1177#endif
1178 PKTFREE(osh, pkt, TRUE);
1179 ret = BCME_NORESOURCE;
1180 }
1181 else
1182 ret = BCME_OK;
1183 dhd_os_sdunlock_txq(bus->dhd);
1184
1185 if ((pktq_len(&bus->txq) >= FCHI) && dhd_doflow)
1186 dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
1187
1188#ifdef DHD_DEBUG
1189 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1190 qcount[prec] = pktq_plen(&bus->txq, prec);
1191#endif
1192 /* Schedule DPC if needed to send queued packet(s) */
1193 if (dhd_deferred_tx && !bus->dpc_sched) {
1194 bus->dpc_sched = TRUE;
1195 dhd_sched_dpc(bus->dhd);
1196 }
1197 } else {
1198#ifdef DHDTHREAD
1199 /* Lock: we're about to use shared data/code (and SDIO) */
1200 dhd_os_sdlock(bus->dhd);
1201#endif /* DHDTHREAD */
1202
1203 /* Otherwise, send it now */
1204 BUS_WAKE(bus);
1205 /* Make sure back plane ht clk is on, no pending allowed */
1206 dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
1207#ifndef SDTEST
1208 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, TRUE);
1209#else
1210 ret = dhdsdio_txpkt(bus, pkt,
1211 (bus->ext_loop ? SDPCM_TEST_CHANNEL : SDPCM_DATA_CHANNEL), TRUE);
1212#endif
1213 if (ret)
1214 bus->dhd->tx_errors++;
1215 else
1216 bus->dhd->dstats.tx_bytes += datalen;
1217
1218 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1219 bus->activity = FALSE;
1220 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
1221 }
1222
1223#ifdef DHDTHREAD
1224 dhd_os_sdunlock(bus->dhd);
1225#endif /* DHDTHREAD */
1226 }
1227
1228#ifndef DHDTHREAD
1229 dhd_os_sdunlock(bus->dhd);
1230#endif /* DHDTHREAD */
1231
1232 return ret;
1233}
1234
1235static uint
1236dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1237{
1238 void *pkt;
1239 uint32 intstatus = 0;
1240 uint retries = 0;
1241 int ret = 0, prec_out;
1242 uint cnt = 0;
1243 uint datalen;
1244 uint8 tx_prec_map;
1245
1246 dhd_pub_t *dhd = bus->dhd;
1247 sdpcmd_regs_t *regs = bus->regs;
1248
1249 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
1250
1251 tx_prec_map = ~bus->flowcontrol;
1252
1253 /* Send frames until the limit or some other event */
1254 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1255 dhd_os_sdlock_txq(bus->dhd);
1256 if ((pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out)) == NULL) {
1257 dhd_os_sdunlock_txq(bus->dhd);
1258 break;
1259 }
1260 dhd_os_sdunlock_txq(bus->dhd);
1261 datalen = PKTLEN(bus->dhd->osh, pkt) - SDPCM_HDRLEN;
1262
1263#ifndef SDTEST
1264 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, TRUE);
1265#else
1266 ret = dhdsdio_txpkt(bus, pkt,
1267 (bus->ext_loop ? SDPCM_TEST_CHANNEL : SDPCM_DATA_CHANNEL), TRUE);
1268#endif
1269 if (ret)
1270 bus->dhd->tx_errors++;
1271 else
1272 bus->dhd->dstats.tx_bytes += datalen;
1273
1274 /* In poll mode, need to check for other events */
1275 if (!bus->intr && cnt)
1276 {
1277 /* Check device status, signal pending interrupt */
1278 R_SDREG(intstatus, &regs->intstatus, retries);
1279 bus->f2txdata++;
1280 if (bcmsdh_regfail(bus->sdh))
1281 break;
1282 if (intstatus & bus->hostintmask)
1283 bus->ipend = TRUE;
1284 }
1285 }
1286
1287 /* Deflow-control stack if needed */
1288 if (dhd_doflow && dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1289 dhd->txoff && (pktq_len(&bus->txq) < FCLOW))
1290 dhd_txflowcontrol(dhd, ALL_INTERFACES, OFF);
1291
1292 return cnt;
1293}
1294
1295int
1296dhd_bus_txctl(struct dhd_bus *bus, uchar *msg, uint msglen)
1297{
1298 uint8 *frame;
1299 uint16 len;
1300 uint32 swheader;
1301 uint retries = 0;
1302 bcmsdh_info_t *sdh = bus->sdh;
1303 uint8 doff = 0;
1304 int ret = -1;
1305 int i;
1306
1307 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
1308
1309 if (bus->dhd->dongle_reset)
1310 return -EIO;
1311
1312 /* Back the pointer to make a room for bus header */
1313 frame = msg - SDPCM_HDRLEN;
1314 len = (msglen += SDPCM_HDRLEN);
1315
1316 /* Add alignment padding (optional for ctl frames) */
1317 if (dhd_alignctl) {
1318 if ((doff = ((uintptr)frame % DHD_SDALIGN))) {
1319 frame -= doff;
1320 len += doff;
1321 msglen += doff;
1322 bzero(frame, doff + SDPCM_HDRLEN);
1323 }
1324 ASSERT(doff < DHD_SDALIGN);
1325 }
1326 doff += SDPCM_HDRLEN;
1327
1328 /* Round send length to next SDIO block */
1329 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1330 uint16 pad = bus->blocksize - (len % bus->blocksize);
1331 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1332 len += pad;
1333 } else if (len % DHD_SDALIGN) {
1334 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1335 }
1336
1337 /* Satisfy length-alignment requirements */
1338 if (forcealign && (len & (ALIGNMENT - 1)))
1339 len = ROUNDUP(len, ALIGNMENT);
1340
1341 ASSERT(ISALIGNED((uintptr)frame, 2));
1342
1343
1344 /* Need to lock here to protect txseq and SDIO tx calls */
1345 dhd_os_sdlock(bus->dhd);
1346
1347 BUS_WAKE(bus);
1348
1349 /* Make sure backplane clock is on */
1350 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
1351
1352 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1353 *(uint16*)frame = htol16((uint16)msglen);
1354 *(((uint16*)frame) + 1) = htol16(~msglen);
1355
1356 /* Software tag: channel, sequence number, data offset */
1357 swheader = ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK)
1358 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1359 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
1360 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1361
1362 if (!TXCTLOK(bus)) {
1363 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1364 __FUNCTION__, bus->tx_max, bus->tx_seq));
1365 bus->ctrl_frame_stat = TRUE;
1366 /* Send from dpc */
1367 bus->ctrl_frame_buf = frame;
1368 bus->ctrl_frame_len = len;
1369
1370 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1371
1372 if (bus->ctrl_frame_stat == FALSE) {
1373 DHD_INFO(("%s: ctrl_frame_stat == FALSE\n", __FUNCTION__));
1374 ret = 0;
1375 } else {
1376 bus->dhd->txcnt_timeout++;
1377 if (!bus->dhd->hang_was_sent)
1378 DHD_ERROR(("%s: ctrl_frame_stat == TRUE txcnt_timeout=%d\n",
1379 __FUNCTION__, bus->dhd->txcnt_timeout));
1380 ret = -1;
1381 bus->ctrl_frame_stat = FALSE;
1382 goto done;
1383 }
1384 }
1385
1386 bus->dhd->txcnt_timeout = 0;
1387
1388 if (ret == -1) {
1389#ifdef DHD_DEBUG
1390 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1391 prhex("Tx Frame", frame, len);
1392 } else if (DHD_HDRS_ON()) {
1393 prhex("TxHdr", frame, MIN(len, 16));
1394 }
1395#endif
1396
1397 do {
1398 ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
1399 frame, len, NULL, NULL, NULL);
1400 ASSERT(ret != BCME_PENDING);
1401
1402 if (ret < 0) {
1403 /* On failure, abort the command and terminate the frame */
1404 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1405 __FUNCTION__, ret));
1406 bus->tx_sderrs++;
1407
1408 bcmsdh_abort(sdh, SDIO_FUNC_2);
1409
1410 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL,
1411 SFC_WF_TERM, NULL);
1412 bus->f1regdata++;
1413
1414 for (i = 0; i < 3; i++) {
1415 uint8 hi, lo;
1416 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1417 SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1418 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1419 SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1420 bus->f1regdata += 2;
1421 if ((hi == 0) && (lo == 0))
1422 break;
1423 }
1424
1425 }
1426 if (ret == 0) {
1427 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1428 }
1429 } while ((ret < 0) && retries++ < TXRETRIES);
1430 }
1431
1432done:
1433 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1434 bus->activity = FALSE;
1435 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
1436 }
1437
1438 dhd_os_sdunlock(bus->dhd);
1439
1440 if (ret)
1441 bus->dhd->tx_ctlerrs++;
1442 else
1443 bus->dhd->tx_ctlpkts++;
1444
1445 if (bus->dhd->txcnt_timeout >= MAX_CNTL_TIMEOUT)
1446 return -ETIMEDOUT;
1447
1448 return ret ? -EIO : 0;
1449}
1450
1451int
1452dhd_bus_rxctl(struct dhd_bus *bus, uchar *msg, uint msglen)
1453{
1454 int timeleft;
1455 uint rxlen = 0;
1456 bool pending;
1457
1458 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
1459
1460 if (bus->dhd->dongle_reset)
1461 return -EIO;
1462
1463 /* Wait until control frame is available */
1464 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1465
1466 dhd_os_sdlock(bus->dhd);
1467 rxlen = bus->rxlen;
1468 bcopy(bus->rxctl, msg, MIN(msglen, rxlen));
1469 bus->rxlen = 0;
1470 dhd_os_sdunlock(bus->dhd);
1471
1472 if (rxlen) {
1473 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1474 __FUNCTION__, rxlen, msglen));
1475 } else if (timeleft == 0) {
1476 DHD_ERROR(("%s: resumed on timeout\n", __FUNCTION__));
1477#ifdef DHD_DEBUG
1478 dhd_os_sdlock(bus->dhd);
1479 dhdsdio_checkdied(bus, NULL, 0);
1480 dhd_os_sdunlock(bus->dhd);
1481#endif /* DHD_DEBUG */
1482 } else if (pending == TRUE) {
1483 DHD_CTL(("%s: canceled\n", __FUNCTION__));
1484 return -ERESTARTSYS;
1485 } else {
1486 DHD_CTL(("%s: resumed for unknown reason?\n", __FUNCTION__));
1487#ifdef DHD_DEBUG
1488 dhd_os_sdlock(bus->dhd);
1489 dhdsdio_checkdied(bus, NULL, 0);
1490 dhd_os_sdunlock(bus->dhd);
1491#endif /* DHD_DEBUG */
1492 }
1493 if (timeleft == 0) {
1494 bus->dhd->rxcnt_timeout++;
1495 DHD_ERROR(("%s: rxcnt_timeout=%d\n", __FUNCTION__, bus->dhd->rxcnt_timeout));
1496 }
1497 else
1498 bus->dhd->rxcnt_timeout = 0;
1499
1500 if (rxlen)
1501 bus->dhd->rx_ctlpkts++;
1502 else
1503 bus->dhd->rx_ctlerrs++;
1504
1505 if (bus->dhd->rxcnt_timeout >= MAX_CNTL_TIMEOUT)
1506 return -ETIMEDOUT;
1507
1508 return rxlen ? (int)rxlen : -EIO;
1509}
1510
1511/* IOVar table */
1512enum {
1513 IOV_INTR = 1,
1514 IOV_POLLRATE,
1515 IOV_SDREG,
1516 IOV_SBREG,
1517 IOV_SDCIS,
1518 IOV_MEMBYTES,
1519 IOV_MEMSIZE,
1520#ifdef DHD_DEBUG
1521 IOV_CHECKDIED,
1522 IOV_SERIALCONS,
1523#endif
1524 IOV_DOWNLOAD,
1525 IOV_SOCRAM_STATE,
1526 IOV_FORCEEVEN,
1527 IOV_SDIOD_DRIVE,
1528 IOV_READAHEAD,
1529 IOV_SDRXCHAIN,
1530 IOV_ALIGNCTL,
1531 IOV_SDALIGN,
1532 IOV_DEVRESET,
1533 IOV_CPU,
1534#ifdef SDTEST
1535 IOV_PKTGEN,
1536 IOV_EXTLOOP,
1537#endif /* SDTEST */
1538 IOV_SPROM,
1539 IOV_TXBOUND,
1540 IOV_RXBOUND,
1541 IOV_TXMINMAX,
1542 IOV_IDLETIME,
1543 IOV_IDLECLOCK,
1544 IOV_SD1IDLE,
1545 IOV_SLEEP,
1546 IOV_DONGLEISOLATION,
1547 IOV_VARS,
1548#ifdef SOFTAP
1549 IOV_FWPATH
1550#endif
1551};
1552
1553const bcm_iovar_t dhdsdio_iovars[] = {
1554 {"intr", IOV_INTR, 0, IOVT_BOOL, 0 },
1555 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0 },
1556 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0 },
1557 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0 },
1558 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0 },
1559 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0 },
1560 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int) },
1561 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0 },
1562 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0 },
1563 {"socram_state", IOV_SOCRAM_STATE, 0, IOVT_BOOL, 0 },
1564 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0 },
1565 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0 },
1566 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0 },
1567 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0 },
1568 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0 },
1569 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0 },
1570 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0 },
1571#ifdef DHD_DEBUG
1572 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
1573 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
1574 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN },
1575 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0 },
1576 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0 },
1577 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0 },
1578 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0 },
1579 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0 },
1580#ifdef DHD_DEBUG
1581 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0 },
1582 {"serial", IOV_SERIALCONS, 0, IOVT_UINT32, 0 },
1583#endif /* DHD_DEBUG */
1584#endif /* DHD_DEBUG */
1585#ifdef SDTEST
1586 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0 },
1587 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t) },
1588#endif /* SDTEST */
1589 {"dngl_isolation", IOV_DONGLEISOLATION, 0, IOVT_UINT32, 0 },
1590#ifdef SOFTAP
1591 {"fwpath", IOV_FWPATH, 0, IOVT_BUFFER, 0 },
1592#endif
1593 {NULL, 0, 0, 0, 0 }
1594};
1595
1596static void
1597dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1598{
1599 uint q1, q2;
1600
1601 if (!div) {
1602 bcm_bprintf(strbuf, "%s N/A", desc);
1603 } else {
1604 q1 = num / div;
1605 q2 = (100 * (num - (q1 * div))) / div;
1606 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1607 }
1608}
1609
1610void
1611dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1612{
1613 dhd_bus_t *bus = dhdp->bus;
1614
1615 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1616 bcm_bprintf(strbuf, "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1617 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1618 bcm_bprintf(strbuf, "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1619 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max, bus->rxskip,
1620 bus->rxlen, bus->rx_seq);
1621 bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1622 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1623 bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1624 bus->pollrate, bus->pollcnt, bus->regfails);
1625
1626 bcm_bprintf(strbuf, "\nAdditional counters:\n");
1627 bcm_bprintf(strbuf, "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1628 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1629 bus->rxc_errors);
1630 bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1631 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1632 bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n",
1633 bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
1634 bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1635 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1636 bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1637 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs, bus->f2rxdata,
1638 bus->f2txdata, bus->f1regdata);
1639 {
1640 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1641 (bus->f2rxhdrs + bus->f2rxdata));
1642 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets, bus->f1regdata);
1643 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1644 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1645 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets, bus->intrcount);
1646 bcm_bprintf(strbuf, "\n");
1647
1648 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1649 bus->dhd->rx_packets);
1650 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts, bus->rxglomframes);
1651 bcm_bprintf(strbuf, "\n");
1652
1653 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets, bus->f2txdata);
1654 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets, bus->f1regdata);
1655 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1656 (bus->f2txdata + bus->f1regdata));
1657 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets, bus->intrcount);
1658 bcm_bprintf(strbuf, "\n");
1659
1660 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1661 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1662 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1663 dhd_dump_pct(strbuf, ", pkts/f1sd",
1664 (bus->dhd->tx_packets + bus->dhd->rx_packets), bus->f1regdata);
1665 dhd_dump_pct(strbuf, ", pkts/sd",
1666 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1667 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1668 dhd_dump_pct(strbuf, ", pkts/int",
1669 (bus->dhd->tx_packets + bus->dhd->rx_packets), bus->intrcount);
1670 bcm_bprintf(strbuf, "\n\n");
1671 }
1672
1673#ifdef SDTEST
1674 if (bus->pktgen_count) {
1675 bcm_bprintf(strbuf, "pktgen config and count:\n");
1676 bcm_bprintf(strbuf, "freq %d count %d print %d total %d min %d len %d\n",
1677 bus->pktgen_freq, bus->pktgen_count, bus->pktgen_print,
1678 bus->pktgen_total, bus->pktgen_minlen, bus->pktgen_maxlen);
1679 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1680 bus->pktgen_sent, bus->pktgen_rcvd, bus->pktgen_fail);
1681 }
1682#endif /* SDTEST */
1683#ifdef DHD_DEBUG
1684 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1685 bus->dpc_sched, (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1686 bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize, bus->roundup);
1687#endif /* DHD_DEBUG */
1688 bcm_bprintf(strbuf, "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1689 bus->clkstate, bus->activity, bus->idletime, bus->idlecount, bus->sleeping);
1690}
1691
1692void
1693dhd_bus_clearcounts(dhd_pub_t *dhdp)
1694{
1695 dhd_bus_t *bus = (dhd_bus_t *)dhdp->bus;
1696
1697 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1698 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1699 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1700 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1701 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1702 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1703}
1704
1705#ifdef SDTEST
1706static int
1707dhdsdio_pktgen_get(dhd_bus_t *bus, uint8 *arg)
1708{
1709 dhd_pktgen_t pktgen;
1710
1711 pktgen.version = DHD_PKTGEN_VERSION;
1712 pktgen.freq = bus->pktgen_freq;
1713 pktgen.count = bus->pktgen_count;
1714 pktgen.print = bus->pktgen_print;
1715 pktgen.total = bus->pktgen_total;
1716 pktgen.minlen = bus->pktgen_minlen;
1717 pktgen.maxlen = bus->pktgen_maxlen;
1718 pktgen.numsent = bus->pktgen_sent;
1719 pktgen.numrcvd = bus->pktgen_rcvd;
1720 pktgen.numfail = bus->pktgen_fail;
1721 pktgen.mode = bus->pktgen_mode;
1722 pktgen.stop = bus->pktgen_stop;
1723
1724 bcopy(&pktgen, arg, sizeof(pktgen));
1725
1726 return 0;
1727}
1728
1729static int
1730dhdsdio_pktgen_set(dhd_bus_t *bus, uint8 *arg)
1731{
1732 dhd_pktgen_t pktgen;
1733 uint oldcnt, oldmode;
1734
1735 bcopy(arg, &pktgen, sizeof(pktgen));
1736 if (pktgen.version != DHD_PKTGEN_VERSION)
1737 return BCME_BADARG;
1738
1739 oldcnt = bus->pktgen_count;
1740 oldmode = bus->pktgen_mode;
1741
1742 bus->pktgen_freq = pktgen.freq;
1743 bus->pktgen_count = pktgen.count;
1744 bus->pktgen_print = pktgen.print;
1745 bus->pktgen_total = pktgen.total;
1746 bus->pktgen_minlen = pktgen.minlen;
1747 bus->pktgen_maxlen = pktgen.maxlen;
1748 bus->pktgen_mode = pktgen.mode;
1749 bus->pktgen_stop = pktgen.stop;
1750
1751 bus->pktgen_tick = bus->pktgen_ptick = 0;
1752 bus->pktgen_len = MAX(bus->pktgen_len, bus->pktgen_minlen);
1753 bus->pktgen_len = MIN(bus->pktgen_len, bus->pktgen_maxlen);
1754
1755 /* Clear counts for a new pktgen (mode change, or was stopped) */
1756 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1757 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1758
1759 return 0;
1760}
1761#endif /* SDTEST */
1762
1763static int
1764dhdsdio_membytes(dhd_bus_t *bus, bool write, uint32 address, uint8 *data, uint size)
1765{
1766 int bcmerror = 0;
1767 uint32 sdaddr;
1768 uint dsize;
1769
1770 /* Determine initial transfer parameters */
1771 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1772 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1773 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1774 else
1775 dsize = size;
1776
1777 /* Set the backplane window to include the start address */
1778 if ((bcmerror = dhdsdio_set_siaddr_window(bus, address))) {
1779 DHD_ERROR(("%s: window change failed\n", __FUNCTION__));
1780 goto xfer_done;
1781 }
1782
1783 /* Do the transfer(s) */
1784 while (size) {
1785 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1786 __FUNCTION__, (write ? "write" : "read"), dsize, sdaddr,
1787 (address & SBSDIO_SBWINDOW_MASK)));
1788 if ((bcmerror = bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize))) {
1789 DHD_ERROR(("%s: membytes transfer failed\n", __FUNCTION__));
1790 break;
1791 }
1792
1793 /* Adjust for next transfer (if any) */
1794 if ((size -= dsize)) {
1795 data += dsize;
1796 address += dsize;
1797 if ((bcmerror = dhdsdio_set_siaddr_window(bus, address))) {
1798 DHD_ERROR(("%s: window change failed\n", __FUNCTION__));
1799 break;
1800 }
1801 sdaddr = 0;
1802 dsize = MIN(SBSDIO_SB_OFT_ADDR_LIMIT, size);
1803 }
1804
1805 }
1806
1807xfer_done:
1808 /* Return the window to backplane enumeration space for core access */
1809 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1810 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n", __FUNCTION__,
1811 bcmsdh_cur_sbwad(bus->sdh)));
1812 }
1813
1814 return bcmerror;
1815}
1816
1817#ifdef DHD_DEBUG
1818static int
1819dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1820{
1821 uint32 addr;
1822 int rv;
1823
1824 /* Read last word in memory to determine address of sdpcm_shared structure */
1825 if ((rv = dhdsdio_membytes(bus, FALSE, bus->ramsize - 4, (uint8 *)&addr, 4)) < 0)
1826 return rv;
1827
1828 addr = ltoh32(addr);
1829
1830 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1831
1832 /*
1833 * Check if addr is valid.
1834 * NVRAM length at the end of memory should have been overwritten.
1835 */
1836 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1837 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n", __FUNCTION__, addr));
1838 return BCME_ERROR;
1839 }
1840
1841 /* Read hndrte_shared structure */
1842 if ((rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *)sh, sizeof(sdpcm_shared_t))) < 0)
1843 return rv;
1844
1845 /* Endianness */
1846 sh->flags = ltoh32(sh->flags);
1847 sh->trap_addr = ltoh32(sh->trap_addr);
1848 sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
1849 sh->assert_file_addr = ltoh32(sh->assert_file_addr);
1850 sh->assert_line = ltoh32(sh->assert_line);
1851 sh->console_addr = ltoh32(sh->console_addr);
1852 sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
1853
1854 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) == 3 && SDPCM_SHARED_VERSION == 1)
1855 return BCME_OK;
1856
1857 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1858 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1859 "is different than sdpcm_shared version %d in dongle\n",
1860 __FUNCTION__, SDPCM_SHARED_VERSION,
1861 sh->flags & SDPCM_SHARED_VERSION_MASK));
1862 return BCME_ERROR;
1863 }
1864
1865 return BCME_OK;
1866}
1867
1868
1869static int
1870dhdsdio_readconsole(dhd_bus_t *bus)
1871{
1872 dhd_console_t *c = &bus->console;
1873 uint8 line[CONSOLE_LINE_MAX], ch;
1874 uint32 n, idx, addr;
1875 int rv;
1876
1877 /* Don't do anything until FWREADY updates console address */
1878 if (bus->console_addr == 0)
1879 return 0;
1880
1881 /* Read console log struct */
1882 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, log);
1883 if ((rv = dhdsdio_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0)
1884 return rv;
1885
1886 /* Allocate console buffer (one time only) */
1887 if (c->buf == NULL) {
1888 c->bufsize = ltoh32(c->log.buf_size);
1889 if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL)
1890 return BCME_NOMEM;
1891 }
1892
1893 idx = ltoh32(c->log.idx);
1894
1895 /* Protect against corrupt value */
1896 if (idx > c->bufsize)
1897 return BCME_ERROR;
1898
1899 /* Skip reading the console buffer if the index pointer has not moved */
1900 if (idx == c->last)
1901 return BCME_OK;
1902
1903 /* Read the console buffer */
1904 addr = ltoh32(c->log.buf);
1905 if ((rv = dhdsdio_membytes(bus, FALSE, addr, c->buf, c->bufsize)) < 0)
1906 return rv;
1907
1908 while (c->last != idx) {
1909 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
1910 if (c->last == idx) {
1911 /* This would output a partial line. Instead, back up
1912 * the buffer pointer and output this line next time around.
1913 */
1914 if (c->last >= n)
1915 c->last -= n;
1916 else
1917 c->last = c->bufsize - n;
1918 goto break2;
1919 }
1920 ch = c->buf[c->last];
1921 c->last = (c->last + 1) % c->bufsize;
1922 if (ch == '\n')
1923 break;
1924 line[n] = ch;
1925 }
1926
1927 if (n > 0) {
1928 if (line[n - 1] == '\r')
1929 n--;
1930 line[n] = 0;
1931 printf("CONSOLE: %s\n", line);
1932 }
1933 }
1934break2:
1935
1936 return BCME_OK;
1937}
1938
1939static int
1940dhdsdio_checkdied(dhd_bus_t *bus, char *data, uint size)
1941{
1942 int bcmerror = 0;
1943 uint msize = 512;
1944 char *mbuffer = NULL;
1945 char *console_buffer = NULL;
1946 uint maxstrlen = 256;
1947 char *str = NULL;
1948 trap_t tr;
1949 sdpcm_shared_t sdpcm_shared;
1950 struct bcmstrbuf strbuf;
1951 uint32 console_ptr, console_size, console_index;
1952 uint8 line[CONSOLE_LINE_MAX], ch;
1953 uint32 n, i, addr;
1954 int rv;
1955
1956 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
1957
1958 if (data == NULL) {
1959 /*
1960 * Called after a rx ctrl timeout. "data" is NULL.
1961 * allocate memory to trace the trap or assert.
1962 */
1963 size = msize;
1964 mbuffer = data = MALLOC(bus->dhd->osh, msize);
1965 if (mbuffer == NULL) {
1966 DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize));
1967 bcmerror = BCME_NOMEM;
1968 goto done;
1969 }
1970 }
1971
1972 if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) {
1973 DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen));
1974 bcmerror = BCME_NOMEM;
1975 goto done;
1976 }
1977
1978 if ((bcmerror = dhdsdio_readshared(bus, &sdpcm_shared)) < 0)
1979 goto done;
1980
1981 bcm_binit(&strbuf, data, size);
1982
1983 bcm_bprintf(&strbuf, "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1984 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1985
1986 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1987 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1988 * (Avoids conflict with real asserts for programmatic parsing of output.)
1989 */
1990 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1991 }
1992
1993 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT|SDPCM_SHARED_TRAP)) == 0) {
1994 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1995 * (Avoids conflict with real asserts for programmatic parsing of output.)
1996 */
1997 bcm_bprintf(&strbuf, "No trap%s in dongle",
1998 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1999 ?"/assrt" :"");
2000 } else {
2001 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2002 /* Download assert */
2003 bcm_bprintf(&strbuf, "Dongle assert");
2004 if (sdpcm_shared.assert_exp_addr != 0) {
2005 str[0] = '\0';
2006 if ((bcmerror = dhdsdio_membytes(bus, FALSE,
2007 sdpcm_shared.assert_exp_addr,
2008 (uint8 *)str, maxstrlen)) < 0)
2009 goto done;
2010
2011 str[maxstrlen - 1] = '\0';
2012 bcm_bprintf(&strbuf, " expr \"%s\"", str);
2013 }
2014
2015 if (sdpcm_shared.assert_file_addr != 0) {
2016 str[0] = '\0';
2017 if ((bcmerror = dhdsdio_membytes(bus, FALSE,
2018 sdpcm_shared.assert_file_addr,
2019 (uint8 *)str, maxstrlen)) < 0)
2020 goto done;
2021
2022 str[maxstrlen - 1] = '\0';
2023 bcm_bprintf(&strbuf, " file \"%s\"", str);
2024 }
2025
2026 bcm_bprintf(&strbuf, " line %d ", sdpcm_shared.assert_line);
2027 }
2028
2029 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2030 if ((bcmerror = dhdsdio_membytes(bus, FALSE,
2031 sdpcm_shared.trap_addr,
2032 (uint8*)&tr, sizeof(trap_t))) < 0)
2033 goto done;
2034
2035 bcm_bprintf(&strbuf,
2036 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2037 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2038 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, "
2039 "r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n\n",
2040 ltoh32(tr.type), ltoh32(tr.epc), ltoh32(tr.cpsr), ltoh32(tr.spsr),
2041 ltoh32(tr.r13), ltoh32(tr.r14), ltoh32(tr.pc),
2042 ltoh32(sdpcm_shared.trap_addr),
2043 ltoh32(tr.r0), ltoh32(tr.r1), ltoh32(tr.r2), ltoh32(tr.r3),
2044 ltoh32(tr.r4), ltoh32(tr.r5), ltoh32(tr.r6), ltoh32(tr.r7));
2045
2046 addr = sdpcm_shared.console_addr + OFFSETOF(hndrte_cons_t, log);
2047 if ((rv = dhdsdio_membytes(bus, FALSE, addr,
2048 (uint8 *)&console_ptr, sizeof(console_ptr))) < 0)
2049 goto printbuf;
2050
2051 addr = sdpcm_shared.console_addr + OFFSETOF(hndrte_cons_t, log.buf_size);
2052 if ((rv = dhdsdio_membytes(bus, FALSE, addr,
2053 (uint8 *)&console_size, sizeof(console_size))) < 0)
2054 goto printbuf;
2055
2056 addr = sdpcm_shared.console_addr + OFFSETOF(hndrte_cons_t, log.idx);
2057 if ((rv = dhdsdio_membytes(bus, FALSE, addr,
2058 (uint8 *)&console_index, sizeof(console_index))) < 0)
2059 goto printbuf;
2060
2061 console_ptr = ltoh32(console_ptr);
2062 console_size = ltoh32(console_size);
2063 console_index = ltoh32(console_index);
2064
2065 if (console_size > CONSOLE_BUFFER_MAX ||
2066 !(console_buffer = MALLOC(bus->dhd->osh, console_size)))
2067 goto printbuf;
2068
2069 if ((rv = dhdsdio_membytes(bus, FALSE, console_ptr,
2070 (uint8 *)console_buffer, console_size)) < 0)
2071 goto printbuf;
2072
2073 for (i = 0, n = 0; i < console_size; i += n + 1) {
2074 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2075 ch = console_buffer[(console_index + i + n) % console_size];
2076 if (ch == '\n')
2077 break;
2078 line[n] = ch;
2079 }
2080
2081
2082 if (n > 0) {
2083 if (line[n - 1] == '\r')
2084 n--;
2085 line[n] = 0;
2086 /* Don't use DHD_ERROR macro since we print
2087 * a lot of information quickly. The macro
2088 * will truncate a lot of the printfs
2089 */
2090
2091 if (dhd_msg_level & DHD_ERROR_VAL) {
2092 printf("CONSOLE: %s\n", line);
2093 DHD_BLOG(line, strlen(line) + 1);
2094 }
2095 }
2096 }
2097 }
2098 }
2099
2100printbuf:
2101 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) {
2102 DHD_ERROR(("%s: %s\n", __FUNCTION__, strbuf.origbuf));
2103 }
2104
2105
2106done:
2107 if (mbuffer)
2108 MFREE(bus->dhd->osh, mbuffer, msize);
2109 if (str)
2110 MFREE(bus->dhd->osh, str, maxstrlen);
2111 if (console_buffer)
2112 MFREE(bus->dhd->osh, console_buffer, console_size);
2113
2114 return bcmerror;
2115}
2116#endif /* #ifdef DHD_DEBUG */
2117
2118
2119int
2120dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2121{
2122 int bcmerror = BCME_OK;
2123
2124 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
2125
2126 /* Basic sanity checks */
2127 if (bus->dhd->up) {
2128 bcmerror = BCME_NOTDOWN;
2129 goto err;
2130 }
2131 if (!len) {
2132 bcmerror = BCME_BUFTOOSHORT;
2133 goto err;
2134 }
2135
2136 /* Free the old ones and replace with passed variables */
2137 if (bus->vars)
2138 MFREE(bus->dhd->osh, bus->vars, bus->varsz);
2139
2140 bus->vars = MALLOC(bus->dhd->osh, len);
2141 bus->varsz = bus->vars ? len : 0;
2142 if (bus->vars == NULL) {
2143 bcmerror = BCME_NOMEM;
2144 goto err;
2145 }
2146
2147 /* Copy the passed variables, which should include the terminating double-null */
2148 bcopy(arg, bus->vars, bus->varsz);
2149err:
2150 return bcmerror;
2151}
2152
2153#ifdef DHD_DEBUG
2154
2155#define CC_PLL_CHIPCTRL_SERIAL_ENAB (1 << 24)
2156static int
2157dhd_serialconsole(dhd_bus_t *bus, bool set, bool enable, int *bcmerror)
2158{
2159 int int_val;
2160 uint32 addr, data;
2161
2162
2163 addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_addr);
2164 data = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol_data);
2165 *bcmerror = 0;
2166
2167 bcmsdh_reg_write(bus->sdh, addr, 4, 1);
2168 if (bcmsdh_regfail(bus->sdh)) {
2169 *bcmerror = BCME_SDIO_ERROR;
2170 return -1;
2171 }
2172 int_val = bcmsdh_reg_read(bus->sdh, data, 4);
2173 if (bcmsdh_regfail(bus->sdh)) {
2174 *bcmerror = BCME_SDIO_ERROR;
2175 return -1;
2176 }
2177 if (!set)
2178 return (int_val & CC_PLL_CHIPCTRL_SERIAL_ENAB);
2179 if (enable)
2180 int_val |= CC_PLL_CHIPCTRL_SERIAL_ENAB;
2181 else
2182 int_val &= ~CC_PLL_CHIPCTRL_SERIAL_ENAB;
2183 bcmsdh_reg_write(bus->sdh, data, 4, int_val);
2184 if (bcmsdh_regfail(bus->sdh)) {
2185 *bcmerror = BCME_SDIO_ERROR;
2186 return -1;
2187 }
2188 if (bus->sih->chip == BCM4330_CHIP_ID) {
2189 uint32 chipcontrol;
2190 addr = SI_ENUM_BASE + OFFSETOF(chipcregs_t, chipcontrol);
2191 chipcontrol = bcmsdh_reg_read(bus->sdh, addr, 4);
2192 chipcontrol &= ~0x8;
2193 if (enable) {
2194 chipcontrol |= 0x8;
2195 chipcontrol &= ~0x3;
2196 }
2197 bcmsdh_reg_write(bus->sdh, addr, 4, chipcontrol);
2198 }
2199
2200 return (int_val & CC_PLL_CHIPCTRL_SERIAL_ENAB);
2201}
2202#endif
2203
2204static int
2205dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name,
2206 void *params, int plen, void *arg, int len, int val_size)
2207{
2208 int bcmerror = 0;
2209 int32 int_val = 0;
2210 bool bool_val = 0;
2211
2212 DHD_ERROR(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n",
2213 __FUNCTION__, actionid, name, params, plen, arg, len, val_size));
2214
2215 if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0)
2216 goto exit;
2217
2218 if (plen >= (int)sizeof(int_val))
2219 bcopy(params, &int_val, sizeof(int_val));
2220
2221 bool_val = (int_val != 0) ? TRUE : FALSE;
2222
2223
2224 /* Some ioctls use the bus */
2225 dhd_os_sdlock(bus->dhd);
2226
2227 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2228 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2229 actionid == IOV_GVAL(IOV_DEVRESET))) {
2230 bcmerror = BCME_NOTREADY;
2231 goto exit;
2232 }
2233
2234 /* Handle sleep stuff before any clock mucking */
2235 if (vi->varid == IOV_SLEEP) {
2236 if (IOV_ISSET(actionid)) {
2237 bcmerror = dhdsdio_bussleep(bus, bool_val);
2238 } else {
2239 int_val = (int32)bus->sleeping;
2240 bcopy(&int_val, arg, val_size);
2241 }
2242 goto exit;
2243 }
2244
2245 /* Request clock to allow SDIO accesses */
2246 if (!bus->dhd->dongle_reset) {
2247 BUS_WAKE(bus);
2248 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2249 }
2250
2251 switch (actionid) {
2252 case IOV_GVAL(IOV_INTR):
2253 int_val = (int32)bus->intr;
2254 bcopy(&int_val, arg, val_size);
2255 break;
2256
2257 case IOV_SVAL(IOV_INTR):
2258 bus->intr = bool_val;
2259 bus->intdis = FALSE;
2260 if (bus->dhd->up) {
2261 if (bus->intr) {
2262 DHD_INTR(("%s: enable SDIO device interrupts\n", __FUNCTION__));
2263 bcmsdh_intr_enable(bus->sdh);
2264 } else {
2265 DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
2266 bcmsdh_intr_disable(bus->sdh);
2267 }
2268 }
2269 break;
2270
2271 case IOV_GVAL(IOV_POLLRATE):
2272 int_val = (int32)bus->pollrate;
2273 bcopy(&int_val, arg, val_size);
2274 break;
2275
2276 case IOV_SVAL(IOV_POLLRATE):
2277 bus->pollrate = (uint)int_val;
2278 bus->poll = (bus->pollrate != 0);
2279 break;
2280
2281 case IOV_GVAL(IOV_IDLETIME):
2282 int_val = bus->idletime;
2283 bcopy(&int_val, arg, val_size);
2284 break;
2285
2286 case IOV_SVAL(IOV_IDLETIME):
2287 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE)) {
2288 bcmerror = BCME_BADARG;
2289 } else {
2290 bus->idletime = int_val;
2291 }
2292 break;
2293
2294 case IOV_GVAL(IOV_IDLECLOCK):
2295 int_val = (int32)bus->idleclock;
2296 bcopy(&int_val, arg, val_size);
2297 break;
2298
2299 case IOV_SVAL(IOV_IDLECLOCK):
2300 bus->idleclock = int_val;
2301 break;
2302
2303 case IOV_GVAL(IOV_SD1IDLE):
2304 int_val = (int32)sd1idle;
2305 bcopy(&int_val, arg, val_size);
2306 break;
2307
2308 case IOV_SVAL(IOV_SD1IDLE):
2309 sd1idle = bool_val;
2310 break;
2311
2312
2313 case IOV_SVAL(IOV_MEMBYTES):
2314 case IOV_GVAL(IOV_MEMBYTES):
2315 {
2316 uint32 address;
2317 uint size, dsize;
2318 uint8 *data;
2319
2320 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2321
2322 ASSERT(plen >= 2*sizeof(int));
2323
2324 address = (uint32)int_val;
2325 bcopy((char *)params + sizeof(int_val), &int_val, sizeof(int_val));
2326 size = (uint)int_val;
2327
2328 /* Do some validation */
2329 dsize = set ? plen - (2 * sizeof(int)) : len;
2330 if (dsize < size) {
2331 DHD_ERROR(("%s: error on %s membytes, addr 0x%08x size %d dsize %d\n",
2332 __FUNCTION__, (set ? "set" : "get"), address, size, dsize));
2333 bcmerror = BCME_BADARG;
2334 break;
2335 }
2336
2337 DHD_INFO(("%s: Request to %s %d bytes at address 0x%08x\n", __FUNCTION__,
2338 (set ? "write" : "read"), size, address));
2339
2340 /* If we know about SOCRAM, check for a fit */
2341 if ((bus->orig_ramsize) &&
2342 ((address > bus->orig_ramsize) || (address + size > bus->orig_ramsize)))
2343 {
2344 uint8 enable, protect;
2345 si_socdevram(bus->sih, FALSE, &enable, &protect);
2346 if (!enable || protect) {
2347 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d bytes at 0x%08x\n",
2348 __FUNCTION__, bus->orig_ramsize, size, address));
2349 DHD_ERROR(("%s: socram enable %d, protect %d\n",
2350 __FUNCTION__, enable, protect));
2351 bcmerror = BCME_BADARG;
2352 break;
2353 }
2354 if (enable && (bus->sih->chip == BCM4330_CHIP_ID)) {
2355 uint32 devramsize = si_socdevram_size(bus->sih);
2356 if ((address < SOCDEVRAM_4330_ARM_ADDR) ||
2357 (address + size > (SOCDEVRAM_4330_ARM_ADDR + devramsize))) {
2358 DHD_ERROR(("%s: bad address 0x%08x, size 0x%08x\n",
2359 __FUNCTION__, address, size));
2360 DHD_ERROR(("%s: socram range 0x%08x,size 0x%08x\n",
2361 __FUNCTION__, SOCDEVRAM_4330_ARM_ADDR, devramsize));
2362 bcmerror = BCME_BADARG;
2363 break;
2364 }
2365 /* move it such that address is real now */
2366 address -= SOCDEVRAM_4330_ARM_ADDR;
2367 address += SOCDEVRAM_4330_BP_ADDR;
2368 DHD_INFO(("%s: Request to %s %d bytes @ Mapped address 0x%08x\n",
2369 __FUNCTION__, (set ? "write" : "read"), size, address));
2370 }
2371 }
2372
2373 /* Generate the actual data pointer */
2374 data = set ? (uint8*)params + 2 * sizeof(int): (uint8*)arg;
2375
2376 /* Call to do the transfer */
2377 bcmerror = dhdsdio_membytes(bus, set, address, data, size);
2378
2379 break;
2380 }
2381
2382 case IOV_GVAL(IOV_MEMSIZE):
2383 int_val = (int32)bus->ramsize;
2384 bcopy(&int_val, arg, val_size);
2385 break;
2386
2387 case IOV_GVAL(IOV_SDIOD_DRIVE):
2388 int_val = (int32)dhd_sdiod_drive_strength;
2389 bcopy(&int_val, arg, val_size);
2390 break;
2391
2392 case IOV_SVAL(IOV_SDIOD_DRIVE):
2393 dhd_sdiod_drive_strength = int_val;
2394 si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh, dhd_sdiod_drive_strength);
2395 break;
2396
2397 case IOV_SVAL(IOV_DOWNLOAD):
2398 bcmerror = dhdsdio_download_state(bus, bool_val);
2399 break;
2400
2401 case IOV_SVAL(IOV_SOCRAM_STATE):
2402 bcmerror = dhdsdio_download_state(bus, bool_val);
2403 break;
2404
2405 case IOV_SVAL(IOV_VARS):
2406 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2407 break;
2408
2409 case IOV_GVAL(IOV_READAHEAD):
2410 int_val = (int32)dhd_readahead;
2411 bcopy(&int_val, arg, val_size);
2412 break;
2413
2414 case IOV_SVAL(IOV_READAHEAD):
2415 if (bool_val && !dhd_readahead)
2416 bus->nextlen = 0;
2417 dhd_readahead = bool_val;
2418 break;
2419
2420 case IOV_GVAL(IOV_SDRXCHAIN):
2421 int_val = (int32)bus->use_rxchain;
2422 bcopy(&int_val, arg, val_size);
2423 break;
2424
2425 case IOV_SVAL(IOV_SDRXCHAIN):
2426 if (bool_val && !bus->sd_rxchain)
2427 bcmerror = BCME_UNSUPPORTED;
2428 else
2429 bus->use_rxchain = bool_val;
2430 break;
2431 case IOV_GVAL(IOV_ALIGNCTL):
2432 int_val = (int32)dhd_alignctl;
2433 bcopy(&int_val, arg, val_size);
2434 break;
2435
2436 case IOV_SVAL(IOV_ALIGNCTL):
2437 dhd_alignctl = bool_val;
2438 break;
2439
2440 case IOV_GVAL(IOV_SDALIGN):
2441 int_val = DHD_SDALIGN;
2442 bcopy(&int_val, arg, val_size);
2443 break;
2444
2445#ifdef DHD_DEBUG
2446 case IOV_GVAL(IOV_VARS):
2447 if (bus->varsz < (uint)len)
2448 bcopy(bus->vars, arg, bus->varsz);
2449 else
2450 bcmerror = BCME_BUFTOOSHORT;
2451 break;
2452#endif /* DHD_DEBUG */
2453
2454#ifdef DHD_DEBUG
2455 case IOV_GVAL(IOV_SDREG):
2456 {
2457 sdreg_t *sd_ptr;
2458 uint32 addr, size;
2459
2460 sd_ptr = (sdreg_t *)params;
2461
2462 addr = (uintptr)bus->regs + sd_ptr->offset;
2463 size = sd_ptr->func;
2464 int_val = (int32)bcmsdh_reg_read(bus->sdh, addr, size);
2465 if (bcmsdh_regfail(bus->sdh))
2466 bcmerror = BCME_SDIO_ERROR;
2467 bcopy(&int_val, arg, sizeof(int32));
2468 break;
2469 }
2470
2471 case IOV_SVAL(IOV_SDREG):
2472 {
2473 sdreg_t *sd_ptr;
2474 uint32 addr, size;
2475
2476 sd_ptr = (sdreg_t *)params;
2477
2478 addr = (uintptr)bus->regs + sd_ptr->offset;
2479 size = sd_ptr->func;
2480 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2481 if (bcmsdh_regfail(bus->sdh))
2482 bcmerror = BCME_SDIO_ERROR;
2483 break;
2484 }
2485
2486 /* Same as above, but offset is not backplane (not SDIO core) */
2487 case IOV_GVAL(IOV_SBREG):
2488 {
2489 sdreg_t sdreg;
2490 uint32 addr, size;
2491
2492 bcopy(params, &sdreg, sizeof(sdreg));
2493
2494 addr = SI_ENUM_BASE + sdreg.offset;
2495 size = sdreg.func;
2496 int_val = (int32)bcmsdh_reg_read(bus->sdh, addr, size);
2497 if (bcmsdh_regfail(bus->sdh))
2498 bcmerror = BCME_SDIO_ERROR;
2499 bcopy(&int_val, arg, sizeof(int32));
2500 break;
2501 }
2502
2503 case IOV_SVAL(IOV_SBREG):
2504 {
2505 sdreg_t sdreg;
2506 uint32 addr, size;
2507
2508 bcopy(params, &sdreg, sizeof(sdreg));
2509
2510 addr = SI_ENUM_BASE + sdreg.offset;
2511 size = sdreg.func;
2512 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2513 if (bcmsdh_regfail(bus->sdh))
2514 bcmerror = BCME_SDIO_ERROR;
2515 break;
2516 }
2517
2518 case IOV_GVAL(IOV_SDCIS):
2519 {
2520 *(char *)arg = 0;
2521
2522 bcmstrcat(arg, "\nFunc 0\n");
2523 bcmsdh_cis_read(bus->sdh, 0x10, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
2524 bcmstrcat(arg, "\nFunc 1\n");
2525 bcmsdh_cis_read(bus->sdh, 0x11, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
2526 bcmstrcat(arg, "\nFunc 2\n");
2527 bcmsdh_cis_read(bus->sdh, 0x12, (uint8 *)arg + strlen(arg), SBSDIO_CIS_SIZE_LIMIT);
2528 break;
2529 }
2530
2531 case IOV_GVAL(IOV_FORCEEVEN):
2532 int_val = (int32)forcealign;
2533 bcopy(&int_val, arg, val_size);
2534 break;
2535
2536 case IOV_SVAL(IOV_FORCEEVEN):
2537 forcealign = bool_val;
2538 break;
2539
2540 case IOV_GVAL(IOV_TXBOUND):
2541 int_val = (int32)dhd_txbound;
2542 bcopy(&int_val, arg, val_size);
2543 break;
2544
2545 case IOV_SVAL(IOV_TXBOUND):
2546 dhd_txbound = (uint)int_val;
2547 break;
2548
2549 case IOV_GVAL(IOV_RXBOUND):
2550 int_val = (int32)dhd_rxbound;
2551 bcopy(&int_val, arg, val_size);
2552 break;
2553
2554 case IOV_SVAL(IOV_RXBOUND):
2555 dhd_rxbound = (uint)int_val;
2556 break;
2557
2558 case IOV_GVAL(IOV_TXMINMAX):
2559 int_val = (int32)dhd_txminmax;
2560 bcopy(&int_val, arg, val_size);
2561 break;
2562
2563 case IOV_SVAL(IOV_TXMINMAX):
2564 dhd_txminmax = (uint)int_val;
2565 break;
2566
2567 case IOV_GVAL(IOV_SERIALCONS):
2568 int_val = dhd_serialconsole(bus, FALSE, 0, &bcmerror);
2569 if (bcmerror != 0)
2570 break;
2571
2572 bcopy(&int_val, arg, val_size);
2573 break;
2574
2575 case IOV_SVAL(IOV_SERIALCONS):
2576 dhd_serialconsole(bus, TRUE, bool_val, &bcmerror);
2577 break;
2578
2579
2580
2581#endif /* DHD_DEBUG */
2582
2583
2584#ifdef SDTEST
2585 case IOV_GVAL(IOV_EXTLOOP):
2586 int_val = (int32)bus->ext_loop;
2587 bcopy(&int_val, arg, val_size);
2588 break;
2589
2590 case IOV_SVAL(IOV_EXTLOOP):
2591 bus->ext_loop = bool_val;
2592 break;
2593
2594 case IOV_GVAL(IOV_PKTGEN):
2595 bcmerror = dhdsdio_pktgen_get(bus, arg);
2596 break;
2597
2598 case IOV_SVAL(IOV_PKTGEN):
2599 bcmerror = dhdsdio_pktgen_set(bus, arg);
2600 break;
2601#endif /* SDTEST */
2602
2603
2604 case IOV_GVAL(IOV_DONGLEISOLATION):
2605 int_val = bus->dhd->dongle_isolation;
2606 bcopy(&int_val, arg, val_size);
2607 break;
2608
2609 case IOV_SVAL(IOV_DONGLEISOLATION):
2610 bus->dhd->dongle_isolation = bool_val;
2611 break;
2612
2613 case IOV_SVAL(IOV_DEVRESET):
2614 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d busstate=%d\n",
2615 __FUNCTION__, bool_val, bus->dhd->dongle_reset,
2616 bus->dhd->busstate));
2617
2618 ASSERT(bus->dhd->osh);
2619 /* ASSERT(bus->cl_devid); */
2620
2621 dhd_bus_devreset(bus->dhd, (uint8)bool_val);
2622
2623 break;
2624#ifdef SOFTAP
2625 case IOV_GVAL(IOV_FWPATH):
2626 {
2627 uint32 fw_path_len;
2628
2629 fw_path_len = strlen(bus->fw_path);
2630 DHD_INFO(("[softap] get fwpath, l=%d\n", len));
2631
2632 if (fw_path_len > len-1) {
2633 bcmerror = BCME_BUFTOOSHORT;
2634 break;
2635 }
2636
2637 if (fw_path_len) {
2638 bcopy(bus->fw_path, arg, fw_path_len);
2639 ((uchar*)arg)[fw_path_len] = 0;
2640 }
2641 break;
2642 }
2643
2644 case IOV_SVAL(IOV_FWPATH):
2645 DHD_INFO(("[softap] set fwpath, idx=%d\n", int_val));
2646
2647 switch (int_val) {
2648 case 1:
2649 bus->fw_path = fw_path; /* ordinary one */
2650 break;
2651 case 2:
2652 bus->fw_path = fw_path2;
2653 break;
2654 default:
2655 bcmerror = BCME_BADARG;
2656 break;
2657 }
2658
2659 DHD_INFO(("[softap] new fw path: %s\n", (bus->fw_path[0] ? bus->fw_path : "NULL")));
2660 break;
2661
2662#endif /* SOFTAP */
2663 case IOV_GVAL(IOV_DEVRESET):
2664 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __FUNCTION__));
2665
2666 /* Get its status */
2667 int_val = (bool) bus->dhd->dongle_reset;
2668 bcopy(&int_val, arg, val_size);
2669
2670 break;
2671
2672 default:
2673 bcmerror = BCME_UNSUPPORTED;
2674 break;
2675 }
2676
2677exit:
2678 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2679 bus->activity = FALSE;
2680 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
2681 }
2682
2683 dhd_os_sdunlock(bus->dhd);
2684
2685 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == FALSE)
2686 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2687
2688 return bcmerror;
2689}
2690
2691static int
2692dhdsdio_write_vars(dhd_bus_t *bus)
2693{
2694 int bcmerror = 0;
2695 uint32 varsize;
2696 uint32 varaddr;
2697 uint8 *vbuffer;
2698 uint32 varsizew;
2699#ifdef DHD_DEBUG
2700 uint8 *nvram_ularray;
2701#endif /* DHD_DEBUG */
2702
2703 /* Even if there are no vars are to be written, we still need to set the ramsize. */
2704 varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0;
2705 varaddr = (bus->ramsize - 4) - varsize;
2706
2707 if (bus->vars) {
2708 if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev == 7)) {
2709 if (((varaddr & 0x3C) == 0x3C) && (varsize > 4)) {
2710 DHD_ERROR(("PR85623WAR in place\n"));
2711 varsize += 4;
2712 varaddr -= 4;
2713 }
2714 }
2715
2716 vbuffer = (uint8 *)MALLOC(bus->dhd->osh, varsize);
2717 if (!vbuffer)
2718 return BCME_NOMEM;
2719
2720 bzero(vbuffer, varsize);
2721 bcopy(bus->vars, vbuffer, bus->varsz);
2722
2723 /* Write the vars list */
2724 bcmerror = dhdsdio_membytes(bus, TRUE, varaddr, vbuffer, varsize);
2725#ifdef DHD_DEBUG
2726 /* Verify NVRAM bytes */
2727 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2728 nvram_ularray = (uint8*)MALLOC(bus->dhd->osh, varsize);
2729 if (!nvram_ularray)
2730 return BCME_NOMEM;
2731
2732 /* Upload image to verify downloaded contents. */
2733 memset(nvram_ularray, 0xaa, varsize);
2734
2735 /* Read the vars list to temp buffer for comparison */
2736 bcmerror = dhdsdio_membytes(bus, FALSE, varaddr, nvram_ularray, varsize);
2737 if (bcmerror) {
2738 DHD_ERROR(("%s: error %d on reading %d nvram bytes at 0x%08x\n",
2739 __FUNCTION__, bcmerror, varsize, varaddr));
2740 }
2741 /* Compare the org NVRAM with the one read from RAM */
2742 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2743 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n", __FUNCTION__));
2744 } else
2745 DHD_ERROR(("%s: Download, Upload and compare of NVRAM succeeded.\n",
2746 __FUNCTION__));
2747
2748 MFREE(bus->dhd->osh, nvram_ularray, varsize);
2749#endif /* DHD_DEBUG */
2750
2751 MFREE(bus->dhd->osh, vbuffer, varsize);
2752 }
2753
2754 /* adjust to the user specified RAM */
2755 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2756 bus->orig_ramsize, bus->ramsize));
2757 DHD_INFO(("Vars are at %d, orig varsize is %d\n",
2758 varaddr, varsize));
2759 varsize = ((bus->orig_ramsize - 4) - varaddr);
2760
2761 /*
2762 * Determine the length token:
2763 * Varsize, converted to words, in lower 16-bits, checksum in upper 16-bits.
2764 */
2765 if (bcmerror) {
2766 varsizew = 0;
2767 } else {
2768 varsizew = varsize / 4;
2769 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2770 varsizew = htol32(varsizew);
2771 }
2772
2773 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize, varsizew));
2774
2775 /* Write the length token to the last word */
2776 bcmerror = dhdsdio_membytes(bus, TRUE, (bus->orig_ramsize - 4),
2777 (uint8*)&varsizew, 4);
2778
2779 return bcmerror;
2780}
2781
2782static int
2783dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2784{
2785 uint retries;
2786 int bcmerror = 0;
2787
2788 /* To enter download state, disable ARM and reset SOCRAM.
2789 * To exit download state, simply reset ARM (default is RAM boot).
2790 */
2791 if (enter) {
2792 bus->alp_only = TRUE;
2793
2794 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2795 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2796 DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
2797 bcmerror = BCME_ERROR;
2798 goto fail;
2799 }
2800
2801 si_core_disable(bus->sih, 0);
2802 if (bcmsdh_regfail(bus->sdh)) {
2803 bcmerror = BCME_SDIO_ERROR;
2804 goto fail;
2805 }
2806
2807 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2808 DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
2809 bcmerror = BCME_ERROR;
2810 goto fail;
2811 }
2812
2813 si_core_reset(bus->sih, 0, 0);
2814 if (bcmsdh_regfail(bus->sdh)) {
2815 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n", __FUNCTION__));
2816 bcmerror = BCME_SDIO_ERROR;
2817 goto fail;
2818 }
2819
2820 /* Clear the top bit of memory */
2821 if (bus->ramsize) {
2822 uint32 zeros = 0;
2823 if (dhdsdio_membytes(bus, TRUE, bus->ramsize - 4, (uint8*)&zeros, 4) < 0) {
2824 bcmerror = BCME_SDIO_ERROR;
2825 goto fail;
2826 }
2827 }
2828 } else {
2829 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2830 DHD_ERROR(("%s: Failed to find SOCRAM core!\n", __FUNCTION__));
2831 bcmerror = BCME_ERROR;
2832 goto fail;
2833 }
2834
2835 if (!si_iscoreup(bus->sih)) {
2836 DHD_ERROR(("%s: SOCRAM core is down after reset?\n", __FUNCTION__));
2837 bcmerror = BCME_ERROR;
2838 goto fail;
2839 }
2840
2841 if ((bcmerror = dhdsdio_write_vars(bus))) {
2842 DHD_ERROR(("%s: could not write vars to RAM\n", __FUNCTION__));
2843 goto fail;
2844 }
2845
2846 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
2847 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
2848 DHD_ERROR(("%s: Can't change back to SDIO core?\n", __FUNCTION__));
2849 bcmerror = BCME_ERROR;
2850 goto fail;
2851 }
2852 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2853
2854
2855 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2856 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2857 DHD_ERROR(("%s: Failed to find ARM core!\n", __FUNCTION__));
2858 bcmerror = BCME_ERROR;
2859 goto fail;
2860 }
2861
2862 si_core_reset(bus->sih, 0, 0);
2863 if (bcmsdh_regfail(bus->sdh)) {
2864 DHD_ERROR(("%s: Failure trying to reset ARM core?\n", __FUNCTION__));
2865 bcmerror = BCME_SDIO_ERROR;
2866 goto fail;
2867 }
2868
2869 /* Allow HT Clock now that the ARM is running. */
2870 bus->alp_only = FALSE;
2871
2872 bus->dhd->busstate = DHD_BUS_LOAD;
2873 }
2874
2875fail:
2876 /* Always return to SDIOD core */
2877 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
2878 si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2879
2880 return bcmerror;
2881}
2882
2883int
2884dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2885 void *params, int plen, void *arg, int len, bool set)
2886{
2887 dhd_bus_t *bus = dhdp->bus;
2888 const bcm_iovar_t *vi = NULL;
2889 int bcmerror = 0;
2890 int val_size;
2891 uint32 actionid;
2892
2893 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
2894
2895 ASSERT(name);
2896 ASSERT(len >= 0);
2897
2898 /* Get MUST have return space */
2899 ASSERT(set || (arg && len));
2900
2901 /* Set does NOT take qualifiers */
2902 ASSERT(!set || (!params && !plen));
2903
2904 /* Look up var locally; if not found pass to host driver */
2905 if ((vi = bcm_iovar_lookup(dhdsdio_iovars, name)) == NULL) {
2906 dhd_os_sdlock(bus->dhd);
2907
2908 BUS_WAKE(bus);
2909
2910 /* Turn on clock in case SD command needs backplane */
2911 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2912
2913 bcmerror = bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len, set);
2914
2915 /* Check for bus configuration changes of interest */
2916
2917 /* If it was divisor change, read the new one */
2918 if (set && strcmp(name, "sd_divisor") == 0) {
2919 if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
2920 &bus->sd_divisor, sizeof(int32), FALSE) != BCME_OK) {
2921 bus->sd_divisor = -1;
2922 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, name));
2923 } else {
2924 DHD_INFO(("%s: noted %s update, value now %d\n",
2925 __FUNCTION__, name, bus->sd_divisor));
2926 }
2927 }
2928 /* If it was a mode change, read the new one */
2929 if (set && strcmp(name, "sd_mode") == 0) {
2930 if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
2931 &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) {
2932 bus->sd_mode = -1;
2933 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, name));
2934 } else {
2935 DHD_INFO(("%s: noted %s update, value now %d\n",
2936 __FUNCTION__, name, bus->sd_mode));
2937 }
2938 }
2939 /* Similar check for blocksize change */
2940 if (set && strcmp(name, "sd_blocksize") == 0) {
2941 int32 fnum = 2;
2942 if (bcmsdh_iovar_op(bus->sdh, "sd_blocksize", &fnum, sizeof(int32),
2943 &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) {
2944 bus->blocksize = 0;
2945 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_blocksize"));
2946 } else {
2947 DHD_INFO(("%s: noted %s update, value now %d\n",
2948 __FUNCTION__, "sd_blocksize", bus->blocksize));
2949 }
2950 }
2951 bus->roundup = MIN(max_roundup, bus->blocksize);
2952
2953 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2954 bus->activity = FALSE;
2955 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
2956 }
2957
2958 dhd_os_sdunlock(bus->dhd);
2959 goto exit;
2960 }
2961
2962 DHD_CTL(("%s: %s %s, len %d plen %d\n", __FUNCTION__,
2963 name, (set ? "set" : "get"), len, plen));
2964
2965 /* set up 'params' pointer in case this is a set command so that
2966 * the convenience int and bool code can be common to set and get
2967 */
2968 if (params == NULL) {
2969 params = arg;
2970 plen = len;
2971 }
2972
2973 if (vi->type == IOVT_VOID)
2974 val_size = 0;
2975 else if (vi->type == IOVT_BUFFER)
2976 val_size = len;
2977 else
2978 /* all other types are integer sized */
2979 val_size = sizeof(int);
2980
2981 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2982 bcmerror = dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len, val_size);
2983
2984exit:
2985 return bcmerror;
2986}
2987
2988void
2989dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2990{
2991 osl_t *osh;
2992 uint32 local_hostintmask;
2993 uint8 saveclk;
2994 uint retries;
2995 int err;
2996 if (!bus->dhd)
2997 return;
2998
2999 osh = bus->dhd->osh;
3000 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
3001
3002 bcmsdh_waitlockfree(NULL);
3003
3004 if (enforce_mutex)
3005 dhd_os_sdlock(bus->dhd);
3006
3007 BUS_WAKE(bus);
3008
3009 /* Change our idea of bus state */
3010 bus->dhd->busstate = DHD_BUS_DOWN;
3011
3012 /* Enable clock for device interrupts */
3013 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
3014
3015 /* Disable and clear interrupts at the chip level also */
3016 W_SDREG(0, &bus->regs->hostintmask, retries);
3017 local_hostintmask = bus->hostintmask;
3018 bus->hostintmask = 0;
3019
3020 /* Force clocks on backplane to be sure F2 interrupt propagates */
3021 saveclk = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
3022 if (!err) {
3023 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3024 (saveclk | SBSDIO_FORCE_HT), &err);
3025 }
3026 if (err) {
3027 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n", __FUNCTION__, err));
3028 }
3029
3030 /* Turn off the bus (F2), free any pending packets */
3031 DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
3032 bcmsdh_intr_disable(bus->sdh);
3033 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1, NULL);
3034
3035 /* Clear any pending interrupts now that F2 is disabled */
3036 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
3037
3038 /* Turn off the backplane clock (only) */
3039 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
3040
3041 /* Clear the data packet queues */
3042 pktq_flush(osh, &bus->txq, TRUE, NULL, 0);
3043
3044 /* Clear any held glomming stuff */
3045 if (bus->glomd)
3046 PKTFREE(osh, bus->glomd, FALSE);
3047
3048 if (bus->glom)
3049 PKTFREE(osh, bus->glom, FALSE);
3050
3051 bus->glom = bus->glomd = NULL;
3052
3053 /* Clear rx control and wake any waiters */
3054 bus->rxlen = 0;
3055 dhd_os_ioctl_resp_wake(bus->dhd);
3056
3057 /* Reset some F2 state stuff */
3058 bus->rxskip = FALSE;
3059 bus->tx_seq = bus->rx_seq = 0;
3060
3061 if (enforce_mutex)
3062 dhd_os_sdunlock(bus->dhd);
3063}
3064
3065
3066int
3067dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
3068{
3069 dhd_bus_t *bus = dhdp->bus;
3070 dhd_timeout_t tmo;
3071 uint retries = 0;
3072 uint8 ready, enable;
3073 int err, ret = 0;
3074 uint8 saveclk;
3075
3076 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
3077
3078 ASSERT(bus->dhd);
3079 if (!bus->dhd)
3080 return 0;
3081
3082 if (enforce_mutex)
3083 dhd_os_sdlock(bus->dhd);
3084
3085 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3086 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
3087 if (bus->clkstate != CLK_AVAIL) {
3088 DHD_ERROR(("%s: clock state is wrong. state = %d\n", __FUNCTION__, bus->clkstate));
3089 goto exit;
3090 }
3091
3092
3093 /* Force clocks on backplane to be sure F2 interrupt propagates */
3094 saveclk = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
3095 if (!err) {
3096 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3097 (saveclk | SBSDIO_FORCE_HT), &err);
3098 }
3099 if (err) {
3100 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n", __FUNCTION__, err));
3101 goto exit;
3102 }
3103
3104 /* Enable function 2 (frame transfers) */
3105 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
3106 &bus->regs->tosbmailboxdata, retries);
3107 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3108
3109 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
3110
3111 /* Give the dongle some time to do its thing and set IOR2 */
3112 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
3113
3114 ready = 0;
3115 while (ready != enable && !dhd_timeout_expired(&tmo))
3116 ready = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY, NULL);
3117
3118
3119 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
3120 __FUNCTION__, enable, ready, tmo.elapsed));
3121
3122
3123 /* If F2 successfully enabled, set core and enable interrupts */
3124 if (ready == enable) {
3125 /* Make sure we're talking to the core. */
3126 if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0)))
3127 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
3128 ASSERT(bus->regs != NULL);
3129
3130 /* Set up the interrupt mask and enable interrupts */
3131 bus->hostintmask = HOSTINTMASK;
3132 /* corerev 4 could use the newer interrupt logic to detect the frames */
3133 if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev == 4) &&
3134 (bus->rxint_mode != SDIO_DEVICE_HMB_RXINT)) {
3135 bus->hostintmask &= ~I_HMB_FRAME_IND;
3136 bus->hostintmask |= I_XMTDATA_AVAIL;
3137 }
3138 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
3139
3140 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK, (uint8)watermark, &err);
3141
3142 /* Set bus state according to enable result */
3143 dhdp->busstate = DHD_BUS_DATA;
3144
3145 /* bcmsdh_intr_unmask(bus->sdh); */
3146
3147 bus->intdis = FALSE;
3148 if (bus->intr) {
3149 DHD_INTR(("%s: enable SDIO device interrupts\n", __FUNCTION__));
3150 bcmsdh_intr_enable(bus->sdh);
3151 } else {
3152 DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
3153 bcmsdh_intr_disable(bus->sdh);
3154 }
3155
3156 }
3157
3158
3159 else {
3160 /* Disable F2 again */
3161 enable = SDIO_FUNC_ENABLE_1;
3162 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
3163 }
3164
3165 /* Restore previous clock setting */
3166 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3167
3168
3169 /* If we didn't come up, turn off backplane clock */
3170 if (dhdp->busstate != DHD_BUS_DATA)
3171 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
3172
3173exit:
3174 if (enforce_mutex)
3175 dhd_os_sdunlock(bus->dhd);
3176
3177 return ret;
3178}
3179
3180static void
3181dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3182{
3183 bcmsdh_info_t *sdh = bus->sdh;
3184 sdpcmd_regs_t *regs = bus->regs;
3185 uint retries = 0;
3186 uint16 lastrbc;
3187 uint8 hi, lo;
3188 int err;
3189
3190 DHD_ERROR(("%s: %sterminate frame%s\n", __FUNCTION__,
3191 (abort ? "abort command, " : ""), (rtx ? ", send NAK" : "")));
3192
3193 if (abort) {
3194 bcmsdh_abort(sdh, SDIO_FUNC_2);
3195 }
3196
3197 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, &err);
3198 bus->f1regdata++;
3199
3200 /* Wait until the packet has been flushed (device/FIFO stable) */
3201 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3202 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI, NULL);
3203 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO, NULL);
3204 bus->f1regdata += 2;
3205
3206 if ((hi == 0) && (lo == 0))
3207 break;
3208
3209 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3210 DHD_ERROR(("%s: count growing: last 0x%04x now 0x%04x\n",
3211 __FUNCTION__, lastrbc, ((hi << 8) + lo)));
3212 }
3213 lastrbc = (hi << 8) + lo;
3214 }
3215
3216 if (!retries) {
3217 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n", __FUNCTION__, lastrbc));
3218 } else {
3219 DHD_INFO(("%s: flush took %d iterations\n", __FUNCTION__, (0xffff - retries)));
3220 }
3221
3222 if (rtx) {
3223 bus->rxrtx++;
3224 W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
3225 bus->f1regdata++;
3226 if (retries <= retry_limit) {
3227 bus->rxskip = TRUE;
3228 }
3229 }
3230
3231 /* Clear partial in any case */
3232 bus->nextlen = 0;
3233
3234 /* If we can't reach the device, signal failure */
3235 if (err || bcmsdh_regfail(sdh))
3236 bus->dhd->busstate = DHD_BUS_DOWN;
3237}
3238
3239static void
3240dhdsdio_read_control(dhd_bus_t *bus, uint8 *hdr, uint len, uint doff)
3241{
3242 bcmsdh_info_t *sdh = bus->sdh;
3243 uint rdlen, pad;
3244
3245 int sdret;
3246
3247 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
3248
3249 /* Control data already received in aligned rxctl */
3250 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3251 goto gotpkt;
3252
3253 ASSERT(bus->rxbuf);
3254 /* Set rxctl for frame (w/optional alignment) */
3255 bus->rxctl = bus->rxbuf;
3256 if (dhd_alignctl) {
3257 bus->rxctl += firstread;
3258 if ((pad = ((uintptr)bus->rxctl % DHD_SDALIGN)))
3259 bus->rxctl += (DHD_SDALIGN - pad);
3260 bus->rxctl -= firstread;
3261 }
3262 ASSERT(bus->rxctl >= bus->rxbuf);
3263
3264 /* Copy the already-read portion over */
3265 bcopy(hdr, bus->rxctl, firstread);
3266 if (len <= firstread)
3267 goto gotpkt;
3268
3269 /* Copy the full data pkt in gSPI case and process ioctl. */
3270 if (bus->bus == SPI_BUS) {
3271 bcopy(hdr, bus->rxctl, len);
3272 goto gotpkt;
3273 }
3274
3275 /* Raise rdlen to next SDIO block to avoid tail command */
3276 rdlen = len - firstread;
3277 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3278 pad = bus->blocksize - (rdlen % bus->blocksize);
3279 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3280 ((len + pad) < bus->dhd->maxctl))
3281 rdlen += pad;
3282 } else if (rdlen % DHD_SDALIGN) {
3283 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3284 }
3285
3286 /* Satisfy length-alignment requirements */
3287 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3288 rdlen = ROUNDUP(rdlen, ALIGNMENT);
3289
3290 /* Drop if the read is too big or it exceeds our maximum */
3291 if ((rdlen + firstread) > bus->dhd->maxctl) {
3292 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3293 __FUNCTION__, rdlen, bus->dhd->maxctl));
3294 bus->dhd->rx_errors++;
3295 dhdsdio_rxfail(bus, FALSE, FALSE);
3296 goto done;
3297 }
3298
3299 if ((len - doff) > bus->dhd->maxctl) {
3300 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
3301 __FUNCTION__, len, (len - doff), bus->dhd->maxctl));
3302 bus->dhd->rx_errors++; bus->rx_toolong++;
3303 dhdsdio_rxfail(bus, FALSE, FALSE);
3304 goto done;
3305 }
3306
3307
3308 /* Read remainder of frame body into the rxctl buffer */
3309 sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
3310 (bus->rxctl + firstread), rdlen, NULL, NULL, NULL);
3311 bus->f2rxdata++;
3312 ASSERT(sdret != BCME_PENDING);
3313
3314 /* Control frame failures need retransmission */
3315 if (sdret < 0) {
3316 DHD_ERROR(("%s: read %d control bytes failed: %d\n", __FUNCTION__, rdlen, sdret));
3317 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3318 dhdsdio_rxfail(bus, TRUE, TRUE);
3319 goto done;
3320 }
3321
3322gotpkt:
3323
3324#ifdef DHD_DEBUG
3325 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3326 prhex("RxCtrl", bus->rxctl, len);
3327 }
3328#endif
3329
3330 /* Point to valid data and indicate its length */
3331 bus->rxctl += doff;
3332 bus->rxlen = len - doff;
3333
3334done:
3335 /* Awake any waiters */
3336 dhd_os_ioctl_resp_wake(bus->dhd);
3337}
3338
3339static uint8
3340dhdsdio_rxglom(dhd_bus_t *bus, uint8 rxseq)
3341{
3342 uint16 dlen, totlen;
3343 uint8 *dptr, num = 0;
3344
3345 uint16 sublen, check;
3346 void *pfirst, *plast, *pnext, *save_pfirst;
3347 osl_t *osh = bus->dhd->osh;
3348
3349 int errcode;
3350 uint8 chan, seq, doff, sfdoff;
3351 uint8 txmax;
3352
3353 int ifidx = 0;
3354 bool usechain = bus->use_rxchain;
3355
3356 /* If packets, issue read(s) and send up packet chain */
3357 /* Return sequence numbers consumed? */
3358
3359 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd, bus->glom));
3360
3361 /* If there's a descriptor, generate the packet chain */
3362 if (bus->glomd) {
3363 dhd_os_sdlock_rxq(bus->dhd);
3364
3365 pfirst = plast = pnext = NULL;
3366 dlen = (uint16)PKTLEN(osh, bus->glomd);
3367 dptr = PKTDATA(osh, bus->glomd);
3368 if (!dlen || (dlen & 1)) {
3369 DHD_ERROR(("%s: bad glomd len (%d), ignore descriptor\n",
3370 __FUNCTION__, dlen));
3371 dlen = 0;
3372 }
3373
3374 for (totlen = num = 0; dlen; num++) {
3375 /* Get (and move past) next length */
3376 sublen = ltoh16_ua(dptr);
3377 dlen -= sizeof(uint16);
3378 dptr += sizeof(uint16);
3379 if ((sublen < SDPCM_HDRLEN) ||
3380 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3381 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3382 __FUNCTION__, num, sublen));
3383 pnext = NULL;
3384 break;
3385 }
3386 if (sublen % DHD_SDALIGN) {
3387 DHD_ERROR(("%s: sublen %d not a multiple of %d\n",
3388 __FUNCTION__, sublen, DHD_SDALIGN));
3389 usechain = FALSE;
3390 }
3391 totlen += sublen;
3392
3393 /* For last frame, adjust read len so total is a block multiple */
3394 if (!dlen) {
3395 sublen += (ROUNDUP(totlen, bus->blocksize) - totlen);
3396 totlen = ROUNDUP(totlen, bus->blocksize);
3397 }
3398
3399 /* Allocate/chain packet for next subframe */
3400 if ((pnext = PKTGET(osh, sublen + DHD_SDALIGN, FALSE)) == NULL) {
3401 DHD_ERROR(("%s: PKTGET failed, num %d len %d\n",
3402 __FUNCTION__, num, sublen));
3403 break;
3404 }
3405 ASSERT(!PKTLINK(pnext));
3406 if (!pfirst) {
3407 ASSERT(!plast);
3408 pfirst = plast = pnext;
3409 } else {
3410 ASSERT(plast);
3411 PKTSETNEXT(osh, plast, pnext);
3412 plast = pnext;
3413 }
3414
3415 /* Adhere to start alignment requirements */
3416 PKTALIGN(osh, pnext, sublen, DHD_SDALIGN);
3417 }
3418
3419 /* If all allocations succeeded, save packet chain in bus structure */
3420 if (pnext) {
3421 DHD_GLOM(("%s: allocated %d-byte packet chain for %d subframes\n",
3422 __FUNCTION__, totlen, num));
3423 if (DHD_GLOM_ON() && bus->nextlen) {
3424 if (totlen != bus->nextlen) {
3425 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d "
3426 "rxseq %d\n", __FUNCTION__, bus->nextlen,
3427 totlen, rxseq));
3428 }
3429 }
3430 bus->glom = pfirst;
3431 pfirst = pnext = NULL;
3432 } else {
3433 if (pfirst)
3434 PKTFREE(osh, pfirst, FALSE);
3435 bus->glom = NULL;
3436 num = 0;
3437 }
3438
3439 /* Done with descriptor packet */
3440 PKTFREE(osh, bus->glomd, FALSE);
3441 bus->glomd = NULL;
3442 bus->nextlen = 0;
3443
3444 dhd_os_sdunlock_rxq(bus->dhd);
3445 }
3446
3447 /* Ok -- either we just generated a packet chain, or had one from before */
3448 if (bus->glom) {
3449 if (DHD_GLOM_ON()) {
3450 DHD_GLOM(("%s: attempt superframe read, packet chain:\n", __FUNCTION__));
3451 for (pnext = bus->glom; pnext; pnext = PKTNEXT(osh, pnext)) {
3452 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3453 pnext, (uint8*)PKTDATA(osh, pnext),
3454 PKTLEN(osh, pnext), PKTLEN(osh, pnext)));
3455 }
3456 }
3457
3458 pfirst = bus->glom;
3459 dlen = (uint16)pkttotlen(osh, pfirst);
3460
3461 /* Do an SDIO read for the superframe. Configurable iovar to
3462 * read directly into the chained packet, or allocate a large
3463 * packet and and copy into the chain.
3464 */
3465 if (usechain) {
3466 errcode = dhd_bcmsdh_recv_buf(bus,
3467 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3468 F2SYNC, (uint8*)PKTDATA(osh, pfirst),
3469 dlen, pfirst, NULL, NULL);
3470 } else if (bus->dataptr) {
3471 errcode = dhd_bcmsdh_recv_buf(bus,
3472 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3473 F2SYNC, bus->dataptr,
3474 dlen, NULL, NULL, NULL);
3475 sublen = (uint16)pktfrombuf(osh, pfirst, 0, dlen, bus->dataptr);
3476 if (sublen != dlen) {
3477 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3478 __FUNCTION__, dlen, sublen));
3479 errcode = -1;
3480 }
3481 pnext = NULL;
3482 } else {
3483 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n", dlen));
3484 errcode = -1;
3485 }
3486 bus->f2rxdata++;
3487 ASSERT(errcode != BCME_PENDING);
3488
3489 /* On failure, kill the superframe, allow a couple retries */
3490 if (errcode < 0) {
3491 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3492 __FUNCTION__, dlen, errcode));
3493 bus->dhd->rx_errors++;
3494
3495 if (bus->glomerr++ < 3) {
3496 dhdsdio_rxfail(bus, TRUE, TRUE);
3497 } else {
3498 bus->glomerr = 0;
3499 dhdsdio_rxfail(bus, TRUE, FALSE);
3500 dhd_os_sdlock_rxq(bus->dhd);
3501 PKTFREE(osh, bus->glom, FALSE);
3502 dhd_os_sdunlock_rxq(bus->dhd);
3503 bus->rxglomfail++;
3504 bus->glom = NULL;
3505 }
3506 return 0;
3507 }
3508
3509#ifdef DHD_DEBUG
3510 if (DHD_GLOM_ON()) {
3511 prhex("SUPERFRAME", PKTDATA(osh, pfirst),
3512 MIN(PKTLEN(osh, pfirst), 48));
3513 }
3514#endif
3515
3516
3517 /* Validate the superframe header */
3518 dptr = (uint8 *)PKTDATA(osh, pfirst);
3519 sublen = ltoh16_ua(dptr);
3520 check = ltoh16_ua(dptr + sizeof(uint16));
3521
3522 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3523 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3524 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3525 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3526 DHD_INFO(("%s: got frame w/nextlen too large (%d) seq %d\n",
3527 __FUNCTION__, bus->nextlen, seq));
3528 bus->nextlen = 0;
3529 }
3530 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3531 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3532
3533 errcode = 0;
3534 if ((uint16)~(sublen^check)) {
3535 DHD_ERROR(("%s (superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
3536 __FUNCTION__, sublen, check));
3537 errcode = -1;
3538 } else if (ROUNDUP(sublen, bus->blocksize) != dlen) {
3539 DHD_ERROR(("%s (superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
3540 __FUNCTION__, sublen, ROUNDUP(sublen, bus->blocksize), dlen));
3541 errcode = -1;
3542 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) != SDPCM_GLOM_CHANNEL) {
3543 DHD_ERROR(("%s (superframe): bad channel %d\n", __FUNCTION__,
3544 SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN])));
3545 errcode = -1;
3546 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3547 DHD_ERROR(("%s (superframe): got second descriptor?\n", __FUNCTION__));
3548 errcode = -1;
3549 } else if ((doff < SDPCM_HDRLEN) ||
3550 (doff > (PKTLEN(osh, pfirst) - SDPCM_HDRLEN))) {
3551 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d pkt %d min %d\n",
3552 __FUNCTION__, doff, sublen, PKTLEN(osh, pfirst), SDPCM_HDRLEN));
3553 errcode = -1;
3554 }
3555
3556 /* Check sequence number of superframe SW header */
3557 if (rxseq != seq) {
3558 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3559 __FUNCTION__, seq, rxseq));
3560 bus->rx_badseq++;
3561 rxseq = seq;
3562 }
3563
3564 /* Check window for sanity */
3565 if ((uint8)(txmax - bus->tx_seq) > 0x40) {
3566 DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n",
3567 __FUNCTION__, txmax, bus->tx_seq));
3568 txmax = bus->tx_seq;
3569 }
3570 bus->tx_max = txmax;
3571
3572 /* Remove superframe header, remember offset */
3573 PKTPULL(osh, pfirst, doff);
3574 sfdoff = doff;
3575
3576 /* Validate all the subframe headers */
3577 for (num = 0, pnext = pfirst; pnext && !errcode;
3578 num++, pnext = PKTNEXT(osh, pnext)) {
3579 dptr = (uint8 *)PKTDATA(osh, pnext);
3580 dlen = (uint16)PKTLEN(osh, pnext);
3581 sublen = ltoh16_ua(dptr);
3582 check = ltoh16_ua(dptr + sizeof(uint16));
3583 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3584 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3585#ifdef DHD_DEBUG
3586 if (DHD_GLOM_ON()) {
3587 prhex("subframe", dptr, 32);
3588 }
3589#endif
3590
3591 if ((uint16)~(sublen^check)) {
3592 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3593 "len/check 0x%04x/0x%04x\n",
3594 __FUNCTION__, num, sublen, check));
3595 errcode = -1;
3596 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3597 DHD_ERROR(("%s (subframe %d): length mismatch: "
3598 "len 0x%04x, expect 0x%04x\n",
3599 __FUNCTION__, num, sublen, dlen));
3600 errcode = -1;
3601 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3602 (chan != SDPCM_EVENT_CHANNEL)) {
3603 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3604 __FUNCTION__, num, chan));
3605 errcode = -1;
3606 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3607 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3608 __FUNCTION__, num, doff, sublen, SDPCM_HDRLEN));
3609 errcode = -1;
3610 }
3611 }
3612
3613 if (errcode) {
3614 /* Terminate frame on error, request a couple retries */
3615 if (bus->glomerr++ < 3) {
3616 /* Restore superframe header space */
3617 PKTPUSH(osh, pfirst, sfdoff);
3618 dhdsdio_rxfail(bus, TRUE, TRUE);
3619 } else {
3620 bus->glomerr = 0;
3621 dhdsdio_rxfail(bus, TRUE, FALSE);
3622 dhd_os_sdlock_rxq(bus->dhd);
3623 PKTFREE(osh, bus->glom, FALSE);
3624 dhd_os_sdunlock_rxq(bus->dhd);
3625 bus->rxglomfail++;
3626 bus->glom = NULL;
3627 }
3628 bus->nextlen = 0;
3629 return 0;
3630 }
3631
3632 /* Basic SD framing looks ok - process each packet (header) */
3633 save_pfirst = pfirst;
3634 bus->glom = NULL;
3635 plast = NULL;
3636
3637 dhd_os_sdlock_rxq(bus->dhd);
3638 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3639 pnext = PKTNEXT(osh, pfirst);
3640 PKTSETNEXT(osh, pfirst, NULL);
3641
3642 dptr = (uint8 *)PKTDATA(osh, pfirst);
3643 sublen = ltoh16_ua(dptr);
3644 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3645 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3646 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3647
3648 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
3649 __FUNCTION__, num, pfirst, PKTDATA(osh, pfirst),
3650 PKTLEN(osh, pfirst), sublen, chan, seq));
3651
3652 ASSERT((chan == SDPCM_DATA_CHANNEL) || (chan == SDPCM_EVENT_CHANNEL));
3653
3654 if (rxseq != seq) {
3655 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3656 __FUNCTION__, seq, rxseq));
3657 bus->rx_badseq++;
3658 rxseq = seq;
3659 }
3660
3661#ifdef DHD_DEBUG
3662 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3663 prhex("Rx Subframe Data", dptr, dlen);
3664 }
3665#endif
3666
3667 PKTSETLEN(osh, pfirst, sublen);
3668 PKTPULL(osh, pfirst, doff);
3669
3670 if (PKTLEN(osh, pfirst) == 0) {
3671 PKTFREE(bus->dhd->osh, pfirst, FALSE);
3672 if (plast) {
3673 PKTSETNEXT(osh, plast, pnext);
3674 } else {
3675 ASSERT(save_pfirst == pfirst);
3676 save_pfirst = pnext;
3677 }
3678 continue;
3679 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) != 0) {
3680 DHD_ERROR(("%s: rx protocol error\n", __FUNCTION__));
3681 bus->dhd->rx_errors++;
3682 PKTFREE(osh, pfirst, FALSE);
3683 if (plast) {
3684 PKTSETNEXT(osh, plast, pnext);
3685 } else {
3686 ASSERT(save_pfirst == pfirst);
3687 save_pfirst = pnext;
3688 }
3689 continue;
3690 }
3691
3692 /* this packet will go up, link back into chain and count it */
3693 PKTSETNEXT(osh, pfirst, pnext);
3694 plast = pfirst;
3695 num++;
3696
3697#ifdef DHD_DEBUG
3698 if (DHD_GLOM_ON()) {
3699 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) nxt/lnk %p/%p\n",
3700 __FUNCTION__, num, pfirst,
3701 PKTDATA(osh, pfirst), PKTLEN(osh, pfirst),
3702 PKTNEXT(osh, pfirst), PKTLINK(pfirst)));
3703 prhex("", (uint8 *)PKTDATA(osh, pfirst),
3704 MIN(PKTLEN(osh, pfirst), 32));
3705 }
3706#endif /* DHD_DEBUG */
3707 }
3708 dhd_os_sdunlock_rxq(bus->dhd);
3709 if (num) {
3710 dhd_os_sdunlock(bus->dhd);
3711 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num, 0);
3712 dhd_os_sdlock(bus->dhd);
3713 }
3714
3715 bus->rxglomframes++;
3716 bus->rxglompkts += num;
3717 }
3718 return num;
3719}
3720
3721/* Return TRUE if there may be more frames to read */
3722static uint
3723dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3724{
3725 osl_t *osh = bus->dhd->osh;
3726 bcmsdh_info_t *sdh = bus->sdh;
3727
3728 uint16 len, check; /* Extracted hardware header fields */
3729 uint8 chan, seq, doff; /* Extracted software header fields */
3730 uint8 fcbits; /* Extracted fcbits from software header */
3731 uint8 delta;
3732
3733 void *pkt; /* Packet for event or data frames */
3734 uint16 pad; /* Number of pad bytes to read */
3735 uint16 rdlen; /* Total number of bytes to read */
3736 uint8 rxseq; /* Next sequence number to expect */
3737 uint rxleft = 0; /* Remaining number of frames allowed */
3738 int sdret; /* Return code from bcmsdh calls */
3739 uint8 txmax; /* Maximum tx sequence offered */
3740 bool len_consistent; /* Result of comparing readahead len and len from hw-hdr */
3741 uint8 *rxbuf;
3742 int ifidx = 0;
3743 uint rxcount = 0; /* Total frames read */
3744
3745#if defined(DHD_DEBUG) || defined(SDTEST)
3746 bool sdtest = FALSE; /* To limit message spew from test mode */
3747#endif
3748
3749 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
3750
3751 ASSERT(maxframes);
3752
3753#ifdef SDTEST
3754 /* Allow pktgen to override maxframes */
3755 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3756 maxframes = bus->pktgen_count;
3757 sdtest = TRUE;
3758 }
3759#endif
3760
3761 /* Not finished unless we encounter no more frames indication */
3762 *finished = FALSE;
3763
3764
3765 for (rxseq = bus->rx_seq, rxleft = maxframes;
3766 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3767 rxseq++, rxleft--) {
3768
3769 /* Handle glomming separately */
3770 if (bus->glom || bus->glomd) {
3771 uint8 cnt;
3772 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3773 __FUNCTION__, bus->glomd, bus->glom));
3774 cnt = dhdsdio_rxglom(bus, rxseq);
3775 DHD_GLOM(("%s: rxglom returned %d\n", __FUNCTION__, cnt));
3776 rxseq += cnt - 1;
3777 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3778 continue;
3779 }
3780
3781 /* Try doing single read if we can */
3782 if (dhd_readahead && bus->nextlen) {
3783 uint16 nextlen = bus->nextlen;
3784 bus->nextlen = 0;
3785
3786 if (bus->bus == SPI_BUS) {
3787 rdlen = len = nextlen;
3788 }
3789 else {
3790 rdlen = len = nextlen << 4;
3791
3792 /* Pad read to blocksize for efficiency */
3793 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3794 pad = bus->blocksize - (rdlen % bus->blocksize);
3795 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3796 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
3797 rdlen += pad;
3798 } else if (rdlen % DHD_SDALIGN) {
3799 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3800 }
3801 }
3802
3803 /* We use bus->rxctl buffer in WinXP for initial control pkt receives.
3804 * Later we use buffer-poll for data as well as control packets.
3805 * This is required because dhd receives full frame in gSPI unlike SDIO.
3806 * After the frame is received we have to distinguish whether it is data
3807 * or non-data frame.
3808 */
3809 /* Allocate a packet buffer */
3810 dhd_os_sdlock_rxq(bus->dhd);
3811 if (!(pkt = PKTGET(osh, rdlen + DHD_SDALIGN, FALSE))) {
3812 if (bus->bus == SPI_BUS) {
3813 bus->usebufpool = FALSE;
3814 bus->rxctl = bus->rxbuf;
3815 if (dhd_alignctl) {
3816 bus->rxctl += firstread;
3817 if ((pad = ((uintptr)bus->rxctl % DHD_SDALIGN)))
3818 bus->rxctl += (DHD_SDALIGN - pad);
3819 bus->rxctl -= firstread;
3820 }
3821 ASSERT(bus->rxctl >= bus->rxbuf);
3822 rxbuf = bus->rxctl;
3823 /* Read the entire frame */
3824 sdret = dhd_bcmsdh_recv_buf(bus,
3825 bcmsdh_cur_sbwad(sdh),
3826 SDIO_FUNC_2,
3827 F2SYNC, rxbuf, rdlen,
3828 NULL, NULL, NULL);
3829 bus->f2rxdata++;
3830 ASSERT(sdret != BCME_PENDING);
3831
3832
3833 /* Control frame failures need retransmission */
3834 if (sdret < 0) {
3835 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3836 __FUNCTION__, rdlen, sdret));
3837 /* dhd.rx_ctlerrs is higher level */
3838 bus->rxc_errors++;
3839 dhd_os_sdunlock_rxq(bus->dhd);
3840 dhdsdio_rxfail(bus, TRUE,
3841 (bus->bus == SPI_BUS) ? FALSE : TRUE);
3842 continue;
3843 }
3844 } else {
3845 /* Give up on data, request rtx of events */
3846 DHD_ERROR(("%s (nextlen): PKTGET failed: len %d rdlen %d "
3847 "expected rxseq %d\n",
3848 __FUNCTION__, len, rdlen, rxseq));
3849 /* Just go try again w/normal header read */
3850 dhd_os_sdunlock_rxq(bus->dhd);
3851 continue;
3852 }
3853 } else {
3854 if (bus->bus == SPI_BUS)
3855 bus->usebufpool = TRUE;
3856
3857 ASSERT(!PKTLINK(pkt));
3858 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
3859 rxbuf = (uint8 *)PKTDATA(osh, pkt);
3860 /* Read the entire frame */
3861 sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
3862 SDIO_FUNC_2,
3863 F2SYNC, rxbuf, rdlen,
3864 pkt, NULL, NULL);
3865 bus->f2rxdata++;
3866 ASSERT(sdret != BCME_PENDING);
3867
3868 if (sdret < 0) {
3869 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3870 __FUNCTION__, rdlen, sdret));
3871 PKTFREE(bus->dhd->osh, pkt, FALSE);
3872 bus->dhd->rx_errors++;
3873 dhd_os_sdunlock_rxq(bus->dhd);
3874 /* Force retry w/normal header read. Don't attempt NAK for
3875 * gSPI
3876 */
3877 dhdsdio_rxfail(bus, TRUE,
3878 (bus->bus == SPI_BUS) ? FALSE : TRUE);
3879 continue;
3880 }
3881 }
3882 dhd_os_sdunlock_rxq(bus->dhd);
3883
3884 /* Now check the header */
3885 bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN);
3886
3887 /* Extract hardware header fields */
3888 len = ltoh16_ua(bus->rxhdr);
3889 check = ltoh16_ua(bus->rxhdr + sizeof(uint16));
3890
3891 /* All zeros means readahead info was bad */
3892 if (!(len|check)) {
3893 DHD_INFO(("%s (nextlen): read zeros in HW header???\n",
3894 __FUNCTION__));
3895 dhd_os_sdlock_rxq(bus->dhd);
3896 PKTFREE2();
3897 dhd_os_sdunlock_rxq(bus->dhd);
3898 GSPI_PR55150_BAILOUT;
3899 continue;
3900 }
3901
3902 /* Validate check bytes */
3903 if ((uint16)~(len^check)) {
3904 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check"
3905 " 0x%04x/0x%04x/0x%04x\n", __FUNCTION__, nextlen,
3906 len, check));
3907 dhd_os_sdlock_rxq(bus->dhd);
3908 PKTFREE2();
3909 dhd_os_sdunlock_rxq(bus->dhd);
3910 bus->rx_badhdr++;
3911 dhdsdio_rxfail(bus, FALSE, FALSE);
3912 GSPI_PR55150_BAILOUT;
3913 continue;
3914 }
3915
3916 /* Validate frame length */
3917 if (len < SDPCM_HDRLEN) {
3918 DHD_ERROR(("%s (nextlen): HW hdr length invalid: %d\n",
3919 __FUNCTION__, len));
3920 dhd_os_sdlock_rxq(bus->dhd);
3921 PKTFREE2();
3922 dhd_os_sdunlock_rxq(bus->dhd);
3923 GSPI_PR55150_BAILOUT;
3924 continue;
3925 }
3926
3927 /* Check for consistency with readahead info */
3928 len_consistent = (nextlen != (ROUNDUP(len, 16) >> 4));
3929 if (len_consistent) {
3930 /* Mismatch, force retry w/normal header (may be >4K) */
3931 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; "
3932 "expected rxseq %d\n",
3933 __FUNCTION__, nextlen, len, ROUNDUP(len, 16), rxseq));
3934 dhd_os_sdlock_rxq(bus->dhd);
3935 PKTFREE2();
3936 dhd_os_sdunlock_rxq(bus->dhd);
3937 dhdsdio_rxfail(bus, TRUE, (bus->bus == SPI_BUS) ? FALSE : TRUE);
3938 GSPI_PR55150_BAILOUT;
3939 continue;
3940 }
3941
3942
3943 /* Extract software header fields */
3944 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3945 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3946 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3947 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3948
3949 bus->nextlen =
3950 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3951 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3952 DHD_INFO(("%s (nextlen): got frame w/nextlen too large"
3953 " (%d), seq %d\n", __FUNCTION__, bus->nextlen,
3954 seq));
3955 bus->nextlen = 0;
3956 }
3957
3958 bus->dhd->rx_readahead_cnt ++;
3959 /* Handle Flow Control */
3960 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3961
3962 delta = 0;
3963 if (~bus->flowcontrol & fcbits) {
3964 bus->fc_xoff++;
3965 delta = 1;
3966 }
3967 if (bus->flowcontrol & ~fcbits) {
3968 bus->fc_xon++;
3969 delta = 1;
3970 }
3971
3972 if (delta) {
3973 bus->fc_rcvd++;
3974 bus->flowcontrol = fcbits;
3975 }
3976
3977 /* Check and update sequence number */
3978 if (rxseq != seq) {
3979 DHD_INFO(("%s (nextlen): rx_seq %d, expected %d\n",
3980 __FUNCTION__, seq, rxseq));
3981 bus->rx_badseq++;
3982 rxseq = seq;
3983 }
3984
3985 /* Check window for sanity */
3986 if ((uint8)(txmax - bus->tx_seq) > 0x40) {
3987 DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n",
3988 __FUNCTION__, txmax, bus->tx_seq));
3989 txmax = bus->tx_seq;
3990 }
3991 bus->tx_max = txmax;
3992
3993#ifdef DHD_DEBUG
3994 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3995 prhex("Rx Data", rxbuf, len);
3996 } else if (DHD_HDRS_ON()) {
3997 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3998 }
3999#endif
4000
4001 if (chan == SDPCM_CONTROL_CHANNEL) {
4002 if (bus->bus == SPI_BUS) {
4003 dhdsdio_read_control(bus, rxbuf, len, doff);
4004 if (bus->usebufpool) {
4005 dhd_os_sdlock_rxq(bus->dhd);
4006 PKTFREE(bus->dhd->osh, pkt, FALSE);
4007 dhd_os_sdunlock_rxq(bus->dhd);
4008 }
4009 continue;
4010 } else {
4011 DHD_ERROR(("%s (nextlen): readahead on control"
4012 " packet %d?\n", __FUNCTION__, seq));
4013 /* Force retry w/normal header read */
4014 bus->nextlen = 0;
4015 dhdsdio_rxfail(bus, FALSE, TRUE);
4016 dhd_os_sdlock_rxq(bus->dhd);
4017 PKTFREE2();
4018 dhd_os_sdunlock_rxq(bus->dhd);
4019 continue;
4020 }
4021 }
4022
4023 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
4024 DHD_ERROR(("Received %d bytes on %d channel. Running out of "
4025 "rx pktbuf's or not yet malloced.\n", len, chan));
4026 continue;
4027 }
4028
4029 /* Validate data offset */
4030 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4031 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
4032 __FUNCTION__, doff, len, SDPCM_HDRLEN));
4033 dhd_os_sdlock_rxq(bus->dhd);
4034 PKTFREE2();
4035 dhd_os_sdunlock_rxq(bus->dhd);
4036 ASSERT(0);
4037 dhdsdio_rxfail(bus, FALSE, FALSE);
4038 continue;
4039 }
4040
4041 /* All done with this one -- now deliver the packet */
4042 goto deliver;
4043 }
4044 /* gSPI frames should not be handled in fractions */
4045 if (bus->bus == SPI_BUS) {
4046 break;
4047 }
4048
4049 /* Read frame header (hardware and software) */
4050 sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
4051 bus->rxhdr, firstread, NULL, NULL, NULL);
4052 bus->f2rxhdrs++;
4053 ASSERT(sdret != BCME_PENDING);
4054
4055 if (sdret < 0) {
4056 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __FUNCTION__, sdret));
4057 bus->rx_hdrfail++;
4058 dhdsdio_rxfail(bus, TRUE, TRUE);
4059 continue;
4060 }
4061
4062#ifdef DHD_DEBUG
4063 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
4064 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
4065 }
4066#endif
4067
4068 /* Extract hardware header fields */
4069 len = ltoh16_ua(bus->rxhdr);
4070 check = ltoh16_ua(bus->rxhdr + sizeof(uint16));
4071
4072 /* All zeros means no more frames */
4073 if (!(len|check)) {
4074 *finished = TRUE;
4075 break;
4076 }
4077
4078 /* Validate check bytes */
4079 if ((uint16)~(len^check)) {
4080 DHD_ERROR(("%s: HW hdr error: len/check 0x%04x/0x%04x\n",
4081 __FUNCTION__, len, check));
4082 bus->rx_badhdr++;
4083 dhdsdio_rxfail(bus, FALSE, FALSE);
4084 continue;
4085 }
4086
4087 /* Validate frame length */
4088 if (len < SDPCM_HDRLEN) {
4089 DHD_ERROR(("%s: HW hdr length invalid: %d\n", __FUNCTION__, len));
4090 continue;
4091 }
4092
4093 /* Extract software header fields */
4094 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4095 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4096 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4097 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4098
4099 /* Validate data offset */
4100 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4101 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d seq %d\n",
4102 __FUNCTION__, doff, len, SDPCM_HDRLEN, seq));
4103 bus->rx_badhdr++;
4104 ASSERT(0);
4105 dhdsdio_rxfail(bus, FALSE, FALSE);
4106 continue;
4107 }
4108
4109 /* Save the readahead length if there is one */
4110 bus->nextlen = bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4111 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4112 DHD_INFO(("%s (nextlen): got frame w/nextlen too large (%d), seq %d\n",
4113 __FUNCTION__, bus->nextlen, seq));
4114 bus->nextlen = 0;
4115 }
4116
4117 /* Handle Flow Control */
4118 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4119
4120 delta = 0;
4121 if (~bus->flowcontrol & fcbits) {
4122 bus->fc_xoff++;
4123 delta = 1;
4124 }
4125 if (bus->flowcontrol & ~fcbits) {
4126 bus->fc_xon++;
4127 delta = 1;
4128 }
4129
4130 if (delta) {
4131 bus->fc_rcvd++;
4132 bus->flowcontrol = fcbits;
4133 }
4134
4135 /* Check and update sequence number */
4136 if (rxseq != seq) {
4137 DHD_INFO(("%s: rx_seq %d, expected %d\n", __FUNCTION__, seq, rxseq));
4138 bus->rx_badseq++;
4139 rxseq = seq;
4140 }
4141
4142 /* Check window for sanity */
4143 if ((uint8)(txmax - bus->tx_seq) > 0x40) {
4144 DHD_ERROR(("%s: got unlikely tx max %d with tx_seq %d\n",
4145 __FUNCTION__, txmax, bus->tx_seq));
4146 txmax = bus->tx_seq;
4147 }
4148 bus->tx_max = txmax;
4149
4150 /* Call a separate function for control frames */
4151 if (chan == SDPCM_CONTROL_CHANNEL) {
4152 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4153 continue;
4154 }
4155
4156 ASSERT((chan == SDPCM_DATA_CHANNEL) || (chan == SDPCM_EVENT_CHANNEL) ||
4157 (chan == SDPCM_TEST_CHANNEL) || (chan == SDPCM_GLOM_CHANNEL));
4158
4159 /* Length to read */
4160 rdlen = (len > firstread) ? (len - firstread) : 0;
4161
4162 /* May pad read to blocksize for efficiency */
4163 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
4164 pad = bus->blocksize - (rdlen % bus->blocksize);
4165 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4166 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4167 rdlen += pad;
4168 } else if (rdlen % DHD_SDALIGN) {
4169 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4170 }
4171
4172 /* Satisfy length-alignment requirements */
4173 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4174 rdlen = ROUNDUP(rdlen, ALIGNMENT);
4175
4176 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4177 /* Too long -- skip this frame */
4178 DHD_ERROR(("%s: too long: len %d rdlen %d\n", __FUNCTION__, len, rdlen));
4179 bus->dhd->rx_errors++; bus->rx_toolong++;
4180 dhdsdio_rxfail(bus, FALSE, FALSE);
4181 continue;
4182 }
4183
4184 dhd_os_sdlock_rxq(bus->dhd);
4185 if (!(pkt = PKTGET(osh, (rdlen + firstread + DHD_SDALIGN), FALSE))) {
4186 /* Give up on data, request rtx of events */
4187 DHD_ERROR(("%s: PKTGET failed: rdlen %d chan %d\n",
4188 __FUNCTION__, rdlen, chan));
4189 bus->dhd->rx_dropped++;
4190 dhd_os_sdunlock_rxq(bus->dhd);
4191 dhdsdio_rxfail(bus, FALSE, RETRYCHAN(chan));
4192 continue;
4193 }
4194 dhd_os_sdunlock_rxq(bus->dhd);
4195
4196 ASSERT(!PKTLINK(pkt));
4197
4198 /* Leave room for what we already read, and align remainder */
4199 ASSERT(firstread < (PKTLEN(osh, pkt)));
4200 PKTPULL(osh, pkt, firstread);
4201 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
4202
4203 /* Read the remaining frame data */
4204 sdret = dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
4205 ((uint8 *)PKTDATA(osh, pkt)), rdlen, pkt, NULL, NULL);
4206 bus->f2rxdata++;
4207 ASSERT(sdret != BCME_PENDING);
4208
4209 if (sdret < 0) {
4210 DHD_ERROR(("%s: read %d %s bytes failed: %d\n", __FUNCTION__, rdlen,
4211 ((chan == SDPCM_EVENT_CHANNEL) ? "event" :
4212 ((chan == SDPCM_DATA_CHANNEL) ? "data" : "test")), sdret));
4213 dhd_os_sdlock_rxq(bus->dhd);
4214 PKTFREE(bus->dhd->osh, pkt, FALSE);
4215 dhd_os_sdunlock_rxq(bus->dhd);
4216 bus->dhd->rx_errors++;
4217 dhdsdio_rxfail(bus, TRUE, RETRYCHAN(chan));
4218 continue;
4219 }
4220
4221 /* Copy the already-read portion */
4222 PKTPUSH(osh, pkt, firstread);
4223 bcopy(bus->rxhdr, PKTDATA(osh, pkt), firstread);
4224
4225#ifdef DHD_DEBUG
4226 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4227 prhex("Rx Data", PKTDATA(osh, pkt), len);
4228 }
4229#endif
4230
4231deliver:
4232 /* Save superframe descriptor and allocate packet frame */
4233 if (chan == SDPCM_GLOM_CHANNEL) {
4234 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4235 DHD_GLOM(("%s: got glom descriptor, %d bytes:\n",
4236 __FUNCTION__, len));
4237#ifdef DHD_DEBUG
4238 if (DHD_GLOM_ON()) {
4239 prhex("Glom Data", PKTDATA(osh, pkt), len);
4240 }
4241#endif
4242 PKTSETLEN(osh, pkt, len);
4243 ASSERT(doff == SDPCM_HDRLEN);
4244 PKTPULL(osh, pkt, SDPCM_HDRLEN);
4245 bus->glomd = pkt;
4246 } else {
4247 DHD_ERROR(("%s: glom superframe w/o descriptor!\n", __FUNCTION__));
4248 dhdsdio_rxfail(bus, FALSE, FALSE);
4249 }
4250 continue;
4251 }
4252
4253 /* Fill in packet len and prio, deliver upward */
4254 PKTSETLEN(osh, pkt, len);
4255 PKTPULL(osh, pkt, doff);
4256
4257#ifdef SDTEST
4258 /* Test channel packets are processed separately */
4259 if (chan == SDPCM_TEST_CHANNEL) {
4260 dhdsdio_testrcv(bus, pkt, seq);
4261 continue;
4262 }
4263#endif /* SDTEST */
4264
4265 if (PKTLEN(osh, pkt) == 0) {
4266 dhd_os_sdlock_rxq(bus->dhd);
4267 PKTFREE(bus->dhd->osh, pkt, FALSE);
4268 dhd_os_sdunlock_rxq(bus->dhd);
4269 continue;
4270 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4271 DHD_ERROR(("%s: rx protocol error\n", __FUNCTION__));
4272 dhd_os_sdlock_rxq(bus->dhd);
4273 PKTFREE(bus->dhd->osh, pkt, FALSE);
4274 dhd_os_sdunlock_rxq(bus->dhd);
4275 bus->dhd->rx_errors++;
4276 continue;
4277 }
4278
4279
4280 /* Unlock during rx call */
4281 dhd_os_sdunlock(bus->dhd);
4282 dhd_rx_frame(bus->dhd, ifidx, pkt, 1, chan);
4283 dhd_os_sdlock(bus->dhd);
4284 }
4285 rxcount = maxframes - rxleft;
4286#ifdef DHD_DEBUG
4287 /* Message if we hit the limit */
4288 if (!rxleft && !sdtest)
4289 DHD_DATA(("%s: hit rx limit of %d frames\n", __FUNCTION__, maxframes));
4290 else
4291#endif /* DHD_DEBUG */
4292 DHD_DATA(("%s: processed %d frames\n", __FUNCTION__, rxcount));
4293 /* Back off rxseq if awaiting rtx, update rx_seq */
4294 if (bus->rxskip)
4295 rxseq--;
4296 bus->rx_seq = rxseq;
4297
4298 return rxcount;
4299}
4300
4301static uint32
4302dhdsdio_hostmail(dhd_bus_t *bus)
4303{
4304 sdpcmd_regs_t *regs = bus->regs;
4305 uint32 intstatus = 0;
4306 uint32 hmb_data;
4307 uint8 fcbits;
4308 uint retries = 0;
4309
4310 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
4311
4312 /* Read mailbox data and ack that we did so */
4313 R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
4314 if (retries <= retry_limit)
4315 W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
4316 bus->f1regdata += 2;
4317
4318 /* Dongle recomposed rx frames, accept them again */
4319 if (hmb_data & HMB_DATA_NAKHANDLED) {
4320 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n", bus->rx_seq));
4321 if (!bus->rxskip) {
4322 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __FUNCTION__));
4323 }
4324 bus->rxskip = FALSE;
4325 intstatus |= FRAME_AVAIL_MASK(bus);
4326 }
4327
4328 /*
4329 * DEVREADY does not occur with gSPI.
4330 */
4331 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4332 bus->sdpcm_ver = (hmb_data & HMB_DATA_VERSION_MASK) >> HMB_DATA_VERSION_SHIFT;
4333 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4334 DHD_ERROR(("Version mismatch, dongle reports %d, expecting %d\n",
4335 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4336 else
4337 DHD_INFO(("Dongle ready, protocol version %d\n", bus->sdpcm_ver));
4338 /* make sure for the SDIO_DEVICE_RXDATAINT_MODE_1 corecontrol is proper */
4339 if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev >= 4) &&
4340 (bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_1)) {
4341 uint32 val;
4342
4343 val = R_REG(bus->dhd->osh, &bus->regs->corecontrol);
4344 val &= ~CC_XMTDATAAVAIL_MODE;
4345 val |= CC_XMTDATAAVAIL_CTRL;
4346 W_REG(bus->dhd->osh, &bus->regs->corecontrol, val);
4347
4348 val = R_REG(bus->dhd->osh, &bus->regs->corecontrol);
4349 }
4350
4351#ifdef DHD_DEBUG
4352 /* Retrieve console state address now that firmware should have updated it */
4353 {
4354 sdpcm_shared_t shared;
4355 if (dhdsdio_readshared(bus, &shared) == 0)
4356 bus->console_addr = shared.console_addr;
4357 }
4358#endif /* DHD_DEBUG */
4359 }
4360
4361 /*
4362 * Flow Control has been moved into the RX headers and this out of band
4363 * method isn't used any more. Leave this here for possibly remaining backward
4364 * compatible with older dongles
4365 */
4366 if (hmb_data & HMB_DATA_FC) {
4367 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
4368
4369 if (fcbits & ~bus->flowcontrol)
4370 bus->fc_xoff++;
4371 if (bus->flowcontrol & ~fcbits)
4372 bus->fc_xon++;
4373
4374 bus->fc_rcvd++;
4375 bus->flowcontrol = fcbits;
4376 }
4377
4378#ifdef DHD_DEBUG
4379 /* At least print a message if FW halted */
4380 if (hmb_data & HMB_DATA_FWHALT) {
4381 DHD_ERROR(("INTERNAL ERROR: FIRMWARE HALTED\n"));
4382 dhdsdio_checkdied(bus, NULL, 0);
4383 }
4384#endif /* DHD_DEBUG */
4385
4386 /* Shouldn't be any others */
4387 if (hmb_data & ~(HMB_DATA_DEVREADY |
4388 HMB_DATA_FWHALT |
4389 HMB_DATA_NAKHANDLED |
4390 HMB_DATA_FC |
4391 HMB_DATA_FWREADY |
4392 HMB_DATA_FCDATA_MASK |
4393 HMB_DATA_VERSION_MASK)) {
4394 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4395 }
4396
4397 return intstatus;
4398}
4399
4400static bool
4401dhdsdio_dpc(dhd_bus_t *bus)
4402{
4403 bcmsdh_info_t *sdh = bus->sdh;
4404 sdpcmd_regs_t *regs = bus->regs;
4405 uint32 intstatus, newstatus = 0;
4406 uint retries = 0;
4407 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4408 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4409 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4410 bool rxdone = TRUE; /* Flag for no more read data */
4411 bool resched = FALSE; /* Flag indicating resched wanted */
4412
4413 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
4414
4415 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4416 DHD_ERROR(("%s: Bus down, ret\n", __FUNCTION__));
4417 bus->intstatus = 0;
4418 return 0;
4419 }
4420
4421 /* Start with leftover status bits */
4422 intstatus = bus->intstatus;
4423
4424 dhd_os_sdlock(bus->dhd);
4425
4426 /* If waiting for HTAVAIL, check status */
4427 if (bus->clkstate == CLK_PENDING) {
4428 int err;
4429 uint8 clkctl, devctl = 0;
4430
4431#ifdef DHD_DEBUG
4432 /* Check for inconsistent device control */
4433 devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4434 if (err) {
4435 DHD_ERROR(("%s: error reading DEVCTL: %d\n", __FUNCTION__, err));
4436 bus->dhd->busstate = DHD_BUS_DOWN;
4437 } else {
4438 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4439 }
4440#endif /* DHD_DEBUG */
4441
4442 /* Read CSR, if clock on switch to AVAIL, else ignore */
4443 clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4444 if (err) {
4445 DHD_ERROR(("%s: error reading CSR: %d\n", __FUNCTION__, err));
4446 bus->dhd->busstate = DHD_BUS_DOWN;
4447 }
4448
4449 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl, clkctl));
4450
4451 if (SBSDIO_HTAV(clkctl)) {
4452 devctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4453 if (err) {
4454 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4455 __FUNCTION__, err));
4456 bus->dhd->busstate = DHD_BUS_DOWN;
4457 }
4458 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4459 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, devctl, &err);
4460 if (err) {
4461 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4462 __FUNCTION__, err));
4463 bus->dhd->busstate = DHD_BUS_DOWN;
4464 }
4465 bus->clkstate = CLK_AVAIL;
4466 } else {
4467 goto clkwait;
4468 }
4469 }
4470
4471 BUS_WAKE(bus);
4472
4473 /* Make sure backplane clock is on */
4474 dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
4475 if (bus->clkstate != CLK_AVAIL)
4476 goto clkwait;
4477
4478 /* Pending interrupt indicates new device status */
4479 if (bus->ipend) {
4480 bus->ipend = FALSE;
4481 R_SDREG(newstatus, &regs->intstatus, retries);
4482 bus->f1regdata++;
4483 if (bcmsdh_regfail(bus->sdh))
4484 newstatus = 0;
4485 newstatus &= bus->hostintmask;
4486 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4487 if (newstatus) {
4488 bus->f1regdata++;
4489 if ((bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_0) &&
4490 (newstatus == I_XMTDATA_AVAIL)) {
4491 }
4492 else
4493 W_SDREG(newstatus, &regs->intstatus, retries);
4494 }
4495 }
4496
4497 /* Merge new bits with previous */
4498 intstatus |= newstatus;
4499 bus->intstatus = 0;
4500
4501 /* Handle flow-control change: read new state in case our ack
4502 * crossed another change interrupt. If change still set, assume
4503 * FC ON for safety, let next loop through do the debounce.
4504 */
4505 if (intstatus & I_HMB_FC_CHANGE) {
4506 intstatus &= ~I_HMB_FC_CHANGE;
4507 W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
4508 R_SDREG(newstatus, &regs->intstatus, retries);
4509 bus->f1regdata += 2;
4510 bus->fcstate = !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4511 intstatus |= (newstatus & bus->hostintmask);
4512 }
4513
4514 /* Just being here means nothing more to do for chipactive */
4515 if (intstatus & I_CHIPACTIVE) {
4516 /* ASSERT(bus->clkstate == CLK_AVAIL); */
4517 intstatus &= ~I_CHIPACTIVE;
4518 }
4519
4520 /* Handle host mailbox indication */
4521 if (intstatus & I_HMB_HOST_INT) {
4522 intstatus &= ~I_HMB_HOST_INT;
4523 intstatus |= dhdsdio_hostmail(bus);
4524 }
4525
4526 /* Generally don't ask for these, can get CRC errors... */
4527 if (intstatus & I_WR_OOSYNC) {
4528 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4529 intstatus &= ~I_WR_OOSYNC;
4530 }
4531
4532 if (intstatus & I_RD_OOSYNC) {
4533 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4534 intstatus &= ~I_RD_OOSYNC;
4535 }
4536
4537 if (intstatus & I_SBINT) {
4538 DHD_ERROR(("Dongle reports SBINT\n"));
4539 intstatus &= ~I_SBINT;
4540 }
4541
4542 /* Would be active due to wake-wlan in gSPI */
4543 if (intstatus & I_CHIPACTIVE) {
4544 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4545 intstatus &= ~I_CHIPACTIVE;
4546 }
4547
4548 /* Ignore frame indications if rxskip is set */
4549 if (bus->rxskip) {
4550 intstatus &= ~FRAME_AVAIL_MASK(bus);
4551 }
4552
4553 /* On frame indication, read available frames */
4554 if (PKT_AVAILABLE(bus, intstatus)) {
4555 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4556 if (rxdone || bus->rxskip)
4557 intstatus &= ~FRAME_AVAIL_MASK(bus);
4558 rxlimit -= MIN(framecnt, rxlimit);
4559 }
4560
4561 /* Keep still-pending events for next scheduling */
4562 bus->intstatus = intstatus;
4563
4564clkwait:
4565 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4566 * or clock availability. (Allows tx loop to check ipend if desired.)
4567 * (Unless register access seems hosed, as we may not be able to ACK...)
4568 */
4569 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4570 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4571 __FUNCTION__, rxdone, framecnt));
4572 bus->intdis = FALSE;
4573#if defined(OOB_INTR_ONLY)
4574 bcmsdh_oob_intr_set(1);
4575#endif /* (OOB_INTR_ONLY) */
4576 bcmsdh_intr_enable(sdh);
4577 }
4578
4579 if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL)) {
4580 int ret, i;
4581
4582 ret = dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
4583 (uint8 *)bus->ctrl_frame_buf, (uint32)bus->ctrl_frame_len,
4584 NULL, NULL, NULL);
4585 ASSERT(ret != BCME_PENDING);
4586
4587 if (ret < 0) {
4588 /* On failure, abort the command and terminate the frame */
4589 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
4590 __FUNCTION__, ret));
4591 bus->tx_sderrs++;
4592
4593 bcmsdh_abort(sdh, SDIO_FUNC_2);
4594
4595 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL,
4596 SFC_WF_TERM, NULL);
4597 bus->f1regdata++;
4598
4599 for (i = 0; i < 3; i++) {
4600 uint8 hi, lo;
4601 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4602 SBSDIO_FUNC1_WFRAMEBCHI, NULL);
4603 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4604 SBSDIO_FUNC1_WFRAMEBCLO, NULL);
4605 bus->f1regdata += 2;
4606 if ((hi == 0) && (lo == 0))
4607 break;
4608 }
4609 }
4610 if (ret == 0) {
4611 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4612 }
4613
4614 bus->ctrl_frame_stat = FALSE;
4615 dhd_wait_event_wakeup(bus->dhd);
4616 }
4617 /* Send queued frames (limit 1 if rx may still be pending) */
4618 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4619 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && DATAOK(bus)) {
4620 framecnt = rxdone ? txlimit : MIN(txlimit, dhd_txminmax);
4621 framecnt = dhdsdio_sendfromq(bus, framecnt);
4622 txlimit -= framecnt;
4623 }
4624 /* Resched the DPC if ctrl cmd is pending on bus credit */
4625 if (bus->ctrl_frame_stat)
4626 resched = TRUE;
4627
4628 /* Resched if events or tx frames are pending, else await next interrupt */
4629 /* On failed register access, all bets are off: no resched or interrupts */
4630 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4631 DHD_ERROR(("%s: failed backplane access over SDIO, halting operation %d \n",
4632 __FUNCTION__, bcmsdh_regfail(sdh)));
4633 bus->dhd->busstate = DHD_BUS_DOWN;
4634 bus->intstatus = 0;
4635 } else if (bus->clkstate == CLK_PENDING) {
4636 /* Awaiting I_CHIPACTIVE; don't resched */
4637 } else if (bus->intstatus || bus->ipend ||
4638 (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) && DATAOK(bus)) ||
4639 PKT_AVAILABLE(bus, bus->intstatus)) { /* Read multiple frames */
4640 resched = TRUE;
4641 }
4642
4643 bus->dpc_sched = resched;
4644
4645 /* If we're done for now, turn off clock request. */
4646 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && (bus->clkstate != CLK_PENDING)) {
4647 bus->activity = FALSE;
4648 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
4649 }
4650
4651 dhd_os_sdunlock(bus->dhd);
4652 return resched;
4653}
4654
4655bool
4656dhd_bus_dpc(struct dhd_bus *bus)
4657{
4658 bool resched;
4659
4660 /* Call the DPC directly. */
4661 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __FUNCTION__));
4662 resched = dhdsdio_dpc(bus);
4663
4664 return resched;
4665}
4666
4667void
4668dhdsdio_isr(void *arg)
4669{
4670 dhd_bus_t *bus = (dhd_bus_t*)arg;
4671 bcmsdh_info_t *sdh;
4672
4673 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
4674
4675 if (!bus) {
4676 DHD_ERROR(("%s : bus is null pointer , exit \n", __FUNCTION__));
4677 return;
4678 }
4679 sdh = bus->sdh;
4680
4681 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4682 DHD_ERROR(("%s : bus is down. we have nothing to do\n", __FUNCTION__));
4683 return;
4684 }
4685
4686 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
4687
4688 /* Count the interrupt call */
4689 bus->intrcount++;
4690 bus->ipend = TRUE;
4691
4692 /* Shouldn't get this interrupt if we're sleeping? */
4693 if (bus->sleeping) {
4694 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4695 return;
4696 }
4697
4698 /* Disable additional interrupts (is this needed now)? */
4699 if (bus->intr) {
4700 DHD_INTR(("%s: disable SDIO interrupts\n", __FUNCTION__));
4701 } else {
4702 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4703 }
4704
4705 bcmsdh_intr_disable(sdh);
4706 bus->intdis = TRUE;
4707
4708#if defined(SDIO_ISR_THREAD)
4709 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __FUNCTION__));
4710 DHD_OS_WAKE_LOCK(bus->dhd);
4711 while (dhdsdio_dpc(bus));
4712 DHD_OS_WAKE_UNLOCK(bus->dhd);
4713#else
4714 bus->dpc_sched = TRUE;
4715 dhd_sched_dpc(bus->dhd);
4716#endif
4717
4718}
4719
4720#ifdef SDTEST
4721static void
4722dhdsdio_pktgen_init(dhd_bus_t *bus)
4723{
4724 /* Default to specified length, or full range */
4725 if (dhd_pktgen_len) {
4726 bus->pktgen_maxlen = MIN(dhd_pktgen_len, MAX_PKTGEN_LEN);
4727 bus->pktgen_minlen = bus->pktgen_maxlen;
4728 } else {
4729 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4730 bus->pktgen_minlen = 0;
4731 }
4732 bus->pktgen_len = (uint16)bus->pktgen_minlen;
4733
4734 /* Default to per-watchdog burst with 10s print time */
4735 bus->pktgen_freq = 1;
4736 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4737 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4738
4739 /* Default to echo mode */
4740 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4741 bus->pktgen_stop = 1;
4742}
4743
4744static void
4745dhdsdio_pktgen(dhd_bus_t *bus)
4746{
4747 void *pkt;
4748 uint8 *data;
4749 uint pktcount;
4750 uint fillbyte;
4751 osl_t *osh = bus->dhd->osh;
4752 uint16 len;
4753
4754 /* Display current count if appropriate */
4755 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4756 bus->pktgen_ptick = 0;
4757 printf("%s: send attempts %d rcvd %d\n",
4758 __FUNCTION__, bus->pktgen_sent, bus->pktgen_rcvd);
4759 }
4760
4761 /* For recv mode, just make sure dongle has started sending */
4762 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4763 if (bus->pktgen_rcv_state == PKTGEN_RCV_IDLE) {
4764 bus->pktgen_rcv_state = PKTGEN_RCV_ONGOING;
4765 dhdsdio_sdtest_set(bus, (uint8)bus->pktgen_total);
4766 }
4767 return;
4768 }
4769
4770 /* Otherwise, generate or request the specified number of packets */
4771 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4772 /* Stop if total has been reached */
4773 if (bus->pktgen_total && (bus->pktgen_sent >= bus->pktgen_total)) {
4774 bus->pktgen_count = 0;
4775 break;
4776 }
4777
4778 /* Allocate an appropriate-sized packet */
4779 len = bus->pktgen_len;
4780 if (!(pkt = PKTGET(osh, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4781 TRUE))) {;
4782 DHD_ERROR(("%s: PKTGET failed!\n", __FUNCTION__));
4783 break;
4784 }
4785 PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4786 data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
4787
4788 /* Write test header cmd and extra based on mode */
4789 switch (bus->pktgen_mode) {
4790 case DHD_PKTGEN_ECHO:
4791 *data++ = SDPCM_TEST_ECHOREQ;
4792 *data++ = (uint8)bus->pktgen_sent;
4793 break;
4794
4795 case DHD_PKTGEN_SEND:
4796 *data++ = SDPCM_TEST_DISCARD;
4797 *data++ = (uint8)bus->pktgen_sent;
4798 break;
4799
4800 case DHD_PKTGEN_RXBURST:
4801 *data++ = SDPCM_TEST_BURST;
4802 *data++ = (uint8)bus->pktgen_count;
4803 break;
4804
4805 default:
4806 DHD_ERROR(("Unrecognized pktgen mode %d\n", bus->pktgen_mode));
4807 PKTFREE(osh, pkt, TRUE);
4808 bus->pktgen_count = 0;
4809 return;
4810 }
4811
4812 /* Write test header length field */
4813 *data++ = (len >> 0);
4814 *data++ = (len >> 8);
4815
4816 /* Then fill in the remainder -- N/A for burst, but who cares... */
4817 for (fillbyte = 0; fillbyte < len; fillbyte++)
4818 *data++ = SDPCM_TEST_FILL(fillbyte, (uint8)bus->pktgen_sent);
4819
4820#ifdef DHD_DEBUG
4821 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4822 data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
4823 prhex("dhdsdio_pktgen: Tx Data", data, PKTLEN(osh, pkt) - SDPCM_HDRLEN);
4824 }
4825#endif
4826
4827 /* Send it */
4828 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, TRUE)) {
4829 bus->pktgen_fail++;
4830 if (bus->pktgen_stop && bus->pktgen_stop == bus->pktgen_fail)
4831 bus->pktgen_count = 0;
4832 }
4833 bus->pktgen_sent++;
4834
4835 /* Bump length if not fixed, wrap at max */
4836 if (++bus->pktgen_len > bus->pktgen_maxlen)
4837 bus->pktgen_len = (uint16)bus->pktgen_minlen;
4838
4839 /* Special case for burst mode: just send one request! */
4840 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4841 break;
4842 }
4843}
4844
4845static void
4846dhdsdio_sdtest_set(dhd_bus_t *bus, uint8 count)
4847{
4848 void *pkt;
4849 uint8 *data;
4850 osl_t *osh = bus->dhd->osh;
4851
4852 /* Allocate the packet */
4853 if (!(pkt = PKTGET(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN, TRUE))) {
4854 DHD_ERROR(("%s: PKTGET failed!\n", __FUNCTION__));
4855 return;
4856 }
4857 PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4858 data = (uint8*)PKTDATA(osh, pkt) + SDPCM_HDRLEN;
4859
4860 /* Fill in the test header */
4861 *data++ = SDPCM_TEST_SEND;
4862 *data++ = count;
4863 *data++ = (bus->pktgen_maxlen >> 0);
4864 *data++ = (bus->pktgen_maxlen >> 8);
4865
4866 /* Send it */
4867 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, TRUE))
4868 bus->pktgen_fail++;
4869}
4870
4871
4872static void
4873dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq)
4874{
4875 osl_t *osh = bus->dhd->osh;
4876 uint8 *data;
4877 uint pktlen;
4878
4879 uint8 cmd;
4880 uint8 extra;
4881 uint16 len;
4882 uint16 offset;
4883
4884 /* Check for min length */
4885 if ((pktlen = PKTLEN(osh, pkt)) < SDPCM_TEST_HDRLEN) {
4886 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n", pktlen));
4887 PKTFREE(osh, pkt, FALSE);
4888 return;
4889 }
4890
4891 /* Extract header fields */
4892 data = PKTDATA(osh, pkt);
4893 cmd = *data++;
4894 extra = *data++;
4895 len = *data++; len += *data++ << 8;
4896 DHD_TRACE(("%s:cmd:%d, xtra:%d,len:%d\n", __FUNCTION__, cmd, extra, len));
4897 /* Check length for relevant commands */
4898 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ || cmd == SDPCM_TEST_ECHORSP) {
4899 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4900 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, pktlen %d seq %d"
4901 " cmd %d extra %d len %d\n", pktlen, seq, cmd, extra, len));
4902 PKTFREE(osh, pkt, FALSE);
4903 return;
4904 }
4905 }
4906
4907 /* Process as per command */
4908 switch (cmd) {
4909 case SDPCM_TEST_ECHOREQ:
4910 /* Rx->Tx turnaround ok (even on NDIS w/current implementation) */
4911 *(uint8 *)(PKTDATA(osh, pkt)) = SDPCM_TEST_ECHORSP;
4912 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, TRUE) == 0) {
4913 bus->pktgen_sent++;
4914 } else {
4915 bus->pktgen_fail++;
4916 PKTFREE(osh, pkt, FALSE);
4917 }
4918 bus->pktgen_rcvd++;
4919 break;
4920
4921 case SDPCM_TEST_ECHORSP:
4922 if (bus->ext_loop) {
4923 PKTFREE(osh, pkt, FALSE);
4924 bus->pktgen_rcvd++;
4925 break;
4926 }
4927
4928 for (offset = 0; offset < len; offset++, data++) {
4929 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4930 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: "
4931 "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4932 offset, len, SDPCM_TEST_FILL(offset, extra), *data));
4933 break;
4934 }
4935 }
4936 PKTFREE(osh, pkt, FALSE);
4937 bus->pktgen_rcvd++;
4938 break;
4939
4940 case SDPCM_TEST_DISCARD:
4941 {
4942 int i = 0;
4943 uint8 *prn = data;
4944 uint8 testval = extra;
4945 for (i = 0; i < len; i++) {
4946 if (*prn != testval) {
4947 DHD_ERROR(("DIErr@Pkt#:%d,Ix:%d, expected:0x%x, got:0x%x\n",
4948 i, bus->pktgen_rcvd_rcvsession, testval, *prn));
4949 prn++; testval++;
4950 }
4951 }
4952 }
4953 PKTFREE(osh, pkt, FALSE);
4954 bus->pktgen_rcvd++;
4955 break;
4956
4957 case SDPCM_TEST_BURST:
4958 case SDPCM_TEST_SEND:
4959 default:
4960 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, pktlen %d seq %d"
4961 " cmd %d extra %d len %d\n", pktlen, seq, cmd, extra, len));
4962 PKTFREE(osh, pkt, FALSE);
4963 break;
4964 }
4965
4966 /* For recv mode, stop at limit (and tell dongle to stop sending) */
4967 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4968 if (bus->pktgen_rcv_state != PKTGEN_RCV_IDLE) {
4969 bus->pktgen_rcvd_rcvsession++;
4970
4971 if (bus->pktgen_total &&
4972 (bus->pktgen_rcvd_rcvsession >= bus->pktgen_total)) {
4973 bus->pktgen_count = 0;
4974 DHD_ERROR(("Pktgen:rcv test complete!\n"));
4975 bus->pktgen_rcv_state = PKTGEN_RCV_IDLE;
4976 dhdsdio_sdtest_set(bus, FALSE);
4977 bus->pktgen_rcvd_rcvsession = 0;
4978 }
4979 }
4980 }
4981}
4982#endif /* SDTEST */
4983
4984extern void
4985dhd_disable_intr(dhd_pub_t *dhdp)
4986{
4987 dhd_bus_t *bus;
4988 bus = dhdp->bus;
4989 bcmsdh_intr_disable(bus->sdh);
4990}
4991
4992extern bool
4993dhd_bus_watchdog(dhd_pub_t *dhdp)
4994{
4995 dhd_bus_t *bus;
4996
4997 DHD_TIMER(("%s: Enter\n", __FUNCTION__));
4998
4999 bus = dhdp->bus;
5000
5001 if (bus->dhd->dongle_reset)
5002 return FALSE;
5003
5004 /* Ignore the timer if simulating bus down */
5005 if (bus->sleeping)
5006 return FALSE;
5007
5008 if (dhdp->busstate == DHD_BUS_DOWN)
5009 return FALSE;
5010
5011 /* Poll period: check device if appropriate. */
5012 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
5013 uint32 intstatus = 0;
5014
5015 /* Reset poll tick */
5016 bus->polltick = 0;
5017
5018 /* Check device if no interrupts */
5019 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
5020
5021 if (!bus->dpc_sched) {
5022 uint8 devpend;
5023 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
5024 SDIOD_CCCR_INTPEND, NULL);
5025 intstatus = devpend & (INTR_STATUS_FUNC1 | INTR_STATUS_FUNC2);
5026 }
5027
5028 /* If there is something, make like the ISR and schedule the DPC */
5029 if (intstatus) {
5030 bus->pollcnt++;
5031 bus->ipend = TRUE;
5032 if (bus->intr) {
5033 bcmsdh_intr_disable(bus->sdh);
5034 }
5035 bus->dpc_sched = TRUE;
5036 dhd_sched_dpc(bus->dhd);
5037
5038 }
5039 }
5040
5041 /* Update interrupt tracking */
5042 bus->lastintrs = bus->intrcount;
5043 }
5044
5045#ifdef DHD_DEBUG
5046 /* Poll for console output periodically */
5047 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
5048 bus->console.count += dhd_watchdog_ms;
5049 if (bus->console.count >= dhd_console_ms) {
5050 bus->console.count -= dhd_console_ms;
5051 /* Make sure backplane clock is on */
5052 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
5053 if (dhdsdio_readconsole(bus) < 0)
5054 dhd_console_ms = 0; /* On error, stop trying */
5055 }
5056 }
5057#endif /* DHD_DEBUG */
5058
5059#ifdef SDTEST
5060 /* Generate packets if configured */
5061 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
5062 /* Make sure backplane clock is on */
5063 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
5064 bus->pktgen_tick = 0;
5065 dhdsdio_pktgen(bus);
5066 }
5067#endif
5068
5069 /* On idle timeout clear activity flag and/or turn off clock */
5070 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
5071 if (++bus->idlecount >= bus->idletime) {
5072 bus->idlecount = 0;
5073 if (bus->activity) {
5074 bus->activity = FALSE;
5075 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
5076 }
5077 }
5078 }
5079
5080 return bus->ipend;
5081}
5082
5083#ifdef DHD_DEBUG
5084extern int
5085dhd_bus_console_in(dhd_pub_t *dhdp, uchar *msg, uint msglen)
5086{
5087 dhd_bus_t *bus = dhdp->bus;
5088 uint32 addr, val;
5089 int rv;
5090 void *pkt;
5091
5092 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
5093 if (bus->console_addr == 0)
5094 return BCME_UNSUPPORTED;
5095
5096 /* Exclusive bus access */
5097 dhd_os_sdlock(bus->dhd);
5098
5099 /* Don't allow input if dongle is in reset */
5100 if (bus->dhd->dongle_reset) {
5101 dhd_os_sdunlock(bus->dhd);
5102 return BCME_NOTREADY;
5103 }
5104
5105 /* Request clock to allow SDIO accesses */
5106 BUS_WAKE(bus);
5107 /* No pend allowed since txpkt is called later, ht clk has to be on */
5108 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
5109
5110 /* Zero cbuf_index */
5111 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, cbuf_idx);
5112 val = htol32(0);
5113 if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
5114 goto done;
5115
5116 /* Write message into cbuf */
5117 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, cbuf);
5118 if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0)
5119 goto done;
5120
5121 /* Write length into vcons_in */
5122 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, vcons_in);
5123 val = htol32(msglen);
5124 if ((rv = dhdsdio_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
5125 goto done;
5126
5127 /* Bump dongle by sending an empty packet on the event channel.
5128 * sdpcm_sendup (RX) checks for virtual console input.
5129 */
5130 if ((pkt = PKTGET(bus->dhd->osh, 4 + SDPCM_RESERVE, TRUE)) != NULL)
5131 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, TRUE);
5132
5133done:
5134 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5135 bus->activity = FALSE;
5136 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
5137 }
5138
5139 dhd_os_sdunlock(bus->dhd);
5140
5141 return rv;
5142}
5143#endif /* DHD_DEBUG */
5144
5145#ifdef DHD_DEBUG
5146static void
5147dhd_dump_cis(uint fn, uint8 *cis)
5148{
5149 uint byte, tag, tdata;
5150 DHD_INFO(("Function %d CIS:\n", fn));
5151
5152 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5153 if ((byte % 16) == 0)
5154 DHD_INFO((" "));
5155 DHD_INFO(("%02x ", cis[byte]));
5156 if ((byte % 16) == 15)
5157 DHD_INFO(("\n"));
5158 if (!tdata--) {
5159 tag = cis[byte];
5160 if (tag == 0xff)
5161 break;
5162 else if (!tag)
5163 tdata = 0;
5164 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5165 tdata = cis[byte + 1] + 1;
5166 else
5167 DHD_INFO(("]"));
5168 }
5169 }
5170 if ((byte % 16) != 15)
5171 DHD_INFO(("\n"));
5172}
5173#endif /* DHD_DEBUG */
5174
5175static bool
5176dhdsdio_chipmatch(uint16 chipid)
5177{
5178 if (chipid == BCM4325_CHIP_ID)
5179 return TRUE;
5180 if (chipid == BCM4329_CHIP_ID)
5181 return TRUE;
5182 if (chipid == BCM4315_CHIP_ID)
5183 return TRUE;
5184 if (chipid == BCM4319_CHIP_ID)
5185 return TRUE;
5186 if (chipid == BCM4336_CHIP_ID)
5187 return TRUE;
5188 if (chipid == BCM4330_CHIP_ID)
5189 return TRUE;
5190 if (chipid == BCM43237_CHIP_ID)
5191 return TRUE;
5192 if (chipid == BCM43362_CHIP_ID)
5193 return TRUE;
5194 if (chipid == BCM43239_CHIP_ID)
5195 return TRUE;
5196 return FALSE;
5197}
5198
5199static void *
5200dhdsdio_probe(uint16 venid, uint16 devid, uint16 bus_no, uint16 slot,
5201 uint16 func, uint bustype, void *regsva, osl_t * osh, void *sdh, void *dev)
5202{
5203 int ret;
5204 dhd_bus_t *bus;
5205 dhd_cmn_t *cmn;
5206#ifdef GET_CUSTOM_MAC_ENABLE
5207 struct ether_addr ea_addr;
5208#endif /* GET_CUSTOM_MAC_ENABLE */
5209#ifdef PROP_TXSTATUS
5210 uint up = 0;
5211#endif
5212
5213 /* Init global variables at run-time, not as part of the declaration.
5214 * This is required to support init/de-init of the driver. Initialization
5215 * of globals as part of the declaration results in non-deterministic
5216 * behavior since the value of the globals may be different on the
5217 * first time that the driver is initialized vs subsequent initializations.
5218 */
5219 dhd_txbound = DHD_TXBOUND;
5220 dhd_rxbound = DHD_RXBOUND;
5221 dhd_alignctl = TRUE;
5222 sd1idle = TRUE;
5223 dhd_readahead = TRUE;
5224 retrydata = FALSE;
5225 dhd_doflow = FALSE;
5226 dhd_dongle_memsize = 0;
5227 dhd_txminmax = DHD_TXMINMAX;
5228
5229 forcealign = TRUE;
5230
5231
5232 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5233 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __FUNCTION__, venid, devid));
5234
5235 /* We make assumptions about address window mappings */
5236 ASSERT((uintptr)regsva == SI_ENUM_BASE);
5237
5238 /* BCMSDH passes venid and devid based on CIS parsing -- but low-power start
5239 * means early parse could fail, so here we should get either an ID
5240 * we recognize OR (-1) indicating we must request power first.
5241 */
5242 /* Check the Vendor ID */
5243 switch (venid) {
5244 case 0x0000:
5245 case VENDOR_BROADCOM:
5246 break;
5247 default:
5248 DHD_ERROR(("%s: unknown vendor: 0x%04x\n",
5249 __FUNCTION__, venid));
5250 return NULL;
5251 }
5252
5253 /* Check the Device ID and make sure it's one that we support */
5254 switch (devid) {
5255 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5256 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5257 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5258 DHD_INFO(("%s: found 4325 Dongle\n", __FUNCTION__));
5259 break;
5260 case BCM4329_D11N_ID: /* 4329 802.11n dualband device */
5261 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5262 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5263 case 0x4329:
5264 DHD_INFO(("%s: found 4329 Dongle\n", __FUNCTION__));
5265 break;
5266 case BCM4315_D11DUAL_ID: /* 4315 802.11a/g id */
5267 case BCM4315_D11G_ID: /* 4315 802.11g id */
5268 case BCM4315_D11A_ID: /* 4315 802.11a id */
5269 DHD_INFO(("%s: found 4315 Dongle\n", __FUNCTION__));
5270 break;
5271 case BCM4319_D11N_ID: /* 4319 802.11n id */
5272 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5273 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5274 DHD_INFO(("%s: found 4319 Dongle\n", __FUNCTION__));
5275 break;
5276 case 0:
5277 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5278 __FUNCTION__));
5279 break;
5280
5281 default:
5282 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5283 __FUNCTION__, venid, devid));
5284 return NULL;
5285 }
5286
5287 if (osh == NULL) {
5288 /* Ask the OS interface part for an OSL handle */
5289 if (!(osh = dhd_osl_attach(sdh, DHD_BUS))) {
5290 DHD_ERROR(("%s: osl_attach failed!\n", __FUNCTION__));
5291 return NULL;
5292 }
5293 }
5294
5295 /* Allocate private bus interface state */
5296 if (!(bus = MALLOC(osh, sizeof(dhd_bus_t)))) {
5297 DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
5298 goto fail;
5299 }
5300 bzero(bus, sizeof(dhd_bus_t));
5301 bus->sdh = sdh;
5302 bus->cl_devid = (uint16)devid;
5303 bus->bus = DHD_BUS;
5304 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5305 bus->usebufpool = FALSE; /* Use bufpool if allocated, else use locally malloced rxbuf */
5306
5307 /* attach the common module */
5308 if (!(cmn = dhd_common_init(bus->cl_devid, osh))) {
5309 DHD_ERROR(("%s: dhd_common_init failed\n", __FUNCTION__));
5310 goto fail;
5311 }
5312
5313 /* attempt to attach to the dongle */
5314 if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) {
5315 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __FUNCTION__));
5316 dhd_common_deinit(NULL, cmn);
5317 goto fail;
5318 }
5319
5320 /* Attach to the dhd/OS/network interface */
5321 if (!(bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE, dev))) {
5322 DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__));
5323 goto fail;
5324 }
5325
5326 bus->dhd->cmn = cmn;
5327 cmn->dhd = bus->dhd;
5328
5329 /* Allocate buffers */
5330 if (!(dhdsdio_probe_malloc(bus, osh, sdh))) {
5331 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __FUNCTION__));
5332 goto fail;
5333 }
5334
5335 if (!(dhdsdio_probe_init(bus, osh, sdh))) {
5336 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __FUNCTION__));
5337 goto fail;
5338 }
5339
5340 if (bus->intr) {
5341 /* Register interrupt callback, but mask it (not operational yet). */
5342 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n", __FUNCTION__));
5343 bcmsdh_intr_disable(sdh);
5344 if ((ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus)) != 0) {
5345 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5346 __FUNCTION__, ret));
5347 goto fail;
5348 }
5349 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __FUNCTION__));
5350 } else {
5351 DHD_INFO(("%s: SDIO interrupt function is NOT registered due to polling mode\n",
5352 __FUNCTION__));
5353 }
5354
5355 DHD_INFO(("%s: completed!!\n", __FUNCTION__));
5356
5357#ifdef GET_CUSTOM_MAC_ENABLE
5358 /* Read MAC address from external customer place */
5359 memset(&ea_addr, 0, sizeof(ea_addr));
5360 ret = dhd_custom_get_mac_address(ea_addr.octet);
5361 if (!ret) {
5362 memcpy(bus->dhd->mac.octet, (void *)&ea_addr, ETHER_ADDR_LEN);
5363 }
5364#endif /* GET_CUSTOM_MAC_ENABLE */
5365
5366 /* if firmware path present try to download and bring up bus */
5367 if (dhd_download_fw_on_driverload && (ret = dhd_bus_start(bus->dhd)) != 0) {
5368 DHD_ERROR(("%s: dhd_bus_start failed\n", __FUNCTION__));
5369 if (ret == BCME_NOTUP)
5370 goto fail;
5371 }
5372 /* Ok, have the per-port tell the stack we're open for business */
5373 if (dhd_net_attach(bus->dhd, 0) != 0) {
5374 DHD_ERROR(("%s: Net attach failed!!\n", __FUNCTION__));
5375 goto fail;
5376 }
5377
5378#ifdef PROP_TXSTATUS
5379 if (dhd_download_fw_on_driverload)
5380 dhd_wl_ioctl_cmd(bus->dhd, WLC_UP, (char *)&up, sizeof(up), TRUE, 0);
5381#endif
5382 return bus;
5383
5384fail:
5385 dhdsdio_release(bus, osh);
5386 return NULL;
5387}
5388
5389static bool
5390dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva,
5391 uint16 devid)
5392{
5393 int err = 0;
5394 uint8 clkctl = 0;
5395
5396 bus->alp_only = TRUE;
5397
5398 /* Return the window to backplane enumeration space for core access */
5399 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE)) {
5400 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __FUNCTION__));
5401 }
5402
5403#ifdef DHD_DEBUG
5404 DHD_ERROR(("F1 signature read @0x18000000=0x%4x\n",
5405 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4)));
5406
5407#endif /* DHD_DEBUG */
5408
5409
5410 /* Force PLL off until si_attach() programs PLL control regs */
5411
5412
5413
5414 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, DHD_INIT_CLKCTL1, &err);
5415 if (!err)
5416 clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, &err);
5417
5418 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5419 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
5420 err, DHD_INIT_CLKCTL1, clkctl));
5421 goto fail;
5422 }
5423
5424
5425#ifdef DHD_DEBUG
5426 if (DHD_INFO_ON()) {
5427 uint fn, numfn;
5428 uint8 *cis[SDIOD_MAX_IOFUNCS];
5429 int err = 0;
5430
5431 numfn = bcmsdh_query_iofnum(sdh);
5432 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5433
5434 /* Make sure ALP is available before trying to read CIS */
5435 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5436 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
5437 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5438
5439 /* Now request ALP be put on the bus */
5440 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5441 DHD_INIT_CLKCTL2, &err);
5442 OSL_DELAY(65);
5443
5444 for (fn = 0; fn <= numfn; fn++) {
5445 if (!(cis[fn] = MALLOC(osh, SBSDIO_CIS_SIZE_LIMIT))) {
5446 DHD_INFO(("dhdsdio_probe: fn %d cis malloc failed\n", fn));
5447 break;
5448 }
5449 bzero(cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5450
5451 if ((err = bcmsdh_cis_read(sdh, fn, cis[fn], SBSDIO_CIS_SIZE_LIMIT))) {
5452 DHD_INFO(("dhdsdio_probe: fn %d cis read err %d\n", fn, err));
5453 MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5454 break;
5455 }
5456 dhd_dump_cis(fn, cis[fn]);
5457 }
5458
5459 while (fn-- > 0) {
5460 ASSERT(cis[fn]);
5461 MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5462 }
5463
5464 if (err) {
5465 DHD_ERROR(("dhdsdio_probe: failure reading or parsing CIS\n"));
5466 goto fail;
5467 }
5468 }
5469#endif /* DHD_DEBUG */
5470
5471 /* si_attach() will provide an SI handle and scan the backplane */
5472 if (!(bus->sih = si_attach((uint)devid, osh, regsva, DHD_BUS, sdh,
5473 &bus->vars, &bus->varsz))) {
5474 DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__));
5475 goto fail;
5476 }
5477
5478 bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
5479
5480 if (!dhdsdio_chipmatch((uint16)bus->sih->chip)) {
5481 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5482 __FUNCTION__, bus->sih->chip));
5483 goto fail;
5484 }
5485
5486
5487 si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
5488
5489
5490 /* Get info on the ARM and SOCRAM cores... */
5491 if (!DHD_NOPMU(bus)) {
5492 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
5493 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
5494 bus->armrev = si_corerev(bus->sih);
5495 } else {
5496 DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__));
5497 goto fail;
5498 }
5499 if (!(bus->orig_ramsize = si_socram_size(bus->sih))) {
5500 DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__));
5501 goto fail;
5502 }
5503 bus->ramsize = bus->orig_ramsize;
5504 if (dhd_dongle_memsize)
5505 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5506
5507 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5508 bus->ramsize, bus->orig_ramsize));
5509 }
5510
5511 /* ...but normally deal with the SDPCMDEV core */
5512 if (!(bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0)) &&
5513 !(bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0))) {
5514 DHD_ERROR(("%s: failed to find SDIODEV core!\n", __FUNCTION__));
5515 goto fail;
5516 }
5517 bus->sdpcmrev = si_corerev(bus->sih);
5518
5519 /* Set core control so an SDIO reset does a backplane reset */
5520 OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
5521 bus->rxint_mode = SDIO_DEVICE_HMB_RXINT;
5522
5523 if ((bus->sih->buscoretype == SDIOD_CORE_ID) && (bus->sdpcmrev >= 4) &&
5524 (bus->rxint_mode == SDIO_DEVICE_RXDATAINT_MODE_1))
5525 {
5526 uint32 val;
5527
5528 val = R_REG(osh, &bus->regs->corecontrol);
5529 val &= ~CC_XMTDATAAVAIL_MODE;
5530 val |= CC_XMTDATAAVAIL_CTRL;
5531 W_REG(osh, &bus->regs->corecontrol, val);
5532 }
5533
5534
5535 pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
5536
5537 /* Locate an appropriately-aligned portion of hdrbuf */
5538 bus->rxhdr = (uint8 *)ROUNDUP((uintptr)&bus->hdrbuf[0], DHD_SDALIGN);
5539
5540 /* Set the poll and/or interrupt flags */
5541 bus->intr = (bool)dhd_intr;
5542 if ((bus->poll = (bool)dhd_poll))
5543 bus->pollrate = 1;
5544
5545 return TRUE;
5546
5547fail:
5548 if (bus->sih != NULL)
5549 si_detach(bus->sih);
5550 return FALSE;
5551}
5552
5553static bool
5554dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh)
5555{
5556 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5557
5558 if (bus->dhd->maxctl) {
5559 bus->rxblen = ROUNDUP((bus->dhd->maxctl + SDPCM_HDRLEN), ALIGNMENT) + DHD_SDALIGN;
5560 if (!(bus->rxbuf = DHD_OS_PREALLOC(osh, DHD_PREALLOC_RXBUF, bus->rxblen))) {
5561 DHD_ERROR(("%s: MALLOC of %d-byte rxbuf failed\n",
5562 __FUNCTION__, bus->rxblen));
5563 goto fail;
5564 }
5565 }
5566 /* Allocate buffer to receive glomed packet */
5567 if (!(bus->databuf = DHD_OS_PREALLOC(osh, DHD_PREALLOC_DATABUF, MAX_DATA_BUF))) {
5568 DHD_ERROR(("%s: MALLOC of %d-byte databuf failed\n",
5569 __FUNCTION__, MAX_DATA_BUF));
5570 /* release rxbuf which was already located as above */
5571 if (!bus->rxblen)
5572 DHD_OS_PREFREE(osh, bus->rxbuf, bus->rxblen);
5573 goto fail;
5574 }
5575
5576 /* Align the buffer */
5577 if ((uintptr)bus->databuf % DHD_SDALIGN)
5578 bus->dataptr = bus->databuf + (DHD_SDALIGN - ((uintptr)bus->databuf % DHD_SDALIGN));
5579 else
5580 bus->dataptr = bus->databuf;
5581
5582 return TRUE;
5583
5584fail:
5585 return FALSE;
5586}
5587
5588static bool
5589dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh)
5590{
5591 int32 fnum;
5592
5593 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5594
5595#ifdef SDTEST
5596 dhdsdio_pktgen_init(bus);
5597#endif /* SDTEST */
5598
5599 /* Disable F2 to clear any intermediate frame state on the dongle */
5600 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1, NULL);
5601
5602 bus->dhd->busstate = DHD_BUS_DOWN;
5603 bus->sleeping = FALSE;
5604 bus->rxflow = FALSE;
5605 bus->prev_rxlim_hit = 0;
5606
5607
5608 /* Done with backplane-dependent accesses, can drop clock... */
5609 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5610
5611 /* ...and initialize clock/power states */
5612 bus->clkstate = CLK_SDONLY;
5613 bus->idletime = (int32)dhd_idletime;
5614 bus->idleclock = DHD_IDLE_ACTIVE;
5615
5616 /* Query the SD clock speed */
5617 if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
5618 &bus->sd_divisor, sizeof(int32), FALSE) != BCME_OK) {
5619 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_divisor"));
5620 bus->sd_divisor = -1;
5621 } else {
5622 DHD_INFO(("%s: Initial value for %s is %d\n",
5623 __FUNCTION__, "sd_divisor", bus->sd_divisor));
5624 }
5625
5626 /* Query the SD bus mode */
5627 if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
5628 &bus->sd_mode, sizeof(int32), FALSE) != BCME_OK) {
5629 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_mode"));
5630 bus->sd_mode = -1;
5631 } else {
5632 DHD_INFO(("%s: Initial value for %s is %d\n",
5633 __FUNCTION__, "sd_mode", bus->sd_mode));
5634 }
5635
5636 /* Query the F2 block size, set roundup accordingly */
5637 fnum = 2;
5638 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(int32),
5639 &bus->blocksize, sizeof(int32), FALSE) != BCME_OK) {
5640 bus->blocksize = 0;
5641 DHD_ERROR(("%s: fail on %s get\n", __FUNCTION__, "sd_blocksize"));
5642 } else {
5643 DHD_INFO(("%s: Initial value for %s is %d\n",
5644 __FUNCTION__, "sd_blocksize", bus->blocksize));
5645 }
5646 bus->roundup = MIN(max_roundup, bus->blocksize);
5647
5648 /* Query if bus module supports packet chaining, default to use if supported */
5649 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5650 &bus->sd_rxchain, sizeof(int32), FALSE) != BCME_OK) {
5651 bus->sd_rxchain = FALSE;
5652 } else {
5653 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5654 __FUNCTION__, (bus->sd_rxchain ? "supports" : "does not support")));
5655 }
5656 bus->use_rxchain = (bool)bus->sd_rxchain;
5657
5658 return TRUE;
5659}
5660
5661bool
5662dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
5663 char *pfw_path, char *pnv_path)
5664{
5665 bool ret;
5666 bus->fw_path = pfw_path;
5667 bus->nv_path = pnv_path;
5668
5669 ret = dhdsdio_download_firmware(bus, osh, bus->sdh);
5670
5671
5672 return ret;
5673}
5674
5675static bool
5676dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh, void *sdh)
5677{
5678 bool ret;
5679
5680 /* Download the firmware */
5681 DHD_OS_WAKE_LOCK(bus->dhd);
5682 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
5683
5684 ret = _dhdsdio_download_firmware(bus) == 0;
5685
5686 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
5687 DHD_OS_WAKE_UNLOCK(bus->dhd);
5688 return ret;
5689}
5690
5691/* Detach and free everything */
5692static void
5693dhdsdio_release(dhd_bus_t *bus, osl_t *osh)
5694{
5695 bool dongle_isolation = FALSE;
5696 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5697
5698 if (bus) {
5699 ASSERT(osh);
5700
5701 /* De-register interrupt handler */
5702 bcmsdh_intr_disable(bus->sdh);
5703 bcmsdh_intr_dereg(bus->sdh);
5704
5705 if (bus->dhd) {
5706 dhd_common_deinit(bus->dhd, NULL);
5707 dongle_isolation = bus->dhd->dongle_isolation;
5708 dhd_detach(bus->dhd);
5709 dhdsdio_release_dongle(bus, osh, dongle_isolation, TRUE);
5710 dhd_free(bus->dhd);
5711 bus->dhd = NULL;
5712 }
5713
5714 dhdsdio_release_malloc(bus, osh);
5715
5716#ifdef DHD_DEBUG
5717 if (bus->console.buf != NULL)
5718 MFREE(osh, bus->console.buf, bus->console.bufsize);
5719#endif
5720
5721 MFREE(osh, bus, sizeof(dhd_bus_t));
5722 }
5723
5724 if (osh)
5725 dhd_osl_detach(osh);
5726
5727 DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
5728}
5729
5730static void
5731dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh)
5732{
5733 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5734
5735 if (bus->dhd && bus->dhd->dongle_reset)
5736 return;
5737
5738 if (bus->rxbuf) {
5739#ifndef DHD_USE_STATIC_BUF
5740 MFREE(osh, bus->rxbuf, bus->rxblen);
5741#endif
5742 bus->rxctl = bus->rxbuf = NULL;
5743 bus->rxlen = 0;
5744 }
5745
5746 if (bus->databuf) {
5747#ifndef DHD_USE_STATIC_BUF
5748 MFREE(osh, bus->databuf, MAX_DATA_BUF);
5749#endif
5750 bus->databuf = NULL;
5751 }
5752
5753 if (bus->vars && bus->varsz) {
5754 MFREE(osh, bus->vars, bus->varsz);
5755 bus->vars = NULL;
5756 }
5757
5758}
5759
5760
5761static void
5762dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag)
5763{
5764 DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__,
5765 bus->dhd, bus->dhd->dongle_reset));
5766
5767 if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag)
5768 return;
5769
5770 if (bus->sih) {
5771 if (bus->dhd) {
5772 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
5773 }
5774#if !defined(BCMLXSDMMC)
5775 if (dongle_isolation == FALSE)
5776 si_watchdog(bus->sih, 4);
5777#endif /* !defined(BCMLXSDMMC) */
5778 if (bus->dhd) {
5779 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
5780 }
5781 si_detach(bus->sih);
5782 if (bus->vars && bus->varsz)
5783 MFREE(osh, bus->vars, bus->varsz);
5784 bus->vars = NULL;
5785 }
5786
5787 DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
5788}
5789
5790static void
5791dhdsdio_disconnect(void *ptr)
5792{
5793 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5794
5795 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5796
5797 if (bus) {
5798 ASSERT(bus->dhd);
5799 dhdsdio_release(bus, bus->dhd->osh);
5800 }
5801
5802 DHD_TRACE(("%s: Disconnected\n", __FUNCTION__));
5803}
5804
5805
5806/* Register/Unregister functions are called by the main DHD entry
5807 * point (e.g. module insertion) to link with the bus driver, in
5808 * order to look for or await the device.
5809 */
5810
5811static bcmsdh_driver_t dhd_sdio = {
5812 dhdsdio_probe,
5813 dhdsdio_disconnect
5814};
5815
5816int
5817dhd_bus_register(void)
5818{
5819 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5820
5821 return bcmsdh_register(&dhd_sdio);
5822}
5823
5824void
5825dhd_bus_unregister(void)
5826{
5827 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
5828
5829 bcmsdh_unregister();
5830}
5831
5832#ifdef BCMEMBEDIMAGE
5833static int
5834dhdsdio_download_code_array(struct dhd_bus *bus)
5835{
5836 int bcmerror = -1;
5837 int offset = 0;
5838 unsigned char *ularray = NULL;
5839
5840 DHD_INFO(("%s: download embedded firmware...\n", __FUNCTION__));
5841
5842 /* Download image */
5843 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5844 bcmerror = dhdsdio_membytes(bus, TRUE, offset,
5845 (uint8 *) (dlarray + offset), MEMBLOCK);
5846 if (bcmerror) {
5847 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
5848 __FUNCTION__, bcmerror, MEMBLOCK, offset));
5849 goto err;
5850 }
5851
5852 offset += MEMBLOCK;
5853 }
5854
5855 if (offset < sizeof(dlarray)) {
5856 bcmerror = dhdsdio_membytes(bus, TRUE, offset,
5857 (uint8 *) (dlarray + offset), sizeof(dlarray) - offset);
5858 if (bcmerror) {
5859 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
5860 __FUNCTION__, bcmerror, sizeof(dlarray) - offset, offset));
5861 goto err;
5862 }
5863 }
5864
5865#ifdef DHD_DEBUG
5866 /* Upload and compare the downloaded code */
5867 {
5868 ularray = MALLOC(bus->dhd->osh, bus->ramsize);
5869 /* Upload image to verify downloaded contents. */
5870 offset = 0;
5871 memset(ularray, 0xaa, bus->ramsize);
5872 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5873 bcmerror = dhdsdio_membytes(bus, FALSE, offset, ularray + offset, MEMBLOCK);
5874 if (bcmerror) {
5875 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5876 __FUNCTION__, bcmerror, MEMBLOCK, offset));
5877 goto err;
5878 }
5879
5880 offset += MEMBLOCK;
5881 }
5882
5883 if (offset < sizeof(dlarray)) {
5884 bcmerror = dhdsdio_membytes(bus, FALSE, offset,
5885 ularray + offset, sizeof(dlarray) - offset);
5886 if (bcmerror) {
5887 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5888 __FUNCTION__, bcmerror, sizeof(dlarray) - offset, offset));
5889 goto err;
5890 }
5891 }
5892
5893 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5894 DHD_ERROR(("%s: Downloaded image is corrupted (%s, %s, %s).\n",
5895 __FUNCTION__, dlimagename, dlimagever, dlimagedate));
5896 goto err;
5897 } else
5898 DHD_ERROR(("%s: Download, Upload and compare succeeded (%s, %s, %s).\n",
5899 __FUNCTION__, dlimagename, dlimagever, dlimagedate));
5900
5901 }
5902#endif /* DHD_DEBUG */
5903
5904err:
5905 if (ularray)
5906 MFREE(bus->dhd->osh, ularray, bus->ramsize);
5907 return bcmerror;
5908}
5909#endif /* BCMEMBEDIMAGE */
5910
5911static int
5912dhdsdio_download_code_file(struct dhd_bus *bus, char *pfw_path)
5913{
5914 int bcmerror = -1;
5915 int offset = 0;
5916 uint len;
5917 void *image = NULL;
5918 uint8 *memblock = NULL, *memptr;
5919
5920 DHD_INFO(("%s: download firmware %s\n", __FUNCTION__, pfw_path));
5921
5922 image = dhd_os_open_image(pfw_path);
5923 if (image == NULL)
5924 goto err;
5925
5926 memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
5927 if (memblock == NULL) {
5928 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
5929 goto err;
5930 }
5931 if ((uint32)(uintptr)memblock % DHD_SDALIGN)
5932 memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
5933
5934 /* Download image */
5935 while ((len = dhd_os_get_image_block((char*)memptr, MEMBLOCK, image))) {
5936 bcmerror = dhdsdio_membytes(bus, TRUE, offset, memptr, len);
5937 if (bcmerror) {
5938 DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
5939 __FUNCTION__, bcmerror, MEMBLOCK, offset));
5940 goto err;
5941 }
5942
5943 offset += MEMBLOCK;
5944 }
5945
5946err:
5947 if (memblock)
5948 MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN);
5949
5950 if (image)
5951 dhd_os_close_image(image);
5952
5953 return bcmerror;
5954}
5955
5956/*
5957 EXAMPLE: nvram_array
5958 nvram_arry format:
5959 name=value
5960 Use carriage return at the end of each assignment, and an empty string with
5961 carriage return at the end of array.
5962
5963 For example:
5964 unsigned char nvram_array[] = {"name1=value1\n", "name2=value2\n", "\n"};
5965 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5966
5967 Search "EXAMPLE: nvram_array" to see how the array is activated.
5968*/
5969
5970void
5971dhd_bus_set_nvram_params(struct dhd_bus * bus, const char *nvram_params)
5972{
5973 bus->nvram_params = nvram_params;
5974}
5975
5976static int
5977dhdsdio_download_nvram(struct dhd_bus *bus)
5978{
5979 int bcmerror = -1;
5980 uint len;
5981 void * image = NULL;
5982 char * memblock = NULL;
5983 char *bufp;
5984 char *pnv_path;
5985 bool nvram_file_exists;
5986
5987 pnv_path = bus->nv_path;
5988
5989 nvram_file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0'));
5990 if (!nvram_file_exists && (bus->nvram_params == NULL))
5991 return (0);
5992
5993 if (nvram_file_exists) {
5994 image = dhd_os_open_image(pnv_path);
5995 if (image == NULL)
5996 goto err;
5997 }
5998
5999 memblock = MALLOC(bus->dhd->osh, MAX_NVRAMBUF_SIZE);
6000 if (memblock == NULL) {
6001 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
6002 __FUNCTION__, MAX_NVRAMBUF_SIZE));
6003 goto err;
6004 }
6005
6006 /* Download variables */
6007 if (nvram_file_exists) {
6008 len = dhd_os_get_image_block(memblock, MAX_NVRAMBUF_SIZE, image);
6009 }
6010 else {
6011 len = strlen(bus->nvram_params);
6012 ASSERT(len <= MAX_NVRAMBUF_SIZE);
6013 memcpy(memblock, bus->nvram_params, len);
6014 }
6015 if (len > 0 && len < MAX_NVRAMBUF_SIZE) {
6016 bufp = (char *)memblock;
6017 bufp[len] = 0;
6018 len = process_nvram_vars(bufp, len);
6019 if (len % 4) {
6020 len += 4 - (len % 4);
6021 }
6022 bufp += len;
6023 *bufp++ = 0;
6024 if (len)
6025 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
6026 if (bcmerror) {
6027 DHD_ERROR(("%s: error downloading vars: %d\n",
6028 __FUNCTION__, bcmerror));
6029 }
6030 }
6031 else {
6032 DHD_ERROR(("%s: error reading nvram file: %d\n",
6033 __FUNCTION__, len));
6034 bcmerror = BCME_SDIO_ERROR;
6035 }
6036
6037err:
6038 if (memblock)
6039 MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE);
6040
6041 if (image)
6042 dhd_os_close_image(image);
6043
6044 return bcmerror;
6045}
6046
6047static int
6048_dhdsdio_download_firmware(struct dhd_bus *bus)
6049{
6050 int bcmerror = -1;
6051 char *p;
6052
6053 bool embed = FALSE; /* download embedded firmware */
6054 bool dlok = FALSE; /* download firmware succeeded */
6055
6056 /* Out immediately if no image to download */
6057 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
6058#ifdef BCMEMBEDIMAGE
6059 embed = TRUE;
6060#else
6061 return 0;
6062#endif
6063 }
6064
6065 /* Keep arm in reset */
6066 if (dhdsdio_download_state(bus, TRUE)) {
6067 DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__));
6068 goto err;
6069 }
6070
6071 /* External image takes precedence if specified */
6072 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
6073
6074 /* replace bcm43xx with bcm4330 or bcm4329 */
6075 if ((p = strstr(bus->fw_path, "bcm43xx"))) {
6076 if (bus->cl_devid == 0x4329) {
6077 *(p + 5)='2';
6078 *(p + 6)='9';
6079 }
6080 if (bus->cl_devid == 0x4330) {
6081 *(p + 5)='3';
6082 *(p + 6)='0';
6083 }
6084 }
6085
6086 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
6087 DHD_ERROR(("%s: dongle image file download failed\n", __FUNCTION__));
6088#ifdef BCMEMBEDIMAGE
6089 embed = TRUE;
6090#else
6091 goto err;
6092#endif
6093 }
6094 else {
6095 embed = FALSE;
6096 dlok = TRUE;
6097 }
6098 }
6099#ifdef BCMEMBEDIMAGE
6100 if (embed) {
6101 if (dhdsdio_download_code_array(bus)) {
6102 DHD_ERROR(("%s: dongle image array download failed\n", __FUNCTION__));
6103 goto err;
6104 }
6105 else {
6106 dlok = TRUE;
6107 }
6108 }
6109#endif
6110 if (!dlok) {
6111 DHD_ERROR(("%s: dongle image download failed\n", __FUNCTION__));
6112 goto err;
6113 }
6114
6115 /* EXAMPLE: nvram_array */
6116 /* If a valid nvram_arry is specified as above, it can be passed down to dongle */
6117 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
6118
6119 /* External nvram takes precedence if specified */
6120 if (dhdsdio_download_nvram(bus)) {
6121 DHD_ERROR(("%s: dongle nvram file download failed\n", __FUNCTION__));
6122 goto err;
6123 }
6124
6125 /* Take arm out of reset */
6126 if (dhdsdio_download_state(bus, FALSE)) {
6127 DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__));
6128 goto err;
6129 }
6130
6131 bcmerror = 0;
6132
6133err:
6134 return bcmerror;
6135}
6136
6137static int
6138dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes,
6139 void *pkt, bcmsdh_cmplt_fn_t complete, void *handle)
6140{
6141 int status;
6142
6143 status = bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete, handle);
6144
6145 return status;
6146}
6147
6148static int
6149dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, uint8 *buf, uint nbytes,
6150 void *pkt, bcmsdh_cmplt_fn_t complete, void *handle)
6151{
6152 return (bcmsdh_send_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete, handle));
6153}
6154
6155uint
6156dhd_bus_chip(struct dhd_bus *bus)
6157{
6158 ASSERT(bus->sih != NULL);
6159 return bus->sih->chip;
6160}
6161
6162void *
6163dhd_bus_pub(struct dhd_bus *bus)
6164{
6165 return bus->dhd;
6166}
6167
6168void *
6169dhd_bus_txq(struct dhd_bus *bus)
6170{
6171 return &bus->txq;
6172}
6173
6174uint
6175dhd_bus_hdrlen(struct dhd_bus *bus)
6176{
6177 return SDPCM_HDRLEN;
6178}
6179
6180int
6181dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag)
6182{
6183 int bcmerror = 0;
6184 dhd_bus_t *bus;
6185
6186 bus = dhdp->bus;
6187
6188 if (flag == TRUE) {
6189 if (!bus->dhd->dongle_reset) {
6190 dhd_os_sdlock(dhdp);
6191 dhd_os_wd_timer(dhdp, 0);
6192#if !defined(IGNORE_ETH0_DOWN)
6193 /* Force flow control as protection when stop come before ifconfig_down */
6194 dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
6195#endif /* !defined(IGNORE_ETH0_DOWN) */
6196 /* Expect app to have torn down any connection before calling */
6197 /* Stop the bus, disable F2 */
6198 dhd_bus_stop(bus, FALSE);
6199
6200#if defined(OOB_INTR_ONLY)
6201 /* Clean up any pending IRQ */
6202 bcmsdh_set_irq(FALSE);
6203#endif /* defined(OOB_INTR_ONLY) */
6204
6205 /* Clean tx/rx buffer pointers, detach from the dongle */
6206 dhdsdio_release_dongle(bus, bus->dhd->osh, TRUE, TRUE);
6207
6208 bus->dhd->dongle_reset = TRUE;
6209 bus->dhd->up = FALSE;
6210 dhd_os_sdunlock(dhdp);
6211
6212 DHD_TRACE(("%s: WLAN OFF DONE\n", __FUNCTION__));
6213 /* App can now remove power from device */
6214 } else
6215 bcmerror = BCME_SDIO_ERROR;
6216 } else {
6217 /* App must have restored power to device before calling */
6218
6219 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __FUNCTION__));
6220
6221 if (bus->dhd->dongle_reset) {
6222 /* Turn on WLAN */
6223#ifdef DHDTHREAD
6224 dhd_os_sdlock(dhdp);
6225#endif /* DHDTHREAD */
6226 /* Reset SD client */
6227 bcmsdh_reset(bus->sdh);
6228
6229 /* Attempt to re-attach & download */
6230 if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
6231 (uint32 *)SI_ENUM_BASE,
6232 bus->cl_devid)) {
6233 /* Attempt to download binary to the dongle */
6234 if (dhdsdio_probe_init(bus, bus->dhd->osh, bus->sdh) &&
6235 dhdsdio_download_firmware(bus, bus->dhd->osh, bus->sdh)) {
6236
6237 /* Re-init bus, enable F2 transfer */
6238 bcmerror = dhd_bus_init((dhd_pub_t *) bus->dhd, FALSE);
6239 if (bcmerror == BCME_OK) {
6240#if defined(OOB_INTR_ONLY)
6241 bcmsdh_set_irq(TRUE);
6242 dhd_enable_oob_intr(bus, TRUE);
6243#endif /* defined(OOB_INTR_ONLY) */
6244
6245 bus->dhd->dongle_reset = FALSE;
6246 bus->dhd->up = TRUE;
6247
6248#if !defined(IGNORE_ETH0_DOWN)
6249 /* Restore flow control */
6250 dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF);
6251#endif
6252 dhd_os_wd_timer(dhdp, dhd_watchdog_ms);
6253
6254 DHD_TRACE(("%s: WLAN ON DONE\n", __FUNCTION__));
6255 } else {
6256 dhd_bus_stop(bus, FALSE);
6257 dhdsdio_release_dongle(bus, bus->dhd->osh,
6258 TRUE, FALSE);
6259 }
6260 } else
6261 bcmerror = BCME_SDIO_ERROR;
6262 } else
6263 bcmerror = BCME_SDIO_ERROR;
6264
6265#ifdef DHDTHREAD
6266 dhd_os_sdunlock(dhdp);
6267#endif /* DHDTHREAD */
6268 } else {
6269 bcmerror = BCME_SDIO_ERROR;
6270 DHD_INFO(("%s called when dongle is not in reset\n",
6271 __FUNCTION__));
6272 DHD_INFO(("Will call dhd_bus_start instead\n"));
6273 sdioh_start(NULL, 1);
6274 if ((bcmerror = dhd_bus_start(dhdp)) != 0)
6275 DHD_ERROR(("%s: dhd_bus_start fail with %d\n",
6276 __FUNCTION__, bcmerror));
6277 }
6278 }
6279 return bcmerror;
6280}
6281
6282int
6283dhd_bus_membytes(dhd_pub_t *dhdp, bool set, uint32 address, uint8 *data, uint size)
6284{
6285 dhd_bus_t *bus;
6286
6287 bus = dhdp->bus;
6288 return dhdsdio_membytes(bus, set, address, data, size);
6289}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 01:18:36 -0400