diff options
author | Vasanthakumar Thiagarajan <vasanth@atheros.com> | 2010-12-06 07:27:58 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2010-12-07 16:54:23 -0500 |
commit | 11441fb8b700bd782ae72d3dd87453fc5bc2ff12 (patch) | |
tree | 5838b8560db554a7ef6107f931b20d81927056d2 /drivers/net/wireless/ath | |
parent | 7090ad1416d0311677c43728494c6028aa2436b6 (diff) |
ath9k_hw: Setup paprd only for supported chains
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_paprd.c | 37 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.h | 16 |
2 files changed, 36 insertions, 17 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c index 850bc9866c1..74cff4365c4 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c | |||
@@ -21,10 +21,12 @@ void ar9003_paprd_enable(struct ath_hw *ah, bool val) | |||
21 | { | 21 | { |
22 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0, | 22 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0, |
23 | AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); | 23 | AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); |
24 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1, | 24 | if (ah->caps.tx_chainmask & BIT(1)) |
25 | AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); | 25 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1, |
26 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2, | 26 | AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); |
27 | AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); | 27 | if (ah->caps.tx_chainmask & BIT(2)) |
28 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2, | ||
29 | AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); | ||
28 | } | 30 | } |
29 | EXPORT_SYMBOL(ar9003_paprd_enable); | 31 | EXPORT_SYMBOL(ar9003_paprd_enable); |
30 | 32 | ||
@@ -57,7 +59,8 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah) | |||
57 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask); | 59 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask); |
58 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask); | 60 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask); |
59 | 61 | ||
60 | for (i = 0; i < 3; i++) { | 62 | |
63 | for (i = 0; i < ah->caps.max_txchains; i++) { | ||
61 | REG_RMW_FIELD(ah, ctrl0[i], | 64 | REG_RMW_FIELD(ah, ctrl0[i], |
62 | AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK, 1); | 65 | AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK, 1); |
63 | REG_RMW_FIELD(ah, ctrl1[i], | 66 | REG_RMW_FIELD(ah, ctrl1[i], |
@@ -102,8 +105,14 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah) | |||
102 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); | 105 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); |
103 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | 106 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, |
104 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); | 107 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); |
105 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | 108 | if (AR_SREV_9485(ah)) |
106 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -6); | 109 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, |
110 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, | ||
111 | -3); | ||
112 | else | ||
113 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | ||
114 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, | ||
115 | -6); | ||
107 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, | 116 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, |
108 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, | 117 | AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, |
109 | -15); | 118 | -15); |
@@ -620,13 +629,15 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah, | |||
620 | AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, | 629 | AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, |
621 | training_power); | 630 | training_power); |
622 | 631 | ||
623 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1, | 632 | if (ah->caps.tx_chainmask & BIT(1)) |
624 | AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, | 633 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1, |
625 | training_power); | 634 | AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, |
635 | training_power); | ||
626 | 636 | ||
627 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2, | 637 | if (ah->caps.tx_chainmask & BIT(2)) |
628 | AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, | 638 | REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2, |
629 | training_power); | 639 | AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, |
640 | training_power); | ||
630 | } | 641 | } |
631 | EXPORT_SYMBOL(ar9003_paprd_populate_single_table); | 642 | EXPORT_SYMBOL(ar9003_paprd_populate_single_table); |
632 | 643 | ||
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index 00cd3e52ce5..6f811c7ada0 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h | |||
@@ -987,7 +987,9 @@ | |||
987 | #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000 | 987 | #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000 |
988 | #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17 | 988 | #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17 |
989 | 989 | ||
990 | #define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + 0x490) | 990 | #define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + \ |
991 | (AR_SREV_9485(ah) ? \ | ||
992 | 0x580 : 0x490)) | ||
991 | #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001 | 993 | #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001 |
992 | #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0 | 994 | #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0 |
993 | #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e | 995 | #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e |
@@ -1003,11 +1005,15 @@ | |||
1003 | #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000 | 1005 | #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000 |
1004 | #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12 | 1006 | #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12 |
1005 | 1007 | ||
1006 | #define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + 0x494) | 1008 | #define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + \ |
1009 | (AR_SREV_9485(ah) ? \ | ||
1010 | 0x584 : 0x494)) | ||
1007 | #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF | 1011 | #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF |
1008 | #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0 | 1012 | #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0 |
1009 | 1013 | ||
1010 | #define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + 0x498) | 1014 | #define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + \ |
1015 | (AR_SREV_9485(ah) ? \ | ||
1016 | 0x588 : 0x498)) | ||
1011 | #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f | 1017 | #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f |
1012 | #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0 | 1018 | #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0 |
1013 | #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0 | 1019 | #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0 |
@@ -1023,7 +1029,9 @@ | |||
1023 | #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000 | 1029 | #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000 |
1024 | #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29 | 1030 | #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29 |
1025 | 1031 | ||
1026 | #define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + 0x49c) | 1032 | #define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + \ |
1033 | (AR_SREV_9485(ah) ? \ | ||
1034 | 0x58c : 0x49c)) | ||
1027 | #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000 | 1035 | #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000 |
1028 | #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16 | 1036 | #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16 |
1029 | #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000 | 1037 | #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000 |