diff options
author | Luis R. Rodriguez <lrodriguez@atheros.com> | 2009-10-19 02:33:34 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-10-30 16:50:36 -0400 |
commit | c75724d1747230abdd37d0594ac5277b867befd4 (patch) | |
tree | 76ba22226b25c46ed01016f33ce72b793d7ec3cf /drivers/net/wireless/ath/ath9k/hw.c | |
parent | 8564328d85f69121744d8337124857a2e726239b (diff) |
ath9k_hw: change the way we initialize the pll for ar9271
We adjust the core clock for ar9271 to 117 MHz; this also
requires us to adjust the baud divider based on the targetted
baud rate.
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 7cee89b81fc..be9c0b69188 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -1040,6 +1040,22 @@ static void ath9k_hw_init_qos(struct ath_hw *ah) | |||
1040 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | 1040 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); |
1041 | } | 1041 | } |
1042 | 1042 | ||
1043 | static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud) | ||
1044 | { | ||
1045 | u32 lcr; | ||
1046 | u32 baud_divider = freq * 1000 * 1000 / 16 / baud; | ||
1047 | |||
1048 | lcr = REG_READ(ah , 0x5100c); | ||
1049 | lcr |= 0x80; | ||
1050 | |||
1051 | REG_WRITE(ah, 0x5100c, lcr); | ||
1052 | REG_WRITE(ah, 0x51004, (baud_divider >> 8)); | ||
1053 | REG_WRITE(ah, 0x51000, (baud_divider & 0xff)); | ||
1054 | |||
1055 | lcr &= ~0x80; | ||
1056 | REG_WRITE(ah, 0x5100c, lcr); | ||
1057 | } | ||
1058 | |||
1043 | static void ath9k_hw_init_pll(struct ath_hw *ah, | 1059 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
1044 | struct ath9k_channel *chan) | 1060 | struct ath9k_channel *chan) |
1045 | { | 1061 | { |
@@ -1103,6 +1119,26 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, | |||
1103 | } | 1119 | } |
1104 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); | 1120 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
1105 | 1121 | ||
1122 | /* Switch the core clock for ar9271 to 117Mhz */ | ||
1123 | if (AR_SREV_9271(ah)) { | ||
1124 | if ((pll == 0x142c) || (pll == 0x2850) ) { | ||
1125 | udelay(500); | ||
1126 | /* set CLKOBS to output AHB clock */ | ||
1127 | REG_WRITE(ah, 0x7020, 0xe); | ||
1128 | /* | ||
1129 | * 0x304: 117Mhz, ahb_ratio: 1x1 | ||
1130 | * 0x306: 40Mhz, ahb_ratio: 1x1 | ||
1131 | */ | ||
1132 | REG_WRITE(ah, 0x50040, 0x304); | ||
1133 | /* | ||
1134 | * makes adjustments for the baud dividor to keep the | ||
1135 | * targetted baud rate based on the used core clock. | ||
1136 | */ | ||
1137 | ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK, | ||
1138 | AR9271_TARGET_BAUD_RATE); | ||
1139 | } | ||
1140 | } | ||
1141 | |||
1106 | udelay(RTC_PLL_SETTLE_DELAY); | 1142 | udelay(RTC_PLL_SETTLE_DELAY); |
1107 | 1143 | ||
1108 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | 1144 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); |