diff options
author | Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> | 2011-12-08 01:29:03 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-12-13 15:30:22 -0500 |
commit | cc78d6b16a6853a3f6c014a6173df41d80f65a35 (patch) | |
tree | f46aeb5c7522cabb05a73da1f94cdbab6e58fdcb /drivers/net/wireless/ath/ath9k/ar9003_mac.c | |
parent | 93fdd59463369f07b69cf7397ccb9b1d28a84df4 (diff) |
ath9k_hw: Fix handling of MCI interrupt
in my previous patches of handling MCI interrupt I overlooked
the case of interrupt status/mask variable being zeroed out in
the below code, so ath_isr does not cache the MCI interrupt
in the intrstatus. finally MCI interrupt handling won't be
handled in ath9k_tasklet for the scheduled interrupts.
Fix this by moving the MCI interrupt code in the appropriate
position in ar9003_hw_get_isr
Cc: Wilson Tsao <wtsao@qca.qualcomm.com>
Cc: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_mac.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_mac.c | 57 |
1 files changed, 29 insertions, 28 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c index 508c2022ea9..631fe4f2e49 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c | |||
@@ -187,34 +187,6 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
187 | isr = REG_READ(ah, AR_ISR); | 187 | isr = REG_READ(ah, AR_ISR); |
188 | } | 188 | } |
189 | 189 | ||
190 | if (async_cause & AR_INTR_ASYNC_MASK_MCI) { | ||
191 | u32 raw_intr, rx_msg_intr; | ||
192 | |||
193 | rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); | ||
194 | raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); | ||
195 | |||
196 | if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef)) | ||
197 | ath_dbg(common, ATH_DBG_MCI, | ||
198 | "MCI gets 0xdeadbeef during MCI int processing" | ||
199 | "new raw_intr=0x%08x, new rx_msg_raw=0x%08x, " | ||
200 | "raw_intr=0x%08x, rx_msg_raw=0x%08x\n", | ||
201 | raw_intr, rx_msg_intr, mci->raw_intr, | ||
202 | mci->rx_msg_intr); | ||
203 | else { | ||
204 | mci->rx_msg_intr |= rx_msg_intr; | ||
205 | mci->raw_intr |= raw_intr; | ||
206 | *masked |= ATH9K_INT_MCI; | ||
207 | |||
208 | if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) | ||
209 | mci->cont_status = | ||
210 | REG_READ(ah, AR_MCI_CONT_STATUS); | ||
211 | |||
212 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr); | ||
213 | REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr); | ||
214 | ath_dbg(common, ATH_DBG_MCI, "AR_INTR_SYNC_MCI\n"); | ||
215 | |||
216 | } | ||
217 | } | ||
218 | 190 | ||
219 | sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; | 191 | sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; |
220 | 192 | ||
@@ -326,6 +298,35 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
326 | ar9003_hw_bb_watchdog_read(ah); | 298 | ar9003_hw_bb_watchdog_read(ah); |
327 | } | 299 | } |
328 | 300 | ||
301 | if (async_cause & AR_INTR_ASYNC_MASK_MCI) { | ||
302 | u32 raw_intr, rx_msg_intr; | ||
303 | |||
304 | rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); | ||
305 | raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); | ||
306 | |||
307 | if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef)) | ||
308 | ath_dbg(common, ATH_DBG_MCI, | ||
309 | "MCI gets 0xdeadbeef during MCI int processing" | ||
310 | "new raw_intr=0x%08x, new rx_msg_raw=0x%08x, " | ||
311 | "raw_intr=0x%08x, rx_msg_raw=0x%08x\n", | ||
312 | raw_intr, rx_msg_intr, mci->raw_intr, | ||
313 | mci->rx_msg_intr); | ||
314 | else { | ||
315 | mci->rx_msg_intr |= rx_msg_intr; | ||
316 | mci->raw_intr |= raw_intr; | ||
317 | *masked |= ATH9K_INT_MCI; | ||
318 | |||
319 | if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) | ||
320 | mci->cont_status = | ||
321 | REG_READ(ah, AR_MCI_CONT_STATUS); | ||
322 | |||
323 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr); | ||
324 | REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr); | ||
325 | ath_dbg(common, ATH_DBG_MCI, "AR_INTR_SYNC_MCI\n"); | ||
326 | |||
327 | } | ||
328 | } | ||
329 | |||
329 | if (sync_cause) { | 330 | if (sync_cause) { |
330 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { | 331 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { |
331 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); | 332 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |