ath9k_hw: check for MCI interrupt in get_isr

check for the condition of MCI interrupt being triggered and
appropriately obtain the values of MCI_INTERRUPT_RX_MSG_RAW and
MCI_INTERRUPT_RAW

Cc: Wilson Tsao <wtsao@qca.qualcomm.com>
Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 34 insertions, 2 deletions

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index ccde784a842..95587e36ab9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -175,15 +175,47 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
         u32 isr = 0;
         u32 mask2 = 0;
         struct ath9k_hw_capabilities *pCap = &ah->caps;
-        u32 sync_cause = 0;
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 sync_cause = 0, async_cause;
 
-        if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
+        async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
+
+        if (async_cause & (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_MASK_MCI)) {
                 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
                                 == AR_RTC_STATUS_ON)
                         isr = REG_READ(ah, AR_ISR);
         }
 
+        if (async_cause & AR_INTR_ASYNC_MASK_MCI) {
+                u32 raw_intr, rx_msg_intr;
+
+                rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
+                raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
+
+                if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef))
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI gets 0xdeadbeef during MCI int processing"
+                                "new raw_intr=0x%08x, new rx_msg_raw=0x%08x, "
+                                "raw_intr=0x%08x, rx_msg_raw=0x%08x\n",
+                                raw_intr, rx_msg_intr, mci->raw_intr,
+                                mci->rx_msg_intr);
+                else {
+                        mci->rx_msg_intr |= rx_msg_intr;
+                        mci->raw_intr |= raw_intr;
+                        *masked |= ATH9K_INT_MCI;
+
+                        if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO)
+                                mci->cont_status =
+                                        REG_READ(ah, AR_MCI_CONT_STATUS);
+
+                        REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
+                        REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
+                        ath_dbg(common, ATH_DBG_MCI, "AR_INTR_SYNC_MCI\n");
+
+                }
+        }
+
         sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
 
         *masked = 0;