diff options
author | Felix Fietkau <nbd@openwrt.org> | 2012-02-15 15:53:16 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2012-02-27 14:05:41 -0500 |
commit | 14fec8d9baffc026beaffa2ee9e911df9d1d4ad2 (patch) | |
tree | 75fda92b8ad61520fd136c733befe196289c548b /drivers/net/wireless/ath/ath9k/ar9002_hw.c | |
parent | d42a179b941a9e4cc6cf41d0f3cbadd75fc48a89 (diff) |
ath9k_hw: remove duplicate initvals
Comparing SHA1 checksums of the initval tables has shown that there are many
tables that are 100% identical.
iniBank{0,1,2,3,7} and iniBB_RfGain are shared by AR5416, AR913x, AR9160
iniBank6 is shared between AR5416 and AR9160
iniBank6TPC is shared between AR913x and AR9160
iniPcieSerdes is the same for all AR9002 based devices
The CCK FIR coefficients are shared between AR9271 and AR9287
Getting rid of those duplicates saves about 7.5k uncompressed (on MIPS).
For AR9003 and later there are some duplicates as well, but I've decided to
leave them in for now, as the initvals for those chips are still actively
maintained by QCA.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9002_hw.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9002_hw.c | 107 |
1 files changed, 34 insertions, 73 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c index 11f192a1ceb..d48f5fe8af7 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c | |||
@@ -35,11 +35,11 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
35 | INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, | 35 | INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, |
36 | ARRAY_SIZE(ar9271Common_9271), 2); | 36 | ARRAY_SIZE(ar9271Common_9271), 2); |
37 | INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, | 37 | INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, |
38 | ar9271Common_normal_cck_fir_coeff_9271, | 38 | ar9287Common_normal_cck_fir_coeff_9287_1_1, |
39 | ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2); | 39 | ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1), 2); |
40 | INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271, | 40 | INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271, |
41 | ar9271Common_japan_2484_cck_fir_coeff_9271, | 41 | ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, |
42 | ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2); | 42 | ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1), 2); |
43 | INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, | 43 | INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, |
44 | ar9271Modes_9271_1_0_only, | 44 | ar9271Modes_9271_1_0_only, |
45 | ARRAY_SIZE(ar9271Modes_9271_1_0_only), 5); | 45 | ARRAY_SIZE(ar9271Modes_9271_1_0_only), 5); |
@@ -54,53 +54,31 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
54 | return; | 54 | return; |
55 | } | 55 | } |
56 | 56 | ||
57 | if (ah->config.pcie_clock_req) | ||
58 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | ||
59 | ar9280PciePhy_clkreq_off_L1_9280, | ||
60 | ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2); | ||
61 | else | ||
62 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | ||
63 | ar9280PciePhy_clkreq_always_on_L1_9280, | ||
64 | ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); | ||
65 | |||
57 | if (AR_SREV_9287_11_OR_LATER(ah)) { | 66 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
58 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, | 67 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, |
59 | ARRAY_SIZE(ar9287Modes_9287_1_1), 5); | 68 | ARRAY_SIZE(ar9287Modes_9287_1_1), 5); |
60 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, | 69 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, |
61 | ARRAY_SIZE(ar9287Common_9287_1_1), 2); | 70 | ARRAY_SIZE(ar9287Common_9287_1_1), 2); |
62 | if (ah->config.pcie_clock_req) | ||
63 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | ||
64 | ar9287PciePhy_clkreq_off_L1_9287_1_1, | ||
65 | ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2); | ||
66 | else | ||
67 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | ||
68 | ar9287PciePhy_clkreq_always_on_L1_9287_1_1, | ||
69 | ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1), | ||
70 | 2); | ||
71 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { | 71 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { |
72 | |||
73 | |||
74 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, | 72 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, |
75 | ARRAY_SIZE(ar9285Modes_9285_1_2), 5); | 73 | ARRAY_SIZE(ar9285Modes_9285_1_2), 5); |
76 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, | 74 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, |
77 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); | 75 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); |
78 | |||
79 | if (ah->config.pcie_clock_req) { | ||
80 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | ||
81 | ar9285PciePhy_clkreq_off_L1_9285_1_2, | ||
82 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); | ||
83 | } else { | ||
84 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | ||
85 | ar9285PciePhy_clkreq_always_on_L1_9285_1_2, | ||
86 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), | ||
87 | 2); | ||
88 | } | ||
89 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { | 76 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { |
90 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, | 77 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, |
91 | ARRAY_SIZE(ar9280Modes_9280_2), 5); | 78 | ARRAY_SIZE(ar9280Modes_9280_2), 5); |
92 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, | 79 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, |
93 | ARRAY_SIZE(ar9280Common_9280_2), 2); | 80 | ARRAY_SIZE(ar9280Common_9280_2), 2); |
94 | 81 | ||
95 | if (ah->config.pcie_clock_req) { | ||
96 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | ||
97 | ar9280PciePhy_clkreq_off_L1_9280, | ||
98 | ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2); | ||
99 | } else { | ||
100 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | ||
101 | ar9280PciePhy_clkreq_always_on_L1_9280, | ||
102 | ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); | ||
103 | } | ||
104 | INIT_INI_ARRAY(&ah->iniModesAdditional, | 82 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
105 | ar9280Modes_fast_clock_9280_2, | 83 | ar9280Modes_fast_clock_9280_2, |
106 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); | 84 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); |
@@ -109,22 +87,6 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
109 | ARRAY_SIZE(ar5416Modes_9160), 5); | 87 | ARRAY_SIZE(ar5416Modes_9160), 5); |
110 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, | 88 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, |
111 | ARRAY_SIZE(ar5416Common_9160), 2); | 89 | ARRAY_SIZE(ar5416Common_9160), 2); |
112 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, | ||
113 | ARRAY_SIZE(ar5416Bank0_9160), 2); | ||
114 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, | ||
115 | ARRAY_SIZE(ar5416BB_RfGain_9160), 3); | ||
116 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, | ||
117 | ARRAY_SIZE(ar5416Bank1_9160), 2); | ||
118 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, | ||
119 | ARRAY_SIZE(ar5416Bank2_9160), 2); | ||
120 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, | ||
121 | ARRAY_SIZE(ar5416Bank3_9160), 3); | ||
122 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, | ||
123 | ARRAY_SIZE(ar5416Bank6_9160), 3); | ||
124 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, | ||
125 | ARRAY_SIZE(ar5416Bank6TPC_9160), 3); | ||
126 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, | ||
127 | ARRAY_SIZE(ar5416Bank7_9160), 2); | ||
128 | if (AR_SREV_9160_11(ah)) { | 90 | if (AR_SREV_9160_11(ah)) { |
129 | INIT_INI_ARRAY(&ah->iniAddac, | 91 | INIT_INI_ARRAY(&ah->iniAddac, |
130 | ar5416Addac_9160_1_1, | 92 | ar5416Addac_9160_1_1, |
@@ -138,22 +100,8 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
138 | ARRAY_SIZE(ar5416Modes_9100), 5); | 100 | ARRAY_SIZE(ar5416Modes_9100), 5); |
139 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, | 101 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, |
140 | ARRAY_SIZE(ar5416Common_9100), 2); | 102 | ARRAY_SIZE(ar5416Common_9100), 2); |
141 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, | ||
142 | ARRAY_SIZE(ar5416Bank0_9100), 2); | ||
143 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, | ||
144 | ARRAY_SIZE(ar5416BB_RfGain_9100), 3); | ||
145 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, | ||
146 | ARRAY_SIZE(ar5416Bank1_9100), 2); | ||
147 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, | ||
148 | ARRAY_SIZE(ar5416Bank2_9100), 2); | ||
149 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, | ||
150 | ARRAY_SIZE(ar5416Bank3_9100), 3); | ||
151 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, | 103 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, |
152 | ARRAY_SIZE(ar5416Bank6_9100), 3); | 104 | ARRAY_SIZE(ar5416Bank6_9100), 3); |
153 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, | ||
154 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); | ||
155 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, | ||
156 | ARRAY_SIZE(ar5416Bank7_9100), 2); | ||
157 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, | 105 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, |
158 | ARRAY_SIZE(ar5416Addac_9100), 2); | 106 | ARRAY_SIZE(ar5416Addac_9100), 2); |
159 | } else { | 107 | } else { |
@@ -161,24 +109,37 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah) | |||
161 | ARRAY_SIZE(ar5416Modes), 5); | 109 | ARRAY_SIZE(ar5416Modes), 5); |
162 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, | 110 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, |
163 | ARRAY_SIZE(ar5416Common), 2); | 111 | ARRAY_SIZE(ar5416Common), 2); |
164 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, | 112 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, |
165 | ARRAY_SIZE(ar5416Bank0), 2); | 113 | ARRAY_SIZE(ar5416Bank6TPC), 3); |
114 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, | ||
115 | ARRAY_SIZE(ar5416Addac), 2); | ||
116 | } | ||
117 | |||
118 | if (!AR_SREV_9280_20_OR_LATER(ah)) { | ||
119 | /* Common for AR5416, AR913x, AR9160 */ | ||
166 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, | 120 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, |
167 | ARRAY_SIZE(ar5416BB_RfGain), 3); | 121 | ARRAY_SIZE(ar5416BB_RfGain), 3); |
122 | |||
123 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, | ||
124 | ARRAY_SIZE(ar5416Bank0), 2); | ||
168 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, | 125 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, |
169 | ARRAY_SIZE(ar5416Bank1), 2); | 126 | ARRAY_SIZE(ar5416Bank1), 2); |
170 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, | 127 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, |
171 | ARRAY_SIZE(ar5416Bank2), 2); | 128 | ARRAY_SIZE(ar5416Bank2), 2); |
172 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, | 129 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, |
173 | ARRAY_SIZE(ar5416Bank3), 3); | 130 | ARRAY_SIZE(ar5416Bank3), 3); |
174 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, | ||
175 | ARRAY_SIZE(ar5416Bank6), 3); | ||
176 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, | ||
177 | ARRAY_SIZE(ar5416Bank6TPC), 3); | ||
178 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, | 131 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, |
179 | ARRAY_SIZE(ar5416Bank7), 2); | 132 | ARRAY_SIZE(ar5416Bank7), 2); |
180 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, | 133 | |
181 | ARRAY_SIZE(ar5416Addac), 2); | 134 | /* Common for AR5416, AR9160 */ |
135 | if (!AR_SREV_9100(ah)) | ||
136 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, | ||
137 | ARRAY_SIZE(ar5416Bank6), 3); | ||
138 | |||
139 | /* Common for AR913x, AR9160 */ | ||
140 | if (!AR_SREV_5416(ah)) | ||
141 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, | ||
142 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); | ||
182 | } | 143 | } |
183 | } | 144 | } |
184 | 145 | ||