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authorTobias Doerffel <tobias.doerffel@gmail.com>2009-06-09 11:33:27 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-06-10 13:27:54 -0400
commite6a3b61681dcb963e6465ffbc4330b44824f35e3 (patch)
tree1628eb26f1a79858391686a64e9e72780cd6340a /drivers/net/wireless/ath/ath5k/reset.c
parent207ee1621722876bb79828689582bf77fd1be200 (diff)
ath5k: added cfg80211 based rfkill support
This patch introduces initial rfkill support for the ath5k driver based on rfkill support in the cfg80211 framework. All rfkill related code is separated into newly created rfkill.c. Changes to existing code are minimal: * added a new data structure ath5k_rfkill to the ath5k_softc structure * inserted calls to HW rfkill init/deinit routines * ath5k_intr() has been extended to handle AR5K_INT_GPIO interrupts Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/reset.c')
-rw-r--r--drivers/net/wireless/ath/ath5k/reset.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index 66067733ddd..bd0a97a38d3 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -1304,23 +1304,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1304 if (ah->ah_version != AR5K_AR5210) 1304 if (ah->ah_version != AR5K_AR5210)
1305 ath5k_hw_set_imr(ah, ah->ah_imr); 1305 ath5k_hw_set_imr(ah, ah->ah_imr);
1306 1306
1307 /*
1308 * Setup RFKill interrupt if rfkill flag is set on eeprom.
1309 * TODO: Use gpio pin and polarity infos from eeprom
1310 * TODO: Handle this in ath5k_intr because it'll result
1311 * a nasty interrupt storm.
1312 */
1313#if 0
1314 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
1315 ath5k_hw_set_gpio_input(ah, 0);
1316 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
1317 if (ah->ah_gpio[0] == 0)
1318 ath5k_hw_set_gpio_intr(ah, 0, 1);
1319 else
1320 ath5k_hw_set_gpio_intr(ah, 0, 0);
1321 }
1322#endif
1323
1324 /* Enable 32KHz clock function for AR5212+ chips 1307 /* Enable 32KHz clock function for AR5212+ chips
1325 * Set clocks to 32KHz operation and use an 1308 * Set clocks to 32KHz operation and use an
1326 * external 32KHz crystal when sleeping if one 1309 * external 32KHz crystal when sleeping if one