diff options
| author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-17 16:15:55 -0500 |
|---|---|---|
| committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-17 16:15:55 -0500 |
| commit | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch) | |
| tree | a8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /drivers/net/wireless/ath/ath5k/reg.h | |
| parent | 406089d01562f1e2bf9f089fd7637009ebaad589 (diff) | |
Patched in Tegra support.
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/reg.h')
| -rw-r--r-- | drivers/net/wireless/ath/ath5k/reg.h | 27 |
1 files changed, 6 insertions, 21 deletions
diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h index 0ea1608b47f..f5c1000045d 100644 --- a/drivers/net/wireless/ath/ath5k/reg.h +++ b/drivers/net/wireless/ath/ath5k/reg.h | |||
| @@ -280,10 +280,6 @@ | |||
| 280 | * 5211/5212 we have one primary and 4 secondary registers. | 280 | * 5211/5212 we have one primary and 4 secondary registers. |
| 281 | * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. | 281 | * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. |
| 282 | * Most of these bits are common for all chipsets. | 282 | * Most of these bits are common for all chipsets. |
| 283 | * | ||
| 284 | * NOTE: On 5211+ TXOK, TXDESC, TXERR, TXEOL and TXURN contain | ||
| 285 | * the logical OR from per-queue interrupt bits found on SISR registers | ||
| 286 | * (see below). | ||
| 287 | */ | 283 | */ |
| 288 | #define AR5K_ISR 0x001c /* Register Address [5210] */ | 284 | #define AR5K_ISR 0x001c /* Register Address [5210] */ |
| 289 | #define AR5K_PISR 0x0080 /* Register Address [5211+] */ | 285 | #define AR5K_PISR 0x0080 /* Register Address [5211+] */ |
| @@ -296,10 +292,7 @@ | |||
| 296 | #define AR5K_ISR_TXOK 0x00000040 /* Frame successfully transmitted */ | 292 | #define AR5K_ISR_TXOK 0x00000040 /* Frame successfully transmitted */ |
| 297 | #define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ | 293 | #define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ |
| 298 | #define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ | 294 | #define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ |
| 299 | #define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout) | 295 | #define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout) */ |
| 300 | * NOTE: We don't have per-queue info for this | ||
| 301 | * one, but we can enable it per-queue through | ||
| 302 | * TXNOFRM_QCU field on TXNOFRM register */ | ||
| 303 | #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ | 296 | #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ |
| 304 | #define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ | 297 | #define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ |
| 305 | #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ | 298 | #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ |
| @@ -309,29 +302,21 @@ | |||
| 309 | #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ | 302 | #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ |
| 310 | #define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ | 303 | #define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ |
| 311 | #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ | 304 | #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ |
| 312 | #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] | 305 | #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ |
| 313 | * 'or' of MCABT, SSERR, DPERR from SISR2 */ | ||
| 314 | #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ | 306 | #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ |
| 315 | #define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ | 307 | #define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ |
| 316 | #define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ | 308 | #define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ |
| 317 | #define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ | 309 | #define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ |
| 318 | #define AR5K_ISR_DPERR 0x00400000 /* Bus parity error [5210] */ | 310 | #define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */ |
| 319 | #define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ | 311 | #define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ |
| 320 | #define AR5K_ISR_TIM 0x00800000 /* [5211+] */ | 312 | #define AR5K_ISR_TIM 0x00800000 /* [5211+] */ |
| 321 | #define AR5K_ISR_BCNMISC 0x00800000 /* Misc beacon related interrupt | 313 | #define AR5K_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, |
| 322 | * 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, | 314 | CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ |
| 323 | * CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ | ||
| 324 | #define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */ | 315 | #define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */ |
| 325 | #define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */ | 316 | #define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */ |
| 326 | #define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */ | 317 | #define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */ |
| 327 | #define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ | 318 | #define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ |
| 328 | 319 | ||
| 329 | #define AR5K_ISR_BITS_FROM_SISRS (AR5K_ISR_TXOK | AR5K_ISR_TXDESC |\ | ||
| 330 | AR5K_ISR_TXERR | AR5K_ISR_TXEOL |\ | ||
| 331 | AR5K_ISR_TXURN | AR5K_ISR_HIUERR |\ | ||
| 332 | AR5K_ISR_BCNMISC | AR5K_ISR_QCBRORN |\ | ||
| 333 | AR5K_ISR_QCBRURN | AR5K_ISR_QTRIG) | ||
| 334 | |||
| 335 | /* | 320 | /* |
| 336 | * Secondary status registers [5211+] (0 - 4) | 321 | * Secondary status registers [5211+] (0 - 4) |
| 337 | * | 322 | * |
| @@ -362,7 +347,7 @@ | |||
| 362 | #define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ | 347 | #define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ |
| 363 | #define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ | 348 | #define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ |
| 364 | #define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ | 349 | #define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ |
| 365 | #define AR5K_SISR2_TSFOOR 0x80000000 /* TSF Out of range */ | 350 | #define AR5K_SISR2_TSFOOR 0x80000000 /* TSF OOR (?) */ |
| 366 | 351 | ||
| 367 | #define AR5K_SISR3 0x0090 /* Register Address [5211+] */ | 352 | #define AR5K_SISR3 0x0090 /* Register Address [5211+] */ |
| 368 | #define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ | 353 | #define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ |