ath5k: Adaptive Noise Immunity (ANI) Implementation

This is an Adaptive Noise Imunity (ANI) implementation for ath5k. I have looked
at both ath9k and HAL sources (they are nearly the same), and even though i
have implemented some things differently, the basic algorithm is practically
the same, for now. I hope that this can serve as a clean start to improve the
algorithm later.

This also adds a possibility to manually control ANI settings, right now only
thru a debugfs file:
  * set lowest sensitivity (=highest noise immunity):
	echo sens-low > /sys/kernel/debug/ath5k/phy0/ani
  * set highest sensitivity (=lowest noise immunity):
	echo sens-high > /sys/kernel/debug/ath5k/phy0/ani
  * automatically control immunity (default):
	echo ani-on > /sys/kernel/debug/ath5k/phy0/ani
  * to see the parameters in use and watch them change:
	cat /sys/kernel/debug/ath5k/phy0/ani

Manually setting sensitivity will turn the automatic control off. You can also
control each of the five immunity parameters (noise immunity, spur immunity,
firstep, ofdm weak signal detection, cck weak signal detection) manually thru
the debugfs file.

This is tested on AR5414 and nearly doubles the thruput in a noisy 2GHz band.

Signed-off-by: Bruno Randolf <br1@einfach.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 26 insertions, 10 deletions

diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h
index f325e664065..cbd11d4c98e 100644
--- a/drivers/net/wireless/ath/ath5k/reg.h
+++ b/drivers/net/wireless/ath/ath5k/reg.h
@@ -212,10 +212,10 @@
  * MIB control register
  */
 #define AR5K_MIBC               0x0040                  /* Register Address */
-#define AR5K_MIBC_COW           0x00000001      /* Warn test indicator */
+#define AR5K_MIBC_COW           0x00000001      /* Counter Overflow Warning */
 #define AR5K_MIBC_FMC           0x00000002      /* Freeze MIB Counters  */
-#define AR5K_MIBC_CMC           0x00000004      /* Clean MIB Counters  */
-#define AR5K_MIBC_MCS           0x00000008      /* MIB counter strobe */
+#define AR5K_MIBC_CMC           0x00000004      /* Clear MIB Counters  */
+#define AR5K_MIBC_MCS           0x00000008      /* MIB counter strobe, increment all */
 
 /*
  * Timeout prescale register
@@ -1516,7 +1516,14 @@
                                 AR5K_NAV_5210 : AR5K_NAV_5211)
 
 /*
- * RTS success register
+ * MIB counters:
+ *
+ * max value is 0xc000, if this is reached we get a MIB interrupt.
+ * they can be controlled via AR5K_MIBC and are cleared on read.
+ */
+
+/*
+ * RTS success (MIB counter)
  */
 #define AR5K_RTS_OK_5210        0x8090
 #define AR5K_RTS_OK_5211        0x8088
@@ -1524,7 +1531,7 @@
                                 AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211)
 
 /*
- * RTS failure register
+ * RTS failure (MIB counter)
  */
 #define AR5K_RTS_FAIL_5210      0x8094
 #define AR5K_RTS_FAIL_5211      0x808c
@@ -1532,7 +1539,7 @@
                                 AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211)
 
 /*
- * ACK failure register
+ * ACK failure (MIB counter)
  */
 #define AR5K_ACK_FAIL_5210      0x8098
 #define AR5K_ACK_FAIL_5211      0x8090
@@ -1540,7 +1547,7 @@
                                 AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211)
 
 /*
- * FCS failure register
+ * FCS failure (MIB counter)
  */
 #define AR5K_FCS_FAIL_5210      0x809c
 #define AR5K_FCS_FAIL_5211      0x8094
@@ -1667,11 +1674,17 @@
 
 /*
  * Profile count registers
+ *
+ * These registers can be cleared and freezed with ATH5K_MIBC, but they do not
+ * generate a MIB interrupt.
+ * Instead of overflowing, they shift by one bit to the right. All registers
+ * shift together, i.e. when one reaches the max, all shift at the same time by
+ * one bit to the right. This way we should always get consistent values.
  */
 #define AR5K_PROFCNT_TX                 0x80ec  /* Tx count */
 #define AR5K_PROFCNT_RX                 0x80f0  /* Rx count */
-#define AR5K_PROFCNT_RXCLR              0x80f4  /* Clear Rx count */
-#define AR5K_PROFCNT_CYCLE              0x80f8  /* Cycle count (?) */
+#define AR5K_PROFCNT_RXCLR              0x80f4  /* Busy count */
+#define AR5K_PROFCNT_CYCLE              0x80f8  /* Cycle counter */
 
 /*
  * Quiet period control registers
@@ -1758,7 +1771,7 @@
 #define AR5K_CCK_FIL_CNT                0x8128
 
 /*
- * PHY Error Counters (?)
+ * PHY Error Counters (same masks as AR5K_PHY_ERR_FIL)
  */
 #define AR5K_PHYERR_CNT1                0x812c
 #define AR5K_PHYERR_CNT1_MASK           0x8130
@@ -1766,6 +1779,9 @@
 #define AR5K_PHYERR_CNT2                0x8134
 #define AR5K_PHYERR_CNT2_MASK           0x8138
 
+/* if the PHY Error Counters reach this maximum, we get MIB interrupts */
+#define ATH5K_PHYERR_CNT_MAX            0x00c00000
+
 /*
  * TSF Threshold register (?)
  */