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authorMike McCormack <mikem@ring3k.org>2009-08-14 01:15:13 -0400
committerDavid S. Miller <davem@davemloft.net>2009-08-14 18:29:57 -0400
commita510996bea68eec2feb7818e9a440bd840613a25 (patch)
treea9222e4fbc58b0f20a8c7ec1c14bee1b430e3853 /drivers/net/sky2.c
parent9b289c3374d2891aac6c12de58e49a16cfbcb6b1 (diff)
sky2: Move tx reset functionality to sky2_tx_reset()
This is pure refactoring. Signed-off-by: Mike McCormack <mikem@ring3k.org> Acked-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sky2.c')
-rw-r--r--drivers/net/sky2.c44
1 files changed, 26 insertions, 18 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index a52b8631783..768ed47da9b 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -1811,6 +1811,31 @@ static void sky2_tx_clean(struct net_device *dev)
1811 netif_tx_unlock_bh(dev); 1811 netif_tx_unlock_bh(dev);
1812} 1812}
1813 1813
1814static void sky2_tx_reset(struct sky2_port* sky2)
1815{
1816 unsigned port = sky2->port;
1817 struct sky2_hw *hw = sky2->hw;
1818
1819 /* Disable Force Sync bit and Enable Alloc bit */
1820 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1821 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1822
1823 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1824 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1825 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1826
1827 /* Reset the PCI FIFO of the async Tx queue */
1828 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1829 BMU_RST_SET | BMU_FIFO_RST);
1830
1831 /* Reset the Tx prefetch units */
1832 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1833 PREF_UNIT_RST_SET);
1834
1835 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1836 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1837}
1838
1814/* Network shutdown */ 1839/* Network shutdown */
1815static int sky2_down(struct net_device *dev) 1840static int sky2_down(struct net_device *dev)
1816{ 1841{
@@ -1852,26 +1877,9 @@ static int sky2_down(struct net_device *dev)
1852 && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 1877 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1853 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 1878 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1854 1879
1855 /* Disable Force Sync bit and Enable Alloc bit */ 1880 sky2_tx_reset(sky2);
1856 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1857 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1858
1859 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1860 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1861 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1862
1863 /* Reset the PCI FIFO of the async Tx queue */
1864 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1865 BMU_RST_SET | BMU_FIFO_RST);
1866
1867 /* Reset the Tx prefetch units */
1868 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1869 PREF_UNIT_RST_SET);
1870
1871 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1872 1881
1873 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 1882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1874 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1875 1883
1876 /* Force any delayed status interrrupt and NAPI */ 1884 /* Force any delayed status interrrupt and NAPI */
1877 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); 1885 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);