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authorLennert Buytenhek <buytenh@wantstofly.org>2009-05-05 23:01:17 -0400
committerDavid S. Miller <davem@davemloft.net>2009-05-06 18:33:38 -0400
commitbecfad979d1875aca15ef2a1eda68782e7ac7769 (patch)
tree735dbc4e04a98132e5911aa4db6681edce5a2bac /drivers/net/mv643xx_eth.c
parent26ef1f17d4741756763d1a399968ce17f236e2fb (diff)
mv643xx_eth: minor register definition cleanup
Move the definitions for the SDMA and port serial configuration register values to where all the other register definitions live, and expand the shifts to 32 bit constants. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/mv643xx_eth.c')
-rw-r--r--drivers/net/mv643xx_eth.c44
1 files changed, 21 insertions, 23 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index 92a867cf8d5..cc16f3e4d89 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -88,7 +88,24 @@ static char mv643xx_eth_driver_version[] = "1.4";
88#define MAC_ADDR_LOW 0x0014 88#define MAC_ADDR_LOW 0x0014
89#define MAC_ADDR_HIGH 0x0018 89#define MAC_ADDR_HIGH 0x0018
90#define SDMA_CONFIG 0x001c 90#define SDMA_CONFIG 0x001c
91#define TX_BURST_SIZE_16_64BIT 0x01000000
92#define TX_BURST_SIZE_4_64BIT 0x00800000
93#define BLM_TX_NO_SWAP 0x00000020
94#define BLM_RX_NO_SWAP 0x00000010
95#define RX_BURST_SIZE_16_64BIT 0x00000008
96#define RX_BURST_SIZE_4_64BIT 0x00000004
91#define PORT_SERIAL_CONTROL 0x003c 97#define PORT_SERIAL_CONTROL 0x003c
98#define SET_MII_SPEED_TO_100 0x01000000
99#define SET_GMII_SPEED_TO_1000 0x00800000
100#define SET_FULL_DUPLEX_MODE 0x00200000
101#define MAX_RX_PACKET_9700BYTE 0x000a0000
102#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
103#define DO_NOT_FORCE_LINK_FAIL 0x00000400
104#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
105#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
106#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
107#define FORCE_LINK_PASS 0x00000002
108#define SERIAL_PORT_ENABLE 0x00000001
92#define PORT_STATUS 0x0044 109#define PORT_STATUS 0x0044
93#define TX_FIFO_EMPTY 0x00000400 110#define TX_FIFO_EMPTY 0x00000400
94#define TX_IN_PROGRESS 0x00000080 111#define TX_IN_PROGRESS 0x00000080
@@ -135,15 +152,8 @@ static char mv643xx_eth_driver_version[] = "1.4";
135 152
136 153
137/* 154/*
138 * SDMA configuration register. 155 * SDMA configuration register default value.
139 */ 156 */
140#define RX_BURST_SIZE_4_64BIT (2 << 1)
141#define RX_BURST_SIZE_16_64BIT (4 << 1)
142#define BLM_RX_NO_SWAP (1 << 4)
143#define BLM_TX_NO_SWAP (1 << 5)
144#define TX_BURST_SIZE_4_64BIT (2 << 22)
145#define TX_BURST_SIZE_16_64BIT (4 << 22)
146
147#if defined(__BIG_ENDIAN) 157#if defined(__BIG_ENDIAN)
148#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 158#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
149 (RX_BURST_SIZE_4_64BIT | \ 159 (RX_BURST_SIZE_4_64BIT | \
@@ -160,22 +170,10 @@ static char mv643xx_eth_driver_version[] = "1.4";
160 170
161 171
162/* 172/*
163 * Port serial control register. 173 * Misc definitions.
164 */ 174 */
165#define SET_MII_SPEED_TO_100 (1 << 24) 175#define DEFAULT_RX_QUEUE_SIZE 128
166#define SET_GMII_SPEED_TO_1000 (1 << 23) 176#define DEFAULT_TX_QUEUE_SIZE 256
167#define SET_FULL_DUPLEX_MODE (1 << 21)
168#define MAX_RX_PACKET_9700BYTE (5 << 17)
169#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
170#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
171#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
172#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
173#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
174#define FORCE_LINK_PASS (1 << 1)
175#define SERIAL_PORT_ENABLE (1 << 0)
176
177#define DEFAULT_RX_QUEUE_SIZE 128
178#define DEFAULT_TX_QUEUE_SIZE 256
179 177
180 178
181/* 179/*