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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/net/mlx4/mlx4.h
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/net/mlx4/mlx4.h')
-rw-r--r--drivers/net/mlx4/mlx4.h459
1 files changed, 459 insertions, 0 deletions
diff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h
new file mode 100644
index 00000000000..a2fcd8402d3
--- /dev/null
+++ b/drivers/net/mlx4/mlx4.h
@@ -0,0 +1,459 @@
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
40#include <linux/mutex.h>
41#include <linux/radix-tree.h>
42#include <linux/timer.h>
43#include <linux/semaphore.h>
44#include <linux/workqueue.h>
45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/driver.h>
48#include <linux/mlx4/doorbell.h>
49
50#define DRV_NAME "mlx4_core"
51#define DRV_VERSION "1.0"
52#define DRV_RELDATE "July 14, 2011"
53
54enum {
55 MLX4_HCR_BASE = 0x80680,
56 MLX4_HCR_SIZE = 0x0001c,
57 MLX4_CLR_INT_SIZE = 0x00008
58};
59
60enum {
61 MLX4_MGM_ENTRY_SIZE = 0x100,
62 MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
63 MLX4_MTT_ENTRY_PER_SEG = 8
64};
65
66enum {
67 MLX4_NUM_PDS = 1 << 15
68};
69
70enum {
71 MLX4_CMPT_TYPE_QP = 0,
72 MLX4_CMPT_TYPE_SRQ = 1,
73 MLX4_CMPT_TYPE_CQ = 2,
74 MLX4_CMPT_TYPE_EQ = 3,
75 MLX4_CMPT_NUM_TYPE
76};
77
78enum {
79 MLX4_CMPT_SHIFT = 24,
80 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
81};
82
83#ifdef CONFIG_MLX4_DEBUG
84extern int mlx4_debug_level;
85#else /* CONFIG_MLX4_DEBUG */
86#define mlx4_debug_level (0)
87#endif /* CONFIG_MLX4_DEBUG */
88
89#define mlx4_dbg(mdev, format, arg...) \
90do { \
91 if (mlx4_debug_level) \
92 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
93} while (0)
94
95#define mlx4_err(mdev, format, arg...) \
96 dev_err(&mdev->pdev->dev, format, ##arg)
97#define mlx4_info(mdev, format, arg...) \
98 dev_info(&mdev->pdev->dev, format, ##arg)
99#define mlx4_warn(mdev, format, arg...) \
100 dev_warn(&mdev->pdev->dev, format, ##arg)
101
102struct mlx4_bitmap {
103 u32 last;
104 u32 top;
105 u32 max;
106 u32 reserved_top;
107 u32 mask;
108 u32 avail;
109 spinlock_t lock;
110 unsigned long *table;
111};
112
113struct mlx4_buddy {
114 unsigned long **bits;
115 unsigned int *num_free;
116 int max_order;
117 spinlock_t lock;
118};
119
120struct mlx4_icm;
121
122struct mlx4_icm_table {
123 u64 virt;
124 int num_icm;
125 int num_obj;
126 int obj_size;
127 int lowmem;
128 int coherent;
129 struct mutex mutex;
130 struct mlx4_icm **icm;
131};
132
133struct mlx4_eq {
134 struct mlx4_dev *dev;
135 void __iomem *doorbell;
136 int eqn;
137 u32 cons_index;
138 u16 irq;
139 u16 have_irq;
140 int nent;
141 struct mlx4_buf_list *page_list;
142 struct mlx4_mtt mtt;
143};
144
145struct mlx4_profile {
146 int num_qp;
147 int rdmarc_per_qp;
148 int num_srq;
149 int num_cq;
150 int num_mcg;
151 int num_mpt;
152 int num_mtt;
153};
154
155struct mlx4_fw {
156 u64 clr_int_base;
157 u64 catas_offset;
158 struct mlx4_icm *fw_icm;
159 struct mlx4_icm *aux_icm;
160 u32 catas_size;
161 u16 fw_pages;
162 u8 clr_int_bar;
163 u8 catas_bar;
164};
165
166#define MGM_QPN_MASK 0x00FFFFFF
167#define MGM_BLCK_LB_BIT 30
168
169struct mlx4_promisc_qp {
170 struct list_head list;
171 u32 qpn;
172};
173
174struct mlx4_steer_index {
175 struct list_head list;
176 unsigned int index;
177 struct list_head duplicates;
178};
179
180struct mlx4_mgm {
181 __be32 next_gid_index;
182 __be32 members_count;
183 u32 reserved[2];
184 u8 gid[16];
185 __be32 qp[MLX4_QP_PER_MGM];
186};
187struct mlx4_cmd {
188 struct pci_pool *pool;
189 void __iomem *hcr;
190 struct mutex hcr_mutex;
191 struct semaphore poll_sem;
192 struct semaphore event_sem;
193 int max_cmds;
194 spinlock_t context_lock;
195 int free_head;
196 struct mlx4_cmd_context *context;
197 u16 token_mask;
198 u8 use_events;
199 u8 toggle;
200};
201
202struct mlx4_uar_table {
203 struct mlx4_bitmap bitmap;
204};
205
206struct mlx4_mr_table {
207 struct mlx4_bitmap mpt_bitmap;
208 struct mlx4_buddy mtt_buddy;
209 u64 mtt_base;
210 u64 mpt_base;
211 struct mlx4_icm_table mtt_table;
212 struct mlx4_icm_table dmpt_table;
213};
214
215struct mlx4_cq_table {
216 struct mlx4_bitmap bitmap;
217 spinlock_t lock;
218 struct radix_tree_root tree;
219 struct mlx4_icm_table table;
220 struct mlx4_icm_table cmpt_table;
221};
222
223struct mlx4_eq_table {
224 struct mlx4_bitmap bitmap;
225 char *irq_names;
226 void __iomem *clr_int;
227 void __iomem **uar_map;
228 u32 clr_mask;
229 struct mlx4_eq *eq;
230 struct mlx4_icm_table table;
231 struct mlx4_icm_table cmpt_table;
232 int have_irq;
233 u8 inta_pin;
234};
235
236struct mlx4_srq_table {
237 struct mlx4_bitmap bitmap;
238 spinlock_t lock;
239 struct radix_tree_root tree;
240 struct mlx4_icm_table table;
241 struct mlx4_icm_table cmpt_table;
242};
243
244struct mlx4_qp_table {
245 struct mlx4_bitmap bitmap;
246 u32 rdmarc_base;
247 int rdmarc_shift;
248 spinlock_t lock;
249 struct mlx4_icm_table qp_table;
250 struct mlx4_icm_table auxc_table;
251 struct mlx4_icm_table altc_table;
252 struct mlx4_icm_table rdmarc_table;
253 struct mlx4_icm_table cmpt_table;
254};
255
256struct mlx4_mcg_table {
257 struct mutex mutex;
258 struct mlx4_bitmap bitmap;
259 struct mlx4_icm_table table;
260};
261
262struct mlx4_catas_err {
263 u32 __iomem *map;
264 struct timer_list timer;
265 struct list_head list;
266};
267
268#define MLX4_MAX_MAC_NUM 128
269#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
270
271struct mlx4_mac_table {
272 __be64 entries[MLX4_MAX_MAC_NUM];
273 int refs[MLX4_MAX_MAC_NUM];
274 struct mutex mutex;
275 int total;
276 int max;
277};
278
279#define MLX4_MAX_VLAN_NUM 128
280#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
281
282struct mlx4_vlan_table {
283 __be32 entries[MLX4_MAX_VLAN_NUM];
284 int refs[MLX4_MAX_VLAN_NUM];
285 struct mutex mutex;
286 int total;
287 int max;
288};
289
290struct mlx4_mac_entry {
291 u64 mac;
292};
293
294struct mlx4_port_info {
295 struct mlx4_dev *dev;
296 int port;
297 char dev_name[16];
298 struct device_attribute port_attr;
299 enum mlx4_port_type tmp_type;
300 struct mlx4_mac_table mac_table;
301 struct radix_tree_root mac_tree;
302 struct mlx4_vlan_table vlan_table;
303 int base_qpn;
304};
305
306struct mlx4_sense {
307 struct mlx4_dev *dev;
308 u8 do_sense_port[MLX4_MAX_PORTS + 1];
309 u8 sense_allowed[MLX4_MAX_PORTS + 1];
310 struct delayed_work sense_poll;
311};
312
313struct mlx4_msix_ctl {
314 u64 pool_bm;
315 spinlock_t pool_lock;
316};
317
318struct mlx4_steer {
319 struct list_head promisc_qps[MLX4_NUM_STEERS];
320 struct list_head steer_entries[MLX4_NUM_STEERS];
321 struct list_head high_prios;
322};
323
324struct mlx4_priv {
325 struct mlx4_dev dev;
326
327 struct list_head dev_list;
328 struct list_head ctx_list;
329 spinlock_t ctx_lock;
330
331 struct list_head pgdir_list;
332 struct mutex pgdir_mutex;
333
334 struct mlx4_fw fw;
335 struct mlx4_cmd cmd;
336
337 struct mlx4_bitmap pd_bitmap;
338 struct mlx4_uar_table uar_table;
339 struct mlx4_mr_table mr_table;
340 struct mlx4_cq_table cq_table;
341 struct mlx4_eq_table eq_table;
342 struct mlx4_srq_table srq_table;
343 struct mlx4_qp_table qp_table;
344 struct mlx4_mcg_table mcg_table;
345 struct mlx4_bitmap counters_bitmap;
346
347 struct mlx4_catas_err catas_err;
348
349 void __iomem *clr_base;
350
351 struct mlx4_uar driver_uar;
352 void __iomem *kar;
353 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
354 struct mlx4_sense sense;
355 struct mutex port_mutex;
356 struct mlx4_msix_ctl msix_ctl;
357 struct mlx4_steer *steer;
358 struct list_head bf_list;
359 struct mutex bf_mutex;
360 struct io_mapping *bf_mapping;
361};
362
363static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
364{
365 return container_of(dev, struct mlx4_priv, dev);
366}
367
368#define MLX4_SENSE_RANGE (HZ * 3)
369
370extern struct workqueue_struct *mlx4_wq;
371
372u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
373void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
374u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
375void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
376u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
377int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
378 u32 reserved_bot, u32 resetrved_top);
379void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
380
381int mlx4_reset(struct mlx4_dev *dev);
382
383int mlx4_alloc_eq_table(struct mlx4_dev *dev);
384void mlx4_free_eq_table(struct mlx4_dev *dev);
385
386int mlx4_init_pd_table(struct mlx4_dev *dev);
387int mlx4_init_uar_table(struct mlx4_dev *dev);
388int mlx4_init_mr_table(struct mlx4_dev *dev);
389int mlx4_init_eq_table(struct mlx4_dev *dev);
390int mlx4_init_cq_table(struct mlx4_dev *dev);
391int mlx4_init_qp_table(struct mlx4_dev *dev);
392int mlx4_init_srq_table(struct mlx4_dev *dev);
393int mlx4_init_mcg_table(struct mlx4_dev *dev);
394
395void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
396void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
397void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
398void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
399void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
400void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
401void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
402void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
403
404void mlx4_start_catas_poll(struct mlx4_dev *dev);
405void mlx4_stop_catas_poll(struct mlx4_dev *dev);
406void mlx4_catas_init(void);
407int mlx4_restart_one(struct pci_dev *pdev);
408int mlx4_register_device(struct mlx4_dev *dev);
409void mlx4_unregister_device(struct mlx4_dev *dev);
410void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
411
412struct mlx4_dev_cap;
413struct mlx4_init_hca_param;
414
415u64 mlx4_make_profile(struct mlx4_dev *dev,
416 struct mlx4_profile *request,
417 struct mlx4_dev_cap *dev_cap,
418 struct mlx4_init_hca_param *init_hca);
419
420int mlx4_cmd_init(struct mlx4_dev *dev);
421void mlx4_cmd_cleanup(struct mlx4_dev *dev);
422void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
423int mlx4_cmd_use_events(struct mlx4_dev *dev);
424void mlx4_cmd_use_polling(struct mlx4_dev *dev);
425
426void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
427void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
428
429void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
430
431void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
432
433void mlx4_handle_catas_err(struct mlx4_dev *dev);
434
435int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
436 enum mlx4_port_type *type);
437void mlx4_do_sense_ports(struct mlx4_dev *dev,
438 enum mlx4_port_type *stype,
439 enum mlx4_port_type *defaults);
440void mlx4_start_sense(struct mlx4_dev *dev);
441void mlx4_stop_sense(struct mlx4_dev *dev);
442void mlx4_sense_init(struct mlx4_dev *dev);
443int mlx4_check_port_params(struct mlx4_dev *dev,
444 enum mlx4_port_type *port_type);
445int mlx4_change_port_types(struct mlx4_dev *dev,
446 enum mlx4_port_type *port_types);
447
448void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
449void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
450
451int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
452int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
453
454int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
455 enum mlx4_protocol prot, enum mlx4_steer_type steer);
456int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
457 int block_mcast_loopback, enum mlx4_protocol prot,
458 enum mlx4_steer_type steer);
459#endif /* MLX4_H */
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