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authorGuo-Fu Tseng <cooldavid@cooldavid.org>2008-10-08 22:48:58 -0400
committerDavid S. Miller <davem@davemloft.net>2008-10-08 22:51:31 -0400
commita821ebe580c535e3e8e354c6ab10516a0e95e202 (patch)
treeb47d39b17146c16b358f8e01e1dc7709564b4ee8 /drivers/net/jme.c
parent0ce2f03bade2046d6eb6184d52d065688382d7bd (diff)
jme: Added half-duplex mode and IPv6 RSS fix
1. Set bit 5 of GPREG1 to 1 to enable hardware workaround for half-duplex mode. Which the MAC processor generates CRS/COL by itself instead of receive it from PHY processor. 2. Set bit 6 of GPREG1 to 1 to enable hardware workaround that masks the MAC processor working right while calculating IPv6 RSS in 10/100 mode. 3. Group the workaround codes all together. Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/jme.c')
-rw-r--r--drivers/net/jme.c51
1 files changed, 33 insertions, 18 deletions
diff --git a/drivers/net/jme.c b/drivers/net/jme.c
index f292df55754..635f616fd97 100644
--- a/drivers/net/jme.c
+++ b/drivers/net/jme.c
@@ -190,7 +190,7 @@ jme_reset_mac_processor(struct jme_adapter *jme)
190 else 190 else
191 gpreg0 = GPREG0_DEFAULT; 191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0); 192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, 0); 193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194} 194}
195 195
196static inline void 196static inline void
@@ -365,7 +365,7 @@ static int
365jme_check_link(struct net_device *netdev, int testonly) 365jme_check_link(struct net_device *netdev, int testonly)
366{ 366{
367 struct jme_adapter *jme = netdev_priv(netdev); 367 struct jme_adapter *jme = netdev_priv(netdev);
368 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr; 368 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
369 char linkmsg[64]; 369 char linkmsg[64];
370 int rc = 0; 370 int rc = 0;
371 371
@@ -437,37 +437,22 @@ jme_check_link(struct net_device *netdev, int testonly)
437 case PHY_LINK_SPEED_10M: 437 case PHY_LINK_SPEED_10M:
438 ghc |= GHC_SPEED_10M; 438 ghc |= GHC_SPEED_10M;
439 strcat(linkmsg, "10 Mbps, "); 439 strcat(linkmsg, "10 Mbps, ");
440 if (is_buggy250(jme->pdev->device, jme->chiprev))
441 jme_set_phyfifoa(jme);
442 break; 440 break;
443 case PHY_LINK_SPEED_100M: 441 case PHY_LINK_SPEED_100M:
444 ghc |= GHC_SPEED_100M; 442 ghc |= GHC_SPEED_100M;
445 strcat(linkmsg, "100 Mbps, "); 443 strcat(linkmsg, "100 Mbps, ");
446 if (is_buggy250(jme->pdev->device, jme->chiprev))
447 jme_set_phyfifob(jme);
448 break; 444 break;
449 case PHY_LINK_SPEED_1000M: 445 case PHY_LINK_SPEED_1000M:
450 ghc |= GHC_SPEED_1000M; 446 ghc |= GHC_SPEED_1000M;
451 strcat(linkmsg, "1000 Mbps, "); 447 strcat(linkmsg, "1000 Mbps, ");
452 if (is_buggy250(jme->pdev->device, jme->chiprev))
453 jme_set_phyfifoa(jme);
454 break; 448 break;
455 default: 449 default:
456 break; 450 break;
457 } 451 }
458 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
459
460 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
461 "Full-Duplex, " :
462 "Half-Duplex, ");
463
464 if (phylink & PHY_LINK_MDI_STAT)
465 strcat(linkmsg, "MDI-X");
466 else
467 strcat(linkmsg, "MDI");
468 452
469 if (phylink & PHY_LINK_DUPLEX) { 453 if (phylink & PHY_LINK_DUPLEX) {
470 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT); 454 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
455 ghc |= GHC_DPX;
471 } else { 456 } else {
472 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT | 457 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
473 TXMCS_BACKOFF | 458 TXMCS_BACKOFF |
@@ -478,6 +463,36 @@ jme_check_link(struct net_device *netdev, int testonly)
478 TXTRHD_TXREN | 463 TXTRHD_TXREN |
479 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL)); 464 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
480 } 465 }
466 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
467 "Full-Duplex, " :
468 "Half-Duplex, ");
469
470 if (phylink & PHY_LINK_MDI_STAT)
471 strcat(linkmsg, "MDI-X");
472 else
473 strcat(linkmsg, "MDI");
474
475 gpreg1 = GPREG1_DEFAULT;
476 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
477 if (!(phylink & PHY_LINK_DUPLEX))
478 gpreg1 |= GPREG1_HALFMODEPATCH;
479 switch (phylink & PHY_LINK_SPEED_MASK) {
480 case PHY_LINK_SPEED_10M:
481 jme_set_phyfifoa(jme);
482 gpreg1 |= GPREG1_RSSPATCH;
483 break;
484 case PHY_LINK_SPEED_100M:
485 jme_set_phyfifob(jme);
486 gpreg1 |= GPREG1_RSSPATCH;
487 break;
488 case PHY_LINK_SPEED_1000M:
489 jme_set_phyfifoa(jme);
490 break;
491 default:
492 break;
493 }
494 }
495 jwrite32(jme, JME_GPREG1, gpreg1);
481 496
482 jme->reg_ghc = ghc; 497 jme->reg_ghc = ghc;
483 jwrite32(jme, JME_GHC, ghc); 498 jwrite32(jme, JME_GHC, ghc);