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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/net/ixgbevf
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/net/ixgbevf')
-rw-r--r--drivers/net/ixgbevf/Makefile38
-rw-r--r--drivers/net/ixgbevf/defines.h297
-rw-r--r--drivers/net/ixgbevf/ethtool.c742
-rw-r--r--drivers/net/ixgbevf/ixgbevf.h318
-rw-r--r--drivers/net/ixgbevf/ixgbevf_main.c3523
-rw-r--r--drivers/net/ixgbevf/mbx.c341
-rw-r--r--drivers/net/ixgbevf/mbx.h99
-rw-r--r--drivers/net/ixgbevf/regs.h85
-rw-r--r--drivers/net/ixgbevf/vf.c426
-rw-r--r--drivers/net/ixgbevf/vf.h174
10 files changed, 6043 insertions, 0 deletions
diff --git a/drivers/net/ixgbevf/Makefile b/drivers/net/ixgbevf/Makefile
new file mode 100644
index 00000000000..1f35d229e71
--- /dev/null
+++ b/drivers/net/ixgbevf/Makefile
@@ -0,0 +1,38 @@
1################################################################################
2#
3# Intel 82599 Virtual Function driver
4# Copyright(c) 1999 - 2010 Intel Corporation.
5#
6# This program is free software; you can redistribute it and/or modify it
7# under the terms and conditions of the GNU General Public License,
8# version 2, as published by the Free Software Foundation.
9#
10# This program is distributed in the hope it will be useful, but WITHOUT
11# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13# more details.
14#
15# You should have received a copy of the GNU General Public License along with
16# this program; if not, write to the Free Software Foundation, Inc.,
17# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18#
19# The full GNU General Public License is included in this distribution in
20# the file called "COPYING".
21#
22# Contact Information:
23# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25#
26################################################################################
27
28#
29# Makefile for the Intel(R) 82599 VF ethernet driver
30#
31
32obj-$(CONFIG_IXGBEVF) += ixgbevf.o
33
34ixgbevf-objs := vf.o \
35 mbx.o \
36 ethtool.o \
37 ixgbevf_main.o
38
diff --git a/drivers/net/ixgbevf/defines.h b/drivers/net/ixgbevf/defines.h
new file mode 100644
index 00000000000..78abb6f1a86
--- /dev/null
+++ b/drivers/net/ixgbevf/defines.h
@@ -0,0 +1,297 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBEVF_DEFINES_H_
29#define _IXGBEVF_DEFINES_H_
30
31/* Device IDs */
32#define IXGBE_DEV_ID_82599_VF 0x10ED
33#define IXGBE_DEV_ID_X540_VF 0x1515
34
35#define IXGBE_VF_IRQ_CLEAR_MASK 7
36#define IXGBE_VF_MAX_TX_QUEUES 1
37#define IXGBE_VF_MAX_RX_QUEUES 1
38#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
39
40/* Link speed */
41typedef u32 ixgbe_link_speed;
42#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
43#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
44
45#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
46#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
47#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
48#define IXGBE_LINKS_UP 0x40000000
49#define IXGBE_LINKS_SPEED_82599 0x30000000
50#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
51#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
52
53/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
54#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
55#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
56#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
57
58/* Interrupt Vector Allocation Registers */
59#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
60
61#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
62
63/* Receive Config masks */
64#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
65#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
66#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
67#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
68#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */
69#define IXGBE_RXDCTL_RLPML_EN 0x00008000
70
71/* DCA Control */
72#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
73
74/* PSRTYPE bit definitions */
75#define IXGBE_PSRTYPE_TCPHDR 0x00000010
76#define IXGBE_PSRTYPE_UDPHDR 0x00000020
77#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
78#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
79#define IXGBE_PSRTYPE_L2HDR 0x00001000
80
81/* SRRCTL bit definitions */
82#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
83#define IXGBE_SRRCTL_RDMTS_SHIFT 22
84#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
85#define IXGBE_SRRCTL_DROP_EN 0x10000000
86#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
87#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
88#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
89#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
90#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
91#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
92#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
93#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
94
95/* Receive Descriptor bit definitions */
96#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
97#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
98#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
99#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
100#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
101#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
102#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
103#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
104#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
105#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
106#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
107#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
108#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
109#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
110#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
111#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
112#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
113#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
114#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
115#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
116#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
117#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
118#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
119#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
120#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
121#define IXGBE_RXDADV_ERR_MASK 0xFFF00000 /* RDESC.ERRORS mask */
122#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
123#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
124#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
125#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
126#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
127#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
128#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
129#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
130#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
131#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
132#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
133#define IXGBE_RXD_PRI_SHIFT 13
134#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
135#define IXGBE_RXD_CFI_SHIFT 12
136
137#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
138#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
139#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
140#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
141#define IXGBE_RXDADV_STAT_MASK 0x000FFFFF /* Stat/NEXTP: bit 0-19 */
142#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
143#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
144#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
145#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
146#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
147#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
148
149#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
150#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
151#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
152#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
153#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
154#define IXGBE_RXDADV_RSCCNT_SHIFT 17
155#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
156#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
157#define IXGBE_RXDADV_SPH 0x8000
158
159#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
160 IXGBE_RXD_ERR_CE | \
161 IXGBE_RXD_ERR_LE | \
162 IXGBE_RXD_ERR_PE | \
163 IXGBE_RXD_ERR_OSE | \
164 IXGBE_RXD_ERR_USE)
165
166#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
167 IXGBE_RXDADV_ERR_CE | \
168 IXGBE_RXDADV_ERR_LE | \
169 IXGBE_RXDADV_ERR_PE | \
170 IXGBE_RXDADV_ERR_OSE | \
171 IXGBE_RXDADV_ERR_USE)
172
173#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
174#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
175#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
176#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
177#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
178#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
179#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
180#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
181#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
182
183/* Transmit Descriptor - Advanced */
184union ixgbe_adv_tx_desc {
185 struct {
186 __le64 buffer_addr; /* Address of descriptor's data buf */
187 __le32 cmd_type_len;
188 __le32 olinfo_status;
189 } read;
190 struct {
191 __le64 rsvd; /* Reserved */
192 __le32 nxtseq_seed;
193 __le32 status;
194 } wb;
195};
196
197/* Receive Descriptor - Advanced */
198union ixgbe_adv_rx_desc {
199 struct {
200 __le64 pkt_addr; /* Packet buffer address */
201 __le64 hdr_addr; /* Header buffer address */
202 } read;
203 struct {
204 struct {
205 union {
206 __le32 data;
207 struct {
208 __le16 pkt_info; /* RSS, Pkt type */
209 __le16 hdr_info; /* Splithdr, hdrlen */
210 } hs_rss;
211 } lo_dword;
212 union {
213 __le32 rss; /* RSS Hash */
214 struct {
215 __le16 ip_id; /* IP id */
216 __le16 csum; /* Packet Checksum */
217 } csum_ip;
218 } hi_dword;
219 } lower;
220 struct {
221 __le32 status_error; /* ext status/error */
222 __le16 length; /* Packet length */
223 __le16 vlan; /* VLAN tag */
224 } upper;
225 } wb; /* writeback */
226};
227
228/* Context descriptors */
229struct ixgbe_adv_tx_context_desc {
230 __le32 vlan_macip_lens;
231 __le32 seqnum_seed;
232 __le32 type_tucmd_mlhl;
233 __le32 mss_l4len_idx;
234};
235
236/* Adv Transmit Descriptor Config Masks */
237#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
238#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
239#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
240#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
241#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
242#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
243#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
244#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
245#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
246#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
247#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
248#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
249#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
250#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
251#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
252#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
253#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
254#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
255 IXGBE_ADVTXD_POPTS_SHIFT)
256#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
257 IXGBE_ADVTXD_POPTS_SHIFT)
258#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
259#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
260#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
261#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
262#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
263
264/* Interrupt register bitmasks */
265
266/* Extended Interrupt Cause Read */
267#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
268#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
269#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
270
271/* Extended Interrupt Cause Set */
272#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
273#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
274#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
275
276/* Extended Interrupt Mask Set */
277#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
278#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
279#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
280
281/* Extended Interrupt Mask Clear */
282#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
283#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
284#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
285
286#define IXGBE_EIMS_ENABLE_MASK ( \
287 IXGBE_EIMS_RTX_QUEUE | \
288 IXGBE_EIMS_MAILBOX | \
289 IXGBE_EIMS_OTHER)
290
291#define IXGBE_EITR_CNT_WDIS 0x80000000
292
293/* Error Codes */
294#define IXGBE_ERR_INVALID_MAC_ADDR -1
295#define IXGBE_ERR_RESET_FAILED -2
296
297#endif /* _IXGBEVF_DEFINES_H_ */
diff --git a/drivers/net/ixgbevf/ethtool.c b/drivers/net/ixgbevf/ethtool.c
new file mode 100644
index 00000000000..deee3754b1f
--- /dev/null
+++ b/drivers/net/ixgbevf/ethtool.c
@@ -0,0 +1,742 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbevf */
29
30#include <linux/types.h>
31#include <linux/module.h>
32#include <linux/slab.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/ethtool.h>
36#include <linux/vmalloc.h>
37#include <linux/if_vlan.h>
38#include <linux/uaccess.h>
39
40#include "ixgbevf.h"
41
42#define IXGBE_ALL_RAR_ENTRIES 16
43
44#ifdef ETHTOOL_GSTATS
45struct ixgbe_stats {
46 char stat_string[ETH_GSTRING_LEN];
47 int sizeof_stat;
48 int stat_offset;
49 int base_stat_offset;
50 int saved_reset_offset;
51};
52
53#define IXGBEVF_STAT(m, b, r) sizeof(((struct ixgbevf_adapter *)0)->m), \
54 offsetof(struct ixgbevf_adapter, m), \
55 offsetof(struct ixgbevf_adapter, b), \
56 offsetof(struct ixgbevf_adapter, r)
57static struct ixgbe_stats ixgbe_gstrings_stats[] = {
58 {"rx_packets", IXGBEVF_STAT(stats.vfgprc, stats.base_vfgprc,
59 stats.saved_reset_vfgprc)},
60 {"tx_packets", IXGBEVF_STAT(stats.vfgptc, stats.base_vfgptc,
61 stats.saved_reset_vfgptc)},
62 {"rx_bytes", IXGBEVF_STAT(stats.vfgorc, stats.base_vfgorc,
63 stats.saved_reset_vfgorc)},
64 {"tx_bytes", IXGBEVF_STAT(stats.vfgotc, stats.base_vfgotc,
65 stats.saved_reset_vfgotc)},
66 {"tx_busy", IXGBEVF_STAT(tx_busy, zero_base, zero_base)},
67 {"multicast", IXGBEVF_STAT(stats.vfmprc, stats.base_vfmprc,
68 stats.saved_reset_vfmprc)},
69 {"rx_csum_offload_good", IXGBEVF_STAT(hw_csum_rx_good, zero_base,
70 zero_base)},
71 {"rx_csum_offload_errors", IXGBEVF_STAT(hw_csum_rx_error, zero_base,
72 zero_base)},
73 {"tx_csum_offload_ctxt", IXGBEVF_STAT(hw_csum_tx_good, zero_base,
74 zero_base)},
75 {"rx_header_split", IXGBEVF_STAT(rx_hdr_split, zero_base, zero_base)},
76};
77
78#define IXGBE_QUEUE_STATS_LEN 0
79#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
80
81#define IXGBEVF_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + IXGBE_QUEUE_STATS_LEN)
82#endif /* ETHTOOL_GSTATS */
83#ifdef ETHTOOL_TEST
84static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
85 "Register test (offline)",
86 "Link test (on/offline)"
87};
88#define IXGBE_TEST_LEN (sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN)
89#endif /* ETHTOOL_TEST */
90
91static int ixgbevf_get_settings(struct net_device *netdev,
92 struct ethtool_cmd *ecmd)
93{
94 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
95 struct ixgbe_hw *hw = &adapter->hw;
96 u32 link_speed = 0;
97 bool link_up;
98
99 ecmd->supported = SUPPORTED_10000baseT_Full;
100 ecmd->autoneg = AUTONEG_DISABLE;
101 ecmd->transceiver = XCVR_DUMMY1;
102 ecmd->port = -1;
103
104 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
105
106 if (link_up) {
107 ethtool_cmd_speed_set(
108 ecmd,
109 (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
110 SPEED_10000 : SPEED_1000);
111 ecmd->duplex = DUPLEX_FULL;
112 } else {
113 ethtool_cmd_speed_set(ecmd, -1);
114 ecmd->duplex = -1;
115 }
116
117 return 0;
118}
119
120static u32 ixgbevf_get_rx_csum(struct net_device *netdev)
121{
122 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
123 return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED;
124}
125
126static int ixgbevf_set_rx_csum(struct net_device *netdev, u32 data)
127{
128 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
129 if (data)
130 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
131 else
132 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
133
134 if (netif_running(netdev)) {
135 if (!adapter->dev_closed)
136 ixgbevf_reinit_locked(adapter);
137 } else {
138 ixgbevf_reset(adapter);
139 }
140
141 return 0;
142}
143
144static int ixgbevf_set_tso(struct net_device *netdev, u32 data)
145{
146 if (data) {
147 netdev->features |= NETIF_F_TSO;
148 netdev->features |= NETIF_F_TSO6;
149 } else {
150 netif_tx_stop_all_queues(netdev);
151 netdev->features &= ~NETIF_F_TSO;
152 netdev->features &= ~NETIF_F_TSO6;
153 netif_tx_start_all_queues(netdev);
154 }
155 return 0;
156}
157
158static u32 ixgbevf_get_msglevel(struct net_device *netdev)
159{
160 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
161 return adapter->msg_enable;
162}
163
164static void ixgbevf_set_msglevel(struct net_device *netdev, u32 data)
165{
166 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
167 adapter->msg_enable = data;
168}
169
170#define IXGBE_GET_STAT(_A_, _R_) (_A_->stats._R_)
171
172static char *ixgbevf_reg_names[] = {
173 "IXGBE_VFCTRL",
174 "IXGBE_VFSTATUS",
175 "IXGBE_VFLINKS",
176 "IXGBE_VFRXMEMWRAP",
177 "IXGBE_VFFRTIMER",
178 "IXGBE_VTEICR",
179 "IXGBE_VTEICS",
180 "IXGBE_VTEIMS",
181 "IXGBE_VTEIMC",
182 "IXGBE_VTEIAC",
183 "IXGBE_VTEIAM",
184 "IXGBE_VTEITR",
185 "IXGBE_VTIVAR",
186 "IXGBE_VTIVAR_MISC",
187 "IXGBE_VFRDBAL0",
188 "IXGBE_VFRDBAL1",
189 "IXGBE_VFRDBAH0",
190 "IXGBE_VFRDBAH1",
191 "IXGBE_VFRDLEN0",
192 "IXGBE_VFRDLEN1",
193 "IXGBE_VFRDH0",
194 "IXGBE_VFRDH1",
195 "IXGBE_VFRDT0",
196 "IXGBE_VFRDT1",
197 "IXGBE_VFRXDCTL0",
198 "IXGBE_VFRXDCTL1",
199 "IXGBE_VFSRRCTL0",
200 "IXGBE_VFSRRCTL1",
201 "IXGBE_VFPSRTYPE",
202 "IXGBE_VFTDBAL0",
203 "IXGBE_VFTDBAL1",
204 "IXGBE_VFTDBAH0",
205 "IXGBE_VFTDBAH1",
206 "IXGBE_VFTDLEN0",
207 "IXGBE_VFTDLEN1",
208 "IXGBE_VFTDH0",
209 "IXGBE_VFTDH1",
210 "IXGBE_VFTDT0",
211 "IXGBE_VFTDT1",
212 "IXGBE_VFTXDCTL0",
213 "IXGBE_VFTXDCTL1",
214 "IXGBE_VFTDWBAL0",
215 "IXGBE_VFTDWBAL1",
216 "IXGBE_VFTDWBAH0",
217 "IXGBE_VFTDWBAH1"
218};
219
220
221static int ixgbevf_get_regs_len(struct net_device *netdev)
222{
223 return (ARRAY_SIZE(ixgbevf_reg_names)) * sizeof(u32);
224}
225
226static void ixgbevf_get_regs(struct net_device *netdev,
227 struct ethtool_regs *regs,
228 void *p)
229{
230 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
231 struct ixgbe_hw *hw = &adapter->hw;
232 u32 *regs_buff = p;
233 u32 regs_len = ixgbevf_get_regs_len(netdev);
234 u8 i;
235
236 memset(p, 0, regs_len);
237
238 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
239
240 /* General Registers */
241 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_VFCTRL);
242 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_VFSTATUS);
243 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
244 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_VFRXMEMWRAP);
245 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_VFFRTIMER);
246
247 /* Interrupt */
248 /* don't read EICR because it can clear interrupt causes, instead
249 * read EICS which is a shadow but doesn't clear EICR */
250 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_VTEICS);
251 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_VTEICS);
252 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
253 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_VTEIMC);
254 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_VTEIAC);
255 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_VTEIAM);
256 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_VTEITR(0));
257 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_VTIVAR(0));
258 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
259
260 /* Receive DMA */
261 for (i = 0; i < 2; i++)
262 regs_buff[14 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDBAL(i));
263 for (i = 0; i < 2; i++)
264 regs_buff[16 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDBAH(i));
265 for (i = 0; i < 2; i++)
266 regs_buff[18 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDLEN(i));
267 for (i = 0; i < 2; i++)
268 regs_buff[20 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDH(i));
269 for (i = 0; i < 2; i++)
270 regs_buff[22 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDT(i));
271 for (i = 0; i < 2; i++)
272 regs_buff[24 + i] = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
273 for (i = 0; i < 2; i++)
274 regs_buff[26 + i] = IXGBE_READ_REG(hw, IXGBE_VFSRRCTL(i));
275
276 /* Receive */
277 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_VFPSRTYPE);
278
279 /* Transmit */
280 for (i = 0; i < 2; i++)
281 regs_buff[29 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDBAL(i));
282 for (i = 0; i < 2; i++)
283 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDBAH(i));
284 for (i = 0; i < 2; i++)
285 regs_buff[33 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDLEN(i));
286 for (i = 0; i < 2; i++)
287 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDH(i));
288 for (i = 0; i < 2; i++)
289 regs_buff[37 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDT(i));
290 for (i = 0; i < 2; i++)
291 regs_buff[39 + i] = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
292 for (i = 0; i < 2; i++)
293 regs_buff[41 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDWBAL(i));
294 for (i = 0; i < 2; i++)
295 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDWBAH(i));
296
297 for (i = 0; i < ARRAY_SIZE(ixgbevf_reg_names); i++)
298 hw_dbg(hw, "%s\t%8.8x\n", ixgbevf_reg_names[i], regs_buff[i]);
299}
300
301static void ixgbevf_get_drvinfo(struct net_device *netdev,
302 struct ethtool_drvinfo *drvinfo)
303{
304 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
305
306 strlcpy(drvinfo->driver, ixgbevf_driver_name, 32);
307 strlcpy(drvinfo->version, ixgbevf_driver_version, 32);
308
309 strlcpy(drvinfo->fw_version, "N/A", 4);
310 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
311}
312
313static void ixgbevf_get_ringparam(struct net_device *netdev,
314 struct ethtool_ringparam *ring)
315{
316 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
317 struct ixgbevf_ring *tx_ring = adapter->tx_ring;
318 struct ixgbevf_ring *rx_ring = adapter->rx_ring;
319
320 ring->rx_max_pending = IXGBEVF_MAX_RXD;
321 ring->tx_max_pending = IXGBEVF_MAX_TXD;
322 ring->rx_mini_max_pending = 0;
323 ring->rx_jumbo_max_pending = 0;
324 ring->rx_pending = rx_ring->count;
325 ring->tx_pending = tx_ring->count;
326 ring->rx_mini_pending = 0;
327 ring->rx_jumbo_pending = 0;
328}
329
330static int ixgbevf_set_ringparam(struct net_device *netdev,
331 struct ethtool_ringparam *ring)
332{
333 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
334 struct ixgbevf_ring *tx_ring = NULL, *rx_ring = NULL;
335 int i, err = 0;
336 u32 new_rx_count, new_tx_count;
337
338 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
339 return -EINVAL;
340
341 new_rx_count = max(ring->rx_pending, (u32)IXGBEVF_MIN_RXD);
342 new_rx_count = min(new_rx_count, (u32)IXGBEVF_MAX_RXD);
343 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
344
345 new_tx_count = max(ring->tx_pending, (u32)IXGBEVF_MIN_TXD);
346 new_tx_count = min(new_tx_count, (u32)IXGBEVF_MAX_TXD);
347 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
348
349 if ((new_tx_count == adapter->tx_ring->count) &&
350 (new_rx_count == adapter->rx_ring->count)) {
351 /* nothing to do */
352 return 0;
353 }
354
355 while (test_and_set_bit(__IXGBEVF_RESETTING, &adapter->state))
356 msleep(1);
357
358 /*
359 * If the adapter isn't up and running then just set the
360 * new parameters and scurry for the exits.
361 */
362 if (!netif_running(adapter->netdev)) {
363 for (i = 0; i < adapter->num_tx_queues; i++)
364 adapter->tx_ring[i].count = new_tx_count;
365 for (i = 0; i < adapter->num_rx_queues; i++)
366 adapter->rx_ring[i].count = new_rx_count;
367 adapter->tx_ring_count = new_tx_count;
368 adapter->rx_ring_count = new_rx_count;
369 goto clear_reset;
370 }
371
372 tx_ring = kcalloc(adapter->num_tx_queues,
373 sizeof(struct ixgbevf_ring), GFP_KERNEL);
374 if (!tx_ring) {
375 err = -ENOMEM;
376 goto clear_reset;
377 }
378
379 rx_ring = kcalloc(adapter->num_rx_queues,
380 sizeof(struct ixgbevf_ring), GFP_KERNEL);
381 if (!rx_ring) {
382 err = -ENOMEM;
383 goto err_rx_setup;
384 }
385
386 ixgbevf_down(adapter);
387
388 memcpy(tx_ring, adapter->tx_ring,
389 adapter->num_tx_queues * sizeof(struct ixgbevf_ring));
390 for (i = 0; i < adapter->num_tx_queues; i++) {
391 tx_ring[i].count = new_tx_count;
392 err = ixgbevf_setup_tx_resources(adapter, &tx_ring[i]);
393 if (err) {
394 while (i) {
395 i--;
396 ixgbevf_free_tx_resources(adapter,
397 &tx_ring[i]);
398 }
399 goto err_tx_ring_setup;
400 }
401 tx_ring[i].v_idx = adapter->tx_ring[i].v_idx;
402 }
403
404 memcpy(rx_ring, adapter->rx_ring,
405 adapter->num_rx_queues * sizeof(struct ixgbevf_ring));
406 for (i = 0; i < adapter->num_rx_queues; i++) {
407 rx_ring[i].count = new_rx_count;
408 err = ixgbevf_setup_rx_resources(adapter, &rx_ring[i]);
409 if (err) {
410 while (i) {
411 i--;
412 ixgbevf_free_rx_resources(adapter,
413 &rx_ring[i]);
414 }
415 goto err_rx_ring_setup;
416 }
417 rx_ring[i].v_idx = adapter->rx_ring[i].v_idx;
418 }
419
420 /*
421 * Only switch to new rings if all the prior allocations
422 * and ring setups have succeeded.
423 */
424 kfree(adapter->tx_ring);
425 adapter->tx_ring = tx_ring;
426 adapter->tx_ring_count = new_tx_count;
427
428 kfree(adapter->rx_ring);
429 adapter->rx_ring = rx_ring;
430 adapter->rx_ring_count = new_rx_count;
431
432 /* success! */
433 ixgbevf_up(adapter);
434
435 goto clear_reset;
436
437err_rx_ring_setup:
438 for(i = 0; i < adapter->num_tx_queues; i++)
439 ixgbevf_free_tx_resources(adapter, &tx_ring[i]);
440
441err_tx_ring_setup:
442 kfree(rx_ring);
443
444err_rx_setup:
445 kfree(tx_ring);
446
447clear_reset:
448 clear_bit(__IXGBEVF_RESETTING, &adapter->state);
449 return err;
450}
451
452static int ixgbevf_get_sset_count(struct net_device *dev, int stringset)
453{
454 switch (stringset) {
455 case ETH_SS_TEST:
456 return IXGBE_TEST_LEN;
457 case ETH_SS_STATS:
458 return IXGBE_GLOBAL_STATS_LEN;
459 default:
460 return -EINVAL;
461 }
462}
463
464static void ixgbevf_get_ethtool_stats(struct net_device *netdev,
465 struct ethtool_stats *stats, u64 *data)
466{
467 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
468 int i;
469
470 ixgbevf_update_stats(adapter);
471 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
472 char *p = (char *)adapter +
473 ixgbe_gstrings_stats[i].stat_offset;
474 char *b = (char *)adapter +
475 ixgbe_gstrings_stats[i].base_stat_offset;
476 char *r = (char *)adapter +
477 ixgbe_gstrings_stats[i].saved_reset_offset;
478 data[i] = ((ixgbe_gstrings_stats[i].sizeof_stat ==
479 sizeof(u64)) ? *(u64 *)p : *(u32 *)p) -
480 ((ixgbe_gstrings_stats[i].sizeof_stat ==
481 sizeof(u64)) ? *(u64 *)b : *(u32 *)b) +
482 ((ixgbe_gstrings_stats[i].sizeof_stat ==
483 sizeof(u64)) ? *(u64 *)r : *(u32 *)r);
484 }
485}
486
487static void ixgbevf_get_strings(struct net_device *netdev, u32 stringset,
488 u8 *data)
489{
490 char *p = (char *)data;
491 int i;
492
493 switch (stringset) {
494 case ETH_SS_TEST:
495 memcpy(data, *ixgbe_gstrings_test,
496 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
497 break;
498 case ETH_SS_STATS:
499 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
500 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
501 ETH_GSTRING_LEN);
502 p += ETH_GSTRING_LEN;
503 }
504 break;
505 }
506}
507
508static int ixgbevf_link_test(struct ixgbevf_adapter *adapter, u64 *data)
509{
510 struct ixgbe_hw *hw = &adapter->hw;
511 bool link_up;
512 u32 link_speed = 0;
513 *data = 0;
514
515 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
516 if (!link_up)
517 *data = 1;
518
519 return *data;
520}
521
522/* ethtool register test data */
523struct ixgbevf_reg_test {
524 u16 reg;
525 u8 array_len;
526 u8 test_type;
527 u32 mask;
528 u32 write;
529};
530
531/* In the hardware, registers are laid out either singly, in arrays
532 * spaced 0x40 bytes apart, or in contiguous tables. We assume
533 * most tests take place on arrays or single registers (handled
534 * as a single-element array) and special-case the tables.
535 * Table tests are always pattern tests.
536 *
537 * We also make provision for some required setup steps by specifying
538 * registers to be written without any read-back testing.
539 */
540
541#define PATTERN_TEST 1
542#define SET_READ_TEST 2
543#define WRITE_NO_TEST 3
544#define TABLE32_TEST 4
545#define TABLE64_TEST_LO 5
546#define TABLE64_TEST_HI 6
547
548/* default VF register test */
549static const struct ixgbevf_reg_test reg_test_vf[] = {
550 { IXGBE_VFRDBAL(0), 2, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
551 { IXGBE_VFRDBAH(0), 2, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
552 { IXGBE_VFRDLEN(0), 2, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
553 { IXGBE_VFRXDCTL(0), 2, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
554 { IXGBE_VFRDT(0), 2, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
555 { IXGBE_VFRXDCTL(0), 2, WRITE_NO_TEST, 0, 0 },
556 { IXGBE_VFTDBAL(0), 2, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
557 { IXGBE_VFTDBAH(0), 2, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
558 { IXGBE_VFTDLEN(0), 2, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
559 { 0, 0, 0, 0 }
560};
561
562static const u32 register_test_patterns[] = {
563 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF
564};
565
566#define REG_PATTERN_TEST(R, M, W) \
567{ \
568 u32 pat, val, before; \
569 for (pat = 0; pat < ARRAY_SIZE(register_test_patterns); pat++) { \
570 before = readl(adapter->hw.hw_addr + R); \
571 writel((register_test_patterns[pat] & W), \
572 (adapter->hw.hw_addr + R)); \
573 val = readl(adapter->hw.hw_addr + R); \
574 if (val != (register_test_patterns[pat] & W & M)) { \
575 hw_dbg(&adapter->hw, \
576 "pattern test reg %04X failed: got " \
577 "0x%08X expected 0x%08X\n", \
578 R, val, (register_test_patterns[pat] & W & M)); \
579 *data = R; \
580 writel(before, adapter->hw.hw_addr + R); \
581 return 1; \
582 } \
583 writel(before, adapter->hw.hw_addr + R); \
584 } \
585}
586
587#define REG_SET_AND_CHECK(R, M, W) \
588{ \
589 u32 val, before; \
590 before = readl(adapter->hw.hw_addr + R); \
591 writel((W & M), (adapter->hw.hw_addr + R)); \
592 val = readl(adapter->hw.hw_addr + R); \
593 if ((W & M) != (val & M)) { \
594 printk(KERN_ERR "set/check reg %04X test failed: got 0x%08X " \
595 "expected 0x%08X\n", R, (val & M), (W & M)); \
596 *data = R; \
597 writel(before, (adapter->hw.hw_addr + R)); \
598 return 1; \
599 } \
600 writel(before, (adapter->hw.hw_addr + R)); \
601}
602
603static int ixgbevf_reg_test(struct ixgbevf_adapter *adapter, u64 *data)
604{
605 const struct ixgbevf_reg_test *test;
606 u32 i;
607
608 test = reg_test_vf;
609
610 /*
611 * Perform the register test, looping through the test table
612 * until we either fail or reach the null entry.
613 */
614 while (test->reg) {
615 for (i = 0; i < test->array_len; i++) {
616 switch (test->test_type) {
617 case PATTERN_TEST:
618 REG_PATTERN_TEST(test->reg + (i * 0x40),
619 test->mask,
620 test->write);
621 break;
622 case SET_READ_TEST:
623 REG_SET_AND_CHECK(test->reg + (i * 0x40),
624 test->mask,
625 test->write);
626 break;
627 case WRITE_NO_TEST:
628 writel(test->write,
629 (adapter->hw.hw_addr + test->reg)
630 + (i * 0x40));
631 break;
632 case TABLE32_TEST:
633 REG_PATTERN_TEST(test->reg + (i * 4),
634 test->mask,
635 test->write);
636 break;
637 case TABLE64_TEST_LO:
638 REG_PATTERN_TEST(test->reg + (i * 8),
639 test->mask,
640 test->write);
641 break;
642 case TABLE64_TEST_HI:
643 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
644 test->mask,
645 test->write);
646 break;
647 }
648 }
649 test++;
650 }
651
652 *data = 0;
653 return *data;
654}
655
656static void ixgbevf_diag_test(struct net_device *netdev,
657 struct ethtool_test *eth_test, u64 *data)
658{
659 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
660 bool if_running = netif_running(netdev);
661
662 set_bit(__IXGBEVF_TESTING, &adapter->state);
663 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
664 /* Offline tests */
665
666 hw_dbg(&adapter->hw, "offline testing starting\n");
667
668 /* Link test performed before hardware reset so autoneg doesn't
669 * interfere with test result */
670 if (ixgbevf_link_test(adapter, &data[1]))
671 eth_test->flags |= ETH_TEST_FL_FAILED;
672
673 if (if_running)
674 /* indicate we're in test mode */
675 dev_close(netdev);
676 else
677 ixgbevf_reset(adapter);
678
679 hw_dbg(&adapter->hw, "register testing starting\n");
680 if (ixgbevf_reg_test(adapter, &data[0]))
681 eth_test->flags |= ETH_TEST_FL_FAILED;
682
683 ixgbevf_reset(adapter);
684
685 clear_bit(__IXGBEVF_TESTING, &adapter->state);
686 if (if_running)
687 dev_open(netdev);
688 } else {
689 hw_dbg(&adapter->hw, "online testing starting\n");
690 /* Online tests */
691 if (ixgbevf_link_test(adapter, &data[1]))
692 eth_test->flags |= ETH_TEST_FL_FAILED;
693
694 /* Online tests aren't run; pass by default */
695 data[0] = 0;
696
697 clear_bit(__IXGBEVF_TESTING, &adapter->state);
698 }
699 msleep_interruptible(4 * 1000);
700}
701
702static int ixgbevf_nway_reset(struct net_device *netdev)
703{
704 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
705
706 if (netif_running(netdev)) {
707 if (!adapter->dev_closed)
708 ixgbevf_reinit_locked(adapter);
709 }
710
711 return 0;
712}
713
714static struct ethtool_ops ixgbevf_ethtool_ops = {
715 .get_settings = ixgbevf_get_settings,
716 .get_drvinfo = ixgbevf_get_drvinfo,
717 .get_regs_len = ixgbevf_get_regs_len,
718 .get_regs = ixgbevf_get_regs,
719 .nway_reset = ixgbevf_nway_reset,
720 .get_link = ethtool_op_get_link,
721 .get_ringparam = ixgbevf_get_ringparam,
722 .set_ringparam = ixgbevf_set_ringparam,
723 .get_rx_csum = ixgbevf_get_rx_csum,
724 .set_rx_csum = ixgbevf_set_rx_csum,
725 .get_tx_csum = ethtool_op_get_tx_csum,
726 .set_tx_csum = ethtool_op_set_tx_ipv6_csum,
727 .get_sg = ethtool_op_get_sg,
728 .set_sg = ethtool_op_set_sg,
729 .get_msglevel = ixgbevf_get_msglevel,
730 .set_msglevel = ixgbevf_set_msglevel,
731 .get_tso = ethtool_op_get_tso,
732 .set_tso = ixgbevf_set_tso,
733 .self_test = ixgbevf_diag_test,
734 .get_sset_count = ixgbevf_get_sset_count,
735 .get_strings = ixgbevf_get_strings,
736 .get_ethtool_stats = ixgbevf_get_ethtool_stats,
737};
738
739void ixgbevf_set_ethtool_ops(struct net_device *netdev)
740{
741 SET_ETHTOOL_OPS(netdev, &ixgbevf_ethtool_ops);
742}
diff --git a/drivers/net/ixgbevf/ixgbevf.h b/drivers/net/ixgbevf/ixgbevf.h
new file mode 100644
index 00000000000..8857df4dd3b
--- /dev/null
+++ b/drivers/net/ixgbevf/ixgbevf.h
@@ -0,0 +1,318 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBEVF_H_
29#define _IXGBEVF_H_
30
31#include <linux/types.h>
32#include <linux/bitops.h>
33#include <linux/timer.h>
34#include <linux/io.h>
35#include <linux/netdevice.h>
36#include <linux/if_vlan.h>
37
38#include "vf.h"
39
40/* wrapper around a pointer to a socket buffer,
41 * so a DMA handle can be stored along with the buffer */
42struct ixgbevf_tx_buffer {
43 struct sk_buff *skb;
44 dma_addr_t dma;
45 unsigned long time_stamp;
46 u16 length;
47 u16 next_to_watch;
48 u16 mapped_as_page;
49};
50
51struct ixgbevf_rx_buffer {
52 struct sk_buff *skb;
53 dma_addr_t dma;
54 struct page *page;
55 dma_addr_t page_dma;
56 unsigned int page_offset;
57};
58
59struct ixgbevf_ring {
60 struct ixgbevf_adapter *adapter; /* backlink */
61 void *desc; /* descriptor ring memory */
62 dma_addr_t dma; /* phys. address of descriptor ring */
63 unsigned int size; /* length in bytes */
64 unsigned int count; /* amount of descriptors */
65 unsigned int next_to_use;
66 unsigned int next_to_clean;
67
68 int queue_index; /* needed for multiqueue queue management */
69 union {
70 struct ixgbevf_tx_buffer *tx_buffer_info;
71 struct ixgbevf_rx_buffer *rx_buffer_info;
72 };
73
74 u16 head;
75 u16 tail;
76
77 unsigned int total_bytes;
78 unsigned int total_packets;
79
80 u16 reg_idx; /* holds the special value that gets the hardware register
81 * offset associated with this ring, which is different
82 * for DCB and RSS modes */
83
84#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
85 /* cpu for tx queue */
86 int cpu;
87#endif
88
89 u64 v_idx; /* maps directly to the index for this ring in the hardware
90 * vector array, can also be used for finding the bit in EICR
91 * and friends that represents the vector for this ring */
92
93 u16 work_limit; /* max work per interrupt */
94 u16 rx_buf_len;
95};
96
97enum ixgbevf_ring_f_enum {
98 RING_F_NONE = 0,
99 RING_F_ARRAY_SIZE /* must be last in enum set */
100};
101
102struct ixgbevf_ring_feature {
103 int indices;
104 int mask;
105};
106
107/* How many Rx Buffers do we bundle into one write to the hardware ? */
108#define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
109
110#define MAX_RX_QUEUES 1
111#define MAX_TX_QUEUES 1
112
113#define IXGBEVF_DEFAULT_TXD 1024
114#define IXGBEVF_DEFAULT_RXD 512
115#define IXGBEVF_MAX_TXD 4096
116#define IXGBEVF_MIN_TXD 64
117#define IXGBEVF_MAX_RXD 4096
118#define IXGBEVF_MIN_RXD 64
119
120/* Supported Rx Buffer Sizes */
121#define IXGBEVF_RXBUFFER_64 64 /* Used for packet split */
122#define IXGBEVF_RXBUFFER_128 128 /* Used for packet split */
123#define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */
124#define IXGBEVF_RXBUFFER_2048 2048
125#define IXGBEVF_MAX_RXBUFFER 16384 /* largest size for single descriptor */
126
127#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
128
129#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
130
131#define IXGBE_TX_FLAGS_CSUM (u32)(1)
132#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
133#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
134#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
135#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
136#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
137#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
138#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
139#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
140
141/* MAX_MSIX_Q_VECTORS of these are allocated,
142 * but we only use one per queue-specific vector.
143 */
144struct ixgbevf_q_vector {
145 struct ixgbevf_adapter *adapter;
146 struct napi_struct napi;
147 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
148 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
149 u8 rxr_count; /* Rx ring count assigned to this vector */
150 u8 txr_count; /* Tx ring count assigned to this vector */
151 u8 tx_itr;
152 u8 rx_itr;
153 u32 eitr;
154 int v_idx; /* vector index in list */
155};
156
157/* Helper macros to switch between ints/sec and what the register uses.
158 * And yes, it's the same math going both ways. The lowest value
159 * supported by all of the ixgbe hardware is 8.
160 */
161#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
162 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
163#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
164
165#define IXGBE_DESC_UNUSED(R) \
166 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
167 (R)->next_to_clean - (R)->next_to_use - 1)
168
169#define IXGBE_RX_DESC_ADV(R, i) \
170 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
171#define IXGBE_TX_DESC_ADV(R, i) \
172 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
173#define IXGBE_TX_CTXTDESC_ADV(R, i) \
174 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
175
176#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
177
178#define OTHER_VECTOR 1
179#define NON_Q_VECTORS (OTHER_VECTOR)
180
181#define MAX_MSIX_Q_VECTORS 2
182#define MAX_MSIX_COUNT 2
183
184#define MIN_MSIX_Q_VECTORS 2
185#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
186
187/* board specific private data structure */
188struct ixgbevf_adapter {
189 struct timer_list watchdog_timer;
190 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
191 u16 bd_number;
192 struct work_struct reset_task;
193 struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
194 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
195
196 /* Interrupt Throttle Rate */
197 u32 itr_setting;
198 u16 eitr_low;
199 u16 eitr_high;
200
201 /* TX */
202 struct ixgbevf_ring *tx_ring; /* One per active queue */
203 int num_tx_queues;
204 u64 restart_queue;
205 u64 hw_csum_tx_good;
206 u64 lsc_int;
207 u64 hw_tso_ctxt;
208 u64 hw_tso6_ctxt;
209 u32 tx_timeout_count;
210
211 /* RX */
212 struct ixgbevf_ring *rx_ring; /* One per active queue */
213 int num_rx_queues;
214 int num_rx_pools; /* == num_rx_queues in 82598 */
215 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
216 u64 hw_csum_rx_error;
217 u64 hw_rx_no_dma_resources;
218 u64 hw_csum_rx_good;
219 u64 non_eop_descs;
220 int num_msix_vectors;
221 int max_msix_q_vectors; /* true count of q_vectors for device */
222 struct ixgbevf_ring_feature ring_feature[RING_F_ARRAY_SIZE];
223 struct msix_entry *msix_entries;
224
225 u64 rx_hdr_split;
226 u32 alloc_rx_page_failed;
227 u32 alloc_rx_buff_failed;
228
229 /* Some features need tri-state capability,
230 * thus the additional *_CAPABLE flags.
231 */
232 u32 flags;
233#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
234#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 1)
235#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 2)
236#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 3)
237#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 4)
238#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 5)
239#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 6)
240#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 7)
241#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 8)
242 /* OS defined structs */
243 struct net_device *netdev;
244 struct pci_dev *pdev;
245
246 /* structs defined in ixgbe_vf.h */
247 struct ixgbe_hw hw;
248 u16 msg_enable;
249 struct ixgbevf_hw_stats stats;
250 u64 zero_base;
251 /* Interrupt Throttle Rate */
252 u32 eitr_param;
253
254 unsigned long state;
255 u32 *config_space;
256 u64 tx_busy;
257 unsigned int tx_ring_count;
258 unsigned int rx_ring_count;
259
260 u32 link_speed;
261 bool link_up;
262 unsigned long link_check_timeout;
263
264 struct work_struct watchdog_task;
265 bool netdev_registered;
266 bool dev_closed;
267};
268
269enum ixbgevf_state_t {
270 __IXGBEVF_TESTING,
271 __IXGBEVF_RESETTING,
272 __IXGBEVF_DOWN
273};
274
275enum ixgbevf_boards {
276 board_82599_vf,
277 board_X540_vf,
278};
279
280extern struct ixgbevf_info ixgbevf_82599_vf_info;
281extern struct ixgbevf_info ixgbevf_X540_vf_info;
282extern struct ixgbe_mbx_operations ixgbevf_mbx_ops;
283
284/* needed by ethtool.c */
285extern char ixgbevf_driver_name[];
286extern const char ixgbevf_driver_version[];
287
288extern int ixgbevf_up(struct ixgbevf_adapter *adapter);
289extern void ixgbevf_down(struct ixgbevf_adapter *adapter);
290extern void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
291extern void ixgbevf_reset(struct ixgbevf_adapter *adapter);
292extern void ixgbevf_set_ethtool_ops(struct net_device *netdev);
293extern int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *,
294 struct ixgbevf_ring *);
295extern int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *,
296 struct ixgbevf_ring *);
297extern void ixgbevf_free_rx_resources(struct ixgbevf_adapter *,
298 struct ixgbevf_ring *);
299extern void ixgbevf_free_tx_resources(struct ixgbevf_adapter *,
300 struct ixgbevf_ring *);
301extern void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
302
303#ifdef ETHTOOL_OPS_COMPAT
304extern int ethtool_ioctl(struct ifreq *ifr);
305
306#endif
307extern void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
308extern void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);
309
310#ifdef DEBUG
311extern char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw);
312#define hw_dbg(hw, format, arg...) \
313 printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg)
314#else
315#define hw_dbg(hw, format, arg...) do {} while (0)
316#endif
317
318#endif /* _IXGBEVF_H_ */
diff --git a/drivers/net/ixgbevf/ixgbevf_main.c b/drivers/net/ixgbevf/ixgbevf_main.c
new file mode 100644
index 00000000000..3b880a27f8d
--- /dev/null
+++ b/drivers/net/ixgbevf/ixgbevf_main.c
@@ -0,0 +1,3523 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/******************************************************************************
30 Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code
31******************************************************************************/
32#include <linux/types.h>
33#include <linux/bitops.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/vmalloc.h>
38#include <linux/string.h>
39#include <linux/in.h>
40#include <linux/ip.h>
41#include <linux/tcp.h>
42#include <linux/ipv6.h>
43#include <linux/slab.h>
44#include <net/checksum.h>
45#include <net/ip6_checksum.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/prefetch.h>
49
50#include "ixgbevf.h"
51
52char ixgbevf_driver_name[] = "ixgbevf";
53static const char ixgbevf_driver_string[] =
54 "Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver";
55
56#define DRV_VERSION "2.1.0-k"
57const char ixgbevf_driver_version[] = DRV_VERSION;
58static char ixgbevf_copyright[] =
59 "Copyright (c) 2009 - 2010 Intel Corporation.";
60
61static const struct ixgbevf_info *ixgbevf_info_tbl[] = {
62 [board_82599_vf] = &ixgbevf_82599_vf_info,
63 [board_X540_vf] = &ixgbevf_X540_vf_info,
64};
65
66/* ixgbevf_pci_tbl - PCI Device ID Table
67 *
68 * Wildcard entries (PCI_ANY_ID) should come last
69 * Last entry must be all 0s
70 *
71 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
72 * Class, Class Mask, private data (not used) }
73 */
74static struct pci_device_id ixgbevf_pci_tbl[] = {
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_VF),
76 board_82599_vf},
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540_VF),
78 board_X540_vf},
79
80 /* required last entry */
81 {0, }
82};
83MODULE_DEVICE_TABLE(pci, ixgbevf_pci_tbl);
84
85MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
86MODULE_DESCRIPTION("Intel(R) 82599 Virtual Function Driver");
87MODULE_LICENSE("GPL");
88MODULE_VERSION(DRV_VERSION);
89
90#define DEFAULT_DEBUG_LEVEL_SHIFT 3
91
92/* forward decls */
93static void ixgbevf_set_itr_msix(struct ixgbevf_q_vector *q_vector);
94static void ixgbevf_write_eitr(struct ixgbevf_adapter *adapter, int v_idx,
95 u32 itr_reg);
96
97static inline void ixgbevf_release_rx_desc(struct ixgbe_hw *hw,
98 struct ixgbevf_ring *rx_ring,
99 u32 val)
100{
101 /*
102 * Force memory writes to complete before letting h/w
103 * know there are new descriptors to fetch. (Only
104 * applicable for weak-ordered memory model archs,
105 * such as IA-64).
106 */
107 wmb();
108 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rx_ring->reg_idx), val);
109}
110
111/*
112 * ixgbevf_set_ivar - set IVAR registers - maps interrupt causes to vectors
113 * @adapter: pointer to adapter struct
114 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
115 * @queue: queue to map the corresponding interrupt to
116 * @msix_vector: the vector to map to the corresponding queue
117 *
118 */
119static void ixgbevf_set_ivar(struct ixgbevf_adapter *adapter, s8 direction,
120 u8 queue, u8 msix_vector)
121{
122 u32 ivar, index;
123 struct ixgbe_hw *hw = &adapter->hw;
124 if (direction == -1) {
125 /* other causes */
126 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
127 ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
128 ivar &= ~0xFF;
129 ivar |= msix_vector;
130 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, ivar);
131 } else {
132 /* tx or rx causes */
133 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
134 index = ((16 * (queue & 1)) + (8 * direction));
135 ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
136 ivar &= ~(0xFF << index);
137 ivar |= (msix_vector << index);
138 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), ivar);
139 }
140}
141
142static void ixgbevf_unmap_and_free_tx_resource(struct ixgbevf_adapter *adapter,
143 struct ixgbevf_tx_buffer
144 *tx_buffer_info)
145{
146 if (tx_buffer_info->dma) {
147 if (tx_buffer_info->mapped_as_page)
148 dma_unmap_page(&adapter->pdev->dev,
149 tx_buffer_info->dma,
150 tx_buffer_info->length,
151 DMA_TO_DEVICE);
152 else
153 dma_unmap_single(&adapter->pdev->dev,
154 tx_buffer_info->dma,
155 tx_buffer_info->length,
156 DMA_TO_DEVICE);
157 tx_buffer_info->dma = 0;
158 }
159 if (tx_buffer_info->skb) {
160 dev_kfree_skb_any(tx_buffer_info->skb);
161 tx_buffer_info->skb = NULL;
162 }
163 tx_buffer_info->time_stamp = 0;
164 /* tx_buffer_info must be completely set up in the transmit path */
165}
166
167#define IXGBE_MAX_TXD_PWR 14
168#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
169
170/* Tx Descriptors needed, worst case */
171#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
172 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
173#ifdef MAX_SKB_FRAGS
174#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
175 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
176#else
177#define DESC_NEEDED TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD)
178#endif
179
180static void ixgbevf_tx_timeout(struct net_device *netdev);
181
182/**
183 * ixgbevf_clean_tx_irq - Reclaim resources after transmit completes
184 * @adapter: board private structure
185 * @tx_ring: tx ring to clean
186 **/
187static bool ixgbevf_clean_tx_irq(struct ixgbevf_adapter *adapter,
188 struct ixgbevf_ring *tx_ring)
189{
190 struct net_device *netdev = adapter->netdev;
191 struct ixgbe_hw *hw = &adapter->hw;
192 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
193 struct ixgbevf_tx_buffer *tx_buffer_info;
194 unsigned int i, eop, count = 0;
195 unsigned int total_bytes = 0, total_packets = 0;
196
197 i = tx_ring->next_to_clean;
198 eop = tx_ring->tx_buffer_info[i].next_to_watch;
199 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
200
201 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
202 (count < tx_ring->work_limit)) {
203 bool cleaned = false;
204 rmb(); /* read buffer_info after eop_desc */
205 for ( ; !cleaned; count++) {
206 struct sk_buff *skb;
207 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
208 tx_buffer_info = &tx_ring->tx_buffer_info[i];
209 cleaned = (i == eop);
210 skb = tx_buffer_info->skb;
211
212 if (cleaned && skb) {
213 unsigned int segs, bytecount;
214
215 /* gso_segs is currently only valid for tcp */
216 segs = skb_shinfo(skb)->gso_segs ?: 1;
217 /* multiply data chunks by size of headers */
218 bytecount = ((segs - 1) * skb_headlen(skb)) +
219 skb->len;
220 total_packets += segs;
221 total_bytes += bytecount;
222 }
223
224 ixgbevf_unmap_and_free_tx_resource(adapter,
225 tx_buffer_info);
226
227 tx_desc->wb.status = 0;
228
229 i++;
230 if (i == tx_ring->count)
231 i = 0;
232 }
233
234 eop = tx_ring->tx_buffer_info[i].next_to_watch;
235 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
236 }
237
238 tx_ring->next_to_clean = i;
239
240#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
241 if (unlikely(count && netif_carrier_ok(netdev) &&
242 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
243 /* Make sure that anybody stopping the queue after this
244 * sees the new next_to_clean.
245 */
246 smp_mb();
247#ifdef HAVE_TX_MQ
248 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
249 !test_bit(__IXGBEVF_DOWN, &adapter->state)) {
250 netif_wake_subqueue(netdev, tx_ring->queue_index);
251 ++adapter->restart_queue;
252 }
253#else
254 if (netif_queue_stopped(netdev) &&
255 !test_bit(__IXGBEVF_DOWN, &adapter->state)) {
256 netif_wake_queue(netdev);
257 ++adapter->restart_queue;
258 }
259#endif
260 }
261
262 /* re-arm the interrupt */
263 if ((count >= tx_ring->work_limit) &&
264 (!test_bit(__IXGBEVF_DOWN, &adapter->state))) {
265 IXGBE_WRITE_REG(hw, IXGBE_VTEICS, tx_ring->v_idx);
266 }
267
268 tx_ring->total_bytes += total_bytes;
269 tx_ring->total_packets += total_packets;
270
271 netdev->stats.tx_bytes += total_bytes;
272 netdev->stats.tx_packets += total_packets;
273
274 return count < tx_ring->work_limit;
275}
276
277/**
278 * ixgbevf_receive_skb - Send a completed packet up the stack
279 * @q_vector: structure containing interrupt and ring information
280 * @skb: packet to send up
281 * @status: hardware indication of status of receive
282 * @rx_ring: rx descriptor ring (for a specific queue) to setup
283 * @rx_desc: rx descriptor
284 **/
285static void ixgbevf_receive_skb(struct ixgbevf_q_vector *q_vector,
286 struct sk_buff *skb, u8 status,
287 struct ixgbevf_ring *ring,
288 union ixgbe_adv_rx_desc *rx_desc)
289{
290 struct ixgbevf_adapter *adapter = q_vector->adapter;
291 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
292
293 if (is_vlan) {
294 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
295
296 __vlan_hwaccel_put_tag(skb, tag);
297 }
298
299 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
300 napi_gro_receive(&q_vector->napi, skb);
301 else
302 netif_rx(skb);
303}
304
305/**
306 * ixgbevf_rx_checksum - indicate in skb if hw indicated a good cksum
307 * @adapter: address of board private structure
308 * @status_err: hardware indication of status of receive
309 * @skb: skb currently being received and modified
310 **/
311static inline void ixgbevf_rx_checksum(struct ixgbevf_adapter *adapter,
312 u32 status_err, struct sk_buff *skb)
313{
314 skb_checksum_none_assert(skb);
315
316 /* Rx csum disabled */
317 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
318 return;
319
320 /* if IP and error */
321 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
322 (status_err & IXGBE_RXDADV_ERR_IPE)) {
323 adapter->hw_csum_rx_error++;
324 return;
325 }
326
327 if (!(status_err & IXGBE_RXD_STAT_L4CS))
328 return;
329
330 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
331 adapter->hw_csum_rx_error++;
332 return;
333 }
334
335 /* It must be a TCP or UDP packet with a valid checksum */
336 skb->ip_summed = CHECKSUM_UNNECESSARY;
337 adapter->hw_csum_rx_good++;
338}
339
340/**
341 * ixgbevf_alloc_rx_buffers - Replace used receive buffers; packet split
342 * @adapter: address of board private structure
343 **/
344static void ixgbevf_alloc_rx_buffers(struct ixgbevf_adapter *adapter,
345 struct ixgbevf_ring *rx_ring,
346 int cleaned_count)
347{
348 struct pci_dev *pdev = adapter->pdev;
349 union ixgbe_adv_rx_desc *rx_desc;
350 struct ixgbevf_rx_buffer *bi;
351 struct sk_buff *skb;
352 unsigned int i;
353 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
354
355 i = rx_ring->next_to_use;
356 bi = &rx_ring->rx_buffer_info[i];
357
358 while (cleaned_count--) {
359 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
360
361 if (!bi->page_dma &&
362 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
363 if (!bi->page) {
364 bi->page = netdev_alloc_page(adapter->netdev);
365 if (!bi->page) {
366 adapter->alloc_rx_page_failed++;
367 goto no_buffers;
368 }
369 bi->page_offset = 0;
370 } else {
371 /* use a half page if we're re-using */
372 bi->page_offset ^= (PAGE_SIZE / 2);
373 }
374
375 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
376 bi->page_offset,
377 (PAGE_SIZE / 2),
378 DMA_FROM_DEVICE);
379 }
380
381 skb = bi->skb;
382 if (!skb) {
383 skb = netdev_alloc_skb(adapter->netdev,
384 bufsz);
385
386 if (!skb) {
387 adapter->alloc_rx_buff_failed++;
388 goto no_buffers;
389 }
390
391 /*
392 * Make buffer alignment 2 beyond a 16 byte boundary
393 * this will result in a 16 byte aligned IP header after
394 * the 14 byte MAC header is removed
395 */
396 skb_reserve(skb, NET_IP_ALIGN);
397
398 bi->skb = skb;
399 }
400 if (!bi->dma) {
401 bi->dma = dma_map_single(&pdev->dev, skb->data,
402 rx_ring->rx_buf_len,
403 DMA_FROM_DEVICE);
404 }
405 /* Refresh the desc even if buffer_addrs didn't change because
406 * each write-back erases this info. */
407 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
408 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
409 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
410 } else {
411 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
412 }
413
414 i++;
415 if (i == rx_ring->count)
416 i = 0;
417 bi = &rx_ring->rx_buffer_info[i];
418 }
419
420no_buffers:
421 if (rx_ring->next_to_use != i) {
422 rx_ring->next_to_use = i;
423 if (i-- == 0)
424 i = (rx_ring->count - 1);
425
426 ixgbevf_release_rx_desc(&adapter->hw, rx_ring, i);
427 }
428}
429
430static inline void ixgbevf_irq_enable_queues(struct ixgbevf_adapter *adapter,
431 u64 qmask)
432{
433 u32 mask;
434 struct ixgbe_hw *hw = &adapter->hw;
435
436 mask = (qmask & 0xFFFFFFFF);
437 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
438}
439
440static inline u16 ixgbevf_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
441{
442 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
443}
444
445static inline u16 ixgbevf_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
446{
447 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
448}
449
450static bool ixgbevf_clean_rx_irq(struct ixgbevf_q_vector *q_vector,
451 struct ixgbevf_ring *rx_ring,
452 int *work_done, int work_to_do)
453{
454 struct ixgbevf_adapter *adapter = q_vector->adapter;
455 struct pci_dev *pdev = adapter->pdev;
456 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
457 struct ixgbevf_rx_buffer *rx_buffer_info, *next_buffer;
458 struct sk_buff *skb;
459 unsigned int i;
460 u32 len, staterr;
461 u16 hdr_info;
462 bool cleaned = false;
463 int cleaned_count = 0;
464 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
465
466 i = rx_ring->next_to_clean;
467 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
468 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
469 rx_buffer_info = &rx_ring->rx_buffer_info[i];
470
471 while (staterr & IXGBE_RXD_STAT_DD) {
472 u32 upper_len = 0;
473 if (*work_done >= work_to_do)
474 break;
475 (*work_done)++;
476
477 rmb(); /* read descriptor and rx_buffer_info after status DD */
478 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
479 hdr_info = le16_to_cpu(ixgbevf_get_hdr_info(rx_desc));
480 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
481 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
482 if (hdr_info & IXGBE_RXDADV_SPH)
483 adapter->rx_hdr_split++;
484 if (len > IXGBEVF_RX_HDR_SIZE)
485 len = IXGBEVF_RX_HDR_SIZE;
486 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
487 } else {
488 len = le16_to_cpu(rx_desc->wb.upper.length);
489 }
490 cleaned = true;
491 skb = rx_buffer_info->skb;
492 prefetch(skb->data - NET_IP_ALIGN);
493 rx_buffer_info->skb = NULL;
494
495 if (rx_buffer_info->dma) {
496 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
497 rx_ring->rx_buf_len,
498 DMA_FROM_DEVICE);
499 rx_buffer_info->dma = 0;
500 skb_put(skb, len);
501 }
502
503 if (upper_len) {
504 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
505 PAGE_SIZE / 2, DMA_FROM_DEVICE);
506 rx_buffer_info->page_dma = 0;
507 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
508 rx_buffer_info->page,
509 rx_buffer_info->page_offset,
510 upper_len);
511
512 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
513 (page_count(rx_buffer_info->page) != 1))
514 rx_buffer_info->page = NULL;
515 else
516 get_page(rx_buffer_info->page);
517
518 skb->len += upper_len;
519 skb->data_len += upper_len;
520 skb->truesize += upper_len;
521 }
522
523 i++;
524 if (i == rx_ring->count)
525 i = 0;
526
527 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
528 prefetch(next_rxd);
529 cleaned_count++;
530
531 next_buffer = &rx_ring->rx_buffer_info[i];
532
533 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
534 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
535 rx_buffer_info->skb = next_buffer->skb;
536 rx_buffer_info->dma = next_buffer->dma;
537 next_buffer->skb = skb;
538 next_buffer->dma = 0;
539 } else {
540 skb->next = next_buffer->skb;
541 skb->next->prev = skb;
542 }
543 adapter->non_eop_descs++;
544 goto next_desc;
545 }
546
547 /* ERR_MASK will only have valid bits if EOP set */
548 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
549 dev_kfree_skb_irq(skb);
550 goto next_desc;
551 }
552
553 ixgbevf_rx_checksum(adapter, staterr, skb);
554
555 /* probably a little skewed due to removing CRC */
556 total_rx_bytes += skb->len;
557 total_rx_packets++;
558
559 /*
560 * Work around issue of some types of VM to VM loop back
561 * packets not getting split correctly
562 */
563 if (staterr & IXGBE_RXD_STAT_LB) {
564 u32 header_fixup_len = skb_headlen(skb);
565 if (header_fixup_len < 14)
566 skb_push(skb, header_fixup_len);
567 }
568 skb->protocol = eth_type_trans(skb, adapter->netdev);
569
570 ixgbevf_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
571
572next_desc:
573 rx_desc->wb.upper.status_error = 0;
574
575 /* return some buffers to hardware, one at a time is too slow */
576 if (cleaned_count >= IXGBEVF_RX_BUFFER_WRITE) {
577 ixgbevf_alloc_rx_buffers(adapter, rx_ring,
578 cleaned_count);
579 cleaned_count = 0;
580 }
581
582 /* use prefetched values */
583 rx_desc = next_rxd;
584 rx_buffer_info = &rx_ring->rx_buffer_info[i];
585
586 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
587 }
588
589 rx_ring->next_to_clean = i;
590 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
591
592 if (cleaned_count)
593 ixgbevf_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
594
595 rx_ring->total_packets += total_rx_packets;
596 rx_ring->total_bytes += total_rx_bytes;
597 adapter->netdev->stats.rx_bytes += total_rx_bytes;
598 adapter->netdev->stats.rx_packets += total_rx_packets;
599
600 return cleaned;
601}
602
603/**
604 * ixgbevf_clean_rxonly - msix (aka one shot) rx clean routine
605 * @napi: napi struct with our devices info in it
606 * @budget: amount of work driver is allowed to do this pass, in packets
607 *
608 * This function is optimized for cleaning one queue only on a single
609 * q_vector!!!
610 **/
611static int ixgbevf_clean_rxonly(struct napi_struct *napi, int budget)
612{
613 struct ixgbevf_q_vector *q_vector =
614 container_of(napi, struct ixgbevf_q_vector, napi);
615 struct ixgbevf_adapter *adapter = q_vector->adapter;
616 struct ixgbevf_ring *rx_ring = NULL;
617 int work_done = 0;
618 long r_idx;
619
620 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
621 rx_ring = &(adapter->rx_ring[r_idx]);
622
623 ixgbevf_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
624
625 /* If all Rx work done, exit the polling mode */
626 if (work_done < budget) {
627 napi_complete(napi);
628 if (adapter->itr_setting & 1)
629 ixgbevf_set_itr_msix(q_vector);
630 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
631 ixgbevf_irq_enable_queues(adapter, rx_ring->v_idx);
632 }
633
634 return work_done;
635}
636
637/**
638 * ixgbevf_clean_rxonly_many - msix (aka one shot) rx clean routine
639 * @napi: napi struct with our devices info in it
640 * @budget: amount of work driver is allowed to do this pass, in packets
641 *
642 * This function will clean more than one rx queue associated with a
643 * q_vector.
644 **/
645static int ixgbevf_clean_rxonly_many(struct napi_struct *napi, int budget)
646{
647 struct ixgbevf_q_vector *q_vector =
648 container_of(napi, struct ixgbevf_q_vector, napi);
649 struct ixgbevf_adapter *adapter = q_vector->adapter;
650 struct ixgbevf_ring *rx_ring = NULL;
651 int work_done = 0, i;
652 long r_idx;
653 u64 enable_mask = 0;
654
655 /* attempt to distribute budget to each queue fairly, but don't allow
656 * the budget to go below 1 because we'll exit polling */
657 budget /= (q_vector->rxr_count ?: 1);
658 budget = max(budget, 1);
659 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
660 for (i = 0; i < q_vector->rxr_count; i++) {
661 rx_ring = &(adapter->rx_ring[r_idx]);
662 ixgbevf_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
663 enable_mask |= rx_ring->v_idx;
664 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
665 r_idx + 1);
666 }
667
668#ifndef HAVE_NETDEV_NAPI_LIST
669 if (!netif_running(adapter->netdev))
670 work_done = 0;
671
672#endif
673 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
674 rx_ring = &(adapter->rx_ring[r_idx]);
675
676 /* If all Rx work done, exit the polling mode */
677 if (work_done < budget) {
678 napi_complete(napi);
679 if (adapter->itr_setting & 1)
680 ixgbevf_set_itr_msix(q_vector);
681 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
682 ixgbevf_irq_enable_queues(adapter, enable_mask);
683 }
684
685 return work_done;
686}
687
688
689/**
690 * ixgbevf_configure_msix - Configure MSI-X hardware
691 * @adapter: board private structure
692 *
693 * ixgbevf_configure_msix sets up the hardware to properly generate MSI-X
694 * interrupts.
695 **/
696static void ixgbevf_configure_msix(struct ixgbevf_adapter *adapter)
697{
698 struct ixgbevf_q_vector *q_vector;
699 struct ixgbe_hw *hw = &adapter->hw;
700 int i, j, q_vectors, v_idx, r_idx;
701 u32 mask;
702
703 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
704
705 /*
706 * Populate the IVAR table and set the ITR values to the
707 * corresponding register.
708 */
709 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
710 q_vector = adapter->q_vector[v_idx];
711 /* XXX for_each_set_bit(...) */
712 r_idx = find_first_bit(q_vector->rxr_idx,
713 adapter->num_rx_queues);
714
715 for (i = 0; i < q_vector->rxr_count; i++) {
716 j = adapter->rx_ring[r_idx].reg_idx;
717 ixgbevf_set_ivar(adapter, 0, j, v_idx);
718 r_idx = find_next_bit(q_vector->rxr_idx,
719 adapter->num_rx_queues,
720 r_idx + 1);
721 }
722 r_idx = find_first_bit(q_vector->txr_idx,
723 adapter->num_tx_queues);
724
725 for (i = 0; i < q_vector->txr_count; i++) {
726 j = adapter->tx_ring[r_idx].reg_idx;
727 ixgbevf_set_ivar(adapter, 1, j, v_idx);
728 r_idx = find_next_bit(q_vector->txr_idx,
729 adapter->num_tx_queues,
730 r_idx + 1);
731 }
732
733 /* if this is a tx only vector halve the interrupt rate */
734 if (q_vector->txr_count && !q_vector->rxr_count)
735 q_vector->eitr = (adapter->eitr_param >> 1);
736 else if (q_vector->rxr_count)
737 /* rx only */
738 q_vector->eitr = adapter->eitr_param;
739
740 ixgbevf_write_eitr(adapter, v_idx, q_vector->eitr);
741 }
742
743 ixgbevf_set_ivar(adapter, -1, 1, v_idx);
744
745 /* set up to autoclear timer, and the vectors */
746 mask = IXGBE_EIMS_ENABLE_MASK;
747 mask &= ~IXGBE_EIMS_OTHER;
748 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, mask);
749}
750
751enum latency_range {
752 lowest_latency = 0,
753 low_latency = 1,
754 bulk_latency = 2,
755 latency_invalid = 255
756};
757
758/**
759 * ixgbevf_update_itr - update the dynamic ITR value based on statistics
760 * @adapter: pointer to adapter
761 * @eitr: eitr setting (ints per sec) to give last timeslice
762 * @itr_setting: current throttle rate in ints/second
763 * @packets: the number of packets during this measurement interval
764 * @bytes: the number of bytes during this measurement interval
765 *
766 * Stores a new ITR value based on packets and byte
767 * counts during the last interrupt. The advantage of per interrupt
768 * computation is faster updates and more accurate ITR for the current
769 * traffic pattern. Constants in this function were computed
770 * based on theoretical maximum wire speed and thresholds were set based
771 * on testing data as well as attempting to minimize response time
772 * while increasing bulk throughput.
773 **/
774static u8 ixgbevf_update_itr(struct ixgbevf_adapter *adapter,
775 u32 eitr, u8 itr_setting,
776 int packets, int bytes)
777{
778 unsigned int retval = itr_setting;
779 u32 timepassed_us;
780 u64 bytes_perint;
781
782 if (packets == 0)
783 goto update_itr_done;
784
785
786 /* simple throttlerate management
787 * 0-20MB/s lowest (100000 ints/s)
788 * 20-100MB/s low (20000 ints/s)
789 * 100-1249MB/s bulk (8000 ints/s)
790 */
791 /* what was last interrupt timeslice? */
792 timepassed_us = 1000000/eitr;
793 bytes_perint = bytes / timepassed_us; /* bytes/usec */
794
795 switch (itr_setting) {
796 case lowest_latency:
797 if (bytes_perint > adapter->eitr_low)
798 retval = low_latency;
799 break;
800 case low_latency:
801 if (bytes_perint > adapter->eitr_high)
802 retval = bulk_latency;
803 else if (bytes_perint <= adapter->eitr_low)
804 retval = lowest_latency;
805 break;
806 case bulk_latency:
807 if (bytes_perint <= adapter->eitr_high)
808 retval = low_latency;
809 break;
810 }
811
812update_itr_done:
813 return retval;
814}
815
816/**
817 * ixgbevf_write_eitr - write VTEITR register in hardware specific way
818 * @adapter: pointer to adapter struct
819 * @v_idx: vector index into q_vector array
820 * @itr_reg: new value to be written in *register* format, not ints/s
821 *
822 * This function is made to be called by ethtool and by the driver
823 * when it needs to update VTEITR registers at runtime. Hardware
824 * specific quirks/differences are taken care of here.
825 */
826static void ixgbevf_write_eitr(struct ixgbevf_adapter *adapter, int v_idx,
827 u32 itr_reg)
828{
829 struct ixgbe_hw *hw = &adapter->hw;
830
831 itr_reg = EITR_INTS_PER_SEC_TO_REG(itr_reg);
832
833 /*
834 * set the WDIS bit to not clear the timer bits and cause an
835 * immediate assertion of the interrupt
836 */
837 itr_reg |= IXGBE_EITR_CNT_WDIS;
838
839 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(v_idx), itr_reg);
840}
841
842static void ixgbevf_set_itr_msix(struct ixgbevf_q_vector *q_vector)
843{
844 struct ixgbevf_adapter *adapter = q_vector->adapter;
845 u32 new_itr;
846 u8 current_itr, ret_itr;
847 int i, r_idx, v_idx = q_vector->v_idx;
848 struct ixgbevf_ring *rx_ring, *tx_ring;
849
850 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
851 for (i = 0; i < q_vector->txr_count; i++) {
852 tx_ring = &(adapter->tx_ring[r_idx]);
853 ret_itr = ixgbevf_update_itr(adapter, q_vector->eitr,
854 q_vector->tx_itr,
855 tx_ring->total_packets,
856 tx_ring->total_bytes);
857 /* if the result for this queue would decrease interrupt
858 * rate for this vector then use that result */
859 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
860 q_vector->tx_itr - 1 : ret_itr);
861 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
862 r_idx + 1);
863 }
864
865 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
866 for (i = 0; i < q_vector->rxr_count; i++) {
867 rx_ring = &(adapter->rx_ring[r_idx]);
868 ret_itr = ixgbevf_update_itr(adapter, q_vector->eitr,
869 q_vector->rx_itr,
870 rx_ring->total_packets,
871 rx_ring->total_bytes);
872 /* if the result for this queue would decrease interrupt
873 * rate for this vector then use that result */
874 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
875 q_vector->rx_itr - 1 : ret_itr);
876 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
877 r_idx + 1);
878 }
879
880 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
881
882 switch (current_itr) {
883 /* counts and packets in update_itr are dependent on these numbers */
884 case lowest_latency:
885 new_itr = 100000;
886 break;
887 case low_latency:
888 new_itr = 20000; /* aka hwitr = ~200 */
889 break;
890 case bulk_latency:
891 default:
892 new_itr = 8000;
893 break;
894 }
895
896 if (new_itr != q_vector->eitr) {
897 u32 itr_reg;
898
899 /* save the algorithm value here, not the smoothed one */
900 q_vector->eitr = new_itr;
901 /* do an exponential smoothing */
902 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
903 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
904 ixgbevf_write_eitr(adapter, v_idx, itr_reg);
905 }
906}
907
908static irqreturn_t ixgbevf_msix_mbx(int irq, void *data)
909{
910 struct net_device *netdev = data;
911 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
912 struct ixgbe_hw *hw = &adapter->hw;
913 u32 eicr;
914 u32 msg;
915
916 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICS);
917 IXGBE_WRITE_REG(hw, IXGBE_VTEICR, eicr);
918
919 if (!hw->mbx.ops.check_for_ack(hw)) {
920 /*
921 * checking for the ack clears the PFACK bit. Place
922 * it back in the v2p_mailbox cache so that anyone
923 * polling for an ack will not miss it. Also
924 * avoid the read below because the code to read
925 * the mailbox will also clear the ack bit. This was
926 * causing lost acks. Just cache the bit and exit
927 * the IRQ handler.
928 */
929 hw->mbx.v2p_mailbox |= IXGBE_VFMAILBOX_PFACK;
930 goto out;
931 }
932
933 /* Not an ack interrupt, go ahead and read the message */
934 hw->mbx.ops.read(hw, &msg, 1);
935
936 if ((msg & IXGBE_MBVFICR_VFREQ_MASK) == IXGBE_PF_CONTROL_MSG)
937 mod_timer(&adapter->watchdog_timer,
938 round_jiffies(jiffies + 1));
939
940out:
941 return IRQ_HANDLED;
942}
943
944static irqreturn_t ixgbevf_msix_clean_tx(int irq, void *data)
945{
946 struct ixgbevf_q_vector *q_vector = data;
947 struct ixgbevf_adapter *adapter = q_vector->adapter;
948 struct ixgbevf_ring *tx_ring;
949 int i, r_idx;
950
951 if (!q_vector->txr_count)
952 return IRQ_HANDLED;
953
954 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
955 for (i = 0; i < q_vector->txr_count; i++) {
956 tx_ring = &(adapter->tx_ring[r_idx]);
957 tx_ring->total_bytes = 0;
958 tx_ring->total_packets = 0;
959 ixgbevf_clean_tx_irq(adapter, tx_ring);
960 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
961 r_idx + 1);
962 }
963
964 if (adapter->itr_setting & 1)
965 ixgbevf_set_itr_msix(q_vector);
966
967 return IRQ_HANDLED;
968}
969
970/**
971 * ixgbevf_msix_clean_rx - single unshared vector rx clean (all queues)
972 * @irq: unused
973 * @data: pointer to our q_vector struct for this interrupt vector
974 **/
975static irqreturn_t ixgbevf_msix_clean_rx(int irq, void *data)
976{
977 struct ixgbevf_q_vector *q_vector = data;
978 struct ixgbevf_adapter *adapter = q_vector->adapter;
979 struct ixgbe_hw *hw = &adapter->hw;
980 struct ixgbevf_ring *rx_ring;
981 int r_idx;
982 int i;
983
984 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
985 for (i = 0; i < q_vector->rxr_count; i++) {
986 rx_ring = &(adapter->rx_ring[r_idx]);
987 rx_ring->total_bytes = 0;
988 rx_ring->total_packets = 0;
989 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
990 r_idx + 1);
991 }
992
993 if (!q_vector->rxr_count)
994 return IRQ_HANDLED;
995
996 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
997 rx_ring = &(adapter->rx_ring[r_idx]);
998 /* disable interrupts on this vector only */
999 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, rx_ring->v_idx);
1000 napi_schedule(&q_vector->napi);
1001
1002
1003 return IRQ_HANDLED;
1004}
1005
1006static irqreturn_t ixgbevf_msix_clean_many(int irq, void *data)
1007{
1008 ixgbevf_msix_clean_rx(irq, data);
1009 ixgbevf_msix_clean_tx(irq, data);
1010
1011 return IRQ_HANDLED;
1012}
1013
1014static inline void map_vector_to_rxq(struct ixgbevf_adapter *a, int v_idx,
1015 int r_idx)
1016{
1017 struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx];
1018
1019 set_bit(r_idx, q_vector->rxr_idx);
1020 q_vector->rxr_count++;
1021 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1022}
1023
1024static inline void map_vector_to_txq(struct ixgbevf_adapter *a, int v_idx,
1025 int t_idx)
1026{
1027 struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx];
1028
1029 set_bit(t_idx, q_vector->txr_idx);
1030 q_vector->txr_count++;
1031 a->tx_ring[t_idx].v_idx = 1 << v_idx;
1032}
1033
1034/**
1035 * ixgbevf_map_rings_to_vectors - Maps descriptor rings to vectors
1036 * @adapter: board private structure to initialize
1037 *
1038 * This function maps descriptor rings to the queue-specific vectors
1039 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1040 * one vector per ring/queue, but on a constrained vector budget, we
1041 * group the rings as "efficiently" as possible. You would add new
1042 * mapping configurations in here.
1043 **/
1044static int ixgbevf_map_rings_to_vectors(struct ixgbevf_adapter *adapter)
1045{
1046 int q_vectors;
1047 int v_start = 0;
1048 int rxr_idx = 0, txr_idx = 0;
1049 int rxr_remaining = adapter->num_rx_queues;
1050 int txr_remaining = adapter->num_tx_queues;
1051 int i, j;
1052 int rqpv, tqpv;
1053 int err = 0;
1054
1055 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1056
1057 /*
1058 * The ideal configuration...
1059 * We have enough vectors to map one per queue.
1060 */
1061 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1062 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1063 map_vector_to_rxq(adapter, v_start, rxr_idx);
1064
1065 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1066 map_vector_to_txq(adapter, v_start, txr_idx);
1067 goto out;
1068 }
1069
1070 /*
1071 * If we don't have enough vectors for a 1-to-1
1072 * mapping, we'll have to group them so there are
1073 * multiple queues per vector.
1074 */
1075 /* Re-adjusting *qpv takes care of the remainder. */
1076 for (i = v_start; i < q_vectors; i++) {
1077 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
1078 for (j = 0; j < rqpv; j++) {
1079 map_vector_to_rxq(adapter, i, rxr_idx);
1080 rxr_idx++;
1081 rxr_remaining--;
1082 }
1083 }
1084 for (i = v_start; i < q_vectors; i++) {
1085 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
1086 for (j = 0; j < tqpv; j++) {
1087 map_vector_to_txq(adapter, i, txr_idx);
1088 txr_idx++;
1089 txr_remaining--;
1090 }
1091 }
1092
1093out:
1094 return err;
1095}
1096
1097/**
1098 * ixgbevf_request_msix_irqs - Initialize MSI-X interrupts
1099 * @adapter: board private structure
1100 *
1101 * ixgbevf_request_msix_irqs allocates MSI-X vectors and requests
1102 * interrupts from the kernel.
1103 **/
1104static int ixgbevf_request_msix_irqs(struct ixgbevf_adapter *adapter)
1105{
1106 struct net_device *netdev = adapter->netdev;
1107 irqreturn_t (*handler)(int, void *);
1108 int i, vector, q_vectors, err;
1109 int ri = 0, ti = 0;
1110
1111 /* Decrement for Other and TCP Timer vectors */
1112 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1113
1114#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
1115 ? &ixgbevf_msix_clean_many : \
1116 (_v)->rxr_count ? &ixgbevf_msix_clean_rx : \
1117 (_v)->txr_count ? &ixgbevf_msix_clean_tx : \
1118 NULL)
1119 for (vector = 0; vector < q_vectors; vector++) {
1120 handler = SET_HANDLER(adapter->q_vector[vector]);
1121
1122 if (handler == &ixgbevf_msix_clean_rx) {
1123 sprintf(adapter->name[vector], "%s-%s-%d",
1124 netdev->name, "rx", ri++);
1125 } else if (handler == &ixgbevf_msix_clean_tx) {
1126 sprintf(adapter->name[vector], "%s-%s-%d",
1127 netdev->name, "tx", ti++);
1128 } else if (handler == &ixgbevf_msix_clean_many) {
1129 sprintf(adapter->name[vector], "%s-%s-%d",
1130 netdev->name, "TxRx", vector);
1131 } else {
1132 /* skip this unused q_vector */
1133 continue;
1134 }
1135 err = request_irq(adapter->msix_entries[vector].vector,
1136 handler, 0, adapter->name[vector],
1137 adapter->q_vector[vector]);
1138 if (err) {
1139 hw_dbg(&adapter->hw,
1140 "request_irq failed for MSIX interrupt "
1141 "Error: %d\n", err);
1142 goto free_queue_irqs;
1143 }
1144 }
1145
1146 sprintf(adapter->name[vector], "%s:mbx", netdev->name);
1147 err = request_irq(adapter->msix_entries[vector].vector,
1148 &ixgbevf_msix_mbx, 0, adapter->name[vector], netdev);
1149 if (err) {
1150 hw_dbg(&adapter->hw,
1151 "request_irq for msix_mbx failed: %d\n", err);
1152 goto free_queue_irqs;
1153 }
1154
1155 return 0;
1156
1157free_queue_irqs:
1158 for (i = vector - 1; i >= 0; i--)
1159 free_irq(adapter->msix_entries[--vector].vector,
1160 &(adapter->q_vector[i]));
1161 pci_disable_msix(adapter->pdev);
1162 kfree(adapter->msix_entries);
1163 adapter->msix_entries = NULL;
1164 return err;
1165}
1166
1167static inline void ixgbevf_reset_q_vectors(struct ixgbevf_adapter *adapter)
1168{
1169 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1170
1171 for (i = 0; i < q_vectors; i++) {
1172 struct ixgbevf_q_vector *q_vector = adapter->q_vector[i];
1173 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1174 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1175 q_vector->rxr_count = 0;
1176 q_vector->txr_count = 0;
1177 q_vector->eitr = adapter->eitr_param;
1178 }
1179}
1180
1181/**
1182 * ixgbevf_request_irq - initialize interrupts
1183 * @adapter: board private structure
1184 *
1185 * Attempts to configure interrupts using the best available
1186 * capabilities of the hardware and kernel.
1187 **/
1188static int ixgbevf_request_irq(struct ixgbevf_adapter *adapter)
1189{
1190 int err = 0;
1191
1192 err = ixgbevf_request_msix_irqs(adapter);
1193
1194 if (err)
1195 hw_dbg(&adapter->hw,
1196 "request_irq failed, Error %d\n", err);
1197
1198 return err;
1199}
1200
1201static void ixgbevf_free_irq(struct ixgbevf_adapter *adapter)
1202{
1203 struct net_device *netdev = adapter->netdev;
1204 int i, q_vectors;
1205
1206 q_vectors = adapter->num_msix_vectors;
1207
1208 i = q_vectors - 1;
1209
1210 free_irq(adapter->msix_entries[i].vector, netdev);
1211 i--;
1212
1213 for (; i >= 0; i--) {
1214 free_irq(adapter->msix_entries[i].vector,
1215 adapter->q_vector[i]);
1216 }
1217
1218 ixgbevf_reset_q_vectors(adapter);
1219}
1220
1221/**
1222 * ixgbevf_irq_disable - Mask off interrupt generation on the NIC
1223 * @adapter: board private structure
1224 **/
1225static inline void ixgbevf_irq_disable(struct ixgbevf_adapter *adapter)
1226{
1227 int i;
1228 struct ixgbe_hw *hw = &adapter->hw;
1229
1230 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, ~0);
1231
1232 IXGBE_WRITE_FLUSH(hw);
1233
1234 for (i = 0; i < adapter->num_msix_vectors; i++)
1235 synchronize_irq(adapter->msix_entries[i].vector);
1236}
1237
1238/**
1239 * ixgbevf_irq_enable - Enable default interrupt generation settings
1240 * @adapter: board private structure
1241 **/
1242static inline void ixgbevf_irq_enable(struct ixgbevf_adapter *adapter,
1243 bool queues, bool flush)
1244{
1245 struct ixgbe_hw *hw = &adapter->hw;
1246 u32 mask;
1247 u64 qmask;
1248
1249 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1250 qmask = ~0;
1251
1252 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
1253
1254 if (queues)
1255 ixgbevf_irq_enable_queues(adapter, qmask);
1256
1257 if (flush)
1258 IXGBE_WRITE_FLUSH(hw);
1259}
1260
1261/**
1262 * ixgbevf_configure_tx - Configure 82599 VF Transmit Unit after Reset
1263 * @adapter: board private structure
1264 *
1265 * Configure the Tx unit of the MAC after a reset.
1266 **/
1267static void ixgbevf_configure_tx(struct ixgbevf_adapter *adapter)
1268{
1269 u64 tdba;
1270 struct ixgbe_hw *hw = &adapter->hw;
1271 u32 i, j, tdlen, txctrl;
1272
1273 /* Setup the HW Tx Head and Tail descriptor pointers */
1274 for (i = 0; i < adapter->num_tx_queues; i++) {
1275 struct ixgbevf_ring *ring = &adapter->tx_ring[i];
1276 j = ring->reg_idx;
1277 tdba = ring->dma;
1278 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1279 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(j),
1280 (tdba & DMA_BIT_MASK(32)));
1281 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(j), (tdba >> 32));
1282 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(j), tdlen);
1283 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(j), 0);
1284 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(j), 0);
1285 adapter->tx_ring[i].head = IXGBE_VFTDH(j);
1286 adapter->tx_ring[i].tail = IXGBE_VFTDT(j);
1287 /* Disable Tx Head Writeback RO bit, since this hoses
1288 * bookkeeping if things aren't delivered in order.
1289 */
1290 txctrl = IXGBE_READ_REG(hw, IXGBE_VFDCA_TXCTRL(j));
1291 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1292 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(j), txctrl);
1293 }
1294}
1295
1296#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1297
1298static void ixgbevf_configure_srrctl(struct ixgbevf_adapter *adapter, int index)
1299{
1300 struct ixgbevf_ring *rx_ring;
1301 struct ixgbe_hw *hw = &adapter->hw;
1302 u32 srrctl;
1303
1304 rx_ring = &adapter->rx_ring[index];
1305
1306 srrctl = IXGBE_SRRCTL_DROP_EN;
1307
1308 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1309 u16 bufsz = IXGBEVF_RXBUFFER_2048;
1310 /* grow the amount we can receive on large page machines */
1311 if (bufsz < (PAGE_SIZE / 2))
1312 bufsz = (PAGE_SIZE / 2);
1313 /* cap the bufsz at our largest descriptor size */
1314 bufsz = min((u16)IXGBEVF_MAX_RXBUFFER, bufsz);
1315
1316 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1317 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1318 srrctl |= ((IXGBEVF_RX_HDR_SIZE <<
1319 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1320 IXGBE_SRRCTL_BSIZEHDR_MASK);
1321 } else {
1322 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1323
1324 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1325 srrctl |= IXGBEVF_RXBUFFER_2048 >>
1326 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1327 else
1328 srrctl |= rx_ring->rx_buf_len >>
1329 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1330 }
1331 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(index), srrctl);
1332}
1333
1334/**
1335 * ixgbevf_configure_rx - Configure 82599 VF Receive Unit after Reset
1336 * @adapter: board private structure
1337 *
1338 * Configure the Rx unit of the MAC after a reset.
1339 **/
1340static void ixgbevf_configure_rx(struct ixgbevf_adapter *adapter)
1341{
1342 u64 rdba;
1343 struct ixgbe_hw *hw = &adapter->hw;
1344 struct net_device *netdev = adapter->netdev;
1345 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1346 int i, j;
1347 u32 rdlen;
1348 int rx_buf_len;
1349
1350 /* Decide whether to use packet split mode or not */
1351 if (netdev->mtu > ETH_DATA_LEN) {
1352 if (adapter->flags & IXGBE_FLAG_RX_PS_CAPABLE)
1353 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1354 else
1355 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1356 } else {
1357 if (adapter->flags & IXGBE_FLAG_RX_1BUF_CAPABLE)
1358 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1359 else
1360 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1361 }
1362
1363 /* Set the RX buffer length according to the mode */
1364 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1365 /* PSRTYPE must be initialized in 82599 */
1366 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1367 IXGBE_PSRTYPE_UDPHDR |
1368 IXGBE_PSRTYPE_IPV4HDR |
1369 IXGBE_PSRTYPE_IPV6HDR |
1370 IXGBE_PSRTYPE_L2HDR;
1371 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
1372 rx_buf_len = IXGBEVF_RX_HDR_SIZE;
1373 } else {
1374 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
1375 if (netdev->mtu <= ETH_DATA_LEN)
1376 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1377 else
1378 rx_buf_len = ALIGN(max_frame, 1024);
1379 }
1380
1381 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1382 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1383 * the Base and Length of the Rx Descriptor Ring */
1384 for (i = 0; i < adapter->num_rx_queues; i++) {
1385 rdba = adapter->rx_ring[i].dma;
1386 j = adapter->rx_ring[i].reg_idx;
1387 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(j),
1388 (rdba & DMA_BIT_MASK(32)));
1389 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(j), (rdba >> 32));
1390 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(j), rdlen);
1391 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(j), 0);
1392 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(j), 0);
1393 adapter->rx_ring[i].head = IXGBE_VFRDH(j);
1394 adapter->rx_ring[i].tail = IXGBE_VFRDT(j);
1395 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1396
1397 ixgbevf_configure_srrctl(adapter, j);
1398 }
1399}
1400
1401static void ixgbevf_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1402{
1403 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1404 struct ixgbe_hw *hw = &adapter->hw;
1405
1406 /* add VID to filter table */
1407 if (hw->mac.ops.set_vfta)
1408 hw->mac.ops.set_vfta(hw, vid, 0, true);
1409 set_bit(vid, adapter->active_vlans);
1410}
1411
1412static void ixgbevf_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1413{
1414 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1415 struct ixgbe_hw *hw = &adapter->hw;
1416
1417 /* remove VID from filter table */
1418 if (hw->mac.ops.set_vfta)
1419 hw->mac.ops.set_vfta(hw, vid, 0, false);
1420 clear_bit(vid, adapter->active_vlans);
1421}
1422
1423static void ixgbevf_restore_vlan(struct ixgbevf_adapter *adapter)
1424{
1425 u16 vid;
1426
1427 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
1428 ixgbevf_vlan_rx_add_vid(adapter->netdev, vid);
1429}
1430
1431static int ixgbevf_write_uc_addr_list(struct net_device *netdev)
1432{
1433 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1434 struct ixgbe_hw *hw = &adapter->hw;
1435 int count = 0;
1436
1437 if ((netdev_uc_count(netdev)) > 10) {
1438 printk(KERN_ERR "Too many unicast filters - No Space\n");
1439 return -ENOSPC;
1440 }
1441
1442 if (!netdev_uc_empty(netdev)) {
1443 struct netdev_hw_addr *ha;
1444 netdev_for_each_uc_addr(ha, netdev) {
1445 hw->mac.ops.set_uc_addr(hw, ++count, ha->addr);
1446 udelay(200);
1447 }
1448 } else {
1449 /*
1450 * If the list is empty then send message to PF driver to
1451 * clear all macvlans on this VF.
1452 */
1453 hw->mac.ops.set_uc_addr(hw, 0, NULL);
1454 }
1455
1456 return count;
1457}
1458
1459/**
1460 * ixgbevf_set_rx_mode - Multicast set
1461 * @netdev: network interface device structure
1462 *
1463 * The set_rx_method entry point is called whenever the multicast address
1464 * list or the network interface flags are updated. This routine is
1465 * responsible for configuring the hardware for proper multicast mode.
1466 **/
1467static void ixgbevf_set_rx_mode(struct net_device *netdev)
1468{
1469 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1470 struct ixgbe_hw *hw = &adapter->hw;
1471
1472 /* reprogram multicast list */
1473 if (hw->mac.ops.update_mc_addr_list)
1474 hw->mac.ops.update_mc_addr_list(hw, netdev);
1475
1476 ixgbevf_write_uc_addr_list(netdev);
1477}
1478
1479static void ixgbevf_napi_enable_all(struct ixgbevf_adapter *adapter)
1480{
1481 int q_idx;
1482 struct ixgbevf_q_vector *q_vector;
1483 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1484
1485 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1486 struct napi_struct *napi;
1487 q_vector = adapter->q_vector[q_idx];
1488 if (!q_vector->rxr_count)
1489 continue;
1490 napi = &q_vector->napi;
1491 if (q_vector->rxr_count > 1)
1492 napi->poll = &ixgbevf_clean_rxonly_many;
1493
1494 napi_enable(napi);
1495 }
1496}
1497
1498static void ixgbevf_napi_disable_all(struct ixgbevf_adapter *adapter)
1499{
1500 int q_idx;
1501 struct ixgbevf_q_vector *q_vector;
1502 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1503
1504 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1505 q_vector = adapter->q_vector[q_idx];
1506 if (!q_vector->rxr_count)
1507 continue;
1508 napi_disable(&q_vector->napi);
1509 }
1510}
1511
1512static void ixgbevf_configure(struct ixgbevf_adapter *adapter)
1513{
1514 struct net_device *netdev = adapter->netdev;
1515 int i;
1516
1517 ixgbevf_set_rx_mode(netdev);
1518
1519 ixgbevf_restore_vlan(adapter);
1520
1521 ixgbevf_configure_tx(adapter);
1522 ixgbevf_configure_rx(adapter);
1523 for (i = 0; i < adapter->num_rx_queues; i++) {
1524 struct ixgbevf_ring *ring = &adapter->rx_ring[i];
1525 ixgbevf_alloc_rx_buffers(adapter, ring, ring->count);
1526 ring->next_to_use = ring->count - 1;
1527 writel(ring->next_to_use, adapter->hw.hw_addr + ring->tail);
1528 }
1529}
1530
1531#define IXGBE_MAX_RX_DESC_POLL 10
1532static inline void ixgbevf_rx_desc_queue_enable(struct ixgbevf_adapter *adapter,
1533 int rxr)
1534{
1535 struct ixgbe_hw *hw = &adapter->hw;
1536 int j = adapter->rx_ring[rxr].reg_idx;
1537 int k;
1538
1539 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
1540 if (IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1541 break;
1542 else
1543 msleep(1);
1544 }
1545 if (k >= IXGBE_MAX_RX_DESC_POLL) {
1546 hw_dbg(hw, "RXDCTL.ENABLE on Rx queue %d "
1547 "not set within the polling period\n", rxr);
1548 }
1549
1550 ixgbevf_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
1551 (adapter->rx_ring[rxr].count - 1));
1552}
1553
1554static void ixgbevf_save_reset_stats(struct ixgbevf_adapter *adapter)
1555{
1556 /* Only save pre-reset stats if there are some */
1557 if (adapter->stats.vfgprc || adapter->stats.vfgptc) {
1558 adapter->stats.saved_reset_vfgprc += adapter->stats.vfgprc -
1559 adapter->stats.base_vfgprc;
1560 adapter->stats.saved_reset_vfgptc += adapter->stats.vfgptc -
1561 adapter->stats.base_vfgptc;
1562 adapter->stats.saved_reset_vfgorc += adapter->stats.vfgorc -
1563 adapter->stats.base_vfgorc;
1564 adapter->stats.saved_reset_vfgotc += adapter->stats.vfgotc -
1565 adapter->stats.base_vfgotc;
1566 adapter->stats.saved_reset_vfmprc += adapter->stats.vfmprc -
1567 adapter->stats.base_vfmprc;
1568 }
1569}
1570
1571static void ixgbevf_init_last_counter_stats(struct ixgbevf_adapter *adapter)
1572{
1573 struct ixgbe_hw *hw = &adapter->hw;
1574
1575 adapter->stats.last_vfgprc = IXGBE_READ_REG(hw, IXGBE_VFGPRC);
1576 adapter->stats.last_vfgorc = IXGBE_READ_REG(hw, IXGBE_VFGORC_LSB);
1577 adapter->stats.last_vfgorc |=
1578 (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGORC_MSB))) << 32);
1579 adapter->stats.last_vfgptc = IXGBE_READ_REG(hw, IXGBE_VFGPTC);
1580 adapter->stats.last_vfgotc = IXGBE_READ_REG(hw, IXGBE_VFGOTC_LSB);
1581 adapter->stats.last_vfgotc |=
1582 (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGOTC_MSB))) << 32);
1583 adapter->stats.last_vfmprc = IXGBE_READ_REG(hw, IXGBE_VFMPRC);
1584
1585 adapter->stats.base_vfgprc = adapter->stats.last_vfgprc;
1586 adapter->stats.base_vfgorc = adapter->stats.last_vfgorc;
1587 adapter->stats.base_vfgptc = adapter->stats.last_vfgptc;
1588 adapter->stats.base_vfgotc = adapter->stats.last_vfgotc;
1589 adapter->stats.base_vfmprc = adapter->stats.last_vfmprc;
1590}
1591
1592static int ixgbevf_up_complete(struct ixgbevf_adapter *adapter)
1593{
1594 struct net_device *netdev = adapter->netdev;
1595 struct ixgbe_hw *hw = &adapter->hw;
1596 int i, j = 0;
1597 int num_rx_rings = adapter->num_rx_queues;
1598 u32 txdctl, rxdctl;
1599
1600 for (i = 0; i < adapter->num_tx_queues; i++) {
1601 j = adapter->tx_ring[i].reg_idx;
1602 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1603 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1604 txdctl |= (8 << 16);
1605 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
1606 }
1607
1608 for (i = 0; i < adapter->num_tx_queues; i++) {
1609 j = adapter->tx_ring[i].reg_idx;
1610 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1611 txdctl |= IXGBE_TXDCTL_ENABLE;
1612 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
1613 }
1614
1615 for (i = 0; i < num_rx_rings; i++) {
1616 j = adapter->rx_ring[i].reg_idx;
1617 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j));
1618 rxdctl |= IXGBE_RXDCTL_ENABLE | IXGBE_RXDCTL_VME;
1619 if (hw->mac.type == ixgbe_mac_X540_vf) {
1620 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
1621 rxdctl |= ((netdev->mtu + ETH_HLEN + ETH_FCS_LEN) |
1622 IXGBE_RXDCTL_RLPML_EN);
1623 }
1624 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(j), rxdctl);
1625 ixgbevf_rx_desc_queue_enable(adapter, i);
1626 }
1627
1628 ixgbevf_configure_msix(adapter);
1629
1630 if (hw->mac.ops.set_rar) {
1631 if (is_valid_ether_addr(hw->mac.addr))
1632 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0);
1633 else
1634 hw->mac.ops.set_rar(hw, 0, hw->mac.perm_addr, 0);
1635 }
1636
1637 clear_bit(__IXGBEVF_DOWN, &adapter->state);
1638 ixgbevf_napi_enable_all(adapter);
1639
1640 /* enable transmits */
1641 netif_tx_start_all_queues(netdev);
1642
1643 ixgbevf_save_reset_stats(adapter);
1644 ixgbevf_init_last_counter_stats(adapter);
1645
1646 /* bring the link up in the watchdog, this could race with our first
1647 * link up interrupt but shouldn't be a problem */
1648 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1649 adapter->link_check_timeout = jiffies;
1650 mod_timer(&adapter->watchdog_timer, jiffies);
1651 return 0;
1652}
1653
1654int ixgbevf_up(struct ixgbevf_adapter *adapter)
1655{
1656 int err;
1657 struct ixgbe_hw *hw = &adapter->hw;
1658
1659 ixgbevf_configure(adapter);
1660
1661 err = ixgbevf_up_complete(adapter);
1662
1663 /* clear any pending interrupts, may auto mask */
1664 IXGBE_READ_REG(hw, IXGBE_VTEICR);
1665
1666 ixgbevf_irq_enable(adapter, true, true);
1667
1668 return err;
1669}
1670
1671/**
1672 * ixgbevf_clean_rx_ring - Free Rx Buffers per Queue
1673 * @adapter: board private structure
1674 * @rx_ring: ring to free buffers from
1675 **/
1676static void ixgbevf_clean_rx_ring(struct ixgbevf_adapter *adapter,
1677 struct ixgbevf_ring *rx_ring)
1678{
1679 struct pci_dev *pdev = adapter->pdev;
1680 unsigned long size;
1681 unsigned int i;
1682
1683 if (!rx_ring->rx_buffer_info)
1684 return;
1685
1686 /* Free all the Rx ring sk_buffs */
1687 for (i = 0; i < rx_ring->count; i++) {
1688 struct ixgbevf_rx_buffer *rx_buffer_info;
1689
1690 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1691 if (rx_buffer_info->dma) {
1692 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
1693 rx_ring->rx_buf_len,
1694 DMA_FROM_DEVICE);
1695 rx_buffer_info->dma = 0;
1696 }
1697 if (rx_buffer_info->skb) {
1698 struct sk_buff *skb = rx_buffer_info->skb;
1699 rx_buffer_info->skb = NULL;
1700 do {
1701 struct sk_buff *this = skb;
1702 skb = skb->prev;
1703 dev_kfree_skb(this);
1704 } while (skb);
1705 }
1706 if (!rx_buffer_info->page)
1707 continue;
1708 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1709 PAGE_SIZE / 2, DMA_FROM_DEVICE);
1710 rx_buffer_info->page_dma = 0;
1711 put_page(rx_buffer_info->page);
1712 rx_buffer_info->page = NULL;
1713 rx_buffer_info->page_offset = 0;
1714 }
1715
1716 size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
1717 memset(rx_ring->rx_buffer_info, 0, size);
1718
1719 /* Zero out the descriptor ring */
1720 memset(rx_ring->desc, 0, rx_ring->size);
1721
1722 rx_ring->next_to_clean = 0;
1723 rx_ring->next_to_use = 0;
1724
1725 if (rx_ring->head)
1726 writel(0, adapter->hw.hw_addr + rx_ring->head);
1727 if (rx_ring->tail)
1728 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1729}
1730
1731/**
1732 * ixgbevf_clean_tx_ring - Free Tx Buffers
1733 * @adapter: board private structure
1734 * @tx_ring: ring to be cleaned
1735 **/
1736static void ixgbevf_clean_tx_ring(struct ixgbevf_adapter *adapter,
1737 struct ixgbevf_ring *tx_ring)
1738{
1739 struct ixgbevf_tx_buffer *tx_buffer_info;
1740 unsigned long size;
1741 unsigned int i;
1742
1743 if (!tx_ring->tx_buffer_info)
1744 return;
1745
1746 /* Free all the Tx ring sk_buffs */
1747
1748 for (i = 0; i < tx_ring->count; i++) {
1749 tx_buffer_info = &tx_ring->tx_buffer_info[i];
1750 ixgbevf_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1751 }
1752
1753 size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
1754 memset(tx_ring->tx_buffer_info, 0, size);
1755
1756 memset(tx_ring->desc, 0, tx_ring->size);
1757
1758 tx_ring->next_to_use = 0;
1759 tx_ring->next_to_clean = 0;
1760
1761 if (tx_ring->head)
1762 writel(0, adapter->hw.hw_addr + tx_ring->head);
1763 if (tx_ring->tail)
1764 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1765}
1766
1767/**
1768 * ixgbevf_clean_all_rx_rings - Free Rx Buffers for all queues
1769 * @adapter: board private structure
1770 **/
1771static void ixgbevf_clean_all_rx_rings(struct ixgbevf_adapter *adapter)
1772{
1773 int i;
1774
1775 for (i = 0; i < adapter->num_rx_queues; i++)
1776 ixgbevf_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1777}
1778
1779/**
1780 * ixgbevf_clean_all_tx_rings - Free Tx Buffers for all queues
1781 * @adapter: board private structure
1782 **/
1783static void ixgbevf_clean_all_tx_rings(struct ixgbevf_adapter *adapter)
1784{
1785 int i;
1786
1787 for (i = 0; i < adapter->num_tx_queues; i++)
1788 ixgbevf_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1789}
1790
1791void ixgbevf_down(struct ixgbevf_adapter *adapter)
1792{
1793 struct net_device *netdev = adapter->netdev;
1794 struct ixgbe_hw *hw = &adapter->hw;
1795 u32 txdctl;
1796 int i, j;
1797
1798 /* signal that we are down to the interrupt handler */
1799 set_bit(__IXGBEVF_DOWN, &adapter->state);
1800 /* disable receives */
1801
1802 netif_tx_disable(netdev);
1803
1804 msleep(10);
1805
1806 netif_tx_stop_all_queues(netdev);
1807
1808 ixgbevf_irq_disable(adapter);
1809
1810 ixgbevf_napi_disable_all(adapter);
1811
1812 del_timer_sync(&adapter->watchdog_timer);
1813 /* can't call flush scheduled work here because it can deadlock
1814 * if linkwatch_event tries to acquire the rtnl_lock which we are
1815 * holding */
1816 while (adapter->flags & IXGBE_FLAG_IN_WATCHDOG_TASK)
1817 msleep(1);
1818
1819 /* disable transmits in the hardware now that interrupts are off */
1820 for (i = 0; i < adapter->num_tx_queues; i++) {
1821 j = adapter->tx_ring[i].reg_idx;
1822 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1823 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j),
1824 (txdctl & ~IXGBE_TXDCTL_ENABLE));
1825 }
1826
1827 netif_carrier_off(netdev);
1828
1829 if (!pci_channel_offline(adapter->pdev))
1830 ixgbevf_reset(adapter);
1831
1832 ixgbevf_clean_all_tx_rings(adapter);
1833 ixgbevf_clean_all_rx_rings(adapter);
1834}
1835
1836void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter)
1837{
1838 struct ixgbe_hw *hw = &adapter->hw;
1839
1840 WARN_ON(in_interrupt());
1841
1842 while (test_and_set_bit(__IXGBEVF_RESETTING, &adapter->state))
1843 msleep(1);
1844
1845 /*
1846 * Check if PF is up before re-init. If not then skip until
1847 * later when the PF is up and ready to service requests from
1848 * the VF via mailbox. If the VF is up and running then the
1849 * watchdog task will continue to schedule reset tasks until
1850 * the PF is up and running.
1851 */
1852 if (!hw->mac.ops.reset_hw(hw)) {
1853 ixgbevf_down(adapter);
1854 ixgbevf_up(adapter);
1855 }
1856
1857 clear_bit(__IXGBEVF_RESETTING, &adapter->state);
1858}
1859
1860void ixgbevf_reset(struct ixgbevf_adapter *adapter)
1861{
1862 struct ixgbe_hw *hw = &adapter->hw;
1863 struct net_device *netdev = adapter->netdev;
1864
1865 if (hw->mac.ops.reset_hw(hw))
1866 hw_dbg(hw, "PF still resetting\n");
1867 else
1868 hw->mac.ops.init_hw(hw);
1869
1870 if (is_valid_ether_addr(adapter->hw.mac.addr)) {
1871 memcpy(netdev->dev_addr, adapter->hw.mac.addr,
1872 netdev->addr_len);
1873 memcpy(netdev->perm_addr, adapter->hw.mac.addr,
1874 netdev->addr_len);
1875 }
1876}
1877
1878static void ixgbevf_acquire_msix_vectors(struct ixgbevf_adapter *adapter,
1879 int vectors)
1880{
1881 int err, vector_threshold;
1882
1883 /* We'll want at least 3 (vector_threshold):
1884 * 1) TxQ[0] Cleanup
1885 * 2) RxQ[0] Cleanup
1886 * 3) Other (Link Status Change, etc.)
1887 */
1888 vector_threshold = MIN_MSIX_COUNT;
1889
1890 /* The more we get, the more we will assign to Tx/Rx Cleanup
1891 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
1892 * Right now, we simply care about how many we'll get; we'll
1893 * set them up later while requesting irq's.
1894 */
1895 while (vectors >= vector_threshold) {
1896 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1897 vectors);
1898 if (!err) /* Success in acquiring all requested vectors. */
1899 break;
1900 else if (err < 0)
1901 vectors = 0; /* Nasty failure, quit now */
1902 else /* err == number of vectors we should try again with */
1903 vectors = err;
1904 }
1905
1906 if (vectors < vector_threshold) {
1907 /* Can't allocate enough MSI-X interrupts? Oh well.
1908 * This just means we'll go with either a single MSI
1909 * vector or fall back to legacy interrupts.
1910 */
1911 hw_dbg(&adapter->hw,
1912 "Unable to allocate MSI-X interrupts\n");
1913 kfree(adapter->msix_entries);
1914 adapter->msix_entries = NULL;
1915 } else {
1916 /*
1917 * Adjust for only the vectors we'll use, which is minimum
1918 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
1919 * vectors we were allocated.
1920 */
1921 adapter->num_msix_vectors = vectors;
1922 }
1923}
1924
1925/*
1926 * ixgbevf_set_num_queues: Allocate queues for device, feature dependent
1927 * @adapter: board private structure to initialize
1928 *
1929 * This is the top level queue allocation routine. The order here is very
1930 * important, starting with the "most" number of features turned on at once,
1931 * and ending with the smallest set of features. This way large combinations
1932 * can be allocated if they're turned on, and smaller combinations are the
1933 * fallthrough conditions.
1934 *
1935 **/
1936static void ixgbevf_set_num_queues(struct ixgbevf_adapter *adapter)
1937{
1938 /* Start with base case */
1939 adapter->num_rx_queues = 1;
1940 adapter->num_tx_queues = 1;
1941 adapter->num_rx_pools = adapter->num_rx_queues;
1942 adapter->num_rx_queues_per_pool = 1;
1943}
1944
1945/**
1946 * ixgbevf_alloc_queues - Allocate memory for all rings
1947 * @adapter: board private structure to initialize
1948 *
1949 * We allocate one ring per queue at run-time since we don't know the
1950 * number of queues at compile-time. The polling_netdev array is
1951 * intended for Multiqueue, but should work fine with a single queue.
1952 **/
1953static int ixgbevf_alloc_queues(struct ixgbevf_adapter *adapter)
1954{
1955 int i;
1956
1957 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1958 sizeof(struct ixgbevf_ring), GFP_KERNEL);
1959 if (!adapter->tx_ring)
1960 goto err_tx_ring_allocation;
1961
1962 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1963 sizeof(struct ixgbevf_ring), GFP_KERNEL);
1964 if (!adapter->rx_ring)
1965 goto err_rx_ring_allocation;
1966
1967 for (i = 0; i < adapter->num_tx_queues; i++) {
1968 adapter->tx_ring[i].count = adapter->tx_ring_count;
1969 adapter->tx_ring[i].queue_index = i;
1970 adapter->tx_ring[i].reg_idx = i;
1971 }
1972
1973 for (i = 0; i < adapter->num_rx_queues; i++) {
1974 adapter->rx_ring[i].count = adapter->rx_ring_count;
1975 adapter->rx_ring[i].queue_index = i;
1976 adapter->rx_ring[i].reg_idx = i;
1977 }
1978
1979 return 0;
1980
1981err_rx_ring_allocation:
1982 kfree(adapter->tx_ring);
1983err_tx_ring_allocation:
1984 return -ENOMEM;
1985}
1986
1987/**
1988 * ixgbevf_set_interrupt_capability - set MSI-X or FAIL if not supported
1989 * @adapter: board private structure to initialize
1990 *
1991 * Attempt to configure the interrupts using the best available
1992 * capabilities of the hardware and the kernel.
1993 **/
1994static int ixgbevf_set_interrupt_capability(struct ixgbevf_adapter *adapter)
1995{
1996 int err = 0;
1997 int vector, v_budget;
1998
1999 /*
2000 * It's easy to be greedy for MSI-X vectors, but it really
2001 * doesn't do us much good if we have a lot more vectors
2002 * than CPU's. So let's be conservative and only ask for
2003 * (roughly) twice the number of vectors as there are CPU's.
2004 */
2005 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2006 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2007
2008 /* A failure in MSI-X entry allocation isn't fatal, but it does
2009 * mean we disable MSI-X capabilities of the adapter. */
2010 adapter->msix_entries = kcalloc(v_budget,
2011 sizeof(struct msix_entry), GFP_KERNEL);
2012 if (!adapter->msix_entries) {
2013 err = -ENOMEM;
2014 goto out;
2015 }
2016
2017 for (vector = 0; vector < v_budget; vector++)
2018 adapter->msix_entries[vector].entry = vector;
2019
2020 ixgbevf_acquire_msix_vectors(adapter, v_budget);
2021
2022out:
2023 return err;
2024}
2025
2026/**
2027 * ixgbevf_alloc_q_vectors - Allocate memory for interrupt vectors
2028 * @adapter: board private structure to initialize
2029 *
2030 * We allocate one q_vector per queue interrupt. If allocation fails we
2031 * return -ENOMEM.
2032 **/
2033static int ixgbevf_alloc_q_vectors(struct ixgbevf_adapter *adapter)
2034{
2035 int q_idx, num_q_vectors;
2036 struct ixgbevf_q_vector *q_vector;
2037 int napi_vectors;
2038 int (*poll)(struct napi_struct *, int);
2039
2040 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2041 napi_vectors = adapter->num_rx_queues;
2042 poll = &ixgbevf_clean_rxonly;
2043
2044 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
2045 q_vector = kzalloc(sizeof(struct ixgbevf_q_vector), GFP_KERNEL);
2046 if (!q_vector)
2047 goto err_out;
2048 q_vector->adapter = adapter;
2049 q_vector->v_idx = q_idx;
2050 q_vector->eitr = adapter->eitr_param;
2051 if (q_idx < napi_vectors)
2052 netif_napi_add(adapter->netdev, &q_vector->napi,
2053 (*poll), 64);
2054 adapter->q_vector[q_idx] = q_vector;
2055 }
2056
2057 return 0;
2058
2059err_out:
2060 while (q_idx) {
2061 q_idx--;
2062 q_vector = adapter->q_vector[q_idx];
2063 netif_napi_del(&q_vector->napi);
2064 kfree(q_vector);
2065 adapter->q_vector[q_idx] = NULL;
2066 }
2067 return -ENOMEM;
2068}
2069
2070/**
2071 * ixgbevf_free_q_vectors - Free memory allocated for interrupt vectors
2072 * @adapter: board private structure to initialize
2073 *
2074 * This function frees the memory allocated to the q_vectors. In addition if
2075 * NAPI is enabled it will delete any references to the NAPI struct prior
2076 * to freeing the q_vector.
2077 **/
2078static void ixgbevf_free_q_vectors(struct ixgbevf_adapter *adapter)
2079{
2080 int q_idx, num_q_vectors;
2081 int napi_vectors;
2082
2083 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2084 napi_vectors = adapter->num_rx_queues;
2085
2086 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
2087 struct ixgbevf_q_vector *q_vector = adapter->q_vector[q_idx];
2088
2089 adapter->q_vector[q_idx] = NULL;
2090 if (q_idx < napi_vectors)
2091 netif_napi_del(&q_vector->napi);
2092 kfree(q_vector);
2093 }
2094}
2095
2096/**
2097 * ixgbevf_reset_interrupt_capability - Reset MSIX setup
2098 * @adapter: board private structure
2099 *
2100 **/
2101static void ixgbevf_reset_interrupt_capability(struct ixgbevf_adapter *adapter)
2102{
2103 pci_disable_msix(adapter->pdev);
2104 kfree(adapter->msix_entries);
2105 adapter->msix_entries = NULL;
2106}
2107
2108/**
2109 * ixgbevf_init_interrupt_scheme - Determine if MSIX is supported and init
2110 * @adapter: board private structure to initialize
2111 *
2112 **/
2113static int ixgbevf_init_interrupt_scheme(struct ixgbevf_adapter *adapter)
2114{
2115 int err;
2116
2117 /* Number of supported queues */
2118 ixgbevf_set_num_queues(adapter);
2119
2120 err = ixgbevf_set_interrupt_capability(adapter);
2121 if (err) {
2122 hw_dbg(&adapter->hw,
2123 "Unable to setup interrupt capabilities\n");
2124 goto err_set_interrupt;
2125 }
2126
2127 err = ixgbevf_alloc_q_vectors(adapter);
2128 if (err) {
2129 hw_dbg(&adapter->hw, "Unable to allocate memory for queue "
2130 "vectors\n");
2131 goto err_alloc_q_vectors;
2132 }
2133
2134 err = ixgbevf_alloc_queues(adapter);
2135 if (err) {
2136 printk(KERN_ERR "Unable to allocate memory for queues\n");
2137 goto err_alloc_queues;
2138 }
2139
2140 hw_dbg(&adapter->hw, "Multiqueue %s: Rx Queue count = %u, "
2141 "Tx Queue count = %u\n",
2142 (adapter->num_rx_queues > 1) ? "Enabled" :
2143 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2144
2145 set_bit(__IXGBEVF_DOWN, &adapter->state);
2146
2147 return 0;
2148err_alloc_queues:
2149 ixgbevf_free_q_vectors(adapter);
2150err_alloc_q_vectors:
2151 ixgbevf_reset_interrupt_capability(adapter);
2152err_set_interrupt:
2153 return err;
2154}
2155
2156/**
2157 * ixgbevf_sw_init - Initialize general software structures
2158 * (struct ixgbevf_adapter)
2159 * @adapter: board private structure to initialize
2160 *
2161 * ixgbevf_sw_init initializes the Adapter private data structure.
2162 * Fields are initialized based on PCI device information and
2163 * OS network device settings (MTU size).
2164 **/
2165static int __devinit ixgbevf_sw_init(struct ixgbevf_adapter *adapter)
2166{
2167 struct ixgbe_hw *hw = &adapter->hw;
2168 struct pci_dev *pdev = adapter->pdev;
2169 int err;
2170
2171 /* PCI config space info */
2172
2173 hw->vendor_id = pdev->vendor;
2174 hw->device_id = pdev->device;
2175 hw->revision_id = pdev->revision;
2176 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2177 hw->subsystem_device_id = pdev->subsystem_device;
2178
2179 hw->mbx.ops.init_params(hw);
2180 hw->mac.max_tx_queues = MAX_TX_QUEUES;
2181 hw->mac.max_rx_queues = MAX_RX_QUEUES;
2182 err = hw->mac.ops.reset_hw(hw);
2183 if (err) {
2184 dev_info(&pdev->dev,
2185 "PF still in reset state, assigning new address\n");
2186 dev_hw_addr_random(adapter->netdev, hw->mac.addr);
2187 } else {
2188 err = hw->mac.ops.init_hw(hw);
2189 if (err) {
2190 printk(KERN_ERR "init_shared_code failed: %d\n", err);
2191 goto out;
2192 }
2193 }
2194
2195 /* Enable dynamic interrupt throttling rates */
2196 adapter->eitr_param = 20000;
2197 adapter->itr_setting = 1;
2198
2199 /* set defaults for eitr in MegaBytes */
2200 adapter->eitr_low = 10;
2201 adapter->eitr_high = 20;
2202
2203 /* set default ring sizes */
2204 adapter->tx_ring_count = IXGBEVF_DEFAULT_TXD;
2205 adapter->rx_ring_count = IXGBEVF_DEFAULT_RXD;
2206
2207 /* enable rx csum by default */
2208 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2209
2210 set_bit(__IXGBEVF_DOWN, &adapter->state);
2211
2212out:
2213 return err;
2214}
2215
2216#define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \
2217 { \
2218 u32 current_counter = IXGBE_READ_REG(hw, reg); \
2219 if (current_counter < last_counter) \
2220 counter += 0x100000000LL; \
2221 last_counter = current_counter; \
2222 counter &= 0xFFFFFFFF00000000LL; \
2223 counter |= current_counter; \
2224 }
2225
2226#define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2227 { \
2228 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \
2229 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \
2230 u64 current_counter = (current_counter_msb << 32) | \
2231 current_counter_lsb; \
2232 if (current_counter < last_counter) \
2233 counter += 0x1000000000LL; \
2234 last_counter = current_counter; \
2235 counter &= 0xFFFFFFF000000000LL; \
2236 counter |= current_counter; \
2237 }
2238/**
2239 * ixgbevf_update_stats - Update the board statistics counters.
2240 * @adapter: board private structure
2241 **/
2242void ixgbevf_update_stats(struct ixgbevf_adapter *adapter)
2243{
2244 struct ixgbe_hw *hw = &adapter->hw;
2245
2246 UPDATE_VF_COUNTER_32bit(IXGBE_VFGPRC, adapter->stats.last_vfgprc,
2247 adapter->stats.vfgprc);
2248 UPDATE_VF_COUNTER_32bit(IXGBE_VFGPTC, adapter->stats.last_vfgptc,
2249 adapter->stats.vfgptc);
2250 UPDATE_VF_COUNTER_36bit(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2251 adapter->stats.last_vfgorc,
2252 adapter->stats.vfgorc);
2253 UPDATE_VF_COUNTER_36bit(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2254 adapter->stats.last_vfgotc,
2255 adapter->stats.vfgotc);
2256 UPDATE_VF_COUNTER_32bit(IXGBE_VFMPRC, adapter->stats.last_vfmprc,
2257 adapter->stats.vfmprc);
2258
2259 /* Fill out the OS statistics structure */
2260 adapter->netdev->stats.multicast = adapter->stats.vfmprc -
2261 adapter->stats.base_vfmprc;
2262}
2263
2264/**
2265 * ixgbevf_watchdog - Timer Call-back
2266 * @data: pointer to adapter cast into an unsigned long
2267 **/
2268static void ixgbevf_watchdog(unsigned long data)
2269{
2270 struct ixgbevf_adapter *adapter = (struct ixgbevf_adapter *)data;
2271 struct ixgbe_hw *hw = &adapter->hw;
2272 u64 eics = 0;
2273 int i;
2274
2275 /*
2276 * Do the watchdog outside of interrupt context due to the lovely
2277 * delays that some of the newer hardware requires
2278 */
2279
2280 if (test_bit(__IXGBEVF_DOWN, &adapter->state))
2281 goto watchdog_short_circuit;
2282
2283 /* get one bit for every active tx/rx interrupt vector */
2284 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
2285 struct ixgbevf_q_vector *qv = adapter->q_vector[i];
2286 if (qv->rxr_count || qv->txr_count)
2287 eics |= (1 << i);
2288 }
2289
2290 IXGBE_WRITE_REG(hw, IXGBE_VTEICS, (u32)eics);
2291
2292watchdog_short_circuit:
2293 schedule_work(&adapter->watchdog_task);
2294}
2295
2296/**
2297 * ixgbevf_tx_timeout - Respond to a Tx Hang
2298 * @netdev: network interface device structure
2299 **/
2300static void ixgbevf_tx_timeout(struct net_device *netdev)
2301{
2302 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2303
2304 /* Do the reset outside of interrupt context */
2305 schedule_work(&adapter->reset_task);
2306}
2307
2308static void ixgbevf_reset_task(struct work_struct *work)
2309{
2310 struct ixgbevf_adapter *adapter;
2311 adapter = container_of(work, struct ixgbevf_adapter, reset_task);
2312
2313 /* If we're already down or resetting, just bail */
2314 if (test_bit(__IXGBEVF_DOWN, &adapter->state) ||
2315 test_bit(__IXGBEVF_RESETTING, &adapter->state))
2316 return;
2317
2318 adapter->tx_timeout_count++;
2319
2320 ixgbevf_reinit_locked(adapter);
2321}
2322
2323/**
2324 * ixgbevf_watchdog_task - worker thread to bring link up
2325 * @work: pointer to work_struct containing our data
2326 **/
2327static void ixgbevf_watchdog_task(struct work_struct *work)
2328{
2329 struct ixgbevf_adapter *adapter = container_of(work,
2330 struct ixgbevf_adapter,
2331 watchdog_task);
2332 struct net_device *netdev = adapter->netdev;
2333 struct ixgbe_hw *hw = &adapter->hw;
2334 u32 link_speed = adapter->link_speed;
2335 bool link_up = adapter->link_up;
2336
2337 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
2338
2339 /*
2340 * Always check the link on the watchdog because we have
2341 * no LSC interrupt
2342 */
2343 if (hw->mac.ops.check_link) {
2344 if ((hw->mac.ops.check_link(hw, &link_speed,
2345 &link_up, false)) != 0) {
2346 adapter->link_up = link_up;
2347 adapter->link_speed = link_speed;
2348 netif_carrier_off(netdev);
2349 netif_tx_stop_all_queues(netdev);
2350 schedule_work(&adapter->reset_task);
2351 goto pf_has_reset;
2352 }
2353 } else {
2354 /* always assume link is up, if no check link
2355 * function */
2356 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
2357 link_up = true;
2358 }
2359 adapter->link_up = link_up;
2360 adapter->link_speed = link_speed;
2361
2362 if (link_up) {
2363 if (!netif_carrier_ok(netdev)) {
2364 hw_dbg(&adapter->hw, "NIC Link is Up, %u Gbps\n",
2365 (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
2366 10 : 1);
2367 netif_carrier_on(netdev);
2368 netif_tx_wake_all_queues(netdev);
2369 }
2370 } else {
2371 adapter->link_up = false;
2372 adapter->link_speed = 0;
2373 if (netif_carrier_ok(netdev)) {
2374 hw_dbg(&adapter->hw, "NIC Link is Down\n");
2375 netif_carrier_off(netdev);
2376 netif_tx_stop_all_queues(netdev);
2377 }
2378 }
2379
2380 ixgbevf_update_stats(adapter);
2381
2382pf_has_reset:
2383 /* Reset the timer */
2384 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
2385 mod_timer(&adapter->watchdog_timer,
2386 round_jiffies(jiffies + (2 * HZ)));
2387
2388 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
2389}
2390
2391/**
2392 * ixgbevf_free_tx_resources - Free Tx Resources per Queue
2393 * @adapter: board private structure
2394 * @tx_ring: Tx descriptor ring for a specific queue
2395 *
2396 * Free all transmit software resources
2397 **/
2398void ixgbevf_free_tx_resources(struct ixgbevf_adapter *adapter,
2399 struct ixgbevf_ring *tx_ring)
2400{
2401 struct pci_dev *pdev = adapter->pdev;
2402
2403 ixgbevf_clean_tx_ring(adapter, tx_ring);
2404
2405 vfree(tx_ring->tx_buffer_info);
2406 tx_ring->tx_buffer_info = NULL;
2407
2408 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2409 tx_ring->dma);
2410
2411 tx_ring->desc = NULL;
2412}
2413
2414/**
2415 * ixgbevf_free_all_tx_resources - Free Tx Resources for All Queues
2416 * @adapter: board private structure
2417 *
2418 * Free all transmit software resources
2419 **/
2420static void ixgbevf_free_all_tx_resources(struct ixgbevf_adapter *adapter)
2421{
2422 int i;
2423
2424 for (i = 0; i < adapter->num_tx_queues; i++)
2425 if (adapter->tx_ring[i].desc)
2426 ixgbevf_free_tx_resources(adapter,
2427 &adapter->tx_ring[i]);
2428
2429}
2430
2431/**
2432 * ixgbevf_setup_tx_resources - allocate Tx resources (Descriptors)
2433 * @adapter: board private structure
2434 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2435 *
2436 * Return 0 on success, negative on failure
2437 **/
2438int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *adapter,
2439 struct ixgbevf_ring *tx_ring)
2440{
2441 struct pci_dev *pdev = adapter->pdev;
2442 int size;
2443
2444 size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
2445 tx_ring->tx_buffer_info = vzalloc(size);
2446 if (!tx_ring->tx_buffer_info)
2447 goto err;
2448
2449 /* round up to nearest 4K */
2450 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
2451 tx_ring->size = ALIGN(tx_ring->size, 4096);
2452
2453 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
2454 &tx_ring->dma, GFP_KERNEL);
2455 if (!tx_ring->desc)
2456 goto err;
2457
2458 tx_ring->next_to_use = 0;
2459 tx_ring->next_to_clean = 0;
2460 tx_ring->work_limit = tx_ring->count;
2461 return 0;
2462
2463err:
2464 vfree(tx_ring->tx_buffer_info);
2465 tx_ring->tx_buffer_info = NULL;
2466 hw_dbg(&adapter->hw, "Unable to allocate memory for the transmit "
2467 "descriptor ring\n");
2468 return -ENOMEM;
2469}
2470
2471/**
2472 * ixgbevf_setup_all_tx_resources - allocate all queues Tx resources
2473 * @adapter: board private structure
2474 *
2475 * If this function returns with an error, then it's possible one or
2476 * more of the rings is populated (while the rest are not). It is the
2477 * callers duty to clean those orphaned rings.
2478 *
2479 * Return 0 on success, negative on failure
2480 **/
2481static int ixgbevf_setup_all_tx_resources(struct ixgbevf_adapter *adapter)
2482{
2483 int i, err = 0;
2484
2485 for (i = 0; i < adapter->num_tx_queues; i++) {
2486 err = ixgbevf_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2487 if (!err)
2488 continue;
2489 hw_dbg(&adapter->hw,
2490 "Allocation for Tx Queue %u failed\n", i);
2491 break;
2492 }
2493
2494 return err;
2495}
2496
2497/**
2498 * ixgbevf_setup_rx_resources - allocate Rx resources (Descriptors)
2499 * @adapter: board private structure
2500 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2501 *
2502 * Returns 0 on success, negative on failure
2503 **/
2504int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter,
2505 struct ixgbevf_ring *rx_ring)
2506{
2507 struct pci_dev *pdev = adapter->pdev;
2508 int size;
2509
2510 size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
2511 rx_ring->rx_buffer_info = vzalloc(size);
2512 if (!rx_ring->rx_buffer_info) {
2513 hw_dbg(&adapter->hw,
2514 "Unable to vmalloc buffer memory for "
2515 "the receive descriptor ring\n");
2516 goto alloc_failed;
2517 }
2518
2519 /* Round up to nearest 4K */
2520 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2521 rx_ring->size = ALIGN(rx_ring->size, 4096);
2522
2523 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
2524 &rx_ring->dma, GFP_KERNEL);
2525
2526 if (!rx_ring->desc) {
2527 hw_dbg(&adapter->hw,
2528 "Unable to allocate memory for "
2529 "the receive descriptor ring\n");
2530 vfree(rx_ring->rx_buffer_info);
2531 rx_ring->rx_buffer_info = NULL;
2532 goto alloc_failed;
2533 }
2534
2535 rx_ring->next_to_clean = 0;
2536 rx_ring->next_to_use = 0;
2537
2538 return 0;
2539alloc_failed:
2540 return -ENOMEM;
2541}
2542
2543/**
2544 * ixgbevf_setup_all_rx_resources - allocate all queues Rx resources
2545 * @adapter: board private structure
2546 *
2547 * If this function returns with an error, then it's possible one or
2548 * more of the rings is populated (while the rest are not). It is the
2549 * callers duty to clean those orphaned rings.
2550 *
2551 * Return 0 on success, negative on failure
2552 **/
2553static int ixgbevf_setup_all_rx_resources(struct ixgbevf_adapter *adapter)
2554{
2555 int i, err = 0;
2556
2557 for (i = 0; i < adapter->num_rx_queues; i++) {
2558 err = ixgbevf_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2559 if (!err)
2560 continue;
2561 hw_dbg(&adapter->hw,
2562 "Allocation for Rx Queue %u failed\n", i);
2563 break;
2564 }
2565 return err;
2566}
2567
2568/**
2569 * ixgbevf_free_rx_resources - Free Rx Resources
2570 * @adapter: board private structure
2571 * @rx_ring: ring to clean the resources from
2572 *
2573 * Free all receive software resources
2574 **/
2575void ixgbevf_free_rx_resources(struct ixgbevf_adapter *adapter,
2576 struct ixgbevf_ring *rx_ring)
2577{
2578 struct pci_dev *pdev = adapter->pdev;
2579
2580 ixgbevf_clean_rx_ring(adapter, rx_ring);
2581
2582 vfree(rx_ring->rx_buffer_info);
2583 rx_ring->rx_buffer_info = NULL;
2584
2585 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2586 rx_ring->dma);
2587
2588 rx_ring->desc = NULL;
2589}
2590
2591/**
2592 * ixgbevf_free_all_rx_resources - Free Rx Resources for All Queues
2593 * @adapter: board private structure
2594 *
2595 * Free all receive software resources
2596 **/
2597static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter)
2598{
2599 int i;
2600
2601 for (i = 0; i < adapter->num_rx_queues; i++)
2602 if (adapter->rx_ring[i].desc)
2603 ixgbevf_free_rx_resources(adapter,
2604 &adapter->rx_ring[i]);
2605}
2606
2607/**
2608 * ixgbevf_open - Called when a network interface is made active
2609 * @netdev: network interface device structure
2610 *
2611 * Returns 0 on success, negative value on failure
2612 *
2613 * The open entry point is called when a network interface is made
2614 * active by the system (IFF_UP). At this point all resources needed
2615 * for transmit and receive operations are allocated, the interrupt
2616 * handler is registered with the OS, the watchdog timer is started,
2617 * and the stack is notified that the interface is ready.
2618 **/
2619static int ixgbevf_open(struct net_device *netdev)
2620{
2621 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2622 struct ixgbe_hw *hw = &adapter->hw;
2623 int err;
2624
2625 /* disallow open during test */
2626 if (test_bit(__IXGBEVF_TESTING, &adapter->state))
2627 return -EBUSY;
2628
2629 if (hw->adapter_stopped) {
2630 ixgbevf_reset(adapter);
2631 /* if adapter is still stopped then PF isn't up and
2632 * the vf can't start. */
2633 if (hw->adapter_stopped) {
2634 err = IXGBE_ERR_MBX;
2635 printk(KERN_ERR "Unable to start - perhaps the PF"
2636 " Driver isn't up yet\n");
2637 goto err_setup_reset;
2638 }
2639 }
2640
2641 /* allocate transmit descriptors */
2642 err = ixgbevf_setup_all_tx_resources(adapter);
2643 if (err)
2644 goto err_setup_tx;
2645
2646 /* allocate receive descriptors */
2647 err = ixgbevf_setup_all_rx_resources(adapter);
2648 if (err)
2649 goto err_setup_rx;
2650
2651 ixgbevf_configure(adapter);
2652
2653 /*
2654 * Map the Tx/Rx rings to the vectors we were allotted.
2655 * if request_irq will be called in this function map_rings
2656 * must be called *before* up_complete
2657 */
2658 ixgbevf_map_rings_to_vectors(adapter);
2659
2660 err = ixgbevf_up_complete(adapter);
2661 if (err)
2662 goto err_up;
2663
2664 /* clear any pending interrupts, may auto mask */
2665 IXGBE_READ_REG(hw, IXGBE_VTEICR);
2666 err = ixgbevf_request_irq(adapter);
2667 if (err)
2668 goto err_req_irq;
2669
2670 ixgbevf_irq_enable(adapter, true, true);
2671
2672 return 0;
2673
2674err_req_irq:
2675 ixgbevf_down(adapter);
2676err_up:
2677 ixgbevf_free_irq(adapter);
2678err_setup_rx:
2679 ixgbevf_free_all_rx_resources(adapter);
2680err_setup_tx:
2681 ixgbevf_free_all_tx_resources(adapter);
2682 ixgbevf_reset(adapter);
2683
2684err_setup_reset:
2685
2686 return err;
2687}
2688
2689/**
2690 * ixgbevf_close - Disables a network interface
2691 * @netdev: network interface device structure
2692 *
2693 * Returns 0, this is not allowed to fail
2694 *
2695 * The close entry point is called when an interface is de-activated
2696 * by the OS. The hardware is still under the drivers control, but
2697 * needs to be disabled. A global MAC reset is issued to stop the
2698 * hardware, and all transmit and receive resources are freed.
2699 **/
2700static int ixgbevf_close(struct net_device *netdev)
2701{
2702 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2703
2704 ixgbevf_down(adapter);
2705 ixgbevf_free_irq(adapter);
2706
2707 ixgbevf_free_all_tx_resources(adapter);
2708 ixgbevf_free_all_rx_resources(adapter);
2709
2710 return 0;
2711}
2712
2713static int ixgbevf_tso(struct ixgbevf_adapter *adapter,
2714 struct ixgbevf_ring *tx_ring,
2715 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2716{
2717 struct ixgbe_adv_tx_context_desc *context_desc;
2718 unsigned int i;
2719 int err;
2720 struct ixgbevf_tx_buffer *tx_buffer_info;
2721 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
2722 u32 mss_l4len_idx, l4len;
2723
2724 if (skb_is_gso(skb)) {
2725 if (skb_header_cloned(skb)) {
2726 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2727 if (err)
2728 return err;
2729 }
2730 l4len = tcp_hdrlen(skb);
2731 *hdr_len += l4len;
2732
2733 if (skb->protocol == htons(ETH_P_IP)) {
2734 struct iphdr *iph = ip_hdr(skb);
2735 iph->tot_len = 0;
2736 iph->check = 0;
2737 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2738 iph->daddr, 0,
2739 IPPROTO_TCP,
2740 0);
2741 adapter->hw_tso_ctxt++;
2742 } else if (skb_is_gso_v6(skb)) {
2743 ipv6_hdr(skb)->payload_len = 0;
2744 tcp_hdr(skb)->check =
2745 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2746 &ipv6_hdr(skb)->daddr,
2747 0, IPPROTO_TCP, 0);
2748 adapter->hw_tso6_ctxt++;
2749 }
2750
2751 i = tx_ring->next_to_use;
2752
2753 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2754 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2755
2756 /* VLAN MACLEN IPLEN */
2757 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2758 vlan_macip_lens |=
2759 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
2760 vlan_macip_lens |= ((skb_network_offset(skb)) <<
2761 IXGBE_ADVTXD_MACLEN_SHIFT);
2762 *hdr_len += skb_network_offset(skb);
2763 vlan_macip_lens |=
2764 (skb_transport_header(skb) - skb_network_header(skb));
2765 *hdr_len +=
2766 (skb_transport_header(skb) - skb_network_header(skb));
2767 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2768 context_desc->seqnum_seed = 0;
2769
2770 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2771 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
2772 IXGBE_ADVTXD_DTYP_CTXT);
2773
2774 if (skb->protocol == htons(ETH_P_IP))
2775 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
2776 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
2777 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2778
2779 /* MSS L4LEN IDX */
2780 mss_l4len_idx =
2781 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
2782 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
2783 /* use index 1 for TSO */
2784 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
2785 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2786
2787 tx_buffer_info->time_stamp = jiffies;
2788 tx_buffer_info->next_to_watch = i;
2789
2790 i++;
2791 if (i == tx_ring->count)
2792 i = 0;
2793 tx_ring->next_to_use = i;
2794
2795 return true;
2796 }
2797
2798 return false;
2799}
2800
2801static bool ixgbevf_tx_csum(struct ixgbevf_adapter *adapter,
2802 struct ixgbevf_ring *tx_ring,
2803 struct sk_buff *skb, u32 tx_flags)
2804{
2805 struct ixgbe_adv_tx_context_desc *context_desc;
2806 unsigned int i;
2807 struct ixgbevf_tx_buffer *tx_buffer_info;
2808 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2809
2810 if (skb->ip_summed == CHECKSUM_PARTIAL ||
2811 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
2812 i = tx_ring->next_to_use;
2813 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2814 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2815
2816 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2817 vlan_macip_lens |= (tx_flags &
2818 IXGBE_TX_FLAGS_VLAN_MASK);
2819 vlan_macip_lens |= (skb_network_offset(skb) <<
2820 IXGBE_ADVTXD_MACLEN_SHIFT);
2821 if (skb->ip_summed == CHECKSUM_PARTIAL)
2822 vlan_macip_lens |= (skb_transport_header(skb) -
2823 skb_network_header(skb));
2824
2825 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2826 context_desc->seqnum_seed = 0;
2827
2828 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
2829 IXGBE_ADVTXD_DTYP_CTXT);
2830
2831 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2832 switch (skb->protocol) {
2833 case __constant_htons(ETH_P_IP):
2834 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
2835 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2836 type_tucmd_mlhl |=
2837 IXGBE_ADVTXD_TUCMD_L4T_TCP;
2838 break;
2839 case __constant_htons(ETH_P_IPV6):
2840 /* XXX what about other V6 headers?? */
2841 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2842 type_tucmd_mlhl |=
2843 IXGBE_ADVTXD_TUCMD_L4T_TCP;
2844 break;
2845 default:
2846 if (unlikely(net_ratelimit())) {
2847 printk(KERN_WARNING
2848 "partial checksum but "
2849 "proto=%x!\n",
2850 skb->protocol);
2851 }
2852 break;
2853 }
2854 }
2855
2856 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2857 /* use index zero for tx checksum offload */
2858 context_desc->mss_l4len_idx = 0;
2859
2860 tx_buffer_info->time_stamp = jiffies;
2861 tx_buffer_info->next_to_watch = i;
2862
2863 adapter->hw_csum_tx_good++;
2864 i++;
2865 if (i == tx_ring->count)
2866 i = 0;
2867 tx_ring->next_to_use = i;
2868
2869 return true;
2870 }
2871
2872 return false;
2873}
2874
2875static int ixgbevf_tx_map(struct ixgbevf_adapter *adapter,
2876 struct ixgbevf_ring *tx_ring,
2877 struct sk_buff *skb, u32 tx_flags,
2878 unsigned int first)
2879{
2880 struct pci_dev *pdev = adapter->pdev;
2881 struct ixgbevf_tx_buffer *tx_buffer_info;
2882 unsigned int len;
2883 unsigned int total = skb->len;
2884 unsigned int offset = 0, size;
2885 int count = 0;
2886 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
2887 unsigned int f;
2888 int i;
2889
2890 i = tx_ring->next_to_use;
2891
2892 len = min(skb_headlen(skb), total);
2893 while (len) {
2894 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2895 size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD);
2896
2897 tx_buffer_info->length = size;
2898 tx_buffer_info->mapped_as_page = false;
2899 tx_buffer_info->dma = dma_map_single(&adapter->pdev->dev,
2900 skb->data + offset,
2901 size, DMA_TO_DEVICE);
2902 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
2903 goto dma_error;
2904 tx_buffer_info->time_stamp = jiffies;
2905 tx_buffer_info->next_to_watch = i;
2906
2907 len -= size;
2908 total -= size;
2909 offset += size;
2910 count++;
2911 i++;
2912 if (i == tx_ring->count)
2913 i = 0;
2914 }
2915
2916 for (f = 0; f < nr_frags; f++) {
2917 struct skb_frag_struct *frag;
2918
2919 frag = &skb_shinfo(skb)->frags[f];
2920 len = min((unsigned int)frag->size, total);
2921 offset = frag->page_offset;
2922
2923 while (len) {
2924 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2925 size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD);
2926
2927 tx_buffer_info->length = size;
2928 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
2929 frag->page,
2930 offset,
2931 size,
2932 DMA_TO_DEVICE);
2933 tx_buffer_info->mapped_as_page = true;
2934 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
2935 goto dma_error;
2936 tx_buffer_info->time_stamp = jiffies;
2937 tx_buffer_info->next_to_watch = i;
2938
2939 len -= size;
2940 total -= size;
2941 offset += size;
2942 count++;
2943 i++;
2944 if (i == tx_ring->count)
2945 i = 0;
2946 }
2947 if (total == 0)
2948 break;
2949 }
2950
2951 if (i == 0)
2952 i = tx_ring->count - 1;
2953 else
2954 i = i - 1;
2955 tx_ring->tx_buffer_info[i].skb = skb;
2956 tx_ring->tx_buffer_info[first].next_to_watch = i;
2957
2958 return count;
2959
2960dma_error:
2961 dev_err(&pdev->dev, "TX DMA map failed\n");
2962
2963 /* clear timestamp and dma mappings for failed tx_buffer_info map */
2964 tx_buffer_info->dma = 0;
2965 tx_buffer_info->time_stamp = 0;
2966 tx_buffer_info->next_to_watch = 0;
2967 count--;
2968
2969 /* clear timestamp and dma mappings for remaining portion of packet */
2970 while (count >= 0) {
2971 count--;
2972 i--;
2973 if (i < 0)
2974 i += tx_ring->count;
2975 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2976 ixgbevf_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2977 }
2978
2979 return count;
2980}
2981
2982static void ixgbevf_tx_queue(struct ixgbevf_adapter *adapter,
2983 struct ixgbevf_ring *tx_ring, int tx_flags,
2984 int count, u32 paylen, u8 hdr_len)
2985{
2986 union ixgbe_adv_tx_desc *tx_desc = NULL;
2987 struct ixgbevf_tx_buffer *tx_buffer_info;
2988 u32 olinfo_status = 0, cmd_type_len = 0;
2989 unsigned int i;
2990
2991 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
2992
2993 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
2994
2995 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
2996
2997 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2998 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
2999
3000 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3001 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3002
3003 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3004 IXGBE_ADVTXD_POPTS_SHIFT;
3005
3006 /* use index 1 context for tso */
3007 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3008 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3009 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3010 IXGBE_ADVTXD_POPTS_SHIFT;
3011
3012 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3013 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3014 IXGBE_ADVTXD_POPTS_SHIFT;
3015
3016 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3017
3018 i = tx_ring->next_to_use;
3019 while (count--) {
3020 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3021 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3022 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3023 tx_desc->read.cmd_type_len =
3024 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3025 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3026 i++;
3027 if (i == tx_ring->count)
3028 i = 0;
3029 }
3030
3031 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3032
3033 /*
3034 * Force memory writes to complete before letting h/w
3035 * know there are new descriptors to fetch. (Only
3036 * applicable for weak-ordered memory model archs,
3037 * such as IA-64).
3038 */
3039 wmb();
3040
3041 tx_ring->next_to_use = i;
3042 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3043}
3044
3045static int __ixgbevf_maybe_stop_tx(struct net_device *netdev,
3046 struct ixgbevf_ring *tx_ring, int size)
3047{
3048 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3049
3050 netif_stop_subqueue(netdev, tx_ring->queue_index);
3051 /* Herbert's original patch had:
3052 * smp_mb__after_netif_stop_queue();
3053 * but since that doesn't exist yet, just open code it. */
3054 smp_mb();
3055
3056 /* We need to check again in a case another CPU has just
3057 * made room available. */
3058 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3059 return -EBUSY;
3060
3061 /* A reprieve! - use start_queue because it doesn't call schedule */
3062 netif_start_subqueue(netdev, tx_ring->queue_index);
3063 ++adapter->restart_queue;
3064 return 0;
3065}
3066
3067static int ixgbevf_maybe_stop_tx(struct net_device *netdev,
3068 struct ixgbevf_ring *tx_ring, int size)
3069{
3070 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3071 return 0;
3072 return __ixgbevf_maybe_stop_tx(netdev, tx_ring, size);
3073}
3074
3075static int ixgbevf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3076{
3077 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3078 struct ixgbevf_ring *tx_ring;
3079 unsigned int first;
3080 unsigned int tx_flags = 0;
3081 u8 hdr_len = 0;
3082 int r_idx = 0, tso;
3083 int count = 0;
3084
3085 unsigned int f;
3086
3087 tx_ring = &adapter->tx_ring[r_idx];
3088
3089 if (vlan_tx_tag_present(skb)) {
3090 tx_flags |= vlan_tx_tag_get(skb);
3091 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3092 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3093 }
3094
3095 /* four things can cause us to need a context descriptor */
3096 if (skb_is_gso(skb) ||
3097 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3098 (tx_flags & IXGBE_TX_FLAGS_VLAN))
3099 count++;
3100
3101 count += TXD_USE_COUNT(skb_headlen(skb));
3102 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
3103 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3104
3105 if (ixgbevf_maybe_stop_tx(netdev, tx_ring, count)) {
3106 adapter->tx_busy++;
3107 return NETDEV_TX_BUSY;
3108 }
3109
3110 first = tx_ring->next_to_use;
3111
3112 if (skb->protocol == htons(ETH_P_IP))
3113 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3114 tso = ixgbevf_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3115 if (tso < 0) {
3116 dev_kfree_skb_any(skb);
3117 return NETDEV_TX_OK;
3118 }
3119
3120 if (tso)
3121 tx_flags |= IXGBE_TX_FLAGS_TSO;
3122 else if (ixgbevf_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3123 (skb->ip_summed == CHECKSUM_PARTIAL))
3124 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3125
3126 ixgbevf_tx_queue(adapter, tx_ring, tx_flags,
3127 ixgbevf_tx_map(adapter, tx_ring, skb, tx_flags, first),
3128 skb->len, hdr_len);
3129
3130 ixgbevf_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
3131
3132 return NETDEV_TX_OK;
3133}
3134
3135/**
3136 * ixgbevf_set_mac - Change the Ethernet Address of the NIC
3137 * @netdev: network interface device structure
3138 * @p: pointer to an address structure
3139 *
3140 * Returns 0 on success, negative on failure
3141 **/
3142static int ixgbevf_set_mac(struct net_device *netdev, void *p)
3143{
3144 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3145 struct ixgbe_hw *hw = &adapter->hw;
3146 struct sockaddr *addr = p;
3147
3148 if (!is_valid_ether_addr(addr->sa_data))
3149 return -EADDRNOTAVAIL;
3150
3151 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3152 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3153
3154 if (hw->mac.ops.set_rar)
3155 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0);
3156
3157 return 0;
3158}
3159
3160/**
3161 * ixgbevf_change_mtu - Change the Maximum Transfer Unit
3162 * @netdev: network interface device structure
3163 * @new_mtu: new value for maximum frame size
3164 *
3165 * Returns 0 on success, negative on failure
3166 **/
3167static int ixgbevf_change_mtu(struct net_device *netdev, int new_mtu)
3168{
3169 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3170 struct ixgbe_hw *hw = &adapter->hw;
3171 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3172 int max_possible_frame = MAXIMUM_ETHERNET_VLAN_SIZE;
3173 u32 msg[2];
3174
3175 if (adapter->hw.mac.type == ixgbe_mac_X540_vf)
3176 max_possible_frame = IXGBE_MAX_JUMBO_FRAME_SIZE;
3177
3178 /* MTU < 68 is an error and causes problems on some kernels */
3179 if ((new_mtu < 68) || (max_frame > max_possible_frame))
3180 return -EINVAL;
3181
3182 hw_dbg(&adapter->hw, "changing MTU from %d to %d\n",
3183 netdev->mtu, new_mtu);
3184 /* must set new MTU before calling down or up */
3185 netdev->mtu = new_mtu;
3186
3187 msg[0] = IXGBE_VF_SET_LPE;
3188 msg[1] = max_frame;
3189 hw->mbx.ops.write_posted(hw, msg, 2);
3190
3191 if (netif_running(netdev))
3192 ixgbevf_reinit_locked(adapter);
3193
3194 return 0;
3195}
3196
3197static void ixgbevf_shutdown(struct pci_dev *pdev)
3198{
3199 struct net_device *netdev = pci_get_drvdata(pdev);
3200 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3201
3202 netif_device_detach(netdev);
3203
3204 if (netif_running(netdev)) {
3205 ixgbevf_down(adapter);
3206 ixgbevf_free_irq(adapter);
3207 ixgbevf_free_all_tx_resources(adapter);
3208 ixgbevf_free_all_rx_resources(adapter);
3209 }
3210
3211#ifdef CONFIG_PM
3212 pci_save_state(pdev);
3213#endif
3214
3215 pci_disable_device(pdev);
3216}
3217
3218static const struct net_device_ops ixgbe_netdev_ops = {
3219 .ndo_open = ixgbevf_open,
3220 .ndo_stop = ixgbevf_close,
3221 .ndo_start_xmit = ixgbevf_xmit_frame,
3222 .ndo_set_rx_mode = ixgbevf_set_rx_mode,
3223 .ndo_set_multicast_list = ixgbevf_set_rx_mode,
3224 .ndo_validate_addr = eth_validate_addr,
3225 .ndo_set_mac_address = ixgbevf_set_mac,
3226 .ndo_change_mtu = ixgbevf_change_mtu,
3227 .ndo_tx_timeout = ixgbevf_tx_timeout,
3228 .ndo_vlan_rx_add_vid = ixgbevf_vlan_rx_add_vid,
3229 .ndo_vlan_rx_kill_vid = ixgbevf_vlan_rx_kill_vid,
3230};
3231
3232static void ixgbevf_assign_netdev_ops(struct net_device *dev)
3233{
3234 dev->netdev_ops = &ixgbe_netdev_ops;
3235 ixgbevf_set_ethtool_ops(dev);
3236 dev->watchdog_timeo = 5 * HZ;
3237}
3238
3239/**
3240 * ixgbevf_probe - Device Initialization Routine
3241 * @pdev: PCI device information struct
3242 * @ent: entry in ixgbevf_pci_tbl
3243 *
3244 * Returns 0 on success, negative on failure
3245 *
3246 * ixgbevf_probe initializes an adapter identified by a pci_dev structure.
3247 * The OS initialization, configuring of the adapter private structure,
3248 * and a hardware reset occur.
3249 **/
3250static int __devinit ixgbevf_probe(struct pci_dev *pdev,
3251 const struct pci_device_id *ent)
3252{
3253 struct net_device *netdev;
3254 struct ixgbevf_adapter *adapter = NULL;
3255 struct ixgbe_hw *hw = NULL;
3256 const struct ixgbevf_info *ii = ixgbevf_info_tbl[ent->driver_data];
3257 static int cards_found;
3258 int err, pci_using_dac;
3259
3260 err = pci_enable_device(pdev);
3261 if (err)
3262 return err;
3263
3264 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
3265 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
3266 pci_using_dac = 1;
3267 } else {
3268 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
3269 if (err) {
3270 err = dma_set_coherent_mask(&pdev->dev,
3271 DMA_BIT_MASK(32));
3272 if (err) {
3273 dev_err(&pdev->dev, "No usable DMA "
3274 "configuration, aborting\n");
3275 goto err_dma;
3276 }
3277 }
3278 pci_using_dac = 0;
3279 }
3280
3281 err = pci_request_regions(pdev, ixgbevf_driver_name);
3282 if (err) {
3283 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3284 goto err_pci_reg;
3285 }
3286
3287 pci_set_master(pdev);
3288
3289#ifdef HAVE_TX_MQ
3290 netdev = alloc_etherdev_mq(sizeof(struct ixgbevf_adapter),
3291 MAX_TX_QUEUES);
3292#else
3293 netdev = alloc_etherdev(sizeof(struct ixgbevf_adapter));
3294#endif
3295 if (!netdev) {
3296 err = -ENOMEM;
3297 goto err_alloc_etherdev;
3298 }
3299
3300 SET_NETDEV_DEV(netdev, &pdev->dev);
3301
3302 pci_set_drvdata(pdev, netdev);
3303 adapter = netdev_priv(netdev);
3304
3305 adapter->netdev = netdev;
3306 adapter->pdev = pdev;
3307 hw = &adapter->hw;
3308 hw->back = adapter;
3309 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3310
3311 /*
3312 * call save state here in standalone driver because it relies on
3313 * adapter struct to exist, and needs to call netdev_priv
3314 */
3315 pci_save_state(pdev);
3316
3317 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3318 pci_resource_len(pdev, 0));
3319 if (!hw->hw_addr) {
3320 err = -EIO;
3321 goto err_ioremap;
3322 }
3323
3324 ixgbevf_assign_netdev_ops(netdev);
3325
3326 adapter->bd_number = cards_found;
3327
3328 /* Setup hw api */
3329 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
3330 hw->mac.type = ii->mac;
3331
3332 memcpy(&hw->mbx.ops, &ixgbevf_mbx_ops,
3333 sizeof(struct ixgbe_mbx_operations));
3334
3335 adapter->flags &= ~IXGBE_FLAG_RX_PS_CAPABLE;
3336 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3337 adapter->flags |= IXGBE_FLAG_RX_1BUF_CAPABLE;
3338
3339 /* setup the private structure */
3340 err = ixgbevf_sw_init(adapter);
3341
3342 netdev->features = NETIF_F_SG |
3343 NETIF_F_IP_CSUM |
3344 NETIF_F_HW_VLAN_TX |
3345 NETIF_F_HW_VLAN_RX |
3346 NETIF_F_HW_VLAN_FILTER;
3347
3348 netdev->features |= NETIF_F_IPV6_CSUM;
3349 netdev->features |= NETIF_F_TSO;
3350 netdev->features |= NETIF_F_TSO6;
3351 netdev->features |= NETIF_F_GRO;
3352 netdev->vlan_features |= NETIF_F_TSO;
3353 netdev->vlan_features |= NETIF_F_TSO6;
3354 netdev->vlan_features |= NETIF_F_IP_CSUM;
3355 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3356 netdev->vlan_features |= NETIF_F_SG;
3357
3358 if (pci_using_dac)
3359 netdev->features |= NETIF_F_HIGHDMA;
3360
3361 /* The HW MAC address was set and/or determined in sw_init */
3362 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
3363 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
3364
3365 if (!is_valid_ether_addr(netdev->dev_addr)) {
3366 printk(KERN_ERR "invalid MAC address\n");
3367 err = -EIO;
3368 goto err_sw_init;
3369 }
3370
3371 init_timer(&adapter->watchdog_timer);
3372 adapter->watchdog_timer.function = ixgbevf_watchdog;
3373 adapter->watchdog_timer.data = (unsigned long)adapter;
3374
3375 INIT_WORK(&adapter->reset_task, ixgbevf_reset_task);
3376 INIT_WORK(&adapter->watchdog_task, ixgbevf_watchdog_task);
3377
3378 err = ixgbevf_init_interrupt_scheme(adapter);
3379 if (err)
3380 goto err_sw_init;
3381
3382 /* pick up the PCI bus settings for reporting later */
3383 if (hw->mac.ops.get_bus_info)
3384 hw->mac.ops.get_bus_info(hw);
3385
3386 strcpy(netdev->name, "eth%d");
3387
3388 err = register_netdev(netdev);
3389 if (err)
3390 goto err_register;
3391
3392 adapter->netdev_registered = true;
3393
3394 netif_carrier_off(netdev);
3395
3396 ixgbevf_init_last_counter_stats(adapter);
3397
3398 /* print the MAC address */
3399 hw_dbg(hw, "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
3400 netdev->dev_addr[0],
3401 netdev->dev_addr[1],
3402 netdev->dev_addr[2],
3403 netdev->dev_addr[3],
3404 netdev->dev_addr[4],
3405 netdev->dev_addr[5]);
3406
3407 hw_dbg(hw, "MAC: %d\n", hw->mac.type);
3408
3409 hw_dbg(hw, "LRO is disabled\n");
3410
3411 hw_dbg(hw, "Intel(R) 82599 Virtual Function\n");
3412 cards_found++;
3413 return 0;
3414
3415err_register:
3416err_sw_init:
3417 ixgbevf_reset_interrupt_capability(adapter);
3418 iounmap(hw->hw_addr);
3419err_ioremap:
3420 free_netdev(netdev);
3421err_alloc_etherdev:
3422 pci_release_regions(pdev);
3423err_pci_reg:
3424err_dma:
3425 pci_disable_device(pdev);
3426 return err;
3427}
3428
3429/**
3430 * ixgbevf_remove - Device Removal Routine
3431 * @pdev: PCI device information struct
3432 *
3433 * ixgbevf_remove is called by the PCI subsystem to alert the driver
3434 * that it should release a PCI device. The could be caused by a
3435 * Hot-Plug event, or because the driver is going to be removed from
3436 * memory.
3437 **/
3438static void __devexit ixgbevf_remove(struct pci_dev *pdev)
3439{
3440 struct net_device *netdev = pci_get_drvdata(pdev);
3441 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3442
3443 set_bit(__IXGBEVF_DOWN, &adapter->state);
3444
3445 del_timer_sync(&adapter->watchdog_timer);
3446
3447 cancel_work_sync(&adapter->reset_task);
3448 cancel_work_sync(&adapter->watchdog_task);
3449
3450 if (adapter->netdev_registered) {
3451 unregister_netdev(netdev);
3452 adapter->netdev_registered = false;
3453 }
3454
3455 ixgbevf_reset_interrupt_capability(adapter);
3456
3457 iounmap(adapter->hw.hw_addr);
3458 pci_release_regions(pdev);
3459
3460 hw_dbg(&adapter->hw, "Remove complete\n");
3461
3462 kfree(adapter->tx_ring);
3463 kfree(adapter->rx_ring);
3464
3465 free_netdev(netdev);
3466
3467 pci_disable_device(pdev);
3468}
3469
3470static struct pci_driver ixgbevf_driver = {
3471 .name = ixgbevf_driver_name,
3472 .id_table = ixgbevf_pci_tbl,
3473 .probe = ixgbevf_probe,
3474 .remove = __devexit_p(ixgbevf_remove),
3475 .shutdown = ixgbevf_shutdown,
3476};
3477
3478/**
3479 * ixgbevf_init_module - Driver Registration Routine
3480 *
3481 * ixgbevf_init_module is the first routine called when the driver is
3482 * loaded. All it does is register with the PCI subsystem.
3483 **/
3484static int __init ixgbevf_init_module(void)
3485{
3486 int ret;
3487 printk(KERN_INFO "ixgbevf: %s - version %s\n", ixgbevf_driver_string,
3488 ixgbevf_driver_version);
3489
3490 printk(KERN_INFO "%s\n", ixgbevf_copyright);
3491
3492 ret = pci_register_driver(&ixgbevf_driver);
3493 return ret;
3494}
3495
3496module_init(ixgbevf_init_module);
3497
3498/**
3499 * ixgbevf_exit_module - Driver Exit Cleanup Routine
3500 *
3501 * ixgbevf_exit_module is called just before the driver is removed
3502 * from memory.
3503 **/
3504static void __exit ixgbevf_exit_module(void)
3505{
3506 pci_unregister_driver(&ixgbevf_driver);
3507}
3508
3509#ifdef DEBUG
3510/**
3511 * ixgbevf_get_hw_dev_name - return device name string
3512 * used by hardware layer to print debugging information
3513 **/
3514char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw)
3515{
3516 struct ixgbevf_adapter *adapter = hw->back;
3517 return adapter->netdev->name;
3518}
3519
3520#endif
3521module_exit(ixgbevf_exit_module);
3522
3523/* ixgbevf_main.c */
diff --git a/drivers/net/ixgbevf/mbx.c b/drivers/net/ixgbevf/mbx.c
new file mode 100644
index 00000000000..7a883312577
--- /dev/null
+++ b/drivers/net/ixgbevf/mbx.c
@@ -0,0 +1,341 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include "mbx.h"
29
30/**
31 * ixgbevf_poll_for_msg - Wait for message notification
32 * @hw: pointer to the HW structure
33 *
34 * returns 0 if it successfully received a message notification
35 **/
36static s32 ixgbevf_poll_for_msg(struct ixgbe_hw *hw)
37{
38 struct ixgbe_mbx_info *mbx = &hw->mbx;
39 int countdown = mbx->timeout;
40
41 while (countdown && mbx->ops.check_for_msg(hw)) {
42 countdown--;
43 udelay(mbx->udelay);
44 }
45
46 /* if we failed, all future posted messages fail until reset */
47 if (!countdown)
48 mbx->timeout = 0;
49
50 return countdown ? 0 : IXGBE_ERR_MBX;
51}
52
53/**
54 * ixgbevf_poll_for_ack - Wait for message acknowledgement
55 * @hw: pointer to the HW structure
56 *
57 * returns 0 if it successfully received a message acknowledgement
58 **/
59static s32 ixgbevf_poll_for_ack(struct ixgbe_hw *hw)
60{
61 struct ixgbe_mbx_info *mbx = &hw->mbx;
62 int countdown = mbx->timeout;
63
64 while (countdown && mbx->ops.check_for_ack(hw)) {
65 countdown--;
66 udelay(mbx->udelay);
67 }
68
69 /* if we failed, all future posted messages fail until reset */
70 if (!countdown)
71 mbx->timeout = 0;
72
73 return countdown ? 0 : IXGBE_ERR_MBX;
74}
75
76/**
77 * ixgbevf_read_posted_mbx - Wait for message notification and receive message
78 * @hw: pointer to the HW structure
79 * @msg: The message buffer
80 * @size: Length of buffer
81 *
82 * returns 0 if it successfully received a message notification and
83 * copied it into the receive buffer.
84 **/
85static s32 ixgbevf_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size)
86{
87 struct ixgbe_mbx_info *mbx = &hw->mbx;
88 s32 ret_val = IXGBE_ERR_MBX;
89
90 ret_val = ixgbevf_poll_for_msg(hw);
91
92 /* if ack received read message, otherwise we timed out */
93 if (!ret_val)
94 ret_val = mbx->ops.read(hw, msg, size);
95
96 return ret_val;
97}
98
99/**
100 * ixgbevf_write_posted_mbx - Write a message to the mailbox, wait for ack
101 * @hw: pointer to the HW structure
102 * @msg: The message buffer
103 * @size: Length of buffer
104 *
105 * returns 0 if it successfully copied message into the buffer and
106 * received an ack to that message within delay * timeout period
107 **/
108static s32 ixgbevf_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size)
109{
110 struct ixgbe_mbx_info *mbx = &hw->mbx;
111 s32 ret_val;
112
113 /* send msg */
114 ret_val = mbx->ops.write(hw, msg, size);
115
116 /* if msg sent wait until we receive an ack */
117 if (!ret_val)
118 ret_val = ixgbevf_poll_for_ack(hw);
119
120 return ret_val;
121}
122
123/**
124 * ixgbevf_read_v2p_mailbox - read v2p mailbox
125 * @hw: pointer to the HW structure
126 *
127 * This function is used to read the v2p mailbox without losing the read to
128 * clear status bits.
129 **/
130static u32 ixgbevf_read_v2p_mailbox(struct ixgbe_hw *hw)
131{
132 u32 v2p_mailbox = IXGBE_READ_REG(hw, IXGBE_VFMAILBOX);
133
134 v2p_mailbox |= hw->mbx.v2p_mailbox;
135 hw->mbx.v2p_mailbox |= v2p_mailbox & IXGBE_VFMAILBOX_R2C_BITS;
136
137 return v2p_mailbox;
138}
139
140/**
141 * ixgbevf_check_for_bit_vf - Determine if a status bit was set
142 * @hw: pointer to the HW structure
143 * @mask: bitmask for bits to be tested and cleared
144 *
145 * This function is used to check for the read to clear bits within
146 * the V2P mailbox.
147 **/
148static s32 ixgbevf_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask)
149{
150 u32 v2p_mailbox = ixgbevf_read_v2p_mailbox(hw);
151 s32 ret_val = IXGBE_ERR_MBX;
152
153 if (v2p_mailbox & mask)
154 ret_val = 0;
155
156 hw->mbx.v2p_mailbox &= ~mask;
157
158 return ret_val;
159}
160
161/**
162 * ixgbevf_check_for_msg_vf - checks to see if the PF has sent mail
163 * @hw: pointer to the HW structure
164 *
165 * returns 0 if the PF has set the Status bit or else ERR_MBX
166 **/
167static s32 ixgbevf_check_for_msg_vf(struct ixgbe_hw *hw)
168{
169 s32 ret_val = IXGBE_ERR_MBX;
170
171 if (!ixgbevf_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFSTS)) {
172 ret_val = 0;
173 hw->mbx.stats.reqs++;
174 }
175
176 return ret_val;
177}
178
179/**
180 * ixgbevf_check_for_ack_vf - checks to see if the PF has ACK'd
181 * @hw: pointer to the HW structure
182 *
183 * returns 0 if the PF has set the ACK bit or else ERR_MBX
184 **/
185static s32 ixgbevf_check_for_ack_vf(struct ixgbe_hw *hw)
186{
187 s32 ret_val = IXGBE_ERR_MBX;
188
189 if (!ixgbevf_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFACK)) {
190 ret_val = 0;
191 hw->mbx.stats.acks++;
192 }
193
194 return ret_val;
195}
196
197/**
198 * ixgbevf_check_for_rst_vf - checks to see if the PF has reset
199 * @hw: pointer to the HW structure
200 *
201 * returns true if the PF has set the reset done bit or else false
202 **/
203static s32 ixgbevf_check_for_rst_vf(struct ixgbe_hw *hw)
204{
205 s32 ret_val = IXGBE_ERR_MBX;
206
207 if (!ixgbevf_check_for_bit_vf(hw, (IXGBE_VFMAILBOX_RSTD |
208 IXGBE_VFMAILBOX_RSTI))) {
209 ret_val = 0;
210 hw->mbx.stats.rsts++;
211 }
212
213 return ret_val;
214}
215
216/**
217 * ixgbevf_obtain_mbx_lock_vf - obtain mailbox lock
218 * @hw: pointer to the HW structure
219 *
220 * return 0 if we obtained the mailbox lock
221 **/
222static s32 ixgbevf_obtain_mbx_lock_vf(struct ixgbe_hw *hw)
223{
224 s32 ret_val = IXGBE_ERR_MBX;
225
226 /* Take ownership of the buffer */
227 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_VFU);
228
229 /* reserve mailbox for vf use */
230 if (ixgbevf_read_v2p_mailbox(hw) & IXGBE_VFMAILBOX_VFU)
231 ret_val = 0;
232
233 return ret_val;
234}
235
236/**
237 * ixgbevf_write_mbx_vf - Write a message to the mailbox
238 * @hw: pointer to the HW structure
239 * @msg: The message buffer
240 * @size: Length of buffer
241 *
242 * returns 0 if it successfully copied message into the buffer
243 **/
244static s32 ixgbevf_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size)
245{
246 s32 ret_val;
247 u16 i;
248
249
250 /* lock the mailbox to prevent pf/vf race condition */
251 ret_val = ixgbevf_obtain_mbx_lock_vf(hw);
252 if (ret_val)
253 goto out_no_write;
254
255 /* flush msg and acks as we are overwriting the message buffer */
256 ixgbevf_check_for_msg_vf(hw);
257 ixgbevf_check_for_ack_vf(hw);
258
259 /* copy the caller specified message to the mailbox memory buffer */
260 for (i = 0; i < size; i++)
261 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_VFMBMEM, i, msg[i]);
262
263 /* update stats */
264 hw->mbx.stats.msgs_tx++;
265
266 /* Drop VFU and interrupt the PF to tell it a message has been sent */
267 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_REQ);
268
269out_no_write:
270 return ret_val;
271}
272
273/**
274 * ixgbevf_read_mbx_vf - Reads a message from the inbox intended for vf
275 * @hw: pointer to the HW structure
276 * @msg: The message buffer
277 * @size: Length of buffer
278 *
279 * returns 0 if it successfuly read message from buffer
280 **/
281static s32 ixgbevf_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size)
282{
283 s32 ret_val = 0;
284 u16 i;
285
286 /* lock the mailbox to prevent pf/vf race condition */
287 ret_val = ixgbevf_obtain_mbx_lock_vf(hw);
288 if (ret_val)
289 goto out_no_read;
290
291 /* copy the message from the mailbox memory buffer */
292 for (i = 0; i < size; i++)
293 msg[i] = IXGBE_READ_REG_ARRAY(hw, IXGBE_VFMBMEM, i);
294
295 /* Acknowledge receipt and release mailbox, then we're done */
296 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_ACK);
297
298 /* update stats */
299 hw->mbx.stats.msgs_rx++;
300
301out_no_read:
302 return ret_val;
303}
304
305/**
306 * ixgbevf_init_mbx_params_vf - set initial values for vf mailbox
307 * @hw: pointer to the HW structure
308 *
309 * Initializes the hw->mbx struct to correct values for vf mailbox
310 */
311static s32 ixgbevf_init_mbx_params_vf(struct ixgbe_hw *hw)
312{
313 struct ixgbe_mbx_info *mbx = &hw->mbx;
314
315 /* start mailbox as timed out and let the reset_hw call set the timeout
316 * value to begin communications */
317 mbx->timeout = 0;
318 mbx->udelay = IXGBE_VF_MBX_INIT_DELAY;
319
320 mbx->size = IXGBE_VFMAILBOX_SIZE;
321
322 mbx->stats.msgs_tx = 0;
323 mbx->stats.msgs_rx = 0;
324 mbx->stats.reqs = 0;
325 mbx->stats.acks = 0;
326 mbx->stats.rsts = 0;
327
328 return 0;
329}
330
331struct ixgbe_mbx_operations ixgbevf_mbx_ops = {
332 .init_params = ixgbevf_init_mbx_params_vf,
333 .read = ixgbevf_read_mbx_vf,
334 .write = ixgbevf_write_mbx_vf,
335 .read_posted = ixgbevf_read_posted_mbx,
336 .write_posted = ixgbevf_write_posted_mbx,
337 .check_for_msg = ixgbevf_check_for_msg_vf,
338 .check_for_ack = ixgbevf_check_for_ack_vf,
339 .check_for_rst = ixgbevf_check_for_rst_vf,
340};
341
diff --git a/drivers/net/ixgbevf/mbx.h b/drivers/net/ixgbevf/mbx.h
new file mode 100644
index 00000000000..ea393eb03f3
--- /dev/null
+++ b/drivers/net/ixgbevf/mbx.h
@@ -0,0 +1,99 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_MBX_H_
29#define _IXGBE_MBX_H_
30
31#include "vf.h"
32
33#define IXGBE_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */
34#define IXGBE_ERR_MBX -100
35
36#define IXGBE_VFMAILBOX 0x002FC
37#define IXGBE_VFMBMEM 0x00200
38
39/* Define mailbox register bits */
40#define IXGBE_VFMAILBOX_REQ 0x00000001 /* Request for PF Ready bit */
41#define IXGBE_VFMAILBOX_ACK 0x00000002 /* Ack PF message received */
42#define IXGBE_VFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
43#define IXGBE_VFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
44#define IXGBE_VFMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */
45#define IXGBE_VFMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */
46#define IXGBE_VFMAILBOX_RSTI 0x00000040 /* PF has reset indication */
47#define IXGBE_VFMAILBOX_RSTD 0x00000080 /* PF has indicated reset done */
48#define IXGBE_VFMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */
49
50#define IXGBE_PFMAILBOX(x) (0x04B00 + (4 * x))
51#define IXGBE_PFMBMEM(vfn) (0x13000 + (64 * vfn))
52
53#define IXGBE_PFMAILBOX_STS 0x00000001 /* Initiate message send to VF */
54#define IXGBE_PFMAILBOX_ACK 0x00000002 /* Ack message recv'd from VF */
55#define IXGBE_PFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
56#define IXGBE_PFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
57#define IXGBE_PFMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */
58
59#define IXGBE_MBVFICR_VFREQ_MASK 0x0000FFFF /* bits for VF messages */
60#define IXGBE_MBVFICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */
61#define IXGBE_MBVFICR_VFACK_MASK 0xFFFF0000 /* bits for VF acks */
62#define IXGBE_MBVFICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */
63
64
65/* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the
66 * PF. The reverse is true if it is IXGBE_PF_*.
67 * Message ACK's are the value or'd with 0xF0000000
68 */
69#define IXGBE_VT_MSGTYPE_ACK 0x80000000 /* Messages below or'd with
70 * this are the ACK */
71#define IXGBE_VT_MSGTYPE_NACK 0x40000000 /* Messages below or'd with
72 * this are the NACK */
73#define IXGBE_VT_MSGTYPE_CTS 0x20000000 /* Indicates that VF is still
74 * clear to send requests */
75#define IXGBE_VT_MSGINFO_SHIFT 16
76/* bits 23:16 are used for exra info for certain messages */
77#define IXGBE_VT_MSGINFO_MASK (0xFF << IXGBE_VT_MSGINFO_SHIFT)
78
79#define IXGBE_VF_RESET 0x01 /* VF requests reset */
80#define IXGBE_VF_SET_MAC_ADDR 0x02 /* VF requests PF to set MAC addr */
81#define IXGBE_VF_SET_MULTICAST 0x03 /* VF requests PF to set MC addr */
82#define IXGBE_VF_SET_VLAN 0x04 /* VF requests PF to set VLAN */
83#define IXGBE_VF_SET_LPE 0x05 /* VF requests PF to set VMOLR.LPE */
84#define IXGBE_VF_SET_MACVLAN 0x06 /* VF requests PF for unicast filter */
85
86/* length of permanent address message returned from PF */
87#define IXGBE_VF_PERMADDR_MSG_LEN 4
88/* word in permanent address message with the current multicast type */
89#define IXGBE_VF_MC_TYPE_WORD 3
90
91#define IXGBE_PF_CONTROL_MSG 0x0100 /* PF control message */
92
93#define IXGBE_VF_MBX_INIT_TIMEOUT 2000 /* number of retries on mailbox */
94#define IXGBE_VF_MBX_INIT_DELAY 500 /* microseconds between retries */
95
96/* forward declaration of the HW struct */
97struct ixgbe_hw;
98
99#endif /* _IXGBE_MBX_H_ */
diff --git a/drivers/net/ixgbevf/regs.h b/drivers/net/ixgbevf/regs.h
new file mode 100644
index 00000000000..189200eeca2
--- /dev/null
+++ b/drivers/net/ixgbevf/regs.h
@@ -0,0 +1,85 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBEVF_REGS_H_
29#define _IXGBEVF_REGS_H_
30
31#define IXGBE_VFCTRL 0x00000
32#define IXGBE_VFSTATUS 0x00008
33#define IXGBE_VFLINKS 0x00010
34#define IXGBE_VFFRTIMER 0x00048
35#define IXGBE_VFRXMEMWRAP 0x03190
36#define IXGBE_VTEICR 0x00100
37#define IXGBE_VTEICS 0x00104
38#define IXGBE_VTEIMS 0x00108
39#define IXGBE_VTEIMC 0x0010C
40#define IXGBE_VTEIAC 0x00110
41#define IXGBE_VTEIAM 0x00114
42#define IXGBE_VTEITR(x) (0x00820 + (4 * x))
43#define IXGBE_VTIVAR(x) (0x00120 + (4 * x))
44#define IXGBE_VTIVAR_MISC 0x00140
45#define IXGBE_VTRSCINT(x) (0x00180 + (4 * x))
46#define IXGBE_VFRDBAL(x) (0x01000 + (0x40 * x))
47#define IXGBE_VFRDBAH(x) (0x01004 + (0x40 * x))
48#define IXGBE_VFRDLEN(x) (0x01008 + (0x40 * x))
49#define IXGBE_VFRDH(x) (0x01010 + (0x40 * x))
50#define IXGBE_VFRDT(x) (0x01018 + (0x40 * x))
51#define IXGBE_VFRXDCTL(x) (0x01028 + (0x40 * x))
52#define IXGBE_VFSRRCTL(x) (0x01014 + (0x40 * x))
53#define IXGBE_VFRSCCTL(x) (0x0102C + (0x40 * x))
54#define IXGBE_VFPSRTYPE 0x00300
55#define IXGBE_VFTDBAL(x) (0x02000 + (0x40 * x))
56#define IXGBE_VFTDBAH(x) (0x02004 + (0x40 * x))
57#define IXGBE_VFTDLEN(x) (0x02008 + (0x40 * x))
58#define IXGBE_VFTDH(x) (0x02010 + (0x40 * x))
59#define IXGBE_VFTDT(x) (0x02018 + (0x40 * x))
60#define IXGBE_VFTXDCTL(x) (0x02028 + (0x40 * x))
61#define IXGBE_VFTDWBAL(x) (0x02038 + (0x40 * x))
62#define IXGBE_VFTDWBAH(x) (0x0203C + (0x40 * x))
63#define IXGBE_VFDCA_RXCTRL(x) (0x0100C + (0x40 * x))
64#define IXGBE_VFDCA_TXCTRL(x) (0x0200c + (0x40 * x))
65#define IXGBE_VFGPRC 0x0101C
66#define IXGBE_VFGPTC 0x0201C
67#define IXGBE_VFGORC_LSB 0x01020
68#define IXGBE_VFGORC_MSB 0x01024
69#define IXGBE_VFGOTC_LSB 0x02020
70#define IXGBE_VFGOTC_MSB 0x02024
71#define IXGBE_VFMPRC 0x01034
72
73#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
74
75#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
76
77#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \
78 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
79
80#define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \
81 readl((a)->hw_addr + (reg) + ((offset) << 2)))
82
83#define IXGBE_WRITE_FLUSH(a) (IXGBE_READ_REG(a, IXGBE_VFSTATUS))
84
85#endif /* _IXGBEVF_REGS_H_ */
diff --git a/drivers/net/ixgbevf/vf.c b/drivers/net/ixgbevf/vf.c
new file mode 100644
index 00000000000..aa3682e8c47
--- /dev/null
+++ b/drivers/net/ixgbevf/vf.c
@@ -0,0 +1,426 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include "vf.h"
29
30/**
31 * ixgbevf_start_hw_vf - Prepare hardware for Tx/Rx
32 * @hw: pointer to hardware structure
33 *
34 * Starts the hardware by filling the bus info structure and media type, clears
35 * all on chip counters, initializes receive address registers, multicast
36 * table, VLAN filter table, calls routine to set up link and flow control
37 * settings, and leaves transmit and receive units disabled and uninitialized
38 **/
39static s32 ixgbevf_start_hw_vf(struct ixgbe_hw *hw)
40{
41 /* Clear adapter stopped flag */
42 hw->adapter_stopped = false;
43
44 return 0;
45}
46
47/**
48 * ixgbevf_init_hw_vf - virtual function hardware initialization
49 * @hw: pointer to hardware structure
50 *
51 * Initialize the hardware by resetting the hardware and then starting
52 * the hardware
53 **/
54static s32 ixgbevf_init_hw_vf(struct ixgbe_hw *hw)
55{
56 s32 status = hw->mac.ops.start_hw(hw);
57
58 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
59
60 return status;
61}
62
63/**
64 * ixgbevf_reset_hw_vf - Performs hardware reset
65 * @hw: pointer to hardware structure
66 *
67 * Resets the hardware by reseting the transmit and receive units, masks and
68 * clears all interrupts.
69 **/
70static s32 ixgbevf_reset_hw_vf(struct ixgbe_hw *hw)
71{
72 struct ixgbe_mbx_info *mbx = &hw->mbx;
73 u32 timeout = IXGBE_VF_INIT_TIMEOUT;
74 s32 ret_val = IXGBE_ERR_INVALID_MAC_ADDR;
75 u32 msgbuf[IXGBE_VF_PERMADDR_MSG_LEN];
76 u8 *addr = (u8 *)(&msgbuf[1]);
77
78 /* Call adapter stop to disable tx/rx and clear interrupts */
79 hw->mac.ops.stop_adapter(hw);
80
81 IXGBE_WRITE_REG(hw, IXGBE_VFCTRL, IXGBE_CTRL_RST);
82 IXGBE_WRITE_FLUSH(hw);
83
84 /* we cannot reset while the RSTI / RSTD bits are asserted */
85 while (!mbx->ops.check_for_rst(hw) && timeout) {
86 timeout--;
87 udelay(5);
88 }
89
90 if (!timeout)
91 return IXGBE_ERR_RESET_FAILED;
92
93 /* mailbox timeout can now become active */
94 mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT;
95
96 msgbuf[0] = IXGBE_VF_RESET;
97 mbx->ops.write_posted(hw, msgbuf, 1);
98
99 msleep(10);
100
101 /* set our "perm_addr" based on info provided by PF */
102 /* also set up the mc_filter_type which is piggy backed
103 * on the mac address in word 3 */
104 ret_val = mbx->ops.read_posted(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN);
105 if (ret_val)
106 return ret_val;
107
108 if (msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK))
109 return IXGBE_ERR_INVALID_MAC_ADDR;
110
111 memcpy(hw->mac.perm_addr, addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
112 hw->mac.mc_filter_type = msgbuf[IXGBE_VF_MC_TYPE_WORD];
113
114 return 0;
115}
116
117/**
118 * ixgbevf_stop_hw_vf - Generic stop Tx/Rx units
119 * @hw: pointer to hardware structure
120 *
121 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
122 * disables transmit and receive units. The adapter_stopped flag is used by
123 * the shared code and drivers to determine if the adapter is in a stopped
124 * state and should not touch the hardware.
125 **/
126static s32 ixgbevf_stop_hw_vf(struct ixgbe_hw *hw)
127{
128 u32 number_of_queues;
129 u32 reg_val;
130 u16 i;
131
132 /*
133 * Set the adapter_stopped flag so other driver functions stop touching
134 * the hardware
135 */
136 hw->adapter_stopped = true;
137
138 /* Disable the receive unit by stopped each queue */
139 number_of_queues = hw->mac.max_rx_queues;
140 for (i = 0; i < number_of_queues; i++) {
141 reg_val = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
142 if (reg_val & IXGBE_RXDCTL_ENABLE) {
143 reg_val &= ~IXGBE_RXDCTL_ENABLE;
144 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val);
145 }
146 }
147
148 IXGBE_WRITE_FLUSH(hw);
149
150 /* Clear interrupt mask to stop from interrupts being generated */
151 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
152
153 /* Clear any pending interrupts */
154 IXGBE_READ_REG(hw, IXGBE_VTEICR);
155
156 /* Disable the transmit unit. Each queue must be disabled. */
157 number_of_queues = hw->mac.max_tx_queues;
158 for (i = 0; i < number_of_queues; i++) {
159 reg_val = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
160 if (reg_val & IXGBE_TXDCTL_ENABLE) {
161 reg_val &= ~IXGBE_TXDCTL_ENABLE;
162 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), reg_val);
163 }
164 }
165
166 return 0;
167}
168
169/**
170 * ixgbevf_mta_vector - Determines bit-vector in multicast table to set
171 * @hw: pointer to hardware structure
172 * @mc_addr: the multicast address
173 *
174 * Extracts the 12 bits, from a multicast address, to determine which
175 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
176 * incoming rx multicast addresses, to determine the bit-vector to check in
177 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
178 * by the MO field of the MCSTCTRL. The MO field is set during initialization
179 * to mc_filter_type.
180 **/
181static s32 ixgbevf_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
182{
183 u32 vector = 0;
184
185 switch (hw->mac.mc_filter_type) {
186 case 0: /* use bits [47:36] of the address */
187 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
188 break;
189 case 1: /* use bits [46:35] of the address */
190 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
191 break;
192 case 2: /* use bits [45:34] of the address */
193 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
194 break;
195 case 3: /* use bits [43:32] of the address */
196 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
197 break;
198 default: /* Invalid mc_filter_type */
199 break;
200 }
201
202 /* vector can only be 12-bits or boundary will be exceeded */
203 vector &= 0xFFF;
204 return vector;
205}
206
207/**
208 * ixgbevf_get_mac_addr_vf - Read device MAC address
209 * @hw: pointer to the HW structure
210 * @mac_addr: pointer to storage for retrieved MAC address
211 **/
212static s32 ixgbevf_get_mac_addr_vf(struct ixgbe_hw *hw, u8 *mac_addr)
213{
214 memcpy(mac_addr, hw->mac.perm_addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
215
216 return 0;
217}
218
219static s32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr)
220{
221 struct ixgbe_mbx_info *mbx = &hw->mbx;
222 u32 msgbuf[3];
223 u8 *msg_addr = (u8 *)(&msgbuf[1]);
224 s32 ret_val;
225
226 memset(msgbuf, 0, sizeof(msgbuf));
227 /*
228 * If index is one then this is the start of a new list and needs
229 * indication to the PF so it can do it's own list management.
230 * If it is zero then that tells the PF to just clear all of
231 * this VF's macvlans and there is no new list.
232 */
233 msgbuf[0] |= index << IXGBE_VT_MSGINFO_SHIFT;
234 msgbuf[0] |= IXGBE_VF_SET_MACVLAN;
235 if (addr)
236 memcpy(msg_addr, addr, 6);
237 ret_val = mbx->ops.write_posted(hw, msgbuf, 3);
238
239 if (!ret_val)
240 ret_val = mbx->ops.read_posted(hw, msgbuf, 3);
241
242 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
243
244 if (!ret_val)
245 if (msgbuf[0] ==
246 (IXGBE_VF_SET_MACVLAN | IXGBE_VT_MSGTYPE_NACK))
247 ret_val = -ENOMEM;
248
249 return ret_val;
250}
251
252/**
253 * ixgbevf_set_rar_vf - set device MAC address
254 * @hw: pointer to hardware structure
255 * @index: Receive address register to write
256 * @addr: Address to put into receive address register
257 * @vmdq: Unused in this implementation
258 **/
259static s32 ixgbevf_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr,
260 u32 vmdq)
261{
262 struct ixgbe_mbx_info *mbx = &hw->mbx;
263 u32 msgbuf[3];
264 u8 *msg_addr = (u8 *)(&msgbuf[1]);
265 s32 ret_val;
266
267 memset(msgbuf, 0, sizeof(msgbuf));
268 msgbuf[0] = IXGBE_VF_SET_MAC_ADDR;
269 memcpy(msg_addr, addr, 6);
270 ret_val = mbx->ops.write_posted(hw, msgbuf, 3);
271
272 if (!ret_val)
273 ret_val = mbx->ops.read_posted(hw, msgbuf, 3);
274
275 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
276
277 /* if nacked the address was rejected, use "perm_addr" */
278 if (!ret_val &&
279 (msgbuf[0] == (IXGBE_VF_SET_MAC_ADDR | IXGBE_VT_MSGTYPE_NACK)))
280 ixgbevf_get_mac_addr_vf(hw, hw->mac.addr);
281
282 return ret_val;
283}
284
285/**
286 * ixgbevf_update_mc_addr_list_vf - Update Multicast addresses
287 * @hw: pointer to the HW structure
288 * @netdev: pointer to net device structure
289 *
290 * Updates the Multicast Table Array.
291 **/
292static s32 ixgbevf_update_mc_addr_list_vf(struct ixgbe_hw *hw,
293 struct net_device *netdev)
294{
295 struct netdev_hw_addr *ha;
296 struct ixgbe_mbx_info *mbx = &hw->mbx;
297 u32 msgbuf[IXGBE_VFMAILBOX_SIZE];
298 u16 *vector_list = (u16 *)&msgbuf[1];
299 u32 cnt, i;
300
301 /* Each entry in the list uses 1 16 bit word. We have 30
302 * 16 bit words available in our HW msg buffer (minus 1 for the
303 * msg type). That's 30 hash values if we pack 'em right. If
304 * there are more than 30 MC addresses to add then punt the
305 * extras for now and then add code to handle more than 30 later.
306 * It would be unusual for a server to request that many multi-cast
307 * addresses except for in large enterprise network environments.
308 */
309
310 cnt = netdev_mc_count(netdev);
311 if (cnt > 30)
312 cnt = 30;
313 msgbuf[0] = IXGBE_VF_SET_MULTICAST;
314 msgbuf[0] |= cnt << IXGBE_VT_MSGINFO_SHIFT;
315
316 i = 0;
317 netdev_for_each_mc_addr(ha, netdev) {
318 if (i == cnt)
319 break;
320 vector_list[i++] = ixgbevf_mta_vector(hw, ha->addr);
321 }
322
323 mbx->ops.write_posted(hw, msgbuf, IXGBE_VFMAILBOX_SIZE);
324
325 return 0;
326}
327
328/**
329 * ixgbevf_set_vfta_vf - Set/Unset vlan filter table address
330 * @hw: pointer to the HW structure
331 * @vlan: 12 bit VLAN ID
332 * @vind: unused by VF drivers
333 * @vlan_on: if true then set bit, else clear bit
334 **/
335static s32 ixgbevf_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
336 bool vlan_on)
337{
338 struct ixgbe_mbx_info *mbx = &hw->mbx;
339 u32 msgbuf[2];
340
341 msgbuf[0] = IXGBE_VF_SET_VLAN;
342 msgbuf[1] = vlan;
343 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
344 msgbuf[0] |= vlan_on << IXGBE_VT_MSGINFO_SHIFT;
345
346 return mbx->ops.write_posted(hw, msgbuf, 2);
347}
348
349/**
350 * ixgbevf_setup_mac_link_vf - Setup MAC link settings
351 * @hw: pointer to hardware structure
352 * @speed: Unused in this implementation
353 * @autoneg: Unused in this implementation
354 * @autoneg_wait_to_complete: Unused in this implementation
355 *
356 * Do nothing and return success. VF drivers are not allowed to change
357 * global settings. Maintained for driver compatibility.
358 **/
359static s32 ixgbevf_setup_mac_link_vf(struct ixgbe_hw *hw,
360 ixgbe_link_speed speed, bool autoneg,
361 bool autoneg_wait_to_complete)
362{
363 return 0;
364}
365
366/**
367 * ixgbevf_check_mac_link_vf - Get link/speed status
368 * @hw: pointer to hardware structure
369 * @speed: pointer to link speed
370 * @link_up: true is link is up, false otherwise
371 * @autoneg_wait_to_complete: true when waiting for completion is needed
372 *
373 * Reads the links register to determine if link is up and the current speed
374 **/
375static s32 ixgbevf_check_mac_link_vf(struct ixgbe_hw *hw,
376 ixgbe_link_speed *speed,
377 bool *link_up,
378 bool autoneg_wait_to_complete)
379{
380 u32 links_reg;
381
382 if (!(hw->mbx.ops.check_for_rst(hw))) {
383 *link_up = false;
384 *speed = 0;
385 return -1;
386 }
387
388 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
389
390 if (links_reg & IXGBE_LINKS_UP)
391 *link_up = true;
392 else
393 *link_up = false;
394
395 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
396 IXGBE_LINKS_SPEED_10G_82599)
397 *speed = IXGBE_LINK_SPEED_10GB_FULL;
398 else
399 *speed = IXGBE_LINK_SPEED_1GB_FULL;
400
401 return 0;
402}
403
404static struct ixgbe_mac_operations ixgbevf_mac_ops = {
405 .init_hw = ixgbevf_init_hw_vf,
406 .reset_hw = ixgbevf_reset_hw_vf,
407 .start_hw = ixgbevf_start_hw_vf,
408 .get_mac_addr = ixgbevf_get_mac_addr_vf,
409 .stop_adapter = ixgbevf_stop_hw_vf,
410 .setup_link = ixgbevf_setup_mac_link_vf,
411 .check_link = ixgbevf_check_mac_link_vf,
412 .set_rar = ixgbevf_set_rar_vf,
413 .update_mc_addr_list = ixgbevf_update_mc_addr_list_vf,
414 .set_uc_addr = ixgbevf_set_uc_addr_vf,
415 .set_vfta = ixgbevf_set_vfta_vf,
416};
417
418struct ixgbevf_info ixgbevf_82599_vf_info = {
419 .mac = ixgbe_mac_82599_vf,
420 .mac_ops = &ixgbevf_mac_ops,
421};
422
423struct ixgbevf_info ixgbevf_X540_vf_info = {
424 .mac = ixgbe_mac_X540_vf,
425 .mac_ops = &ixgbevf_mac_ops,
426};
diff --git a/drivers/net/ixgbevf/vf.h b/drivers/net/ixgbevf/vf.h
new file mode 100644
index 00000000000..10306b492ee
--- /dev/null
+++ b/drivers/net/ixgbevf/vf.h
@@ -0,0 +1,174 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef __IXGBE_VF_H__
29#define __IXGBE_VF_H__
30
31#include <linux/pci.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
34#include <linux/if_ether.h>
35#include <linux/netdevice.h>
36
37#include "defines.h"
38#include "regs.h"
39#include "mbx.h"
40
41struct ixgbe_hw;
42
43/* iterator type for walking multicast address lists */
44typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
45 u32 *vmdq);
46struct ixgbe_mac_operations {
47 s32 (*init_hw)(struct ixgbe_hw *);
48 s32 (*reset_hw)(struct ixgbe_hw *);
49 s32 (*start_hw)(struct ixgbe_hw *);
50 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
51 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
52 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
53 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
54 s32 (*stop_adapter)(struct ixgbe_hw *);
55 s32 (*get_bus_info)(struct ixgbe_hw *);
56
57 /* Link */
58 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
59 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
60 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
61 bool *);
62
63 /* RAR, Multicast, VLAN */
64 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32);
65 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
66 s32 (*init_rx_addrs)(struct ixgbe_hw *);
67 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
68 s32 (*enable_mc)(struct ixgbe_hw *);
69 s32 (*disable_mc)(struct ixgbe_hw *);
70 s32 (*clear_vfta)(struct ixgbe_hw *);
71 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
72};
73
74enum ixgbe_mac_type {
75 ixgbe_mac_unknown = 0,
76 ixgbe_mac_82599_vf,
77 ixgbe_mac_X540_vf,
78 ixgbe_num_macs
79};
80
81struct ixgbe_mac_info {
82 struct ixgbe_mac_operations ops;
83 u8 addr[6];
84 u8 perm_addr[6];
85
86 enum ixgbe_mac_type type;
87
88 s32 mc_filter_type;
89
90 bool get_link_status;
91 u32 max_tx_queues;
92 u32 max_rx_queues;
93 u32 max_msix_vectors;
94};
95
96struct ixgbe_mbx_operations {
97 s32 (*init_params)(struct ixgbe_hw *hw);
98 s32 (*read)(struct ixgbe_hw *, u32 *, u16);
99 s32 (*write)(struct ixgbe_hw *, u32 *, u16);
100 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16);
101 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16);
102 s32 (*check_for_msg)(struct ixgbe_hw *);
103 s32 (*check_for_ack)(struct ixgbe_hw *);
104 s32 (*check_for_rst)(struct ixgbe_hw *);
105};
106
107struct ixgbe_mbx_stats {
108 u32 msgs_tx;
109 u32 msgs_rx;
110
111 u32 acks;
112 u32 reqs;
113 u32 rsts;
114};
115
116struct ixgbe_mbx_info {
117 struct ixgbe_mbx_operations ops;
118 struct ixgbe_mbx_stats stats;
119 u32 timeout;
120 u32 udelay;
121 u32 v2p_mailbox;
122 u16 size;
123};
124
125struct ixgbe_hw {
126 void *back;
127
128 u8 __iomem *hw_addr;
129
130 struct ixgbe_mac_info mac;
131 struct ixgbe_mbx_info mbx;
132
133 u16 device_id;
134 u16 subsystem_vendor_id;
135 u16 subsystem_device_id;
136 u16 vendor_id;
137
138 u8 revision_id;
139 bool adapter_stopped;
140};
141
142struct ixgbevf_hw_stats {
143 u64 base_vfgprc;
144 u64 base_vfgptc;
145 u64 base_vfgorc;
146 u64 base_vfgotc;
147 u64 base_vfmprc;
148
149 u64 last_vfgprc;
150 u64 last_vfgptc;
151 u64 last_vfgorc;
152 u64 last_vfgotc;
153 u64 last_vfmprc;
154
155 u64 vfgprc;
156 u64 vfgptc;
157 u64 vfgorc;
158 u64 vfgotc;
159 u64 vfmprc;
160
161 u64 saved_reset_vfgprc;
162 u64 saved_reset_vfgptc;
163 u64 saved_reset_vfgorc;
164 u64 saved_reset_vfgotc;
165 u64 saved_reset_vfmprc;
166};
167
168struct ixgbevf_info {
169 enum ixgbe_mac_type mac;
170 struct ixgbe_mac_operations *mac_ops;
171};
172
173#endif /* __IXGBE_VF_H__ */
174
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-17 11:18:47 -0400