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authorJesse Brandeburg <jesse.brandeburg@intel.com>2009-03-13 18:14:30 -0400
committerDavid S. Miller <davem@davemloft.net>2009-03-14 15:41:11 -0400
commit2a41ff81162c7c406bb2a04e425a7ed51c85d89d (patch)
tree561dbcbdc8ae5280c3e4bbd059a17f8ba9659bb4 /drivers/net/ixgbe/ixgbe_main.c
parent9a1a69adad69ce4e85c9cbb40a3f960a7cb015cf (diff)
ixgbe: Cleanup on the Rx init path
This cleans up the following pieces of the Rx initialization path: - Enable the ECC memory fault interrupt in OTHER causes. - Fix an 82598 initialization of RDRXCTL when depending on RSS and VMDq to be enabled. We don't need these features enabled to safely set the MVMEN bit to allow multiple SRRCTL register mappings into the RXDCTL registers. - Fix the RSS initialization path to not stomp on DCB accidentally. When configuring the MRQC (multiple Rx queue contol) register, we want to make sure we only OR in features as necessary, instead of full assignment. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_main.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c29
1 files changed, 14 insertions, 15 deletions
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index d5563e4d3b3..39781c84daf 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -1464,6 +1464,7 @@ static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1464 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 1464 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1465 mask |= IXGBE_EIMS_GPI_SDP1; 1465 mask |= IXGBE_EIMS_GPI_SDP1;
1466 if (adapter->hw.mac.type == ixgbe_mac_82599EB) { 1466 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1467 mask |= IXGBE_EIMS_ECC;
1467 mask |= IXGBE_EIMS_GPI_SDP1; 1468 mask |= IXGBE_EIMS_GPI_SDP1;
1468 mask |= IXGBE_EIMS_GPI_SDP2; 1469 mask |= IXGBE_EIMS_GPI_SDP2;
1469 } 1470 }
@@ -1795,12 +1796,9 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1795 * effects of setting this bit are only that SRRCTL must be 1796 * effects of setting this bit are only that SRRCTL must be
1796 * fully programmed [0..15] 1797 * fully programmed [0..15]
1797 */ 1798 */
1798 if (adapter->flags & 1799 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1799 (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) { 1800 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1800 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 1801 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1801 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1802 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1803 }
1804 } 1802 }
1805 1803
1806 /* Program MRQC for the distribution of queues */ 1804 /* Program MRQC for the distribution of queues */
@@ -1837,16 +1835,17 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1837 for (i = 0; i < 10; i++) 1835 for (i = 0; i < 10; i++)
1838 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); 1836 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1839 1837
1840 mrqc = IXGBE_MRQC_RSSEN 1838 if (hw->mac.type == ixgbe_mac_82598EB)
1839 mrqc |= IXGBE_MRQC_RSSEN;
1841 /* Perform hash on these packet types */ 1840 /* Perform hash on these packet types */
1842 | IXGBE_MRQC_RSS_FIELD_IPV4 1841 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1843 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 1842 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1844 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP 1843 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1845 | IXGBE_MRQC_RSS_FIELD_IPV6 1844 | IXGBE_MRQC_RSS_FIELD_IPV6
1846 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP 1845 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1847 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 1846 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1848 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 1847 }
1849 } 1848 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1850 1849
1851 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 1850 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1852 1851