diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
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committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
commit | fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch) | |
tree | a57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/net/ixgbe/ixgbe_dcb.h | |
parent | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff) |
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_dcb.h')
-rw-r--r-- | drivers/net/ixgbe/ixgbe_dcb.h | 167 |
1 files changed, 167 insertions, 0 deletions
diff --git a/drivers/net/ixgbe/ixgbe_dcb.h b/drivers/net/ixgbe/ixgbe_dcb.h new file mode 100644 index 00000000000..e85826ae032 --- /dev/null +++ b/drivers/net/ixgbe/ixgbe_dcb.h | |||
@@ -0,0 +1,167 @@ | |||
1 | /******************************************************************************* | ||
2 | |||
3 | Intel 10 Gigabit PCI Express Linux driver | ||
4 | Copyright(c) 1999 - 2011 Intel Corporation. | ||
5 | |||
6 | This program is free software; you can redistribute it and/or modify it | ||
7 | under the terms and conditions of the GNU General Public License, | ||
8 | version 2, as published by the Free Software Foundation. | ||
9 | |||
10 | This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | more details. | ||
14 | |||
15 | You should have received a copy of the GNU General Public License along with | ||
16 | this program; if not, write to the Free Software Foundation, Inc., | ||
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
18 | |||
19 | The full GNU General Public License is included in this distribution in | ||
20 | the file called "COPYING". | ||
21 | |||
22 | Contact Information: | ||
23 | Linux NICS <linux.nics@intel.com> | ||
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | ||
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | ||
26 | |||
27 | *******************************************************************************/ | ||
28 | |||
29 | #ifndef _DCB_CONFIG_H_ | ||
30 | #define _DCB_CONFIG_H_ | ||
31 | |||
32 | #include "ixgbe_type.h" | ||
33 | |||
34 | /* DCB data structures */ | ||
35 | |||
36 | #define IXGBE_MAX_PACKET_BUFFERS 8 | ||
37 | #define MAX_USER_PRIORITY 8 | ||
38 | #define MAX_TRAFFIC_CLASS 8 | ||
39 | #define MAX_BW_GROUP 8 | ||
40 | #define BW_PERCENT 100 | ||
41 | |||
42 | #define DCB_TX_CONFIG 0 | ||
43 | #define DCB_RX_CONFIG 1 | ||
44 | |||
45 | /* DCB error Codes */ | ||
46 | #define DCB_SUCCESS 0 | ||
47 | #define DCB_ERR_CONFIG -1 | ||
48 | #define DCB_ERR_PARAM -2 | ||
49 | |||
50 | /* Transmit and receive Errors */ | ||
51 | /* Error in bandwidth group allocation */ | ||
52 | #define DCB_ERR_BW_GROUP -3 | ||
53 | /* Error in traffic class bandwidth allocation */ | ||
54 | #define DCB_ERR_TC_BW -4 | ||
55 | /* Traffic class has both link strict and group strict enabled */ | ||
56 | #define DCB_ERR_LS_GS -5 | ||
57 | /* Link strict traffic class has non zero bandwidth */ | ||
58 | #define DCB_ERR_LS_BW_NONZERO -6 | ||
59 | /* Link strict bandwidth group has non zero bandwidth */ | ||
60 | #define DCB_ERR_LS_BWG_NONZERO -7 | ||
61 | /* Traffic class has zero bandwidth */ | ||
62 | #define DCB_ERR_TC_BW_ZERO -8 | ||
63 | |||
64 | #define DCB_NOT_IMPLEMENTED 0x7FFFFFFF | ||
65 | |||
66 | struct dcb_pfc_tc_debug { | ||
67 | u8 tc; | ||
68 | u8 pause_status; | ||
69 | u64 pause_quanta; | ||
70 | }; | ||
71 | |||
72 | enum strict_prio_type { | ||
73 | prio_none = 0, | ||
74 | prio_group, | ||
75 | prio_link | ||
76 | }; | ||
77 | |||
78 | /* DCB capability definitions */ | ||
79 | #define IXGBE_DCB_PG_SUPPORT 0x00000001 | ||
80 | #define IXGBE_DCB_PFC_SUPPORT 0x00000002 | ||
81 | #define IXGBE_DCB_BCN_SUPPORT 0x00000004 | ||
82 | #define IXGBE_DCB_UP2TC_SUPPORT 0x00000008 | ||
83 | #define IXGBE_DCB_GSP_SUPPORT 0x00000010 | ||
84 | |||
85 | #define IXGBE_DCB_8_TC_SUPPORT 0x80 | ||
86 | |||
87 | struct dcb_support { | ||
88 | /* DCB capabilities */ | ||
89 | u32 capabilities; | ||
90 | |||
91 | /* Each bit represents a number of TCs configurable in the hw. | ||
92 | * If 8 traffic classes can be configured, the value is 0x80. | ||
93 | */ | ||
94 | u8 traffic_classes; | ||
95 | u8 pfc_traffic_classes; | ||
96 | }; | ||
97 | |||
98 | /* Traffic class bandwidth allocation per direction */ | ||
99 | struct tc_bw_alloc { | ||
100 | u8 bwg_id; /* Bandwidth Group (BWG) ID */ | ||
101 | u8 bwg_percent; /* % of BWG's bandwidth */ | ||
102 | u8 link_percent; /* % of link bandwidth */ | ||
103 | u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ | ||
104 | u16 data_credits_refill; /* Credit refill amount in 64B granularity */ | ||
105 | u16 data_credits_max; /* Max credits for a configured packet buffer | ||
106 | * in 64B granularity.*/ | ||
107 | enum strict_prio_type prio_type; /* Link or Group Strict Priority */ | ||
108 | }; | ||
109 | |||
110 | enum dcb_pfc_type { | ||
111 | pfc_disabled = 0, | ||
112 | pfc_enabled_full, | ||
113 | pfc_enabled_tx, | ||
114 | pfc_enabled_rx | ||
115 | }; | ||
116 | |||
117 | /* Traffic class configuration */ | ||
118 | struct tc_configuration { | ||
119 | struct tc_bw_alloc path[2]; /* One each for Tx/Rx */ | ||
120 | enum dcb_pfc_type dcb_pfc; /* Class based flow control setting */ | ||
121 | |||
122 | u16 desc_credits_max; /* For Tx Descriptor arbitration */ | ||
123 | u8 tc; /* Traffic class (TC) */ | ||
124 | }; | ||
125 | |||
126 | struct dcb_num_tcs { | ||
127 | u8 pg_tcs; | ||
128 | u8 pfc_tcs; | ||
129 | }; | ||
130 | |||
131 | struct ixgbe_dcb_config { | ||
132 | struct dcb_support support; | ||
133 | struct dcb_num_tcs num_tcs; | ||
134 | struct tc_configuration tc_config[MAX_TRAFFIC_CLASS]; | ||
135 | u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */ | ||
136 | bool pfc_mode_enable; | ||
137 | |||
138 | u32 dcb_cfg_version; /* Not used...OS-specific? */ | ||
139 | u32 link_speed; /* For bandwidth allocation validation purpose */ | ||
140 | }; | ||
141 | |||
142 | /* DCB driver APIs */ | ||
143 | void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en); | ||
144 | void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *, int, u16 *); | ||
145 | void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *, u16 *); | ||
146 | void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *, int, u8 *); | ||
147 | void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *, int, u8 *); | ||
148 | |||
149 | /* DCB credits calculation */ | ||
150 | s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill, __u16 *max, int max_frame); | ||
151 | s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *, | ||
152 | struct ixgbe_dcb_config *, int, u8); | ||
153 | |||
154 | /* DCB hw initialization */ | ||
155 | s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, u16 *refill, u16 *max, | ||
156 | u8 *bwg_id, u8 *prio_type, u8 *tc_prio); | ||
157 | s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en); | ||
158 | s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *); | ||
159 | |||
160 | /* DCB definitions for credit calculation */ | ||
161 | #define DCB_CREDIT_QUANTUM 64 /* DCB Quantum */ | ||
162 | #define MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */ | ||
163 | #define DCB_MAX_TSO_SIZE (32*1024) /* MAX TSO packet size supported in DCB mode */ | ||
164 | #define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */ | ||
165 | #define MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1204 / 64B */ | ||
166 | |||
167 | #endif /* _DCB_CONFIG_H */ | ||