ixgbe: consolidate packet buffer allocation

Consolidate packet buffer allocation currently being
done in the DCB path and main path. This allows the
feature set and packet buffer requirements to be done
once.

This is prep work to allow DCB to coexist with other
features namely, flow director.

CC: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 1 insertions, 38 deletions

diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index 0d7bc915635..324a5051f81 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -1114,27 +1114,8 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
 {
         u32 fdirctrl = 0;
-        u32 pbsize;
         int i;
 
-        /*
-         * Before enabling Flow Director, the Rx Packet Buffer size
-         * must be reduced.  The new value is the current size minus
-         * flow director memory usage size.
-         */
-        pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
-        IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
-            (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
-
-        /*
-         * The defaults in the HW for RX PB 1-7 are not zero and so should be
-         * initialized to zero for non DCB mode otherwise actual total RX PB
-         * would be bigger than programmed and filter space would run into
-         * the PB 0 region.
-         */
-        for (i = 1; i < 8; i++)
-                IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
-
         /* Send interrupt when 64 filters are left */
         fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
 
@@ -1202,27 +1183,8 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
 {
         u32 fdirctrl = 0;
-        u32 pbsize;
         int i;
 
-        /*
-         * Before enabling Flow Director, the Rx Packet Buffer size
-         * must be reduced.  The new value is the current size minus
-         * flow director memory usage size.
-         */
-        pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
-        IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
-            (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
-
-        /*
-         * The defaults in the HW for RX PB 1-7 are not zero and so should be
-         * initialized to zero for non DCB mode otherwise actual total RX PB
-         * would be bigger than programmed and filter space would run into
-         * the PB 0 region.
-         */
-        for (i = 1; i < 8; i++)
-                IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
-
         /* Send interrupt when 64 filters are left */
         fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
 
@@ -2146,6 +2108,7 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
         .read_analog_reg8       = &ixgbe_read_analog_reg8_82599,
         .write_analog_reg8      = &ixgbe_write_analog_reg8_82599,
         .setup_link             = &ixgbe_setup_mac_link_82599,
+        .set_rxpba              = &ixgbe_set_rxpba_generic,
         .check_link             = &ixgbe_check_mac_link_generic,
         .get_link_capabilities  = &ixgbe_get_link_capabilities_82599,
         .led_on                 = &ixgbe_led_on_generic,