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authorJoe Perches <joe@perches.com>2010-05-14 03:19:28 -0400
committerDavid S. Miller <davem@davemloft.net>2010-05-14 03:19:28 -0400
commita4b770972b8f819e408d7cc3ae9637e15bff62f6 (patch)
tree62e3c413b084c106d750cf6cc0701709cde30100 /drivers/net/ixgb
parent21ce849ba5cc178740c6532ba3dded852296ad91 (diff)
drivers/net: Remove unnecessary returns from void function()s
This patch removes from drivers/net/ all the unnecessary return; statements that precede the last closing brace of void functions. It does not remove the returns that are immediately preceded by a label as gcc doesn't like that. It also does not remove null void functions with return. Done via: $ grep -rP --include=*.[ch] -l "return;\n}" net/ | \ xargs perl -i -e 'local $/ ; while (<>) { s/\n[ \t\n]+return;\n}/\n}/g; print; }' with some cleanups by hand. Compile tested x86 allmodconfig only. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgb')
-rw-r--r--drivers/net/ixgb/ixgb_ee.c10
-rw-r--r--drivers/net/ixgb/ixgb_hw.c17
2 files changed, 0 insertions, 27 deletions
diff --git a/drivers/net/ixgb/ixgb_ee.c b/drivers/net/ixgb/ixgb_ee.c
index 06303a36aaf..813993f9c65 100644
--- a/drivers/net/ixgb/ixgb_ee.c
+++ b/drivers/net/ixgb/ixgb_ee.c
@@ -58,7 +58,6 @@ ixgb_raise_clock(struct ixgb_hw *hw,
58 *eecd_reg = *eecd_reg | IXGB_EECD_SK; 58 *eecd_reg = *eecd_reg | IXGB_EECD_SK;
59 IXGB_WRITE_REG(hw, EECD, *eecd_reg); 59 IXGB_WRITE_REG(hw, EECD, *eecd_reg);
60 udelay(50); 60 udelay(50);
61 return;
62} 61}
63 62
64/****************************************************************************** 63/******************************************************************************
@@ -77,7 +76,6 @@ ixgb_lower_clock(struct ixgb_hw *hw,
77 *eecd_reg = *eecd_reg & ~IXGB_EECD_SK; 76 *eecd_reg = *eecd_reg & ~IXGB_EECD_SK;
78 IXGB_WRITE_REG(hw, EECD, *eecd_reg); 77 IXGB_WRITE_REG(hw, EECD, *eecd_reg);
79 udelay(50); 78 udelay(50);
80 return;
81} 79}
82 80
83/****************************************************************************** 81/******************************************************************************
@@ -127,7 +125,6 @@ ixgb_shift_out_bits(struct ixgb_hw *hw,
127 /* We leave the "DI" bit set to "0" when we leave this routine. */ 125 /* We leave the "DI" bit set to "0" when we leave this routine. */
128 eecd_reg &= ~IXGB_EECD_DI; 126 eecd_reg &= ~IXGB_EECD_DI;
129 IXGB_WRITE_REG(hw, EECD, eecd_reg); 127 IXGB_WRITE_REG(hw, EECD, eecd_reg);
130 return;
131} 128}
132 129
133/****************************************************************************** 130/******************************************************************************
@@ -192,7 +189,6 @@ ixgb_setup_eeprom(struct ixgb_hw *hw)
192 /* Set CS */ 189 /* Set CS */
193 eecd_reg |= IXGB_EECD_CS; 190 eecd_reg |= IXGB_EECD_CS;
194 IXGB_WRITE_REG(hw, EECD, eecd_reg); 191 IXGB_WRITE_REG(hw, EECD, eecd_reg);
195 return;
196} 192}
197 193
198/****************************************************************************** 194/******************************************************************************
@@ -226,7 +222,6 @@ ixgb_standby_eeprom(struct ixgb_hw *hw)
226 eecd_reg &= ~IXGB_EECD_SK; 222 eecd_reg &= ~IXGB_EECD_SK;
227 IXGB_WRITE_REG(hw, EECD, eecd_reg); 223 IXGB_WRITE_REG(hw, EECD, eecd_reg);
228 udelay(50); 224 udelay(50);
229 return;
230} 225}
231 226
232/****************************************************************************** 227/******************************************************************************
@@ -250,7 +245,6 @@ ixgb_clock_eeprom(struct ixgb_hw *hw)
250 eecd_reg &= ~IXGB_EECD_SK; 245 eecd_reg &= ~IXGB_EECD_SK;
251 IXGB_WRITE_REG(hw, EECD, eecd_reg); 246 IXGB_WRITE_REG(hw, EECD, eecd_reg);
252 udelay(50); 247 udelay(50);
253 return;
254} 248}
255 249
256/****************************************************************************** 250/******************************************************************************
@@ -270,7 +264,6 @@ ixgb_cleanup_eeprom(struct ixgb_hw *hw)
270 IXGB_WRITE_REG(hw, EECD, eecd_reg); 264 IXGB_WRITE_REG(hw, EECD, eecd_reg);
271 265
272 ixgb_clock_eeprom(hw); 266 ixgb_clock_eeprom(hw);
273 return;
274} 267}
275 268
276/****************************************************************************** 269/******************************************************************************
@@ -359,7 +352,6 @@ ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
359 checksum = (u16) EEPROM_SUM - checksum; 352 checksum = (u16) EEPROM_SUM - checksum;
360 353
361 ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum); 354 ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum);
362 return;
363} 355}
364 356
365/****************************************************************************** 357/******************************************************************************
@@ -414,8 +406,6 @@ ixgb_write_eeprom(struct ixgb_hw *hw, u16 offset, u16 data)
414 406
415 /* clear the init_ctrl_reg_1 to signify that the cache is invalidated */ 407 /* clear the init_ctrl_reg_1 to signify that the cache is invalidated */
416 ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR); 408 ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR);
417
418 return;
419} 409}
420 410
421/****************************************************************************** 411/******************************************************************************
diff --git a/drivers/net/ixgb/ixgb_hw.c b/drivers/net/ixgb/ixgb_hw.c
index cd247b8d2b7..397acabccab 100644
--- a/drivers/net/ixgb/ixgb_hw.c
+++ b/drivers/net/ixgb/ixgb_hw.c
@@ -413,8 +413,6 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
413 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 413 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
414 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 414 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
415 } 415 }
416
417 return;
418} 416}
419 417
420/****************************************************************************** 418/******************************************************************************
@@ -483,7 +481,6 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw,
483 } 481 }
484 482
485 pr_debug("MC Update Complete\n"); 483 pr_debug("MC Update Complete\n");
486 return;
487} 484}
488 485
489/****************************************************************************** 486/******************************************************************************
@@ -566,8 +563,6 @@ ixgb_mta_set(struct ixgb_hw *hw,
566 mta_reg |= (1 << hash_bit); 563 mta_reg |= (1 << hash_bit);
567 564
568 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg); 565 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
569
570 return;
571} 566}
572 567
573/****************************************************************************** 568/******************************************************************************
@@ -600,7 +595,6 @@ ixgb_rar_set(struct ixgb_hw *hw,
600 595
601 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 596 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
602 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 597 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
603 return;
604} 598}
605 599
606/****************************************************************************** 600/******************************************************************************
@@ -616,7 +610,6 @@ ixgb_write_vfta(struct ixgb_hw *hw,
616 u32 value) 610 u32 value)
617{ 611{
618 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value); 612 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
619 return;
620} 613}
621 614
622/****************************************************************************** 615/******************************************************************************
@@ -631,7 +624,6 @@ ixgb_clear_vfta(struct ixgb_hw *hw)
631 624
632 for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++) 625 for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
633 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 626 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
634 return;
635} 627}
636 628
637/****************************************************************************** 629/******************************************************************************
@@ -1050,7 +1042,6 @@ ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
1050 temp_reg = IXGB_READ_REG(hw, XOFFRXC); 1042 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1051 temp_reg = IXGB_READ_REG(hw, XOFFTXC); 1043 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1052 temp_reg = IXGB_READ_REG(hw, RJC); 1044 temp_reg = IXGB_READ_REG(hw, RJC);
1053 return;
1054} 1045}
1055 1046
1056/****************************************************************************** 1047/******************************************************************************
@@ -1066,7 +1057,6 @@ ixgb_led_on(struct ixgb_hw *hw)
1066 /* To turn on the LED, clear software-definable pin 0 (SDP0). */ 1057 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1067 ctrl0_reg &= ~IXGB_CTRL0_SDP0; 1058 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1068 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1059 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1069 return;
1070} 1060}
1071 1061
1072/****************************************************************************** 1062/******************************************************************************
@@ -1082,7 +1072,6 @@ ixgb_led_off(struct ixgb_hw *hw)
1082 /* To turn off the LED, set software-definable pin 0 (SDP0). */ 1072 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1083 ctrl0_reg |= IXGB_CTRL0_SDP0; 1073 ctrl0_reg |= IXGB_CTRL0_SDP0;
1084 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1074 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1085 return;
1086} 1075}
1087 1076
1088/****************************************************************************** 1077/******************************************************************************
@@ -1122,8 +1111,6 @@ ixgb_get_bus_info(struct ixgb_hw *hw)
1122 1111
1123 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ? 1112 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1124 ixgb_bus_width_64 : ixgb_bus_width_32; 1113 ixgb_bus_width_64 : ixgb_bus_width_32;
1125
1126 return;
1127} 1114}
1128 1115
1129/****************************************************************************** 1116/******************************************************************************
@@ -1210,8 +1197,6 @@ ixgb_optics_reset(struct ixgb_hw *hw)
1210 IXGB_PHY_ADDRESS, 1197 IXGB_PHY_ADDRESS,
1211 MDIO_MMD_PMAPMD); 1198 MDIO_MMD_PMAPMD);
1212 } 1199 }
1213
1214 return;
1215} 1200}
1216 1201
1217/****************************************************************************** 1202/******************************************************************************
@@ -1272,6 +1257,4 @@ ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1272 1257
1273 /* SerDes needs extra delay */ 1258 /* SerDes needs extra delay */
1274 msleep(IXGB_SUN_PHY_RESET_DELAY); 1259 msleep(IXGB_SUN_PHY_RESET_DELAY);
1275
1276 return;
1277} 1260}