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authorDavid Gibson <david@gibson.dropbear.id.au>2007-08-22 23:56:01 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:51:52 -0400
commit1d3bb996481e116f5f2b127cbd29b83365d2cf62 (patch)
treeb612a1dbf51c920fb5a9758a6d35f9ed37eb927f /drivers/net/ibm_newemac/core.h
parent03233b90b0977d577322a6e1ddd56d9cc570d406 (diff)
Device tree aware EMAC driver
Based on BenH's earlier work, this is a new version of the EMAC driver for the built-in ethernet found on PowerPC 4xx embedded CPUs. The same ASIC is also found in the Axon bridge chip. This new version is designed to work in the arch/powerpc tree, using the device tree to probe the device, rather than the old and ugly arch/ppc OCP layer. This driver is designed to sit alongside the old driver (that lies in drivers/net/ibm_emac and this one in drivers/net/ibm_newemac). The old driver is left in place to support arch/ppc until arch/ppc itself reaches its final demise (not too long now, with luck). This driver still has a number of things that could do with cleaning up, but I think they can be fixed up after merging. Specifically: - Should be adjusted to properly use the dma mapping API. Axon needs this. - Probe logic needs reworking, in conjuction with the general probing code for of_platform devices. The dependencies here between EMAC, MAL, ZMII etc. make this complicated. At present, it usually works, because we initialize and register the sub-drivers before the EMAC driver itself, and (being in driver code) runs after the devices themselves have been instantiated from the device tree. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/ibm_newemac/core.h')
-rw-r--r--drivers/net/ibm_newemac/core.h355
1 files changed, 355 insertions, 0 deletions
diff --git a/drivers/net/ibm_newemac/core.h b/drivers/net/ibm_newemac/core.h
new file mode 100644
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+++ b/drivers/net/ibm_newemac/core.h
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1/*
2 * drivers/net/ibm_newemac/core.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Johnnie Peters <jpeters@mvista.com>
12 * Copyright 2000, 2001 MontaVista Softare Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 */
20#ifndef __IBM_NEWEMAC_CORE_H
21#define __IBM_NEWEMAC_CORE_H
22
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/kernel.h>
27#include <linux/interrupt.h>
28#include <linux/netdevice.h>
29#include <linux/dma-mapping.h>
30#include <linux/spinlock.h>
31
32#include <asm/of_platform.h>
33#include <asm/io.h>
34#include <asm/dcr.h>
35
36#include "emac.h"
37#include "phy.h"
38#include "zmii.h"
39#include "rgmii.h"
40#include "mal.h"
41#include "tah.h"
42#include "debug.h"
43
44#define NUM_TX_BUFF CONFIG_IBM_NEW_EMAC_TXB
45#define NUM_RX_BUFF CONFIG_IBM_NEW_EMAC_RXB
46
47/* Simple sanity check */
48#if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
49#error Invalid number of buffer descriptors (greater than 256)
50#endif
51
52#define EMAC_MIN_MTU 46
53
54/* Maximum L2 header length (VLAN tagged, no FCS) */
55#define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4)
56
57/* RX BD size for the given MTU */
58static inline int emac_rx_size(int mtu)
59{
60 if (mtu > ETH_DATA_LEN)
61 return MAL_MAX_RX_SIZE;
62 else
63 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
64}
65
66#define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment())
67
68#define EMAC_RX_SKB_HEADROOM \
69 EMAC_DMA_ALIGN(CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM)
70
71/* Size of RX skb for the given MTU */
72static inline int emac_rx_skb_size(int mtu)
73{
74 int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
75 return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
76}
77
78/* RX DMA sync size */
79static inline int emac_rx_sync_size(int mtu)
80{
81 return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
82}
83
84/* Driver statistcs is split into two parts to make it more cache friendly:
85 * - normal statistics (packet count, etc)
86 * - error statistics
87 *
88 * When statistics is requested by ethtool, these parts are concatenated,
89 * normal one goes first.
90 *
91 * Please, keep these structures in sync with emac_stats_keys.
92 */
93
94/* Normal TX/RX Statistics */
95struct emac_stats {
96 u64 rx_packets;
97 u64 rx_bytes;
98 u64 tx_packets;
99 u64 tx_bytes;
100 u64 rx_packets_csum;
101 u64 tx_packets_csum;
102};
103
104/* Error statistics */
105struct emac_error_stats {
106 u64 tx_undo;
107
108 /* Software RX Errors */
109 u64 rx_dropped_stack;
110 u64 rx_dropped_oom;
111 u64 rx_dropped_error;
112 u64 rx_dropped_resize;
113 u64 rx_dropped_mtu;
114 u64 rx_stopped;
115 /* BD reported RX errors */
116 u64 rx_bd_errors;
117 u64 rx_bd_overrun;
118 u64 rx_bd_bad_packet;
119 u64 rx_bd_runt_packet;
120 u64 rx_bd_short_event;
121 u64 rx_bd_alignment_error;
122 u64 rx_bd_bad_fcs;
123 u64 rx_bd_packet_too_long;
124 u64 rx_bd_out_of_range;
125 u64 rx_bd_in_range;
126 /* EMAC IRQ reported RX errors */
127 u64 rx_parity;
128 u64 rx_fifo_overrun;
129 u64 rx_overrun;
130 u64 rx_bad_packet;
131 u64 rx_runt_packet;
132 u64 rx_short_event;
133 u64 rx_alignment_error;
134 u64 rx_bad_fcs;
135 u64 rx_packet_too_long;
136 u64 rx_out_of_range;
137 u64 rx_in_range;
138
139 /* Software TX Errors */
140 u64 tx_dropped;
141 /* BD reported TX errors */
142 u64 tx_bd_errors;
143 u64 tx_bd_bad_fcs;
144 u64 tx_bd_carrier_loss;
145 u64 tx_bd_excessive_deferral;
146 u64 tx_bd_excessive_collisions;
147 u64 tx_bd_late_collision;
148 u64 tx_bd_multple_collisions;
149 u64 tx_bd_single_collision;
150 u64 tx_bd_underrun;
151 u64 tx_bd_sqe;
152 /* EMAC IRQ reported TX errors */
153 u64 tx_parity;
154 u64 tx_underrun;
155 u64 tx_sqe;
156 u64 tx_errors;
157};
158
159#define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \
160 sizeof(struct emac_error_stats)) \
161 / sizeof(u64))
162
163struct emac_instance {
164 struct net_device *ndev;
165 struct resource rsrc_regs;
166 struct emac_regs __iomem *emacp;
167 struct of_device *ofdev;
168 struct device_node **blist; /* bootlist entry */
169
170 /* MAL linkage */
171 u32 mal_ph;
172 struct of_device *mal_dev;
173 u32 mal_rx_chan;
174 u32 mal_tx_chan;
175 struct mal_instance *mal;
176 struct mal_commac commac;
177
178 /* PHY infos */
179 u32 phy_mode;
180 u32 phy_map;
181 u32 phy_address;
182 u32 phy_feat_exc;
183 struct mii_phy phy;
184 struct mutex link_lock;
185 struct delayed_work link_work;
186 int link_polling;
187
188 /* Shared MDIO if any */
189 u32 mdio_ph;
190 struct of_device *mdio_dev;
191 struct emac_instance *mdio_instance;
192 struct mutex mdio_lock;
193
194 /* ZMII infos if any */
195 u32 zmii_ph;
196 u32 zmii_port;
197 struct of_device *zmii_dev;
198
199 /* RGMII infos if any */
200 u32 rgmii_ph;
201 u32 rgmii_port;
202 struct of_device *rgmii_dev;
203
204 /* TAH infos if any */
205 u32 tah_ph;
206 u32 tah_port;
207 struct of_device *tah_dev;
208
209 /* IRQs */
210 int wol_irq;
211 int emac_irq;
212
213 /* OPB bus frequency in Mhz */
214 u32 opb_bus_freq;
215
216 /* Cell index within an ASIC (for clk mgmnt) */
217 u32 cell_index;
218
219 /* Max supported MTU */
220 u32 max_mtu;
221
222 /* Feature bits (from probe table) */
223 unsigned int features;
224
225 /* Tx and Rx fifo sizes & other infos in bytes */
226 u32 tx_fifo_size;
227 u32 tx_fifo_size_gige;
228 u32 rx_fifo_size;
229 u32 rx_fifo_size_gige;
230 u32 fifo_entry_size;
231 u32 mal_burst_size; /* move to MAL ? */
232
233 /* Descriptor management
234 */
235 struct mal_descriptor *tx_desc;
236 int tx_cnt;
237 int tx_slot;
238 int ack_slot;
239
240 struct mal_descriptor *rx_desc;
241 int rx_slot;
242 struct sk_buff *rx_sg_skb; /* 1 */
243 int rx_skb_size;
244 int rx_sync_size;
245
246 struct sk_buff *tx_skb[NUM_TX_BUFF];
247 struct sk_buff *rx_skb[NUM_RX_BUFF];
248
249 /* Stats
250 */
251 struct emac_error_stats estats;
252 struct net_device_stats nstats;
253 struct emac_stats stats;
254
255 /* Misc
256 */
257 int reset_failed;
258 int stop_timeout; /* in us */
259 int no_mcast;
260 int mcast_pending;
261 struct work_struct reset_work;
262 spinlock_t lock;
263};
264
265/*
266 * Features of various EMAC implementations
267 */
268
269/*
270 * No flow control on 40x according to the original driver
271 */
272#define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001
273/*
274 * Cell is an EMAC4
275 */
276#define EMAC_FTR_EMAC4 0x00000002
277/*
278 * For the 440SPe, AMCC inexplicably changed the polarity of
279 * the "operation complete" bit in the MII control register.
280 */
281#define EMAC_FTR_STACR_OC_INVERT 0x00000004
282/*
283 * Set if we have a TAH.
284 */
285#define EMAC_FTR_HAS_TAH 0x00000008
286/*
287 * Set if we have a ZMII.
288 */
289#define EMAC_FTR_HAS_ZMII 0x00000010
290/*
291 * Set if we have a RGMII.
292 */
293#define EMAC_FTR_HAS_RGMII 0x00000020
294/*
295 * Set if we have axon-type STACR
296 */
297#define EMAC_FTR_HAS_AXON_STACR 0x00000040
298
299
300/* Right now, we don't quite handle the always/possible masks on the
301 * most optimal way as we don't have a way to say something like
302 * always EMAC4. Patches welcome.
303 */
304enum {
305 EMAC_FTRS_ALWAYS = 0,
306
307 EMAC_FTRS_POSSIBLE =
308#ifdef CONFIG_IBM_NEW_EMAC_EMAC4
309 EMAC_FTR_EMAC4 | EMAC_FTR_HAS_AXON_STACR |
310 EMAC_FTR_STACR_OC_INVERT |
311#endif
312#ifdef CONFIG_IBM_NEW_EMAC_TAH
313 EMAC_FTR_HAS_TAH |
314#endif
315#ifdef CONFIG_IBM_NEW_EMAC_ZMII
316 EMAC_FTR_HAS_ZMII |
317#endif
318#ifdef CONFIG_IBM_NEW_EMAC_RGMII
319 EMAC_FTR_HAS_RGMII |
320#endif
321 0,
322};
323
324static inline int emac_has_feature(struct emac_instance *dev,
325 unsigned long feature)
326{
327 return (EMAC_FTRS_ALWAYS & feature) ||
328 (EMAC_FTRS_POSSIBLE & dev->features & feature);
329}
330
331
332/* Ethtool get_regs complex data.
333 * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
334 * when available.
335 *
336 * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
337 * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
338 * Each register component is preceded with emac_ethtool_regs_subhdr.
339 * Order of the optional headers follows their relative bit posititions
340 * in emac_ethtool_regs_hdr.components
341 */
342#define EMAC_ETHTOOL_REGS_ZMII 0x00000001
343#define EMAC_ETHTOOL_REGS_RGMII 0x00000002
344#define EMAC_ETHTOOL_REGS_TAH 0x00000004
345
346struct emac_ethtool_regs_hdr {
347 u32 components;
348};
349
350struct emac_ethtool_regs_subhdr {
351 u32 version;
352 u32 index;
353};
354
355#endif /* __IBM_NEWEMAC_CORE_H */
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