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authorBruce Allan <bruce.w.allan@intel.com>2009-10-26 07:24:02 -0400
committerDavid S. Miller <davem@davemloft.net>2009-10-26 19:16:25 -0400
commit5ccdcecb72692d46d7a9264e62751241c7eca559 (patch)
treec82d7487a41fed230234578f1ddbe1b35ea59e5e /drivers/net/e1000e/ich8lan.c
parentca15df58b1b98f073393eef3704674b45d1cb474 (diff)
e1000e: allow for swflag to be held over consecutive PHY accesses
PCH-based parts (82577/82578) and some ICH8-based parts (82566) need to hold the swflag (sw/fw/hw hardware semaphore) over consecutive PHY accesses in order to perform sw-driven PHY configuration during initialization to workaround known hardware issues (see follow-on patch). This patch provides new PHY read/write functions (and function pointers) that will allow accessing the PHY registers assuming the swflag has already been acquired. The actual PHY register access code has moved into helper functions that are called with a flag indicating whether or not the swflag has already been acquired and acquires/releases it if not. The functions called from within the updated PHY access functions had to be updated to assume the swflag was already acquired, and other functions that called those functions were also updated to acquire/release the swflag. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e/ich8lan.c')
-rw-r--r--drivers/net/e1000e/ich8lan.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index aaaaf2ca408..b6388b9535f 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -250,9 +250,11 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
250 250
251 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; 251 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
252 phy->ops.read_phy_reg = e1000_read_phy_reg_hv; 252 phy->ops.read_phy_reg = e1000_read_phy_reg_hv;
253 phy->ops.read_phy_reg_locked = e1000_read_phy_reg_hv_locked;
253 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 254 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
254 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 255 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
255 phy->ops.write_phy_reg = e1000_write_phy_reg_hv; 256 phy->ops.write_phy_reg = e1000_write_phy_reg_hv;
257 phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;
256 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 258 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
257 259
258 phy->id = e1000_phy_unknown; 260 phy->id = e1000_phy_unknown;
@@ -313,6 +315,8 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
313 case IGP03E1000_E_PHY_ID: 315 case IGP03E1000_E_PHY_ID:
314 phy->type = e1000_phy_igp_3; 316 phy->type = e1000_phy_igp_3;
315 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 317 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
318 phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;
319 phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;
316 break; 320 break;
317 case IFE_E_PHY_ID: 321 case IFE_E_PHY_ID:
318 case IFE_PLUS_E_PHY_ID: 322 case IFE_PLUS_E_PHY_ID: