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authorCasey Leedom <leedom@chelsio.com>2010-06-25 08:11:05 -0400
committerDavid S. Miller <davem@davemloft.net>2010-06-29 02:59:34 -0400
commit17edf2594fef0c7ff186720915a9a73f77fee96b (patch)
treee839350c6a427a77bb2a7add3de5ebb5154e4ed9 /drivers/net/cxgb4/t4_hw.h
parent81323b74a83d4144367184926a80e030e2354d25 (diff)
cxgb4vf: Add new macros and definitions for hardware constants
Add new macros and definitions for hardware constants. Signed-off-by: Casey Leedom Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/cxgb4/t4_hw.h')
-rw-r--r--drivers/net/cxgb4/t4_hw.h39
1 files changed, 39 insertions, 0 deletions
diff --git a/drivers/net/cxgb4/t4_hw.h b/drivers/net/cxgb4/t4_hw.h
index 98c02bedc02..e875d095af3 100644
--- a/drivers/net/cxgb4/t4_hw.h
+++ b/drivers/net/cxgb4/t4_hw.h
@@ -67,6 +67,45 @@ enum {
67 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 67 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
68 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 68 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
69 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 69 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
70
71 SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */
72 SGE_TIMER_UPD_CIDX = 7, /* update cidx only */
73
74 SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */
75
76 SGE_INTRDST_PCI = 0, /* interrupt destination is PCI-E */
77 SGE_INTRDST_IQ = 1, /* destination is an ingress queue */
78
79 SGE_UPDATEDEL_NONE = 0, /* ingress queue pidx update delivery */
80 SGE_UPDATEDEL_INTR = 1, /* interrupt */
81 SGE_UPDATEDEL_STPG = 2, /* status page */
82 SGE_UPDATEDEL_BOTH = 3, /* interrupt and status page */
83
84 SGE_HOSTFCMODE_NONE = 0, /* egress queue cidx updates */
85 SGE_HOSTFCMODE_IQ = 1, /* sent to ingress queue */
86 SGE_HOSTFCMODE_STPG = 2, /* sent to status page */
87 SGE_HOSTFCMODE_BOTH = 3, /* ingress queue and status page */
88
89 SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */
90 SGE_FETCHBURSTMIN_32B = 1,
91 SGE_FETCHBURSTMIN_64B = 2,
92 SGE_FETCHBURSTMIN_128B = 3,
93
94 SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */
95 SGE_FETCHBURSTMAX_128B = 1,
96 SGE_FETCHBURSTMAX_256B = 2,
97 SGE_FETCHBURSTMAX_512B = 3,
98
99 SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */
100 SGE_CIDXFLUSHTHRESH_2 = 1,
101 SGE_CIDXFLUSHTHRESH_4 = 2,
102 SGE_CIDXFLUSHTHRESH_8 = 3,
103 SGE_CIDXFLUSHTHRESH_16 = 4,
104 SGE_CIDXFLUSHTHRESH_32 = 5,
105 SGE_CIDXFLUSHTHRESH_64 = 6,
106 SGE_CIDXFLUSHTHRESH_128 = 7,
107
108 SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */
70}; 109};
71 110
72struct sge_qstat { /* data written to SGE queue status entries */ 111struct sge_qstat { /* data written to SGE queue status entries */