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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /drivers/net/can/c_can/c_can.h
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'drivers/net/can/c_can/c_can.h')
-rw-r--r--drivers/net/can/c_can/c_can.h177
1 files changed, 38 insertions, 139 deletions
diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
index d2e1c21b143..9b7fbef3d09 100644
--- a/drivers/net/can/c_can/c_can.h
+++ b/drivers/net/can/c_can/c_can.h
@@ -22,132 +22,43 @@
22#ifndef C_CAN_H 22#ifndef C_CAN_H
23#define C_CAN_H 23#define C_CAN_H
24 24
25enum reg { 25/* c_can IF registers */
26 C_CAN_CTRL_REG = 0, 26struct c_can_if_regs {
27 C_CAN_CTRL_EX_REG, 27 u16 com_req;
28 C_CAN_STS_REG, 28 u16 com_mask;
29 C_CAN_ERR_CNT_REG, 29 u16 mask1;
30 C_CAN_BTR_REG, 30 u16 mask2;
31 C_CAN_INT_REG, 31 u16 arb1;
32 C_CAN_TEST_REG, 32 u16 arb2;
33 C_CAN_BRPEXT_REG, 33 u16 msg_cntrl;
34 C_CAN_IF1_COMREQ_REG, 34 u16 data[4];
35 C_CAN_IF1_COMMSK_REG, 35 u16 _reserved[13];
36 C_CAN_IF1_MASK1_REG,
37 C_CAN_IF1_MASK2_REG,
38 C_CAN_IF1_ARB1_REG,
39 C_CAN_IF1_ARB2_REG,
40 C_CAN_IF1_MSGCTRL_REG,
41 C_CAN_IF1_DATA1_REG,
42 C_CAN_IF1_DATA2_REG,
43 C_CAN_IF1_DATA3_REG,
44 C_CAN_IF1_DATA4_REG,
45 C_CAN_IF2_COMREQ_REG,
46 C_CAN_IF2_COMMSK_REG,
47 C_CAN_IF2_MASK1_REG,
48 C_CAN_IF2_MASK2_REG,
49 C_CAN_IF2_ARB1_REG,
50 C_CAN_IF2_ARB2_REG,
51 C_CAN_IF2_MSGCTRL_REG,
52 C_CAN_IF2_DATA1_REG,
53 C_CAN_IF2_DATA2_REG,
54 C_CAN_IF2_DATA3_REG,
55 C_CAN_IF2_DATA4_REG,
56 C_CAN_TXRQST1_REG,
57 C_CAN_TXRQST2_REG,
58 C_CAN_NEWDAT1_REG,
59 C_CAN_NEWDAT2_REG,
60 C_CAN_INTPND1_REG,
61 C_CAN_INTPND2_REG,
62 C_CAN_MSGVAL1_REG,
63 C_CAN_MSGVAL2_REG,
64}; 36};
65 37
66static const u16 reg_map_c_can[] = { 38/* c_can hardware registers */
67 [C_CAN_CTRL_REG] = 0x00, 39struct c_can_regs {
68 [C_CAN_STS_REG] = 0x02, 40 u16 control;
69 [C_CAN_ERR_CNT_REG] = 0x04, 41 u16 status;
70 [C_CAN_BTR_REG] = 0x06, 42 u16 err_cnt;
71 [C_CAN_INT_REG] = 0x08, 43 u16 btr;
72 [C_CAN_TEST_REG] = 0x0A, 44 u16 interrupt;
73 [C_CAN_BRPEXT_REG] = 0x0C, 45 u16 test;
74 [C_CAN_IF1_COMREQ_REG] = 0x10, 46 u16 brp_ext;
75 [C_CAN_IF1_COMMSK_REG] = 0x12, 47 u16 _reserved1;
76 [C_CAN_IF1_MASK1_REG] = 0x14, 48 struct c_can_if_regs ifregs[2]; /* [0] = IF1 and [1] = IF2 */
77 [C_CAN_IF1_MASK2_REG] = 0x16, 49 u16 _reserved2[8];
78 [C_CAN_IF1_ARB1_REG] = 0x18, 50 u16 txrqst1;
79 [C_CAN_IF1_ARB2_REG] = 0x1A, 51 u16 txrqst2;
80 [C_CAN_IF1_MSGCTRL_REG] = 0x1C, 52 u16 _reserved3[6];
81 [C_CAN_IF1_DATA1_REG] = 0x1E, 53 u16 newdat1;
82 [C_CAN_IF1_DATA2_REG] = 0x20, 54 u16 newdat2;
83 [C_CAN_IF1_DATA3_REG] = 0x22, 55 u16 _reserved4[6];
84 [C_CAN_IF1_DATA4_REG] = 0x24, 56 u16 intpnd1;
85 [C_CAN_IF2_COMREQ_REG] = 0x40, 57 u16 intpnd2;
86 [C_CAN_IF2_COMMSK_REG] = 0x42, 58 u16 _reserved5[6];
87 [C_CAN_IF2_MASK1_REG] = 0x44, 59 u16 msgval1;
88 [C_CAN_IF2_MASK2_REG] = 0x46, 60 u16 msgval2;
89 [C_CAN_IF2_ARB1_REG] = 0x48, 61 u16 _reserved6[6];
90 [C_CAN_IF2_ARB2_REG] = 0x4A,
91 [C_CAN_IF2_MSGCTRL_REG] = 0x4C,
92 [C_CAN_IF2_DATA1_REG] = 0x4E,
93 [C_CAN_IF2_DATA2_REG] = 0x50,
94 [C_CAN_IF2_DATA3_REG] = 0x52,
95 [C_CAN_IF2_DATA4_REG] = 0x54,
96 [C_CAN_TXRQST1_REG] = 0x80,
97 [C_CAN_TXRQST2_REG] = 0x82,
98 [C_CAN_NEWDAT1_REG] = 0x90,
99 [C_CAN_NEWDAT2_REG] = 0x92,
100 [C_CAN_INTPND1_REG] = 0xA0,
101 [C_CAN_INTPND2_REG] = 0xA2,
102 [C_CAN_MSGVAL1_REG] = 0xB0,
103 [C_CAN_MSGVAL2_REG] = 0xB2,
104};
105
106static const u16 reg_map_d_can[] = {
107 [C_CAN_CTRL_REG] = 0x00,
108 [C_CAN_CTRL_EX_REG] = 0x02,
109 [C_CAN_STS_REG] = 0x04,
110 [C_CAN_ERR_CNT_REG] = 0x08,
111 [C_CAN_BTR_REG] = 0x0C,
112 [C_CAN_BRPEXT_REG] = 0x0E,
113 [C_CAN_INT_REG] = 0x10,
114 [C_CAN_TEST_REG] = 0x14,
115 [C_CAN_TXRQST1_REG] = 0x88,
116 [C_CAN_TXRQST2_REG] = 0x8A,
117 [C_CAN_NEWDAT1_REG] = 0x9C,
118 [C_CAN_NEWDAT2_REG] = 0x9E,
119 [C_CAN_INTPND1_REG] = 0xB0,
120 [C_CAN_INTPND2_REG] = 0xB2,
121 [C_CAN_MSGVAL1_REG] = 0xC4,
122 [C_CAN_MSGVAL2_REG] = 0xC6,
123 [C_CAN_IF1_COMREQ_REG] = 0x100,
124 [C_CAN_IF1_COMMSK_REG] = 0x102,
125 [C_CAN_IF1_MASK1_REG] = 0x104,
126 [C_CAN_IF1_MASK2_REG] = 0x106,
127 [C_CAN_IF1_ARB1_REG] = 0x108,
128 [C_CAN_IF1_ARB2_REG] = 0x10A,
129 [C_CAN_IF1_MSGCTRL_REG] = 0x10C,
130 [C_CAN_IF1_DATA1_REG] = 0x110,
131 [C_CAN_IF1_DATA2_REG] = 0x112,
132 [C_CAN_IF1_DATA3_REG] = 0x114,
133 [C_CAN_IF1_DATA4_REG] = 0x116,
134 [C_CAN_IF2_COMREQ_REG] = 0x120,
135 [C_CAN_IF2_COMMSK_REG] = 0x122,
136 [C_CAN_IF2_MASK1_REG] = 0x124,
137 [C_CAN_IF2_MASK2_REG] = 0x126,
138 [C_CAN_IF2_ARB1_REG] = 0x128,
139 [C_CAN_IF2_ARB2_REG] = 0x12A,
140 [C_CAN_IF2_MSGCTRL_REG] = 0x12C,
141 [C_CAN_IF2_DATA1_REG] = 0x130,
142 [C_CAN_IF2_DATA2_REG] = 0x132,
143 [C_CAN_IF2_DATA3_REG] = 0x134,
144 [C_CAN_IF2_DATA4_REG] = 0x136,
145};
146
147enum c_can_dev_id {
148 BOSCH_C_CAN_PLATFORM,
149 BOSCH_C_CAN,
150 BOSCH_D_CAN,
151}; 62};
152 63
153/* c_can private data structure */ 64/* c_can private data structure */
@@ -155,23 +66,16 @@ struct c_can_priv {
155 struct can_priv can; /* must be the first member */ 66 struct can_priv can; /* must be the first member */
156 struct napi_struct napi; 67 struct napi_struct napi;
157 struct net_device *dev; 68 struct net_device *dev;
158 struct device *device;
159 int tx_object; 69 int tx_object;
160 int current_status; 70 int current_status;
161 int last_status; 71 int last_status;
162 u16 (*read_reg) (struct c_can_priv *priv, enum reg index); 72 u16 (*read_reg) (struct c_can_priv *priv, void *reg);
163 void (*write_reg) (struct c_can_priv *priv, enum reg index, u16 val); 73 void (*write_reg) (struct c_can_priv *priv, void *reg, u16 val);
164 void __iomem *base; 74 struct c_can_regs __iomem *regs;
165 const u16 *regs;
166 unsigned long irq_flags; /* for request_irq() */ 75 unsigned long irq_flags; /* for request_irq() */
167 unsigned int tx_next; 76 unsigned int tx_next;
168 unsigned int tx_echo; 77 unsigned int tx_echo;
169 void *priv; /* for board-specific data */ 78 void *priv; /* for board-specific data */
170 u16 irqstatus;
171 enum c_can_dev_id type;
172 u32 __iomem *raminit_ctrlreg;
173 unsigned int instance;
174 void (*raminit) (const struct c_can_priv *priv, bool enable);
175}; 79};
176 80
177struct net_device *alloc_c_can_dev(void); 81struct net_device *alloc_c_can_dev(void);
@@ -179,9 +83,4 @@ void free_c_can_dev(struct net_device *dev);
179int register_c_can_dev(struct net_device *dev); 83int register_c_can_dev(struct net_device *dev);
180void unregister_c_can_dev(struct net_device *dev); 84void unregister_c_can_dev(struct net_device *dev);
181 85
182#ifdef CONFIG_PM
183int c_can_power_up(struct net_device *dev);
184int c_can_power_down(struct net_device *dev);
185#endif
186
187#endif /* C_CAN_H */ 86#endif /* C_CAN_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 17:31:14 -0400